Display device and electronic device including the same

Abstract

The invention provides a display device and an electronic device. The display device includes: a base layer; pixels, each including a sub-pixel; a demultiplexer; a drive circuit portion; a data line connecting the demultiplexer to the sub-pixel; a data base line connecting the demultiplexer to the driving circuit portion and including a first data base line and a second data base line; a data connection line connected to the data base line and including a first data connection line having a 1-1 data connection line and a 1-2 data connection line and a second data connection line having a 2-1 data connection line and a 2-2 data connection line; a bridge layer including a first bridge layer connected to the (1-1) th data connection line and the (1-2) th data connection line, and a second bridge layer connected to the (2-1) th data connection line and the (2-2) th data connection line; and an intermediate bridge pattern layer connecting the first data base line to the first bridge layer, overlapping the second bridge layer, and having a width greater than a width of the first data base line.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0094584, filed with the Korean Intellectual Property Office on July 17, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Various embodiments of the present invention relate to display devices, and more specifically, to display devices including intermediate bridging pattern layers and electronic devices including display devices. Background Technology

[0004] In recent years, as information is increasingly viewed through display devices, the development of display devices has continued. Typically, a display device includes pixels and multiple lines electrically connected to the pixels and patterned according to a structure. Ideally, these multiple lines should be patterned according to a desired structure. Summary of the Invention

[0005] According to an embodiment of the present invention, a display device defines a display area and a non-display area. The display device includes: a base layer formed across the display area and the non-display area; pixels disposed on the base layer and in the display area, wherein each pixel includes a sub-pixel; a demultiplexer disposed in the non-display area; a driving circuit portion disposed adjacent to the demultiplexer and in the non-display area; data lines electrically connecting the demultiplexer to the sub-pixels; data base lines electrically connecting the demultiplexer to the driving circuit portion, wherein the data base lines include a first data base line and a second data base line; and data connection lines electrically connecting the demultiplexer to the data base lines, wherein the data connection lines include a first data connection line and a second data connection line, wherein the first data connection line is electrically connected to... The system comprises: a first data base line and including a first-1 data connection line and a first-2 data connection line, and a second data connection line electrically connected to the second data base line and including a second-1 data connection line and a second-2 data connection line; a bridging layer including a first bridging layer and a second bridging layer, wherein the first bridging layer is electrically connected to the first-1 data connection line and the first-2 data connection line, and the second bridging layer is electrically connected to the second-1 data connection line and the second-2 data connection line; and an intermediate bridging pattern layer electrically connecting the first data base line to the first bridging layer, wherein the intermediate bridging pattern layer overlaps with the second bridging layer and has a width greater than the width of the first data base line.

[0006] In an embodiment of the present invention, the intermediate bridging pattern layer includes a side surface that forms an interface angle with respect to the layer on which the intermediate bridging pattern layer is disposed, wherein the interface angle is in the range of 30° to 70°.

[0007] In an embodiment of the present invention, the intermediate bridge pattern layer has a width of 6 μm or more.

[0008] In an embodiment of the present invention, the intermediate bridge pattern layer has a thickness in a range of 3600 Å to 4200 Å.

[0009] In an embodiment of the present invention, the intermediate bridge pattern layer includes a first conductive layer including titanium (Ti) and a second conductive layer disposed on the first conductive layer and including aluminum (Al), wherein the first conductive layer has a thickness in a range of 200 Å to 400 Å, and wherein the second conductive layer has a thickness in a range of 3200 Å to 3800 Å.

[0010] In an embodiment of the present invention, the display device further includes a first interlayer conductive layer disposed on the base layer, a second interlayer conductive layer disposed on the first interlayer conductive layer, and a transistor conductive layer disposed on the second interlayer conductive layer, wherein the data connection lines are formed of the first interlayer conductive layer, wherein the data base lines and the intermediate bridge pattern layer are formed of the second interlayer conductive layer, and wherein the bridge layer is formed of the transistor conductive layer.

[0011] In an embodiment of the present invention, the pixel includes a first pixel and a second pixel adjacent to each other in a first direction, wherein the demultiplexer includes a first demultiplexing transistor and a second demultiplexing transistor, wherein the first pixel is electrically connected to the first demultiplexing transistor, and wherein the second pixel is electrically connected to the second demultiplexing transistor.

[0012] In an embodiment of the present invention, the display device further includes a first selection control line electrically connected to a gate electrode of the first demultiplexing transistor, and a second selection control line electrically connected to a gate electrode of the second demultiplexing transistor, wherein each of the first selection control line and the second selection control line extends in the first direction.

[0013] In an embodiment of the present invention, the first demultiplexing transistor includes a plurality of first demultiplexing transistors, wherein the second demultiplexing transistor includes a plurality of second demultiplexing transistors, wherein the 1-1 data connection line is electrically connected to one of the plurality of first demultiplexing transistors, wherein the 2-1 data connection line is electrically connected to another of the plurality of first demultiplexing transistors, wherein the 1-2 data connection line is electrically connected to one of the plurality of second demultiplexing transistors, and wherein the 2-2 data connection line is electrically connected to another of the plurality of second demultiplexing transistors.

[0014] In an embodiment of the present invention, the 1-1 data connection line, the 1-2 data connection line, the 2-1 data connection line, and the 2-2 data connection line extend in a second direction different from the first direction.

[0015] In an embodiment of the present invention, the first bridge layer electrically connects the first-1 data connection line and the first-2 data connection line to each other, and wherein the second bridge layer electrically connects the second-1 data connection line and the second-2 data connection line to each other.

[0016] In an embodiment of the present invention, the second bridge layer is disposed between the first bridge layer and the first data line, such that the intermediate bridge pattern layer and the second bridge layer overlap each other.

[0017] In an embodiment of the present invention, at least a portion of the data base line extends in the second direction.

[0018] In an embodiment of the present invention, the display device further comprises a bridge pattern layer electrically connecting the first data base line and the intermediate bridge pattern layer to each other and disposed on a layer different from the layer on which the first data base line and the intermediate bridge pattern layer are disposed.

[0019] In an embodiment of the present invention, the sub-pixel comprises a first sub-pixel, a second sub-pixel, and a third sub-pixel, wherein the data line comprises a first-1 data line electrically connected to the first sub-pixel of the first pixel, a second-1 data line electrically connected to the second sub-pixel of the first pixel, a third-1 data line electrically connected to the third sub-pixel of the first pixel, a first-2 data line electrically connected to the first sub-pixel of the second pixel, a second-2 data line electrically connected to the second sub-pixel of the second pixel, and a third-2 data line electrically connected to the third sub-pixel of the second pixel, wherein the first-1 data line, the second-1 data line, and the third-1 data line are electrically connected to a plurality of first demultiplexing transistors, respectively, and wherein the first-2 data line, the second-2 data line, and the third-2 data line are electrically connected to a plurality of second demultiplexing transistors, respectively.

[0020] In an embodiment of the present invention, the data base line further comprises a third data base line, wherein the data connection line further comprises a third data connection line comprising a third-1 data connection line and a third-2 data connection line and electrically connected to the third data base line, and wherein the third-1 data connection line extends in the second direction and overlaps the first bridge layer and the second bridge layer.

[0021] In an embodiment of the present invention, the bridge layer further comprises a third bridge layer electrically connected to the third-1 data connection line and the third-2 data connection line, and wherein the second bridge layer is disposed between the first bridge layer and the third bridge layer.

[0022] In an embodiment of the present invention, the intermediate bridge pattern layer is disposed across the second bridge layer and the third bridge layer, and overlaps at least a portion of the second bridge layer and at least a portion of the third bridge layer.

[0023] In an embodiment of the present invention, the intermediate bridge pattern layer includes a first intermediate bridge pattern layer and a second intermediate bridge pattern layer, wherein the first intermediate bridge pattern layer overlaps the second bridge layer and the second intermediate bridge pattern layer overlaps the third bridge layer, and wherein the first intermediate bridge pattern layer and the second intermediate bridge pattern layer are spaced apart from each other.

[0024] In an embodiment of the present invention, the intermediate bridge pattern layer includes a protrusion protruding in a direction between the second bridge layer and the third bridge layer.

[0025] According to an embodiment of the present invention, an electronic device includes a display device; and a power module configured to provide power to the display device, wherein the display device defines a display area and a non-display area, and includes a base layer formed across the display area and the non-display area; pixels disposed on the base layer and in the display area, wherein each of the pixels includes a sub-pixel; a demultiplexer disposed in the non-display area; a driving circuit portion disposed adjacent to the demultiplexer and in the non-display area; a data line electrically connecting the demultiplexer to the sub-pixel; a data base line electrically connecting the demultiplexer to the driving circuit portion, wherein the data base line includes a first data base line and a second data base line; a data connection line electrically connecting the demultiplexer to the data base line, wherein the data connection line includes a first data connection line and a second data connection line, wherein the first data connection line is electrically connected to the first data base line and includes a 1-1 data connection line and a 1-2 data connection line, and the second data connection line is electrically connected to the second data base line and includes a 2-1 data connection line and a 2-2 data connection line; a bridge layer including a first bridge layer and a second bridge layer, wherein the first bridge layer is electrically connected to the 1-1 data connection line and the 1-2 data connection line, and the second bridge layer is electrically connected to the 2-1 data connection line and the 2-2 data connection line; and an intermediate bridge pattern layer electrically connecting the first data base line to the first bridge layer, wherein the intermediate bridge pattern layer overlaps the second bridge layer and has a width greater than a width of the first data base line.

[0026] In an embodiment of the present invention, the intermediate bridge pattern layer includes a side surface forming an interface angle with respect to a layer on which the intermediate bridge pattern layer is disposed.

[0027] In an embodiment of the present invention, the display device further includes a bridge pattern layer electrically connecting the intermediate bridge pattern layer to the first data base line.

[0028] In an embodiment of the present invention, the 2-1 data connection line overlaps the first bridge layer.

[0029] In an embodiment of the present application, the data base line includes a third data base line, wherein the data connection line includes a third data connection line including a 3-1 data connection line and a 3-2 data connection line and electrically connected to the third data base line, and wherein the 3-1 data connection line overlaps the first bridge layer and the second bridge layer.

[0030] In an embodiment of the present application, the bridge layer includes a third bridge layer electrically connected to the 3-1 data connection line and the 3-2 data connection line, and wherein the intermediate bridge pattern layer overlaps the third bridge layer. BRIEF DESCRIPTION OF DRAWINGS

[0031] Figure 1 is a schematic perspective view showing a display device according to an embodiment of the present application.

[0032] Figure 2 is a schematic plan view showing a display device according to an embodiment of the present application.

[0033] Figure 3 is a schematic side view showing a display device according to an embodiment of the present application.

[0034] Figure 4 is a schematic view for describing a display device according to an embodiment of the present application.

[0035] Figure 5 is a schematic plan view showing a display region and a non-display region in which a drive circuit portion is provided according to an embodiment of the present application.

[0036] Figure 6 is a schematic plan view showing a region in which a first demultiplexing transistor and a second demultiplexing transistor of a demultiplexer and a line electrically connected to the first demultiplexing transistor and the second demultiplexing transistor are provided according to an embodiment of the present application.

[0037] Figure 7 is a schematic cross-sectional view showing a display device according to an embodiment of the present application.

[0038] Figure 8 is a schematic cross-sectional view showing a circuit layer according to an embodiment of the present application.

[0039] Figure 9 is a schematic plan view showing a region between a demultiplexer and a drive circuit portion according to an embodiment of the present application.

[0040] Figure 10 is a schematic cross-sectional view taken along Figure 9 line A- of

[0041] Figure 11is a schematic cross-sectional view taken along line B- Figure 9

[0042] Figure 12 is a schematic cross-sectional view taken along line C- Figure 9

[0043] Figure 13 is a schematic cross-sectional view taken along line D- Figure 9

[0044] Figure 14 Figure 15 are schematic diagrams for describing a process risk that can occur during an etching process of a conductive layer.

[0045] Figure 16 is a schematic plan view showing a region between a demultiplexer and a driving circuit portion according to an embodiment of the present application.

[0046] Figure 17 is a schematic plan view showing a region between a demultiplexer and a driving circuit portion according to an embodiment of the present application.

[0047] Figure 18 is a block diagram of an electronic device according to an embodiment.

[0048] Figure 19 are schematic diagrams showing various embodiments of an electronic device. DETAILED DESCRIPTION

[0049] Since the present disclosure allows for various changes and numerous embodiments, an exemplary embodiment of the present application will be illustrated in the drawings and described in detail in the written description. However, this is not intended to limit the present application to a particular mode of practice, and it is to be understood that all changes, equivalents, and substitutions included in this disclosure are intended to be encompassed by the present application.

[0050] It will be understood that, although the terms "first", "second", etc. can be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element discussed below could be termed a second element without departing from the teachings of the present application. Similarly, a second element could be termed a first element. In the present disclosure, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0051] ​​​​​​​Further, in the case where the first portion such as a layer, a film, a region, or a plate is disposed on the second portion, the first portion can not only be directly on the second portion, but a third portion can be interposed therebetween. Also, when expressed that the first portion such as a layer, a film, a region, or a plate is formed on the second portion, the surface of the second portion on which the first portion is formed is not limited to the upper surface of the second portion, but can include other surfaces of the second portion such as a side surface or a lower surface. Conversely, in the case where the first portion such as a layer, a film, a region, or a plate is under the second portion, the first portion can not only be directly under the second portion, but a third portion can be interposed therebetween.

[0052] In the drawings and specification, like reference numerals and / or characters can denote like elements, and so, repeated description can be omitted or simplified.

[0053] In view of the measurements discussed and the errors associated with measurements of particular quantities (e.g., limitations of the measurement system), "about" or "approximately," as used herein, includes the recited value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art. For example, "about" can mean within one or more standard deviations, or within ± 30%, ± 20%, ± 10%, or ± 5% of the recited value.

[0054] Various embodiments of the present application relate to a display device and an electronic device including the same. Hereinafter, a display device and an electronic device including the same according to embodiments will be described with reference to the accompanying drawings.

[0055] Embodiments of the present application relate to a display device having improved display quality and an electronic device including the same. According to embodiments of the present application, a display device includes a display area and a non-display area, a demultiplexer, a driving circuit portion, and a data line. The display device further includes an intermediate bridging pattern layer, which can provide increased electrical connectivity while reducing the risk of shorting or residual conductive structures during manufacturing. The intermediate bridging pattern layer can include specific geometric properties, such as controlled width and interface angles, to improve its performance and ensure reliable production results.

[0056] The intermediate bridging pattern layer overlaps other conductive elements in a structured manner, minimizing manufacturing defects and improving electrical performance. This approach significantly reduces the likelihood of accidental connections, which can cause data distortion and reduce display quality. By fine-tuning materials such as titanium and aluminum in the layered composition, the device can achieve an excellent balance of structure and function.

[0057] In addition, the present application embodiments disclose an arrangement of sub-pixels and lines in a display area, including a technique of managing connections through a demultiplexer and a bridge layer. This can provide a high resolution output and efficient data transmission for each pixel. Furthermore, according to the present application embodiments, a display device can have enhanced integration of its various circuit components, which can increase overall device functionality and manufacturing yield.

[0058] The present application embodiments can provide a solution for precise line structuring and efficient data processing while addressing challenges such as short circuit and defect risks. Accordingly, a display device with improved performance and display quality and an electronic device including the display device can be provided.

[0059] Figure 1 FIG. 1 is a schematic perspective view illustrating a display device DD according to an embodiment of the present application. Figure 2 FIG. 2 is a schematic plan view illustrating the display device DD according to an embodiment of the present application. Figure 3 FIG. 3 is a schematic side view illustrating the display device DD according to an embodiment of the present application.

[0060] Referring to FIGS. 1 to 3, Figures 1 to 3 The display device DD is configured to emit light. The display device DD can include a display panel PNL, a driving circuit portion DC, a pad PD, a circuit board CB, and a demultiplexer DUX. The display panel PNL can include a base layer BSL therein. The display device DD can include a display area DA and a non-display area NDA.

[0061] The base layer BSL can form a base surface of the display device DD. In the present application embodiments, the base layer BSL can be a bottom substrate for disposing layers forming the display device DD. The base layer BSL can be a rigid or flexible substrate or film. For example, the base layer BSL can include a glass material. In addition, the base layer BSL can include, for example, a silicon material. Furthermore, the base layer BSL can include, for example, polyimide. However, the present application is not limited to the above examples.

[0062] A plane defined in the present specification can extend in a first direction DR1 and a second direction DR2, and can be defined based on a plane on which the base layer BSL is disposed. In the present application embodiments, a third direction DR3 can correspond to a thickness direction of the base layer BSL. The third direction DR3 can correspond to a light output direction of the display device DD.

[0063] The display area DA can refer to an area in which the pixels PXL are disposed. The non-display area NDA can refer to an area in which the pixels PXL are not disposed. The non-display area NDA can be disposed around a periphery of the display area DA. The non-display area NDA can at least partially surround the display area DA. The lines electrically connected to the pixels PXL in the display area DA, the driving circuit portion DC, the pad PD, and / or the circuit board CB can be disposed in the non-display area NDA.

[0064] According to an embodiment of the present application, the pixels PXL (or the sub-pixels SPX) can be arranged in a stripe or PENTILE ® arrangement structure or the like, but the present application is not limited thereto.

[0065] According to an embodiment of the present application, each of the pixels PXL (or the sub-pixels SPX) can include a first sub-pixel SPX1, a second sub-pixel SPX2, and a third sub-pixel SPX3. Each of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 can be a sub-pixel. At least one first sub-pixel SPX1, at least one second sub-pixel SPX2, and at least one third sub-pixel SPX3 can form a pixel unit that can emit light of various colors.

[0066] Each of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 can emit monochromatic light.

[0067] For example, the first sub-pixel SPX1 can be a red pixel configured to emit light of a red color (e.g., a first color). The second sub-pixel SPX2 can be a green pixel configured to emit light of a green color (e.g., a second color), and the third sub-pixel SPX3 can be a blue pixel configured to emit light of a blue color (e.g., a third color). The red pixel can provide light having a wavelength band in a range of 600 nm to 750 nm. The green pixel can provide light having a wavelength band in a range of 480 nm to 560 nm. The blue pixel can provide light having a wavelength band in a range of 370 nm to 460 nm.

[0068] According to an embodiment of the present application, the number of the second sub-pixels SPX2 can be greater than the number of the first sub-pixels SPX1, or greater than the number of the third sub-pixels SPX3. The color, the arrangement order, the type, and / or the number of the first sub-pixels SPX1, the second sub-pixels SPX2, and the third sub-pixels SPX3 forming each pixel unit are not limited to a specific example.

[0069] The driving circuit section DC can be located in the non-display area NDA. For example, the driving circuit section DC can be located on one side of the display area DA (e.g., at the bottom). The driving circuit section DC can be located on one side of the demultiplexer DUX. The driving circuit section DC can be located between the demultiplexer DUX and the pad PD.

[0070] The driving circuit section DC can generate signals and voltages for driving the display panel PNL (e.g., pixels PXL). The driving circuit section DC may include integrated circuits and may be disposed on the display panel PNL (e.g., base layer BSL) in various ways.

[0071] The circuit board CB can be attached to a portion of the display panel PNL (e.g., the base layer BSL) within the non-display area NDA. The circuit board CB can be electrically connected to the display panel PNL and the drive circuitry DC.

[0072] The circuit board CB can provide image data, timing signals, drive voltages, etc., to the display panel PNL and the driving circuit DC section. For example, the circuit board CB may include a flexible printed circuit board, a chip-on-film device, or the like. However, the invention is not limited to the examples described above. In embodiments of the invention, the circuit board CB can be electrically connected to the pad PD via a conductive adhesive component such as an anisotropic conductive film.

[0073] The pad PD can be located in the non-display area NDA. The pad PD can be electrically connected to the drive circuit section DC. The pad PD can also be electrically connected to the circuit board CB. The pad PD can serve as an interface between the display panel PNL and the circuit board CB. Therefore, image data, timing signals, drive voltages, etc., provided from the circuit board CB can be supplied to the drive circuit section DC via the pad PD.

[0074] The demultiplexer DUX can be located in the non-display area NDA. The demultiplexer DUX can be located between the display area DA and the drive circuit section DC. The demultiplexer DUX can extend along one side of the display area DA to cover the side of the display area DA where the drive circuit section DC is located.

[0075] The demultiplexer (DUX) can be connected via data cable (DL) (see reference). Figure 4 The demultiplexer DUX is electrically connected to the sub-pixel SPX. The demultiplexer DUX can be connected via the data connection line DCL (see reference). Figure 5 ) and Data Baseline DBL (Reference) Figure 5 The demultiplexer DUX is electrically connected to the drive circuit section DC. In this embodiment of the invention, the demultiplexer DUX can select one of the data lines DL and transmit the data signal provided from the drive circuit section DC to the selected data line DL.

[0076] Figure 4 is a schematic diagram for describing a display device DD according to an embodiment of the present disclosure.

[0077] Referring to Figure 4 , the driving circuit portion DC can include a controller CON, a data driver DDV, a demultiplexer DUX, a gate driver GDV, and an emission control driver EDV. The display device DD can include a data base line DBL, data lines DL, gate lines GL, and emission control lines EL.

[0078] The controller CON can be configured to convert a control signal and image data provided from a circuit board CB (e.g., a processor) to match a specification of the display device DD, and to provide a required control signal, image data, etc. to the data driver DDV, the demultiplexer DUX, the gate driver GDV, and the emission control driver EDV.

[0079] Each of the sub-pixels SPX disposed in the display area DA can be electrically connected to a corresponding data line DL, a corresponding gate line GL, and a corresponding emission control line EL.

[0080] The sub-pixel SPX can receive a data voltage from the data line DL in response to a gate signal received from the gate line GL. The sub-pixel SPX can emit light with a luminance corresponding to the data voltage in response to an emission control signal received from the emission control line EL.

[0081] The data driver DDV can receive a control signal and image data from the controller CON, and generate a data voltage to be provided to the demultiplexer DUX through the data base line DBL. The data driver DDV can provide the data voltage to the demultiplexer DUX through the data base line DBL.

[0082] The demultiplexer DUX can apply the data voltage received through the data base line DBL to some of the data lines DL, and to other data lines DL at different points in time. The structural features of the demultiplexer DUX will be described later with reference to Figure 5 the subsequent drawings.

[0083] The gate driver GDV can receive a control signal from the controller CON and generate a gate signal to be provided to the gate line GL. In the present embodiment, the gate driver GDV can provide the gate signal through the gate line GL. Each gate signal can be provided in the form of a pulse. The number of pulses can be set to different values according to the embodiment. The gate driver GDV can be configured in the form of a shift register, and thus generate the gate signal in such a way that a gate start signal is sequentially transferred to a subsequent stage circuit under the control of a clock signal.

[0084] The emission control driver EDV can supply an emission control signal through an emission control line EL to determine an emission duration of the sub-pixel SPX. For example, the emission of each of the sub-pixels SPX can be controlled by determining whether a current flows through the corresponding light emitting element based on a voltage level of the emission control signal.

[0085] Figure 5 is a schematic plan view showing the display region DA and the non-display region NDA in which the drive circuit portion DC is provided, according to an embodiment of the present application.

[0086] Referring to Figure 5 , the display device DD can include a data connection line DCL and a bridge layer BR.

[0087] The drive circuit portion DC (e.g., the data driver DDV) can be electrically connected to the demultiplexer DUX through the data base line DBL, the bridge layer BR, and the data connection line DCL. The demultiplexer DUX can be electrically connected to the sub-pixels SPX in the display region DA through the data lines DL.

[0088] Each of the data base lines DBL can be connected to a portion of the corresponding bridge layer BR and electrically connected to the corresponding data connection lines DCL which are branched from each other through the bridge layer BR. The branched data connection lines DCL can be connected to the respective corresponding data lines DL through the first demultiplexing transistor TD1 and the second demultiplexing transistor TD2 (refer to Figure 6 ) of the demultiplexer DUX. Accordingly, a data signal provided to a single data base line DBL can be selectively provided to two or more data lines DL.

[0089] Figure 6 is a schematic plan view showing the first demultiplexing transistor TD1 and the second demultiplexing transistor TD2 of the demultiplexer DUX and a region in which lines electrically connected to the first demultiplexing transistor TD1 and the second demultiplexing transistor TD2 are provided, according to an embodiment of the present application.

[0090] Referring to Figure 6 , an electrical connection structure connected to the first demultiplexing transistor TD1 and the second demultiplexing transistor TD2 of the demultiplexer DUX is shown. The display device DD can include a first selection control line CLO and a second selection control line CLE.

[0091] In the present embodiment, the demultiplexer DUX can include two types of demultiplexing transistors. However, the type and the number of the demultiplexing transistors used to form the demultiplexer DUX are not limited to the specific examples.

[0092] In an embodiment of the present invention, the demultiplexer DUX can include first demultiplexing transistors TD1 and second demultiplexing transistors TD2, wherein each of the first demultiplexing transistors TD1 includes a first gate electrode electrically connected to the first selection control line CLO, and each of the second demultiplexing transistors TD2 includes a second gate electrode electrically connected to the second selection control line CLE.

[0093] The pixel PXL can include a first pixel PXL1 and a second pixel PXL2 adjacent to each other, and each of the first pixel PXL1 and the second pixel PXL2 includes first to third sub-pixels SPX1 to SPX3. For example, the first pixel PXL1 and the second pixel PXL2 can be adjacent to each other in a row direction (e.g., a first direction DR1).

[0094] In an embodiment of the present invention, the first pixel PXL1 can be electrically connected to the first demultiplexing transistor TD1, and the second pixel PXL2 can be electrically connected to the second demultiplexing transistor TD2.

[0095] The data line DL can include a first data line DL1, a second data line DL2, and a third data line DL3.

[0096] The data line DL can be electrically connected to the first demultiplexing transistor TD1 and the second demultiplexing transistor TD2.

[0097] The first data line DL1 can include a 1-1 data line DL1-1 and a 1-2 data line DL1-2. The 1-1 data line DL1-1 can be electrically connected to the corresponding first demultiplexing transistor TD1. The 1-2 data line DL1-2 can be electrically connected to the corresponding second demultiplexing transistor TD2.

[0098] The second data line DL2 can include a 2-1 data line DL2-1 and a 2-2 data line DL2-2. The 2-1 data line DL2-1 can be electrically connected to the corresponding first demultiplexing transistor TD1. The 2-2 data line DL2-2 can be electrically connected to the corresponding second demultiplexing transistor TD2.

[0099] The third data line DL3 can include a 3-1 data line DL3-1 and a 3-2 data line DL3-2. The 3-1 data line DL3-1 can be electrically connected to the corresponding first demultiplexing transistor TD1. The 3-2 data line DL3-2 can be electrically connected to the corresponding second demultiplexing transistor TD2.

[0100] The data connection line DCL can include a first data connection line DCL1, a second data connection line DCL2, and a third data connection line DCL3.

[0101] The data connection line DCL can be electrically connected to the first demultiplexing transistor TD1 and the second demultiplexing transistor TD2.

[0102] The first data connection line DCL1 can include a 1-1 data connection line DCL1-1 and a 1-2 data connection line DCL1-2. The 1-1 data connection line DCL1-1 can be electrically connected to the corresponding first demultiplexing transistor TD1. The 1-2 data connection line DCL1-2 can be electrically connected to the corresponding second demultiplexing transistor TD2.

[0103] The second data connection line DCL2 can include a 2-1 data connection line DCL2-1 and a 2-2 data connection line DCL2-2. The 2-1 data connection line DCL2-1 can be electrically connected to the corresponding first demultiplexing transistor TD1. The 2-2 data connection line DCL2-2 can be electrically connected to the corresponding second demultiplexing transistor TD2.

[0104] The third data connection line DCL3 can include a 3-1 data connection line DCL3-1 and a 3-2 data connection line DCL3-2. The 3-1 data connection line DCL3-1 can be electrically connected to the corresponding first demultiplexing transistor TD1. The 3-2 data connection line DCL3-2 can be electrically connected to the corresponding second demultiplexing transistor TD2.

[0105] The 1-1 data line DL1-1 can be electrically connected to the first sub-pixel SPX1 of the first pixel PXL1. The 1-2 data line DL1-2 can be electrically connected to the first sub-pixel SPX1 of the second pixel PXL2.

[0106] The 2-1 data line DL2-1 can be electrically connected to the second sub-pixel SPX2 of the first pixel PXL1. The 2-2 data line DL2-2 can be electrically connected to the second sub-pixel SPX2 of the second pixel PXL2.

[0107] The 3-1 data line DL3-1 can be electrically connected to the third sub-pixel SPX3 of the first pixel PXL1. The 3-2 data line DL3-2 can be electrically connected to the third sub-pixel SPX3 of the second pixel PXL2.

[0108] A first electrode of one of the first demultiplexing transistors TD1 (e.g., the first-first demultiplexing transistor TD1) can be electrically connected to the 1-1 data connection line DCL1-1, and a second electrode of the first demultiplexing transistor TD1 (e.g., the first-first demultiplexing transistor TD1) can be electrically connected to the 1-1 data line DL1-1.

[0109] The first electrode of another one (e.g., the second-first demultiplexing transistor TD1) of the first demultiplexing transistors TD1 can be electrically connected to the 2-1 data connection line DCL2-1, and the second electrode of the first demultiplexing transistor TD1 (e.g., the second-first demultiplexing transistor TD1) can be electrically connected to the 2-1 data line DL2-1.

[0110] The first electrode of the remaining one (e.g., the third-first demultiplexing transistor TD1) of the first demultiplexing transistors TD1 can be electrically connected to the 3-1 data connection line DCL3-1, and the second electrode of the first demultiplexing transistor TD1 (e.g., the third-first demultiplexing transistor TD1) can be electrically connected to the 3-1 data line DL3-1.

[0111] The first electrode of one (e.g., the first-second demultiplexing transistor TD2) of the second demultiplexing transistors TD2 can be electrically connected to the 1-2 data connection line DCL1-2, and the second electrode of the second demultiplexing transistor TD2 (e.g., the first-second demultiplexing transistor TD2) can be electrically connected to the 1-2 data line DL1-2.

[0112] The first electrode of another one (e.g., the second-second demultiplexing transistor TD2) of the second demultiplexing transistors TD2 can be electrically connected to the 2-2 data connection line DCL2-2, and the second electrode of the second demultiplexing transistor TD2 (e.g., the second-second demultiplexing transistor TD2) can be electrically connected to the 2-2 data line DL2-2.

[0113] The first electrode of the remaining one (e.g., the third-second demultiplexing transistor TD2) of the second demultiplexing transistors TD2 can be electrically connected to the 3-2 data connection line DCL3-2, and the second electrode of the second demultiplexing transistor TD2 (e.g., the third-second demultiplexing transistor TD2) can be electrically connected to the 3-2 data line DL3-2.

[0114] Each of the data base lines DBL can be electrically connected to a corresponding data connection line DCL through a corresponding bridge layer BR.

[0115] The data base lines DBL can include a first data base line DBL1, a second data base line DBL2, and a third data base line DBL3. The bridge layers BR can include a first bridge layer BR1, a second bridge layer BR2, and a third bridge layer BR3.

[0116] The first data base line DBL1 can extend in the second direction DR2 and can be electrically connected to the 1-1st data connection line DCL1-1 and the 1-2nd data connection line DCL1-2 through the first bridge layer BR1. For example, the first bridge layer BR1 can extend in the first direction DR1 and the 1-1st data connection line DCL1-1 and the 1-2nd data connection line DCL1-2 can extend in the second direction DR2. The 1-1st data connection line DCL1-1 and the 1-2nd data connection line DCL1-2 can be electrically connected to the first bridge layer BR1 at respective specific positions.

[0117] The second data base line DBL2 can extend in the second direction DR2 and can be electrically connected to the 2-1st data connection line DCL2-1 and the 2-2nd data connection line DCL2-2 through the second bridge layer BR2. For example, the second bridge layer BR2 can extend in the first direction DR1 and the 2-1st data connection line DCL2-1 and the 2-2nd data connection line DCL2-2 can extend in the second direction DR2. The 2-1st data connection line DCL2-1 and the 2-2nd data connection line DCL2-2 can be electrically connected to the second bridge layer BR2 at respective specific positions.

[0118] The third data base line DBL3 can extend in the second direction DR2 and can be electrically connected to the 3-1st data connection line DCL3-1 and the 3-2nd data connection line DCL3-2 through the third bridge layer BR3. For example, the third bridge layer BR3 can extend in the first direction DR1 and the 3-1st data connection line DCL3-1 and the 3-2nd data connection line DCL3-2 can extend in the second direction DR2. The 3-1st data connection line DCL3-1 and the 3-2nd data connection line DCL3-2 can be electrically connected to the third bridge layer BR3 at respective specific positions.

[0119] Accordingly, a data voltage provided through any one of the data base lines DBL can be provided to any one of the sub-pixels SPX of the first pixel PXL1 through the corresponding first demultiplexing transistor TD1 or can be provided to any one of the sub-pixels SPX of the second pixel PXL2 through the corresponding second demultiplexing transistor TD2.

[0120] The first selection control line CLO can extend in the first direction DR1 and can be electrically connected to the first demultiplexing transistors TD1 at a plurality of nodes, respectively.

[0121] The first selection control line CLO can provide a first selection control signal to the first gate electrode of each of the first demultiplexing transistors TD1. In the case where the first selection control signal is provided to the first gate electrode of the first demultiplexing transistor TD1, the first demultiplexing transistor TD1 can be turned on, while the second demultiplexing transistor TD2 can remain in an off state. Thus, a data signal provided through any one of the data base lines DBL can be provided to a corresponding one of the sub-pixels SPX of the first pixel PXL1 through the corresponding first demultiplexing transistor TD1 and the corresponding data line DL in response to the first selection control signal.

[0122] The second selection control line CLE can extend in the first direction DR1 and can be electrically connected to the second demultiplexing transistors TD2 at a plurality of nodes, respectively.

[0123] The second selection control line CLE can provide a second selection control signal to the second gate electrode of each of the second demultiplexing transistors TD2. In the case where the second selection control signal is provided to the second gate electrode of the second demultiplexing transistor TD2, the second demultiplexing transistor TD2 can be turned on, while the first demultiplexing transistor TD1 can remain in an off state. Thus, a data signal provided through any one of the data base lines DBL can be provided to a corresponding one of the sub-pixels SPX of the second pixel PXL2 through the corresponding second demultiplexing transistor TD2 and the corresponding data line DL in response to the second selection control signal.

[0124] In an embodiment of the present application, the first demultiplexing transistor TD1 can be turned on, and the second demultiplexing transistor TD2 can be turned off. In this case, a data signal provided to the first data base line DBL1 can be provided to the first sub-pixel SPX1 of the first pixel PXL1 through the first bridge layer BR1, the first-1 data connection line DCL1-1, the corresponding first demultiplexing transistor TD1, and the first-1 data line DL1-1.

[0125] In an embodiment of the present application, the first demultiplexing transistor TD1 can be turned off, and the second demultiplexing transistor TD2 can be turned on. In this case, a data signal provided to the first data base line DBL1 can be provided to the first sub-pixel SPX1 of the second pixel PXL2 through the first bridge layer BR1, the first-2 data connection line DCL1-2, the corresponding second demultiplexing transistor TD2, and the first-2 data line DL1-2.

[0126] In the embodiment of the present application, the first demultiplexing transistor TD1 can be turned on, and the second demultiplexing transistor TD2 can be turned off. In this case, the data signal provided to the second data base line DBL2 can be provided to the second sub-pixel SPX2 of the first pixel PXL1 through the second bridge layer BR2, the 2-1 data connection line DCL2-1, the corresponding first demultiplexing transistor TD1, and the 2-1 data line DL2-1.

[0127] In the embodiment of the present application, the first demultiplexing transistor TD1 can be turned off, and the second demultiplexing transistor TD2 can be turned on. In this case, the data signal provided to the second data base line DBL2 can be provided to the second sub-pixel SPX2 of the second pixel PXL2 through the second bridge layer BR2, the 2-2 data connection line DCL2-2, the corresponding second demultiplexing transistor TD2, and the 2-2 data line DL2-2.

[0128] In the embodiment of the present application, the first demultiplexing transistor TD1 can be turned on, and the second demultiplexing transistor TD2 can be turned off. In this case, the data signal provided to the third data base line DBL3 can be provided to the third sub-pixel SPX3 of the first pixel PXL1 through the third bridge layer BR3, the 3-1 data connection line DCL3-1, the corresponding first demultiplexing transistor TD1, and the 3-1 data line DL3-1.

[0129] In the embodiment of the present application, the first demultiplexing transistor TD1 can be turned off, and the second demultiplexing transistor TD2 can be turned on. In this case, the data signal provided to the third data base line DBL3 can be provided to the third sub-pixel SPX3 of the second pixel PXL2 through the third bridge layer BR3, the 3-2 data connection line DCL3-2, the corresponding second demultiplexing transistor TD2, and the 3-2 data line DL3-2.

[0130] According to the embodiment of the present application, the operation of the sub-pixel SPX can be controlled by the demultiplexer DUX, thereby improving the integration degree of the circuit and the degree of freedom of design, and improving the transmission speed of the data signal.

[0131] In the embodiment of the present application, the bridge layer BR can extend in the first direction DR1, and can include a plurality of bridge layers BR. At least part of the data base line DBL can extend in the second direction DR2, and can include a plurality of data base lines DBL. In this case, at least some parts of the data base line DBL can intersect with the bridge layer BR in a plan view.

[0132] Hereinafter, a plan view and a cross-sectional view of the display device DD will be described in more detail with reference to the accompanying drawings. Figures 7 to 15 The plan view and the cross-sectional view of the display device DD will be described in more detail.

[0133] Figure 7 is a schematic cross-sectional view illustrating a display device DD according to an embodiment of the present application.

[0134] Referring to Figure 7 , the display device DD (or display panel PNL) can include a circuit layer CIL and a light emitting element layer LEL.

[0135] The circuit layer CIL can include a base layer BSL. The circuit layer CIL can include a layer including a pixel circuit. The circuit layer CIL can be a layer including a circuit (e.g., a first demultiplexing transistor TD1 and a second demultiplexing transistor TD2) for forming a demultiplexer DUX.

[0136] The light emitting element layer LEL can be disposed on the circuit layer CIL. The light emitting element layer LEL can include a light emitting element LD for forming a pixel PXL. The light emitting element LD can include an organic light emitting diode or a light emitting diode including an inorganic material. However, the present application is not limited to the above-described examples.

[0137] Referring to Figure 8 , a stack structure confined in the circuit layer CIL will be described. Figure 8 is a schematic cross-sectional view illustrating a circuit layer CIL according to an embodiment of the present application. In Figure 8 the drawings hereafter, layers (e.g., layers patterned by the same process) that are the same as the layers described with reference to Figure 8 may be denoted by the same hatching.

[0138] Referring to Figure 8 , the circuit layer CIL can include a conductive layer, an insulating layer, and the like disposed on the base layer BSL. For example, the circuit layer CIL can have a structure formed by stacking the base layer BSL, the buffer layer BFL, the active layer ACT, the gate insulating layer GI, the lower interlayer conductive layer LICL, the first interlayer insulating layer ILD1, the first interlayer conductive layer ICL1, the second interlayer insulating layer ILD2, the second interlayer conductive layer ICL2, the third interlayer insulating layer ILD3, the first transistor conductive layer SD1, the first via layer VIA1, the second transistor conductive layer SD2, and the second via layer VIA2, each of which has at least a portion patterned. The stack structure can form a pixel circuit as well as the first demultiplexing transistor TD1 and the second demultiplexing transistor TD2.

[0139] The buffer layer BFL can be disposed on the base layer BSL. The buffer layer BFL can prevent impurities or water from penetrating into the active layer ACT.

[0140] The active layer ACT can be provided on the buffer layer BFL. The active layer ACT can include a semiconductor. For example, the active layer ACT can include at least one of polysilicon, low temperature polysilicon (LTPS), amorphous silicon, and oxide semiconductor.

[0141] The lower interlayer conductive layer LICL, the first interlayer conductive layer ICL1, the second interlayer conductive layer ICL2, the first transistor conductive layer SD1, and the second transistor conductive layer SD2 can include a conductive material, and each can have a single layer or a multi-layer structure. In the present embodiment, the first transistor conductive layer SD1 can be a layer in which a source / drain electrode layer of a transistor included in the circuit layer CIL is formed.

[0142] The gate insulating layer GI, the first interlayer insulating layer ILD1, the second interlayer insulating layer ILD2, the third interlayer insulating layer ILD3, the first via layer VIA1, and the second via layer VIA2 can be provided between the conductive layers (e.g., the lower interlayer conductive layer LICL, the first interlayer conductive layer ICL1, the second interlayer conductive layer ICL2, the first transistor conductive layer SD1, and the second transistor conductive layer SD2) included in the circuit layer CIL, and can include various insulating materials such as inorganic materials and / or organic materials. At least some of the conductive layers can be electrically connected to each other by a contact member CNP (see Figure 9 ) that penetrates at least one insulating layer.

[0143] A display device DD including a demultiplexer DUX and lines electrically connected thereto in an embodiment of the present application will be described with reference to Figures 9 to 15

[0144] Figure 9 is a schematic plan view showing a region between the demultiplexer DUX and the drive circuit portion DC according to the embodiment of the present application. Figure 10 is a schematic cross-sectional view taken along line A- Figure 9 in . Figure 11 is a schematic cross-sectional view taken along line B- Figure 9 in . Figure 12 is a schematic cross-sectional view taken along line C- Figure 9 in . Figure 13 is a schematic cross-sectional view taken along line D- Figure 9 in . Figure 14 and Figure 15 are schematic views for describing a process risk that can occur during an etching process for a conductive layer.

[0145] A display device DD including a demultiplexer DUX and lines electrically connected thereto in an embodiment of the present application will be described with reference to Figures 9 to 13 ​The first interlayer conductive layer ICL1, the second interlayer conductive layer ICL2, and the first transistor conductive layer SD1 can each be patterned to form lines electrically connected to the demultiplexer DUX.

[0146] In embodiments of the application, the first-1 data connection line DCL1-1, the second-1 data connection line DCL2-1, the third-1 data connection line DCL3-1, the first-2 data connection line DCL1-2, the second-2 data connection line DCL2-2, and the third-2 data connection line DCL3-2 can be sequentially arranged in the first direction DR1.

[0147] The first-1 data connection line DCL1-1 and the first-2 data connection line DCL1-2 can be formed by patterning the first interlayer conductive layer ICL1, and can each extend in the second direction DR2.

[0148] The first-1 data connection line DCL1-1 can be electrically connected to the first portion of the first bridge layer BR1 by a contact member CNP that passes through the second interlayer insulating layer ILD2 and the third interlayer insulating layer ILD3.

[0149] The first-2 data connection line DCL1-2 can be electrically connected to the second portion of the first bridge layer BR1 by a contact member CNP that passes through the second interlayer insulating layer ILD2 and the third interlayer insulating layer ILD3.

[0150] The first bridge layer BR1 can be formed from the first transistor conductive layer SD1, and can extend in the first direction DR1. As the first bridge layer BR1 extends in the first direction DR1, in a plan view, the first bridge layer BR1 can overlap the second-1 data connection line DCL2-1 and the third-1 data connection line DCL3-1. The first bridge layer BR1 can electrically connect the first-1 data connection line DCL1-1 and the first-2 data connection line DCL1-2, which are spaced apart from each other in the first direction DR1, to each other.

[0151] The second-1 data connection line DCL2-1 and the second-2 data connection line DCL2-2 can be formed by patterning the first interlayer conductive layer ICL1, and can each extend in the second direction DR2.

[0152] The second-1 data connection line DCL2-1 can be electrically connected to the first portion of the second bridge layer BR2 by a contact member CNP that passes through the second interlayer insulating layer ILD2 and the third interlayer insulating layer ILD3.

[0153] The second-2 data connection line DCL2-2 can be electrically connected to the second portion of the second bridge layer BR2 by a contact member CNP that passes through the second interlayer insulating layer ILD2 and the third interlayer insulating layer ILD3.

[0154] The second bridge layer BR2 can be formed of the first transistor conductive layer SD1 and can extend in the first direction DR1. Since the second bridge layer BR2 extends in the first direction DR1, in a plan view, the second bridge layer BR2 can overlap the 3-1 data connection line DCL3-1 and the intermediate bridge pattern layer IBP. The second bridge layer BR2 can electrically connect the 2-1 data connection line DCL2-1 and the 2-2 data connection line DCL2-2, which are spaced apart from each other in the first direction DR1, to each other. The second bridge layer BR2 can be disposed between the first bridge layer BR1 and the first data base line DBL1.

[0155] The 3-1 data connection line DCL3-1 and the 3-2 data connection line DCL3-2 can be formed by patterning the first interlayer conductive layer ICL1 and can each extend in the second direction DR2.

[0156] The 3-1 data connection line DCL3-1 can be electrically connected to the first portion of the third bridge layer BR3 through the contact member CNP that passes through the second interlayer insulating layer ILD2 and the third interlayer insulating layer ILD3.

[0157] The 3-2 data connection line DCL3-2 can be electrically connected to the second portion of the third bridge layer BR3 through the contact member CNP that passes through the second interlayer insulating layer ILD2 and the third interlayer insulating layer ILD3.

[0158] The third bridge layer BR3 can be formed of the first transistor conductive layer SD1 and can extend in the first direction DR1. Since the third bridge layer BR3 extends in the first direction DR1, in a plan view, the third bridge layer BR3 can overlap the intermediate bridge pattern layer IBP. The third bridge layer BR3 can electrically connect the 3-1 data connection line DCL3-1 and the 3-2 data connection line DCL3-2, which are spaced apart from each other in the first direction DR1, to each other. In a plan view, the third bridge layer BR3 can be disposed between the first bridge layer BR1 and the first data base line DBL1. Also, in a plan view, the third bridge layer BR3 can be disposed between the second bridge layer BR2 and the first data base line DBL1.

[0159] The first bridge layer BR1 can be more adjacent to the display area DA than the second bridge layer BR2 and the third bridge layer BR3. The second bridge layer BR2 can be more adjacent to the display area DA than the third bridge layer BR3. For example, in a plan view, the second bridge layer BR2 can be disposed between the first bridge layer BR1 and the third bridge layer BR3.

[0160] The first data connection line DCL1 can extend to the first bridge layer BR1 in the second direction DR2. The second data connection line DCL2 can extend to the second bridge layer BR2 in the second direction DR2. The third data connection line DCL3 can extend to the third bridge layer BR3 in the second direction DR2.

[0161] The second data connection line DCL2 can extend longer than the first data connection line DCL1. Accordingly, at least a portion of the second data connection line DCL2 can overlap the first bridge layer BR1 in a plan view. Also, for example, at least a portion of the second data connection line DCL2 can overlap the first bridge layer BR1 perpendicularly.

[0162] The third data connection line DCL3 can extend longer than each of the first data connection line DCL1 and the second data connection line DCL2. Accordingly, at least a portion of the third data connection line DCL3 can overlap each of the first bridge layer BR1 and the second bridge layer BR2 in a plan view. Also, for example, at least a portion of the third data connection line DCL3 can overlap each of the first bridge layer BR1 and the second bridge layer BR2 perpendicularly.

[0163] In an embodiment of the present disclosure, the display device DD can include an intermediate bridge pattern layer IBP electrically connecting the first bridge layer BR1 and the first data base line DBL1 to each other. The display device DD can further include a bridge pattern layer BRP.

[0164] A first portion of the intermediate bridge pattern layer IBP can be electrically connected to the first bridge layer BR1 through a contact member CNP passing through the third interlayer insulating layer ILD3.

[0165] A second portion of the intermediate bridge pattern layer IBP can be electrically connected to the bridge pattern layer BRP through a contact member CNP passing through the third interlayer insulating layer ILD3.

[0166] The intermediate bridge pattern layer IBP can be formed of a second interlayer conductive layer ICL2. The intermediate bridge pattern layer IBP can overlap each of the second bridge layer BR2 and the third bridge layer BR3 in a plan view. For example, the intermediate bridge pattern layer IBP can overlap each of the second bridge layer BR2 and the third bridge layer BR3 perpendicularly.

[0167] The intermediate bridge pattern layer IBP can extend between the first bridge layer BR1 and the first data base line DBL1 in the second direction DR2. At least a portion of the intermediate bridge pattern layer IBP can have a relatively expanded shape. For example, the intermediate bridge pattern layer IBP can have a polygonal shape or a rounded shape.

[0168] For example, at least a portion of the intermediate bridge pattern layer IBP can extend in the first direction DR1, and at least another portion of the intermediate bridge pattern layer IBP can extend in the second direction DR2. The intermediate bridge pattern layer IBP can form a certain surface area.

[0169] The intermediate bridge pattern layer IBP can be disposed across the second bridge layer BR2 and the third bridge layer BR3. Further, the intermediate bridge pattern layer IBP can overlap at least a portion of the second bridge layer BR2 in a longitudinal direction of the second bridge layer BR2. The intermediate bridge pattern layer IBP can overlap at least a portion of the third bridge layer BR3 in a longitudinal direction of the third bridge layer BR3.

[0170] A width of the intermediate bridge pattern layer IBP can be greater than a width of the first data base line DBL1. A width of the intermediate bridge pattern layer IBP can be greater than a width of each of the second data base line DBL2 and the third data base line DBL3.

[0171] For example, the intermediate bridge pattern layer IBP can have a first width W1 in the first direction DR1. The first data base line DBL1 can have a second width W2 in the first direction DR1. The first width W1 can be greater than the second width W2.

[0172] In a plan view, the intermediate bridge pattern layer IBP can substantially overlap a large area of each of the second bridge layer BR2 and the third bridge layer BR3.

[0173] The intermediate bridge pattern layer IBP can be formed of the second interlayer conductive layer ICL2. The second bridge layer BR2 and the third bridge layer BR3, which can be formed of the first transistor conductive layer SD1, can be disposed on the intermediate bridge pattern layer IBP. For example, the second bridge layer BR2 and the third bridge layer BR3 can be disposed above the intermediate bridge pattern layer IBP.

[0174] In the present embodiment, the intermediate bridge pattern layer IBP can have a shape extending in a planar direction to cover a relatively large area, and can reduce a risk that can occur in a line structure due to an overlap between the second interlayer conductive layer ICL2 and the first transistor conductive layer SD1 in a plan view. Reference will be made to Figure 14 and Figure 15 Further related descriptions are provided.

[0175] In Figure 14 and Figure 15 In the first phase PHASE1, after the second interlayer conductive layer ICL2 is patterned on the second interlayer insulating layer ILD2, a third interlayer insulating layer ILD3 covering the second interlayer conductive layer ICL2 is formed, and a process step for forming a base conductive portion SD_B of the first transistor conductive layer SD1 is formed. In the second phase PHASE2, the first transistor conductive layer SD1 is formed on the base conductive portion SD_B.Figure 14 and Figure 15 In the second phase PHASE2, the second phase PHASE2 refers to a process step subsequent to the first phase PHASE1, and represents a process step subsequent to etching the base conductive portion SD_B.

[0176] The second interlayer conductive layer ICL2 can have a relatively large thickness. For example, the thickness of the second interlayer conductive layer ICL2 can be greater than each of the thickness of the lower interlayer conductive layer LICL and the thickness of the first interlayer conductive layer ICL1. For example, the thickness of the second interlayer conductive layer ICL2 can be in a range of 3600A to 4200A. For example, the thickness of the first interlayer conductive layer ICL1 can be in a range of 2800A to 3200A. For example, the thickness of the lower interlayer conductive layer LICL can be in a range of 2800A to 3200A.

[0177] In this case, the second interlayer conductive layer ICL2 can be disposed on the second interlayer insulating layer ILD2, thereby forming a step difference at one end thereof.

[0178] The side surface S of the second interlayer conductive layer ICL2 can form an interface angle ANG with respect to a plane on which the base layer BSL is disposed (or a surface on which the second interlayer insulating layer ILD2 is disposed).

[0179] Referring to Figure 14 In a case where the side surface S of the second interlayer conductive layer ICL2 can form a relatively large slope such that the interface angle ANG is formed with a relatively large value, after the etching process of the base conductive portion SD_B is performed, at least a portion of the base conductive portion SD_B can remain unetched in a region adjacent to the side surface S, thereby causing a residual conductive portion SD_E.

[0180] Referring to Figure 15 In a case where the side surface S of the second interlayer conductive layer ICL2 can form a relatively gentle slope such that the interface angle ANG is formed with a relatively small value, the risk that at least a portion of the base conductive portion SD_B remains unetched in a region adjacent to the side surface S after the etching process of the base conductive portion SD_B is performed can be reduced, and thus the risk that the residual conductive portion SD_E remains can also be reduced.

[0181] Experimentally, in a case where the side surface S of the second interlayer conductive layer ICL2 has a relatively steep taper, leading to formation of a residual conductive portion SD_E adjacent to the second interlayer conductive layer ICL2, there can be a risk of short-circuiting between conductive structures formed by the first transistor conductive layer SD1 patterned on the third interlayer insulating layer ILD3. For example, in a case where a residual conductive portion SD_E or the like is formed around the second bridge layer BR2 and the third bridge layer BR3 formed by the first transistor conductive layer SD1, there can be a risk of short-circuiting between the second bridge layer BR2 and the third bridge layer BR3. If a short-circuiting problem occurs between the second bridge layer BR2 and the third bridge layer BR3 to which different data signals are supplied, the data signals can be distorted, which can lead to a decrease in display quality.

[0182] In contrast, when a relatively gentle taper is formed in the side surface S of the second interlayer conductive layer ICL2, the risk of short-circuiting between conductive structures formed by the first transistor conductive layer SD1 patterned on the third interlayer insulating layer ILD3 or the like can be reduced. For example, in the embodiment of the present application, the risk of forming a residual conductive portion SD_E or the like around the second bridge layer BR2 and the third bridge layer BR3 formed by the first transistor conductive layer SD1 can be reduced. As a result, the risk of short-circuiting between the second bridge layer BR2 and the third bridge layer BR3 can also be reduced. Furthermore, with the reduction in the risk of short-circuiting, the defect rate in the manufacture of the display device DD can be reduced, thereby improving the process yield.

[0183] Referring again to Figures 9 to 13 , the intermediate bridge pattern layer IBP can be patterned to have a relatively large width, and the side surface S of the intermediate bridge pattern layer IBP can have a gentle slope.

[0184] For example, the interface angle ANG formed by the side surface S of the intermediate bridge pattern layer IBP can be 70° or less. The interface angle ANG can be with respect to the direction of the side surface S and the plane of the underlying layer BSL on which the intermediate bridge pattern layer IBP is disposed. The interface angle ANG can be with respect to the side surface S and the base on which the intermediate bridge pattern layer IBP is disposed. For example, the interface angle ANG formed by the side surface S of the intermediate bridge pattern layer IBP can be in the range of 30° to 70°. Furthermore, in order for the interface angle ANG to have the above-mentioned numerical range, the first width W1 of the intermediate bridge pattern layer IBP can be 6 μm or more. In the embodiment of the present application, the first width W1 of the intermediate bridge pattern layer IBP can be in the range of 6 μm to 15 μm. According to the embodiment of the present application, in a case where the intermediate bridge pattern layer IBP is 6 μm or more, the side interface angle of the photoresist layer for forming the intermediate bridge pattern layer IBP can be formed relatively gently, thereby reducing the interface angle ANG of the side surface S of the intermediate bridge pattern layer IBP.

[0185] For example, the thickness of the intermediate bridge pattern layer IBP can be in the range of 3600A to 4200A. For example, the intermediate bridge pattern layer IBP can include a first conductive layer CL1 including titanium (Ti) and a second conductive layer CL2 disposed on the first conductive layer CL1 and including aluminum (Al). For example, the thickness of the first conductive layer CL1 can be in the range of 200A to 400A, and the thickness of the second conductive layer CL2 can be in the range of 3200A to 3800A. In the present embodiment, the thickness of the first conductive layer CL1 can be about 300A, and the thickness of the second conductive layer CL2 can be about 3500A.

[0186] In the case where the first width W1 of the intermediate bridge pattern layer IBP and the interface angle ANG satisfy the above numerical ranges, as described above (i.e., similarly to Figure 15 the second phase PHASE2), an undesirable residual conductive portion SD_E can not be formed around the second interlayer conductive layer ICL2 of which the intermediate bridge pattern layer IBP is formed. Accordingly, the risk of data signal distortion that can cause a decrease in display quality can be reduced, thereby enabling a display device DD having improved display quality to be provided. In addition, since a line can be formed in a relatively small area, the resolution characteristics of the sub-pixel SPX can be improved, thereby resulting in a display device DD having high resolution characteristics.

[0187] The bridge pattern layer BRP can be electrically connected to the intermediate bridge pattern layer IBP through a contact member CNP that passes through the third interlayer insulating layer ILD3. The bridge pattern layer BRP can be disposed in a different layer from the intermediate bridge pattern layer IBP and the first data base line DBL1. The bridge pattern layer BRP can be electrically connected to the first data base line DBL1 through a contact member CNP that passes through the third interlayer insulating layer ILD3. Accordingly, the first data base line DBL1 can be electrically connected to the 1-1 data connection line DCL1-1 and the 1-2 data connection line DCL1-2 through the bridge pattern layer BRP, the intermediate bridge pattern layer IBP, and the first bridge layer BR1.

[0188] The second bridge layer BR2 can be electrically connected to the second data base line DBL2 through a contact member CNP that passes through the third interlayer insulating layer ILD3. Accordingly, the second data base line DBL2 can be electrically connected to the 2-1 data connection line DCL2-1 and the 2-2 data connection line DCL2-2 through the second bridge layer BR2.

[0189] The third bridge layer BR3 can be electrically connected to the third data base line DBL3 through the contact member CNP passing through the third interlayer insulation layer ILD3. Accordingly, the third data base line DBL3 can be electrically connected to the 3-1 data connection line DCL3-1 and the 3-2 data connection line DCL3-2 through the third bridge layer BR3.

[0190] A display device DD according to an embodiment of the present application will be described with reference to the accompanying drawings. Figure 16 A display device DD according to an embodiment of the present application will be described with reference to the accompanying drawings.

[0191] Figure 16 FIG. 7 is a schematic plan view showing a region between a demultiplexer DUX and a driving circuit portion DC according to an embodiment of the present application.

[0192] The display device DD according to the present embodiment differs from the display device DD according to the above-described embodiment in that the intermediate bridge pattern layer IBP includes a first intermediate bridge pattern layer IBP1 and a second intermediate bridge pattern layer IBP2 spaced apart from each other.

[0193] The first intermediate bridge pattern layer IBP1 and the second intermediate bridge pattern layer IBP2 can be spaced apart from each other in the second direction DR2 and can be disposed to correspond to the second bridge layer BR2 and the third bridge layer BR3, respectively.

[0194] The first intermediate bridge pattern layer IBP1 can overlap the second bridge layer BR2 in a plan view. Also, for example, the first intermediate bridge pattern layer IBP1 can overlap the second bridge layer BR2 perpendicularly. The first intermediate bridge pattern layer IBP1 can be disposed between the first bridge layer BR1 and the third bridge layer BR3. The first intermediate bridge pattern layer IBP1 can be disposed between the 3-1 data connection line DCL3-1 and the 2-2 data connection line DCL2-2.

[0195] The second intermediate bridge pattern layer IBP2 can overlap the third bridge layer BR3 in a plan view. Also, for example, the second intermediate bridge pattern layer IBP2 can overlap the third bridge layer BR3 perpendicularly. The second intermediate bridge pattern layer IBP2 can be disposed between the second bridge layer BR2 and the bridge pattern layer BRP. The second intermediate bridge pattern layer IBP2 can be disposed between the 3-1 data connection line DCL3-1 and the 3-2 data connection line DCL3-2.

[0196] In the present embodiment, the first intermediate bridge pattern layer IBP1 and the second intermediate bridge pattern layer IBP2 can each have a relatively large first width W1. Thus, as described above, the risk of forming an undesirable residual conductive portion SD_E or the like around the first intermediate bridge pattern layer IBP1 and the second intermediate bridge pattern layer IBP2 can be reduced, and the risk of a decrease in display quality can be reduced.

[0197] Reference will be made to Figure 17 A display device DD including a demultiplexer DUX and a line electrically connected thereto according to an embodiment of the present application will be described.

[0198] Figure 17 is a schematic plan view showing a region between the demultiplexer DUX and the drive circuit portion DC according to an embodiment of the present application.

[0199] The display device DD according to the present embodiment differs from the display device DD according to the above-described embodiment in that the intermediate bridge pattern layer IBP includes a protrusion PRU that protrudes in a certain direction (e.g., the first direction DR1).

[0200] The protrusion PRU can protrude from one or more side surfaces of the intermediate bridge pattern layer IBP. The protrusion PRU can include a first protrusion formed at a first side of the intermediate bridge pattern layer IBP and a second protrusion formed at a second side of the intermediate bridge pattern layer IBP. The protrusion PRU can include a plurality of protrusions, and the number of protrusions PRU is not limited to a certain number.

[0201] The protrusion PRU can be disposed between the second bridge layer BR2 and the third bridge layer BR3. The protrusion PRU can protrude from a side surface of the intermediate bridge pattern layer IBP that is located between the second bridge layer BR2 and the third bridge layer BR3.

[0202] The present embodiment also allows the intermediate bridge pattern layer IBP to have a relatively large width. Thus, as described above, the risk of forming an undesirable residual conductive portion SD_E or the like around the intermediate bridge pattern layer IBP can be reduced, and the risk of a decrease in display quality can be reduced.

[0203] Further, the protrusion PRU can have a relatively small width due to its protruding shape. For example, the protrusion PRU can have a triangular shape. Thus, a step difference can be formed around the protrusion PRU. Even if a residual conductive portion SD_E is formed around the second bridge layer BR2 and the third bridge layer BR3, the step difference formed by the protrusion PRU can increase the path through which the residual conductive portions SD_E contact each other. Thus, the risk of a short circuit occurring between the second bridge layer BR2 and the third bridge layer BR3 can be preliminarily prevented.

[0204] The display device DD according to the embodiments can be applied to various types of electronic devices. In the embodiments, the electronic device includes the display device DD described above, and can further include other modules or devices having other functions in addition to the display device DD.

[0205] Figure 18 is a block diagram of an electronic device 10 according to an embodiment. Referring to Figure 18 , the electronic device 10 can include a display module 11, a processor 12, a memory 13, and a power module 14.

[0206] The processor 12 can include at least one of a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller.

[0207] The memory 13 can store data and / or information for operating the processor 12 or the display module 11. When the processor 12 executes an application stored in the memory 13, an image data signal and / or an input control signal can be transmitted to the display module 11. The display module 11 can process the provided signal and output image information on a display screen.

[0208] The power module 14 can include a power supply module such as a power adapter or a battery device, and a power conversion module. The power conversion module converts power supplied by the power supply module and generates power for operating the electronic device 10.

[0209] According to the embodiments as described above, at least one of the above-described components of the electronic device 10 can be included in the display device DD. In addition, in terms of functions, some of the respective modules included in one module can be included in the display device DD, and other modules can be provided separately from the display device DD. For example, the display module 11 is included in the display device DD, while the processor 12, the memory 13, and the power module 14 are not included in the display device DD and are provided separately in the electronic device 10.

[0210] Figure 19 Schematic diagrams showing various embodiments of the electronic device 10.

[0211] Referring to Figure 19, various types of electronic devices to which the display device DD is applied can include: electronic devices for displaying images, such as a smartphone 10_1a, a tablet computer 10_1b, a notebook computer 10_1c, a television (TV) 10_1d, and a desktop display 10_1e; wearable electronic devices including display modules, such as smart glasses 10_2a, a head-mounted display (HMD) 10_2b, and a smart watch 10_2c; and in-vehicle electronic devices 10_3 including display modules, such as a central information display (CID) and an interior mirror display disposed at an instrument cluster, a center fascia, and an instrument panel of a vehicle.

[0212] Various embodiments of the present application can provide a display device in which a structure of a line is appropriately patterned in a desired structure, and an electronic device including the display device.

[0213] Various embodiments of the present application can provide a display device capable of improving a process yield, and an electronic device including the display device.

[0214] Various embodiments of the present application can provide a display device capable of preventing a risk of an undesired residual conductive structure occurring during a manufacturing process, and an electronic device including the display device.

[0215] Various embodiments of the present application can provide a display device capable of reducing a risk of a short circuit occurring between lines, and an electronic device including the display device.

[0216] Although the present application has been particularly shown and described with reference to embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details can be made therein without departing from the spirit and scope of the present application.

[0217] Therefore, the embodiments disclosed in this specification are merely for illustrative purposes and are not intended to limit the technical spirit of the present application.

Claims

1. A display device defining a display area and a non-display area, the display device comprising: a base layer formed across the display area and the non-display area; pixels disposed on the base layer and in the display area, wherein each of the pixels includes sub-pixels; a demultiplexer disposed in the non-display area; a driving circuit portion disposed adjacent to the demultiplexer and in the non-display area; data lines electrically connecting the demultiplexer to the sub-pixels; data base lines electrically connecting the demultiplexer to the driving circuit portion, wherein the data base lines include a first data base line and a second data base line; data connection lines electrically connecting the demultiplexer to the data base lines, wherein the data connection lines include a first data connection line and a second data connection line, wherein the first data connection line is electrically connected to the first data base line and includes a 1-1 data connection line and a 1-2 data connection line, and the second data connection line is electrically connected to the second data base line and includes a 2-1 data connection line and a 2-2 data connection line; bridge layers including a first bridge layer and a second bridge layer, wherein the first bridge layer is electrically connected to the 1-1 data connection line and the 1-2 data connection line, and the second bridge layer is electrically connected to the 2-1 data connection line and the 2-2 data connection line; and an intermediate bridge pattern layer electrically connecting the first data base line to the first bridge layer, wherein the intermediate bridge pattern layer overlaps the second bridge layer and has a width greater than a width of the first data base line. 2.The display device of claim 1, wherein the intermediate bridge pattern layer includes a side surface forming an interface angle with respect to a layer on which the intermediate bridge pattern layer is disposed, and wherein the interface angle is in a range of 30° to 70°.

3. The display device according to claim 2, wherein the width of the intermediate bridge pattern layer is 6 µm or more.

4. The display device according to claim 2, wherein a thickness of the intermediate bridge pattern layer is in a range of 3600 Å to 4200 Å. 5.The display device of claim 4, wherein the intermediate bridge pattern layer includes a first conductive layer including titanium and a second conductive layer disposed on the first conductive layer and including aluminum, wherein a thickness of the first conductive layer is in a range of 200 Å to 400 Å, and wherein a thickness of the second conductive layer is in a range of 3200 Å to 3800 Å. 6.The display device of claim 2, further comprising: a first interlayer conductive layer disposed on the base layer; a second interlayer conductive layer disposed on the first interlayer conductive layer; and a transistor conductive layer disposed on the second interlayer conductive layer, wherein the data connection lines are formed of the first interlayer conductive layer, wherein the data base lines and the intermediate bridge pattern layer are formed of the second interlayer conductive layer, and wherein the bridge layers are formed of the transistor conductive layer. 7.The display device of claim 1, the pixels include a first pixel and a second pixel adjacent to each other in a first direction, wherein ​ The demultiplexer includes a first demultiplexing transistor and a second demultiplexing transistor, The first pixel is electrically connected to the first demultiplexing transistor, and The second pixel is electrically connected to the second demultiplexing transistor.

8. The display device of claim 7, further comprising: a first selection control line electrically connected to a gate electrode of the first demultiplexing transistor; and a second selection control line electrically connected to a gate electrode of the second demultiplexing transistor, Each of the first selection control line and the second selection control line extends in the first direction.

9. The display device of claim 7, The first demultiplexing transistor includes a plurality of first demultiplexing transistors, wherein The second demultiplexing transistor includes a plurality of second demultiplexing transistors, The first 1-1 data connection line is electrically connected to one of the plurality of first demultiplexing transistors, The first 2-1 data connection line is electrically connected to another of the plurality of first demultiplexing transistors, The first 1-2 data connection line is electrically connected to one of the plurality of second demultiplexing transistors, and The first 2-2 data connection line is electrically connected to another of the plurality of second demultiplexing transistors. The first 1-1 data connection line, the first 1-2 data connection line, the first 2-1 data connection line, and the first 2-2 data connection line extend in a second direction different from the first direction.

10. The display device of claim 9, wherein, 11. The display device of claim 10, The first bridge layer electrically connects the first 1-1 data connection line and the first 1-2 data connection line spaced apart from each other in the first direction to each other, and wherein The second bridge layer electrically connects the first 2-1 data connection line and the first 2-2 data connection line spaced apart from each other in the first direction to each other. The second bridge layer is disposed between the first bridge layer and the first data base line such that the intermediate bridge pattern layer and the second bridge layer overlap each other.

12. The display device of claim 11, wherein, At least a portion of the data base line extends in the second direction.

13. The display device of claim 12, wherein, 14. The display device of claim 13, further comprising a bridge pattern layer electrically connecting the first data base line and the intermediate bridge pattern layer to each other and disposed on a layer different from a layer on which the first data base line and the intermediate bridge pattern layer are disposed.

15. The display device of claim 10, The sub-pixels include a first sub-pixel, a second sub-pixel, and a third sub-pixel, wherein, The data line includes a first 1-1 data line electrically connected to the first sub-pixel of the first pixel, a first 2-1 data line electrically connected to the second sub-pixel of the first pixel, a first 3-1 data line electrically connected to the third sub-pixel of the first pixel, a first 1-2 data line electrically connected to the first sub-pixel of the second pixel, a first 2-2 data line electrically connected to the second sub-pixel of the second pixel, and a first 3-2 data line electrically connected to the third sub-pixel of the second pixel, ​ The first 1-1 data line, the first 2-1 data line, and the first 3-1 data line are electrically connected to the plurality of first demultiplexing transistors, respectively. The first 1-2 data line, the first 2-2 data line, and the first 3-2 data line are electrically connected to the plurality of second demultiplexing transistors, respectively.

16. The display device of claim 15, wherein, The data base lines further include a third data base line. The data connection lines further include a third data connection line, the third data connection line including a third 1-1 data connection line and a third 1-2 data connection line and being electrically connected to the third data base line. The third 1-1 data connection line extends in the second direction and overlaps the first bridge layer and the second bridge layer.

17. The display device of claim 16, wherein, The bridge layers further include a third bridge layer, the third bridge layer being electrically connected to the third 1-1 data connection line and the third 1-2 data connection line. The second bridge layer is disposed between the first bridge layer and the third bridge layer.

18. The display device of claim 17, wherein, The intermediate bridge pattern layer is disposed across the second bridge layer and the third bridge layer and overlaps at least a portion of the second bridge layer and at least a portion of the third bridge layer.

19. The display device of claim 17, wherein The intermediate bridge pattern layer includes a first intermediate bridge pattern layer and a second intermediate bridge pattern layer, wherein the first intermediate bridge pattern layer overlaps the second bridge layer and the second intermediate bridge pattern layer overlaps the third bridge layer. The first intermediate bridge pattern layer and the second intermediate bridge pattern layer are spaced apart from each other.

20. An electronic device comprising: a display device; and a power module configured to provide power to the display device, wherein the display device defines a display area and a non-display area and includes: a base layer formed across the display area and the non-display area; pixels disposed on the base layer and in the display area, wherein each of the pixels includes a sub-pixel; a demultiplexer disposed in the non-display area; a drive circuit portion disposed adjacent to the demultiplexer and in the non-display area; data lines electrically connecting the demultiplexer to the sub-pixels; data base lines electrically connecting the demultiplexer to the drive circuit portion, wherein the data base lines include a first data base line and a second data base line; data connection lines electrically connecting the demultiplexer to the data base lines, wherein the data connection lines include a first data connection line and a second data connection line, wherein the first data connection line is electrically connected to the first data base line and includes a first 1-1 data connection line and a first 1-2 data connection line, and the second data connection line is electrically connected to the second data base line and includes a second 1-1 data connection line and a second 1-2 data connection line; a bridge layer including a first bridge layer and a second bridge layer, wherein the first bridge layer is electrically connected to the first-1 data connection line and the first-2 data connection line, and the second bridge layer is electrically connected to the second-1 data connection line and the second-2 data connection line; and an intermediate bridge pattern layer electrically connecting the first data base line to the first bridge layer, wherein the intermediate bridge pattern layer overlaps the second bridge layer and has a width greater than a width of the first data base line.

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