A method and apparatus for fault logging of a CPU platform

Abstract

The application provides a CPU platform fault log recording method and device, comprising: receiving the running log data stream output by the CPU debugging serial port in real time; collecting the sampling value of the key power supply voltage and monitoring the hardware signal line to obtain the restart event signal and the shutdown event signal; packaging into a structured log recording unit; and writing the compressed log data block back to the flash memory; in response to the external reading instruction, reading the log data block from the specified log area of the flash memory and transmitting to the host end diagnostic tool; reorganizing and displaying in time sequence for fault analysis. The application can construct a log recording channel completely independent of the main CPU and operating system without increasing any additional hardware cost, ensuring that even in the most extreme system failure scenario, the complete context information at the fault moment can be reliably saved, thereby greatly improving the diagnosis efficiency and accuracy of the occasional fault.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computer hardware fault diagnosis, in particular to a fault log recording method and device of a CPU platform. BACKGROUND

[0002] With the in-depth promotion of information technology application innovation, notebook computers, desktop computers, all-in-one computers and other computing devices are widely used. However, during the research and development, quality inspection and actual use of these devices, engineers and users often encounter some difficult-to-reproduce occasional failures, such as system sudden blue screen, deadlock, automatic restart or complete power failure without warning. The biggest challenge in locating such problems is "difficult to reproduce" and "difficult to investigate". The fault often occurs in a flash, and is usually accompanied by the failure of the system core components, resulting in the loss of key diagnostic information.

[0003] To solve the above problems, the prior art mainly adopts a log recording method, which relies on the operating system to write running logs and error information into the hard disk storage. However, when a system-level crash or sudden power failure occurs, the log data that is still in the operating system cache and has not been written into the hard disk in time will be immediately lost, and these data contain the most valuable clues before the fault is triggered. In order to improve reliability, some high-reliability server systems use a baseboard management controller (BMC) in combination with an independent non-volatile storage medium (such as a TF card) to record logs. Although this solution is effective, it introduces additional dedicated chips and storage hardware, significantly increasing the material cost and circuit board design complexity, which is economically unaffordable for cost-controlled consumer or popular domestic computing devices. Finally, the existing log content is often limited to software-level error information, lacking key hardware state context (such as power voltage fluctuation), making it difficult for engineers to determine whether the problem is a software defect, hardware instability or power quality issue when analyzing the problem, greatly prolonging the fault location period. SUMMARY

[0004] The present application provides a fault log recording method and device of a CPU platform to solve the problems of easy loss of logs, high storage cost and difficult fault reproduction in the prior art.

[0005] In a first aspect, the present application provides a fault log recording method of a CPU platform, the method comprising: receiving a running log data stream output by a CPU debugging serial port in real time; collecting sample values of key power voltages and monitoring hardware signal lines to obtain restart event signals and shutdown event signals; combining the current data packet in the running log data stream, the sampling value of the key power supply voltage, the restart event signal and the shutdown event signal, embedding a time stamp, and encapsulating into a structured log record unit; storing the structured log record unit into a specified log area of a flash memory in a circularly overwritten manner; calling a lightweight compression algorithm to perform batch compression processing on the structured log record unit stored in the specified log area, and writing back the compressed log data block to the flash memory; when the host operating system is running normally, receiving an external reading instruction from a host-side diagnostic tool; in response to the external reading instruction, reading the log data block from the specified log area of the flash memory and transmitting to the host-side diagnostic tool; the host-side diagnostic tool receives the log data block and reorganizes and displays it in time sequence for fault analysis.

[0006] Preferably, the sampling value of the key power supply voltage comprises: based on the existing ADC module of the embedded controller of the CPU platform, collecting one or more of the CPU core voltage, memory voltage and system bus voltage.

[0007] Preferably, the structured log record unit is stored in a specified log area of a flash memory in a circularly overwritten manner, comprising: dividing the specified log area of the flash memory into N fixed-size storage blocks, where N is an integer greater than or equal to 64, and the size of each storage block is 4KB; writing the structured log record unit in the order of storage blocks, and when the Nth storage block is full, automatically overwriting the first storage block.

[0008] Preferably, the lightweight compression algorithm is called to perform batch compression processing on the structured log record unit stored in the specified log area, comprising: using LZSS compression algorithm or LZW compression algorithm to perform compression operation on the accumulated multiple structured log record units; the execution priority of the compression operation is set to the lowest, and it is only started when the CPU utilization of the embedded controller is less than 20%.

[0009] Preferably, the host-side diagnostic tool receives the log data block and reorganizes and displays it in time sequence, comprising: performing a corresponding decompression algorithm on the received log data block to restore the original structured log record unit; extracting the timestamp, running log data, power supply voltage value and event signal from each of the structured log record units; synchronously displaying the text log curve and the power supply voltage change curve in the form of a time axis, and marking the restart / shutdown event at the corresponding time point.

[0010] Preferably, it further comprises: monitoring the system task load in real time by the task scheduler of the embedded controller; determining that the system enters an idle state when detecting that there is no high-priority task to be executed within a continuous 10 ms time window; triggering execution of the lightweight compression algorithm.

[0011] Preferably, it further comprises: suspending assembly of the current structured log record unit immediately upon monitoring the restart event signal or the shutdown event signal; forcing writing of the combined data in the cache to the flash memory after adding an emergency event flag, and executing subsequent procedures after completion of the writing operation.

[0012] In a second aspect, the present application provides a fault log recording device for a CPU platform, comprising: a data stream receiving module for receiving running log data stream output by a CPU debugging serial port in real time; an event signal monitoring module for collecting sampling values of key power supply voltages and monitoring hardware signal lines to obtain a restart event signal and a shutdown event signal; a packaging module for combining current data packets in the running log data stream, the sampling values of the key power supply voltages, the restart event signal and the shutdown event signal, embedding a timestamp, and packaging into structured log record units; a storage module for storing the structured log record units in a specified log area of a flash memory in a cyclic overwriting manner; a compression module for calling a lightweight compression algorithm to perform batch compression processing on the structured log record units stored in the specified log area, and writing the compressed log data block back to the flash memory; a reading module for receiving an external reading instruction from a host-side diagnostic tool when the host operating system is running normally; in response to the external reading instruction, reading the log data block from the specified log area of the flash memory and transmitting it to the host-side diagnostic tool; a reorganization and display module for the host-side diagnostic tool to receive the log data block and reorganize and display it in chronological sequence for use in fault analysis.

[0013] In a third aspect, the present application provides a readable medium comprising execution instructions, when a processor of an electronic device executes the execution instructions, the electronic device executes the method according to any one of the first aspect.

[0014] In a fourth aspect, the present application provides an electronic device comprising a processor and a memory storing execution instructions, when the processor executes the execution instructions stored in the memory, the processor executes the method according to any one of the first aspect.

[0015] The present application provides a CPU platform fault log recording method and device, which receives running log data stream output by CPU debugging serial port in real time; collects sampling value of key power supply voltage and monitors hardware signal line to obtain restart event signal and shutdown event signal; combines current data packet in running log data stream, sampling value of key power supply voltage, restart event signal and shutdown event signal, embeds time stamp and encapsulates into structured log recording unit; stores structured log recording unit into specified log area of flash memory in cyclic coverage writing mode; calls lightweight compression algorithm to perform batch compression processing on structured log recording unit stored in specified log area, and writes compressed log data block back to flash memory; when host operating system runs normally, receives external reading instruction from host end diagnosis tool; in response to external reading instruction, reads log data block from specified log area of flash memory and transmits to host end diagnosis tool; host end diagnosis tool receives log data block and reorganizes and displays according to time sequence for fault analysis. The present application can construct a log recording channel completely independent of main CPU and operating system without increasing any additional hardware cost, ensures that complete context information at fault moment can be reliably saved even in the most extreme system failure scenario, thereby greatly improving diagnosis efficiency and accuracy of incidental faults.

[0016] Further effects of the above-described preferred, non-conventional modes will be explained in the following in connection with the specific embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0017] In order to more clearly illustrate the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings described below are only some embodiments described in the present application, and those skilled in the art can also obtain other drawings according to these drawings without creative labor.

[0018] Figure 1 A schematic diagram of a CPU platform fault log recording method provided by an embodiment of the present application; Figure 2A schematic diagram of another CPU platform fault log recording method provided by an embodiment of the present application is shown in FIG. 2. Figure 3 A schematic diagram of another CPU platform fault log recording method provided by an embodiment of the present application is shown in FIG. 2. Figure 4 A schematic diagram of a CPU platform fault log recording device provided by an embodiment of the present application is shown in FIG. 3. Figure 5 A schematic diagram of the structure of an electronic device provided by an embodiment of the present application is shown in FIG. 4. DETAILED DESCRIPTION

[0019] To make the objectives, technical solutions, and advantages of the present application clearer, the technical solutions of the present application will be described below in detail with specific embodiments and corresponding drawings. Obviously, the described embodiments are only some of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort belong to the scope of protection of the present application.

[0020] With the in-depth promotion of information technology application innovation, computing devices such as notebooks, desktops, and all-in-one computers are being widely applied. However, in the research and development, quality inspection, and actual use of these devices, engineers and users often encounter some difficult-to-reproduce occasional failures, such as sudden blue screen, deadlock, automatic restart, or complete power failure of the system without warning. The biggest challenge in locating such problems is “difficult to reproduce” and “difficult to obtain evidence”. The fault often occurs and disappears in a flash, and is usually accompanied by the failure of the core components of the system, resulting in the loss of key diagnostic information.

[0021] To solve the above problems, the existing technical solutions mainly adopt log recording methods, relying on the operating system to write running logs and error information into the hard disk storage. However, when a system-level crash or sudden power failure occurs, the log data that is still in the operating system cache and has not been written into the hard disk in time will be immediately lost, and these data contain the most valuable clues before the fault is triggered. In order to improve reliability, some high-reliability server systems use a baseboard management controller (BMC) in combination with an independent non-volatile storage medium (such as a TF card) to record logs. Although this solution is effective, it introduces additional dedicated chips and storage hardware, significantly increasing the material cost and circuit board design complexity, which is economically difficult for cost-controlled consumer or popular domestic computing devices to bear. Finally, the existing log content is often limited to software-level error information, lacking key hardware state context (such as power voltage fluctuations), making it difficult for engineers to determine whether the problem is a software defect, hardware instability, or power quality issue when analyzing the problem, greatly prolonging the fault location period.

[0022] Therefore, the present application provides a fault log recording method of a CPU platform. Referring to Figure 1 As shown in the figure, a specific embodiment of the fault log recording method of the CPU platform provided by the present application. The method comprises: Step 101, real-time receiving the running log data stream output by the CPU debugging serial port; Specifically, this step is the entrance of the whole method and the source of data collection. The CPU debugging serial port can be a special hardware interface provided on a domestic CPU chip such as "Feiteng, Longxin" for outputting underlying debugging information, usually following the UART communication protocol. When the CPU is running normally or even when an exception occurs, its kernel, driver or operating system will output a large amount of running state, error report, register value and other key diagnostic data in the form of continuous data stream through this serial port in real time. The "real-time receiving" of this step means that through another serial port of the pre-existing embedded controller on the motherboard, a direct physical connection with the debugging serial port of the CPU is established, so that all data flowing through this channel can be captured continuously and passively. Through this step, even the last moment output log before the system completely crashes can be reliably captured by an independent hardware unit that can still work in extreme cases, leaving the most critical evidence for fault analysis. For example, when the CPU is about to trigger a system crash due to a fatal error in a driver, the last few error messages and stack traces output by the CPU through the debugging serial port before it loses control will be recorded by the embedded controller without omission.

[0023] Step 102, collecting the sampling value of the key power voltage and monitoring the hardware signal line to obtain the restart event signal and shutdown event signal; Many accidental failures are not caused by pure software errors, but by underlying hardware problems such as unstable power quality, voltage transient drop, hardware timing exception, etc. Traditional logs only contain software information, making it difficult for analysts to understand the whole picture. Therefore, it is necessary to collect and monitor various data to determine the fault. Specifically, collecting the sampling value of the key power voltage can be completed by multiplexing the ADC module usually integrated inside the embedded controller. This module converts the analog voltage values of the CPU core voltage, memory voltage and system bus voltage and other key power nodes into digital quantities at a certain sampling frequency (such as not less than 10Hz) and precision (such as 12 bits). At the same time, the embedded controller monitors the level change of the specific hardware signal line on the motherboard representing the system state to accurately perceive the occurrence of the restart event or shutdown event. Through this step, a multi-dimensional diagnostic data set is constructed, enabling subsequent analysis to accurately correlate the abnormal events at the software level with the voltage fluctuations and system events at the hardware level on the timeline, greatly improving the accuracy and efficiency of fault root cause analysis.

[0024] Step 103, combine the current data packet in the running log data stream, the sampling value of the key power voltage, the restart event signal and the shutdown event signal, embed a timestamp, and encapsulate into a structured log record unit; The original data stream is disorganized and lacks correlation, and must be integrated through a common time reference and converted into a standardized data format that is convenient for storage, retrieval and subsequent processing. Specifically, this step is a key process of standardizing, correlating and structuring the collected multi-source, heterogeneous original data. The current data packet refers to a complete information unit parsed from the continuous debugging serial port data stream according to the protocol. The core operation of this step is "combination" and "encapsulation", that is, the software log fragments, hardware voltage sampling values and system event signals obtained in the same time period are packaged, and a timestamp generated by the high-precision clock inside the embedded controller is embedded, and finally a structured log record unit with uniform format is formed.

[0025] Step 104, store the structured log record unit in the specified log area of the flash memory in a circularly overwritten manner; Specifically, this step solves the problem of non-volatile and sustainable storage of diagnostic data, and is the core link to ensure that the log is reliable and not lost. The physical entity of the flash memory is a non-volatile FLASH chip integrated inside the embedded controller, which is mainly used to store the firmware of the controller itself. In this embodiment, a specific area is divided from the remaining space as a specified log area for log recording. By cleverly reusing existing hardware resources, zero additional hardware cost is achieved. The circularly overwritten writing method is an efficient storage management strategy, and its specific implementation includes: first, divide the limited log storage area into N (N≥64) fixed-size storage blocks (such as 4KB each); then, write the structured log record unit in order according to the block; when the last block (the Nth block) is full, the storage management module will automatically loop back to the first block, overwrite the oldest data, and continue to write. Because of the objective constraint of limited FLASH capacity of the embedded controller, it is necessary to ensure that the storage space can be recycled and used sustainably, and the system running data in the recent period of time is always given priority to save, realizing automatic and long-term log recording under limited resources.

[0026] Step 105, call a lightweight compression algorithm to perform batch compression processing on the structured log record units stored in the specified log area, and write the compressed log data block back to the flash memory; Specifically, this step is a depth optimization for limited storage space, significantly improving storage efficiency without increasing cost. The lightweight compression algorithm refers to LZSS or LZW and other lossless compression algorithms with low computational complexity and small memory occupation, which is suitable for running on microcontrollers with limited computing resources such as embedded controllers. Batch compression processing refers to starting the compression task by the task scheduler when the embedded controller detects that it is in an idle state (i.e. CPU utilization is less than 20%), and centrally compressing multiple uncompressed structured log record units accumulated in the flash memory. The log data block formed after compression will be written back to the flash memory, which can usually save 50% or more of the storage space. In this way, while absolutely guaranteeing the real-time performance of the main function of the system, the effective log recording time and capacity are expanded several times by utilizing the idle computing period, greatly increasing the opportunity to capture low-frequency occasional faults.

[0027] Step 106, when the host operating system is running normally, receiving an external read instruction from the host-side diagnostic tool; in response to the external read instruction, reading a log data block from a specified log area of the flash memory and transmitting it to the host-side diagnostic tool; Specifically, this step builds a data export channel that can read log data from the independent flash memory when the system resumes normal operation. After the device is restarted after a fault and normally enters the operating system, engineers or maintenance personnel can run a dedicated host-side diagnostic tool. The tool sends an external read instruction to the embedded controller through the standard motherboard interface such as LPC or USB provided by the embedded controller. The communication protocol stack in the embedded controller will locate and read the corresponding log data block from the specified log area of the flash memory according to the instruction parameters (such as the requested time range) after receiving the instruction, and then transmit the data block back to the tool software on the host side through the same interface. This step conveniently obtains diagnostic data stored in independent hardware in a standardized and non-intrusive manner. It avoids complex operations such as disassembling the device or using a special hardware debugger.

[0028] Step 107, the host-side diagnostic tool receives the log data block and reorganizes and displays it in chronological order for fault analysis.

[0029] Specifically, the host-side diagnostic tool sequentially performs decompression, parsing and data reorganization operations after receiving the log data block. The host-side diagnostic tool software arranges all data in correct time order according to the time stamp in each structured log record unit, and presents the data to the user in an integrated, multi-view visual interface. In general, a comprehensive view based on a time axis is included, which synchronously displays a content list of the text log, a curve diagram of the key power voltage change over time, and clearly marks the occurrence points of system events such as restart and shutdown at specific positions of the time axis. The analyst can intuitively and panoramically observe the cause-and-effect and correlation between the software behavior and the hardware state parameters before and after the fault occurs, thereby quickly locating the starting point and mode of the abnormal sequence, and greatly accelerating the diagnosis process of the complex fault.

[0030] Through the above technical solutions, it can be known that the beneficial effects of the embodiment are that the application can construct a log record channel completely independent of the main CPU and the operating system without increasing any additional hardware cost, and ensure that the complete context information at the fault moment can be reliably saved even in the most extreme system failure scenario, thereby greatly improving the diagnosis efficiency and accuracy of the occasional fault.

[0031] Figure 1 As shown, it is only a basic embodiment of the method of the application, and on the basis of certain optimization and expansion, other preferred embodiments of the method can also be obtained.

[0032] As shown, it is only a basic embodiment of the method of the application, and on the basis of certain optimization and expansion, other preferred embodiments of the method can also be obtained. Figure 2 As shown, it is another specific embodiment of the fault log recording method of the CPU platform of the application. This embodiment is further described on the basis of the foregoing embodiment. In this embodiment, the method comprises the following steps: Step 201, real-time monitoring of system task load by a task scheduler of the embedded controller; Specifically, the task scheduler is a core component of the embedded controller firmware, which is responsible for managing the execution order of all tasks and CPU resource allocation. Real-time monitoring of system task load means that the scheduler continuously tracks the running state of the CPU, dynamically senses whether a high-priority task (such as key power-on / off timing control, keyboard scan event processing, fan speed execution and other key real-time tasks) is running or waiting to run. This monitoring mechanism is dynamic and active, rather than simply timing polling. The embedded controller is a resource-limited microcontroller, and its primary task is to ensure the stability and real-time response of the motherboard basic functions. Any additional computing task, such as log compression, must not interfere with the execution of these key tasks. Therefore, continuous monitoring of task load is a prerequisite for making correct scheduling decisions.

[0033] Step 202: When it is detected that no high-priority tasks need to be executed within a continuous 10ms time window, the system is determined to enter an idle state; Furthermore, the "continuous 10ms time window" is a balanced empirical value. It is long enough to confirm that the system has indeed achieved a brief period of stable idle time (avoiding misjudgments caused by minor gaps between tasks), yet short enough to make timely use of fragmented idle time. The criterion is that no high-priority tasks need to be executed. This means that during this period, there are no tasks in the task queue that are urgent enough to require immediate processing. This ensures that the system is only marked as "idle" when it is sufficiently idle. It also prevents the compression algorithm from being triggered at any moment that could affect the system's real-time response.

[0034] Step 203: Trigger the execution of the lightweight compression algorithm.

[0035] Specifically, this step is the final action following the first two monitoring and judgment steps. Once the system is officially determined to have entered an "idle state," the task scheduler will immediately trigger or start a lightweight compression task. The compression algorithm (such as LZSS / LZW) will then gain CPU execution privileges to process the uncompressed log data accumulated in the flash memory. This ensures that the performance impact of the compression operation on the system's main functions is reduced to negligible levels, achieving full utilization of idle computing power.

[0036] As can be seen from the above technical solutions, the beneficial effects of this embodiment are: The present invention, through real-time monitoring, strict criteria, and event triggering mechanisms, ensures that compression operations are performed only within a 100% safe idle time window of the system, thereby guaranteeing the real-time performance and reliability of the embedded controller's main functions. Simultaneously, it utilizes fragmented computing resources that would otherwise be wasted, significantly improving the efficiency of storage space utilization.

[0037] like Figure 3 The image shows another specific embodiment of a fault log recording method for a CPU platform according to the present invention. This embodiment further describes the method based on the foregoing embodiments, and includes the following steps: Step 301: When a restart event signal or a shutdown event signal is detected, immediately suspend the assembly of the current structured log recording unit; Specifically, this step marks the beginning of the system's rapid response mechanism to impending extreme failures. Reboot or shutdown event signals are hard indicators that the embedded controller accurately captures by monitoring motherboard hardware signal lines, signifying that the system is about to enter an abnormal shutdown or reboot process. Once such a signal is detected, it means the system may completely lose power or reset within a very short timeframe, leaving a very limited window for data preservation. Therefore, the embedded controller immediately suspends the ongoing structured logging unit assembly process to prevent the loss of all cached data due to data processing delays at the last moment before system crash.

[0038] Step 302: Add an emergency event flag to the combined data in the cache and force write it to the flash memory, and wait for the write operation to complete before proceeding with the subsequent process.

[0039] Furthermore, the data already assembled in the cache refers to the portion of data that has been prepared during the paused assembly process, potentially including recent log fragments and voltage sampling values. The system will forcefully write these potentially incomplete but extremely important data blocks to the flash memory with the highest priority. An emergency event flag will be added to these blocks to facilitate quick location of the system anomaly during subsequent analysis. The system will synchronously wait for the flash memory controller to confirm the completion of this write operation before allowing the hardware to continue with subsequent restart or shutdown procedures. This "blocking" write ensures the absolute reliability of the physical data storage and prevents the problem of write commands being issued but data not actually stored in flash memory due to momentary power interruptions in asynchronous write mode.

[0040] As can be seen from the above technical solutions, the beneficial effects of this embodiment are: the present invention greatly improves the ability and reliability of capturing and saving critical information at the moment of failure under extreme failure scenarios. By immediately pausing the normal process, forcing synchronous writing, and adding event markers, it ensures that as much diagnostic data as possible can be safely saved to the flash memory even in the last few milliseconds of the system's lifecycle.

[0041] like Figure 4 The image shows a specific embodiment of a fault log recording device for a CPU platform according to the present invention. This embodiment of the device is used to execute... Figures 1-3 The physical apparatus of the method. Its technical solution is essentially the same as the above embodiments, and the corresponding descriptions in the above embodiments also apply to this embodiment. The apparatus in this embodiment includes: The data stream receiving module 401 is configured to receive the runtime log data stream output by the CPU debug serial port in real time. The event signal monitoring module 402 is configured to collect sampled values ​​of critical power supply voltages and monitor hardware signal lines to obtain restart event signals and shutdown event signals. The encapsulation module 403 is configured to combine the current data packet in the running log data stream, the sampling value of the key power supply voltage, the restart event signal and the shutdown event signal, and embed a time stamp to encapsulate into a structured log record unit; The storage module 404 is configured to store the structured log record unit to a specified log area of the flash memory in a circularly overwritten manner; The compression module 405 is configured to call a lightweight compression algorithm to perform batch compression processing on the structured log record unit stored in the specified log area, and write back the compressed log data block to the flash memory; The reading module 406 is configured to receive an external reading instruction from the host-side diagnostic tool when the host operating system is normally running; in response to the external reading instruction, read the log data block from the specified log area of the flash memory and transmit to the host-side diagnostic tool; The reorganization and display module 407 is configured to receive the log data block by the host-side diagnostic tool, and reorganize and display in time sequence for fault analysis.

[0042] Figure 5 is a structural schematic diagram of an electronic device provided by an embodiment of the present application. At the hardware level, the electronic device includes a processor, and optionally further includes an internal bus, a network interface, and a memory. The memory can include a memory such as a random-access memory (RAM), and can also include a non-volatile memory such as at least one disk memory. Of course, the electronic device can also include other hardware required by a business.

[0043] The processor, the network interface, and the memory can be connected to each other through the internal bus, which can be an industry standard architecture (ISA) bus, a peripheral component interconnect (PCI) bus, or an extended industry standard architecture (EISA) bus, etc. The bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 5 In the figure, only one bidirectional arrow is used to represent, but it does not mean that there is only one bus or only one type of bus.

[0044] Memory is used to store instructions for execution. Specifically, instructions for execution are computer programs that can be executed. Memory can include main memory and non-volatile memory, and it provides the processor with execution instructions and data.

[0045] In one possible implementation, the processor reads the corresponding execution instructions from non-volatile memory into main memory and then executes them. Alternatively, it can obtain the corresponding execution instructions from other devices to form a fault logging device for the CPU platform at the logical level. The processor executes the execution instructions stored in the memory to implement the fault logging method for a CPU platform provided in any embodiment of the present invention.

[0046] The above is as described in the present invention. Figure 4 The method executed by the fault log recording device of the CPU platform provided in the illustrated embodiment can be applied to a processor or implemented by a processor. The processor may be an integrated circuit chip with signal processing capabilities. During implementation, each step of the above method can be completed by integrated logic circuits in the processor's hardware or by instructions in software form. The processor can be a general-purpose processor, including a Central Processing Unit (CPU), a Network Processor (NP), etc.; it can also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field-Programmable Gate Array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this invention. The general-purpose processor can be a microprocessor or any conventional processor.

[0047] The steps of the method disclosed in the embodiments of this invention can be directly manifested as being executed by a hardware decoding processor, or executed by a combination of hardware and software modules in the decoding processor. The software modules can reside in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. This storage medium is located in memory, and the processor reads information from the memory and, in conjunction with its hardware, completes the steps of the above method.

[0048] The embodiment of the present application further provides a readable medium, which stores an execution instruction, and the execution instruction stored is executed by a processor of an electronic device, so that the electronic device executes the CPU platform fault log recording method provided in any one of the embodiments of the present application, and is particularly used for executing the method shown in Figure 1 、 Figure 2 、 Figure 3 .

[0049] The electronic device in each of the foregoing embodiments can be a computer.

[0050] Those skilled in the art should understand that the embodiments of the present application can be provided as a method or a computer program product. Therefore, the present application can adopt a complete hardware embodiment, a complete software embodiment, or a combination of software and hardware.

[0051] Each of the embodiments of the present application is described in a progressive manner, and the same or similar parts of each of the embodiments can be referred to each other. Each of the embodiments mainly explains the difference from other embodiments. In particular, for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the related parts can be referred to the part of the method embodiment.

[0052] It should be further noted that the terms "comprising", "containing" or any other variant thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed, or further includes the elements inherent to such process, method, article or device. Without more limitations, the element defined by the statement "comprising a" does not exclude the presence of another identical element in the process, method, article or device including the element.

[0053] The above is only the embodiment of the present application, and is not used to limit the present application. The present application can have various changes and modifications for those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the scope of claims of the present application.

Claims

1. A method for failure logging of a CPU platform, the method comprising: The method comprises: real-time receiving a running log data stream of a CPU debugging serial port output; collecting sampling values of key power supply voltages and monitoring hardware signal lines to obtain a restart event signal and a shutdown event signal; combining a current data packet in the running log data stream, the sampling values of the key power supply voltages, the restart event signal and the shutdown event signal, embedding a time stamp and encapsulating into a structured log record unit; storing the structured log record unit in a specified log area of a flash memory in a cyclic coverage writing manner; calling a lightweight compression algorithm to perform batch compression processing on the structured log record units stored in the specified log area of the flash memory and writing the compressed log data block back to the flash memory; when the host operating system is normally running, receiving an external reading instruction from a host-side diagnosis tool; in response to the external reading instruction, reading the log data block from the specified log area of the flash memory and transmitting to the host-side diagnosis tool; the host-side diagnosis tool receives the log data block and reorganizes and displays it in time sequence for fault analysis.

2. The method of claim 1, wherein, The collecting of the sampling values of the key power supply voltages comprises: based on the existing ADC module of the embedded controller of the CPU platform, collecting one or more of the CPU core voltage, the memory voltage and the system bus voltage.

3. The method of claim 1, wherein, The storing of the structured log record unit in the specified log area of the flash memory in a cyclic coverage writing manner comprises: dividing the specified log area of the flash memory into N fixed-size storage blocks, where N is an integer greater than or equal to 64, and the size of each storage block is 4 KB; writing the structured log record unit in the order of the storage blocks, and when the Nth storage block is full, automatically overwriting the first storage block.

4. The method of claim 2, wherein, The calling of the lightweight compression algorithm to perform batch compression processing on the structured log record units stored in the specified log area comprises: using the LZSS compression algorithm or the LZW compression algorithm to perform compression operation on the accumulated multiple structured log record units; the execution priority of the compression operation is set to the lowest, and it is started only when the CPU utilization of the embedded controller is less than 20%.

5. The method of claim 1, wherein, The receiving of the log data block by the host-side diagnosis tool and the reorganization and display in time sequence comprises: performing a corresponding decompression algorithm on the received log data block to restore the original structured log record unit; extracting the time stamp, running log data, power supply voltage value and event signal from each structured log record unit; synchronously displaying the text log curve and the power supply voltage change curve in the form of a time axis, and marking the restart / shutdown event at the corresponding time point.

6. The method of claim 1, wherein, Further comprising: real-time monitoring of system task load by a task scheduler of the embedded controller; when it is detected that there is no high-priority task to be executed in a continuous 10 ms time window, it is determined that the system enters an idle state; triggering the execution of the lightweight compression algorithm.

7. The method of claim 1, wherein, Further comprising: immediately pause assembling of the current structured log unit upon monitoring the restart event signal or the shutdown event signal; force write the combined data in the cache with the emergency event flag to the flash memory and wait for the write operation to complete before executing the subsequent process.

8. A fault logging apparatus for a CPU platform, characterized by comprising: The method comprises the following steps: a data stream receiving module for receiving running log data stream output by CPU debugging serial port in real time; an event signal monitoring module for collecting sampling values of key power supply voltage and monitoring hardware signal lines to obtain restart event signal and shutdown event signal; a packaging module for combining current data packet in the running log data stream, the sampling values of key power supply voltage, the restart event signal and the shutdown event signal, embedding time stamp and packaging into structured log unit; a storage module for storing the structured log unit in a specified log area of flash memory in a cyclic overwriting manner; a compression module for calling lightweight compression algorithm to perform batch compression processing on the structured log unit stored in the specified log area and writing the compressed log data block back to the flash memory; a reading module for receiving external reading instruction from host end diagnostic tool when the host operating system is running normally; in response to the external reading instruction, reading the log data block from the specified log area of the flash memory and transmitting to the host end diagnostic tool; a recombination and display module for the host end diagnostic tool to receive the log data block and recombine and display in time sequence for fault analysis.

9. A computer readable storage medium, characterized in that, The computer readable storage medium comprises a stored program, wherein the program executes the method of any one of claims 1 to 7 when running.

10. An electronic device, comprising: The electronic device comprises: a processor; a memory for storing executable instructions of the processor; the processor is configured to read the executable instructions from the memory and execute the instructions to implement the method of any one of claims 1 to 7.

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