Design method of buffer circuit for removing noise of DC-DC switch node and circuit

Abstract

The invention discloses a design method of a buffer circuit for removing DC-DC switching node noise and a circuit, and relates to the technical field of switching power supply noise suppression, and the method comprises the steps: measuring the ringing frequency fr of a resonant circuit switching node; the method comprises the steps of determining a ringing frequency fr, determining a test capacitance Ctest by combining the ringing frequency fr, calculating a parasitic capacitance Cp according to the test capacitance Ctest, calculating characteristic impedance Z0 according to the parasitic capacitance Cp and the ringing frequency fr, further determining a buffer resistor Rsn, calculating a buffer capacitance Csn according to the parasitic capacitance Cp, and finally determining rated power PR of the buffer resistor Rsn according to the buffer capacitance Csn, an input voltage Vin and a switching frequency fsw. By quantizing the parameters of the RC buffer circuit, the higher harmonic noise of the switching node of the DC-DC converter is efficiently removed, and the additional power consumption is minimized.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of switching power supply noise suppression, in particular to a design method and circuit of a buffer circuit for removing DC-DC switching node noise. BACKGROUND

[0002] In existing switching power supplies, the switching node of the step-down converter forms a high-frequency resonant circuit (with a frequency of hundreds of MHz) due to the parasitic inductance (Lp) and parasitic capacitance (Cp), which leads to the deterioration of electromagnetic interference (EMI). Although the traditional RC buffer circuit can suppress noise, it has two major defects: (1) parameter design relies on trial and error experience, and lacks a systematic calculation process; (2) the buffer resistor continuously consumes energy (loss power is (Csn×Vin 2 ×fsw) during the switching period, reducing system efficiency.

[0003] The existing document "Optimum Design of RC Snubbers for Switching Regulators" (IEEE, 1979) discloses a systematic RC parameter design method based on theoretical derivation, which achieves:

[0004] 1. Establish an equivalent model:

[0005] The problem is simplified to a series resonant circuit consisting of parasitic inductance (Lp), parasitic capacitance (Cp), and an ideal switch (i.e., a classical RLC second-order circuit). Ringing (oscillation) is generated by the Lp-Cp circuit at the switching-off instant.

[0006] 2. Define the critical damping condition:

[0007] It is pointed out that the optimal working state of the RC buffer circuit is to make the entire system (the original Lp-Cp circuit plus the buffer circuit) in a critical damping state. Critical damping is a state between over-damping (no oscillation but slow response) and under-damping (oscillation), which can completely eliminate ringing, minimize voltage spikes, and achieve the fastest response speed.

[0008] 3. Derive the optimal parameter calculation formula:

[0009] By solving the differential equation of the circuit under the critical damping condition, a set of simple design formulas is derived:

[0010] Buffer resistor ;

[0011] Buffer capacitor Cs>Cp (usually Cs≥4Cp);

[0012] Where Lp is the parasitic inductance of the circuit, Cp is the output capacitance of the switch (Coss).

[0013] In practical applications, since Cs is much larger than Cp (Cs » Cp), the above resistance formula can be simplified as: Rsnub ≈ .

[0014] 4. Design methodology:

[0015] Measure Cp: Measure the output capacitance Coss of the switch (i.e. Cp) under high voltage bias using a capacitance meter.

[0016] Measure ringing frequency fr: Measure the ringing frequency of the drain-source voltage Vds without a snubber circuit using an oscilloscope. The resonant frequency of the original circuit is fr = 1 / (2π*sqrt(Lp*Cp)). ).

[0017] Calculate Lp: Use the measured Cp and fr to back-calculate the parasitic inductance: Lp = 1 / ((2π*fr)^2*Cp).

[0018] Select Cs: According to the empirical rule, select Cs = 4Cp or larger.

[0019] Calculate Rsnub: Substitute Lp, Cp, and Cs into the formula to calculate the optimal snubber resistance value.

[0020] It aims to most effectively suppress the voltage spike and ringing caused by parasitic inductance (mainly transformer leakage inductance or wiring inductance) and parasitic capacitance (mainly the junction capacitance Coss of the switch) when the power switch (such as MOSFET or BJT) is turned off. However, it has engineering practice problems:

[0021] 1. Accurate measurement of parasitic parameters (Lp and Cp)

[0022] Nonlinearity of Cp: The junction capacitance Coss of the power switch (especially MOSFET) is not a constant value, it will change dramatically (inversely nonlinear) with the voltage (Vds) applied across it. Its assumption that Cp is constant, but in the actual switching process, Vds changes from nearly 0V to several hundred volts, and the value of Cp may change by an order of magnitude. Which Coss at which voltage should be taken as Cp is a difficult problem. The results differ greatly when the high voltage bias is set differently during measurement.

[0023] Distribution of Lp: The loop parasitic inductance Lp is not a centralized, independent component. It is composed of transformer leakage inductance, PCB wiring inductance, component lead inductance and other distributed parameters, which are difficult to accurately separate and measure. The Lp obtained by backstepping through the ringing frequency is actually an equivalent "total" parasitic inductance, but its accuracy is highly dependent on the accuracy of Cp value (Lp∝1 / Cp). Since Cp is difficult to measure accurately, the error of Lp will also be amplified.

[0024] 2. Accurate extraction of ringing frequency (fr)

[0025] Poor waveform quality: Without a snubber circuit, there is usually a very high voltage spike followed by a decaying ring on the Vds waveform. This spike will saturate or distort the oscilloscope waveform, making the starting point of the ring unclear, and it is difficult to accurately determine the start and end points of the first oscillation period, thereby introducing frequency measurement errors.

[0026] Noise interference: The switching node itself is a noise hotspot, and the ringing signal is easily disturbed, further increasing the difficulty of automatic measurement, often requiring manual measurement, which is highly subjective and has poor repeatability.

[0027] Multiple resonance points: In complex actual circuits, there may be multiple resonance loops composed of different parasitic parameters, resulting in multiple frequency superpositions on the waveform. This makes it difficult to extract that unique fr used to calculate the main resonance.

[0028] 3. Loss optimization problem

[0029] Conflict between theoretical optimization and efficiency optimization: Its "optimization" refers to the optimal (critical damping) of ringing suppression, but not necessarily the optimal of conversion efficiency.

[0030] The power consumption of the snubber resistance Rsnub is P_loss=0.5*Cs*Vds^2*fsw (fsw is the switching frequency). The larger Cs is, the greater the loss is.

[0031] In order to pursue perfect critical damping, a larger Cs (such as 4Cp) is selected, which will result in a huge energy loss on the resistance. In high-frequency and high-voltage applications, this will significantly reduce the overall efficiency of the power supply.

[0032] Therefore, although it proposes a theoretical formula, it does not solve the problems of parasitic parameter measurement, accurate extraction of ringing frequency and loss optimization in actual engineering. SUMMARY

[0033] The purpose of the present application is to provide a design method and circuit of a snubber circuit for removing DC-DC switching node noise, and to quantitatively design the snubber circuit parameters, while effectively suppressing the ringing noise of the switching node and minimizing the additional power consumption.

[0034] The application solves the above problems by the following technical solutions:

[0035] A design method of a buffer circuit for removing DC-DC switching node noise, comprising:

[0036] Step S1, measuring the ringing frequency fr of the resonant loop switching node;

[0037] Step S2, determining the test capacitor Ctest in combination with the ringing frequency fr, calculating the parasitic capacitor Cp according to the test capacitor Ctest, calculating the characteristic impedance Z0 according to the parasitic capacitor Cp and the ringing frequency fr, and then determining the buffer resistance Rsn, calculating the buffer capacitor Csn according to the parasitic capacitor Cp, and finally determining the rated power PR of the buffer resistance Rsn according to the buffer capacitor Csn, the input voltage Vin and the switching frequency fsw.

[0038] Further, the method for measuring the ringing frequency fr of the resonant loop switching node is to directly contact the switching node with an oscilloscope probe, capture the ringing waveform of the switching node, and extract the fundamental frequency, i.e. the ringing frequency fr.

[0039] Further, the oscilloscope removes the ground lead and adopts a ground adapter to minimize inductance.

[0040] Further, the method for determining the test capacitor Ctest in combination with the ringing frequency fr is to connect the test capacitor Ctest in parallel between the switching node and the ground, and adjust the value of the test capacitor Ctest so that the new ringing frequency fr_new satisfies: fr_new=fr / 2.

[0041] Further, the calculation formula for calculating the parasitic capacitor Cp according to the test capacitor Ctest is: Cp=Ctest / 3.

[0042] The derivation process is as follows:

[0043] Principle: When no buffer circuit is added, the ringing frequency fr of the resonant loop is: fr=1 / (2π ).

[0044] After connecting the test capacitor Ctest in parallel, the total capacitance becomes (Cp+Ctest), and the new ringing frequency fr_new is: fr_new=1 / (2π ).

[0045] Objective: We adjust Ctest so that the new frequency fr_new becomes half of the original frequency fr, i.e. fr_new=fr / 2.

[0046] Substitute the formula to establish the equation:

[0047] 1 / (2π )=(1 / (2π )) / 2;

[0048] Simplify the solution:

[0049] Multiply both sides by 2π, and approximate: 1 / =1 / (2* );

[0050] Take the reciprocal of both sides: =2* ;

[0051] Square both sides: Lp*(Cp+Ctest)=4*Lp*Cp;

[0052] Divide both sides by Lp(Lp≠0): Cp+Ctest=4*Cp;

[0053] Solve for Ctest: Ctest=4Cp-Cp, i.e. Ctest=3Cp.

[0054] Therefore: Cp=Ctest / 3.

[0055] Conclusion: When the capacity of the test capacitor Ctest in parallel is exactly three times the parasitic capacitance Cp, the resonance frequency will be reduced to half of the original frequency. We can find the Ctest that makes the frequency halve through experiments, and then we can deduce the exact value of Cp. The relationship Cp=Ctest / 3 is based on the strict mathematical derivation of the resonance frequency formula, and it is accurate.

[0056] Further, the calculation formula of characteristic impedance Z0 according to the parasitic capacitance Cp and the ringing frequency fr is: Z0=1 / (2πfrCp).

[0057] Further, the calculation formula of the buffer resistance Rsn is: Rsn=Z0.

[0058] Further, the formula for calculating the buffer capacitance Csn according to the parasitic capacitance Cp is: Csn=2×Cp.

[0059] Further, the calculation formula of the rated power PR of the buffer resistance Rsn according to the buffer capacitance Csn, the input voltage Vin and the switching frequency fsw is: PR≥2×(CsnVin 2 fsw / 2)=CsnVin 2 fsw.

[0060] A circuit for removing DC-DC switching node noise, comprising an input voltage Vin, a switching tube SW H and a switching tube SW LA filter capacitor Cin is connected in parallel across the input voltage Vin, and the switching transistor SW L An RC snubber circuit is connected in parallel, the RC snubber circuit including a snubber resistor Rsn and a snubber capacitor Csn connected in series, and the switching transistor SW H and switching transistor SW L The nodes between them are connected by inductor L and load R. L The load R is then connected to the negative terminal of the input voltage Vin. L A capacitor Co is connected in parallel. The rated power PR of the buffer resistor Rsn and the value of the buffer capacitor Csn are determined according to the design method of a buffer circuit for removing noise from DC-DC switching nodes.

[0061] Compared with the prior art, the present invention has the following advantages and beneficial effects:

[0062] (1) This invention efficiently removes high-order harmonic noise from the switching nodes of the DC-DC converter by quantizing the parameters of the RC buffer circuit and minimizes additional power consumption.

[0063] (2) This invention aims to achieve a balance between optimal damping effect and loss. Through experimental methods, Csn = 2Cp, and the theoretical loss is P_loss_min(invention) = 0.5 * (2Cp) * Vin² * fsw = 1 * Cp * Vin² * fsw. Traditional critical damping methods, such as the Severns formula, aim to achieve critical damping and typically recommend Cs ≥ 4Cp. Their theoretical minimum loss is:

[0064] P_loss_min(traditional) = 0.5 * (4Cp) * Vin² * fsw = 2 * Cp * Vin² * fsw. Therefore, theoretically, under the premise of achieving similar noise suppression effect, the theoretical switching loss of this invention is only half that of the traditional classical method. This proves its advantage of "minimizing additional power consumption" in principle.

[0065] (3) The present invention quantifies and correlates parameters: establishes a mathematical mapping chain of ringing frequency fr → parasitic capacitance Cp → buffer resistor Rsn / buffer capacitor Csn, eliminating the trial and error process.

[0066] (4) The present invention adopts a loss optimization mechanism: by accurately matching Rsn=Z0, the critical state of damping is ensured, and the additional loss caused by over-damping is avoided.

[0067] (5) The present invention proposes a probe grounding adapter method to realize the measurement of parasitic parameters and the accurate extraction of ringing frequency in actual engineering, suppress the influence of parasitic parameters of the measurement system, and improve the reliability of measurement. Attached Figure Description

[0068] Figure 1 Flow chart of the present application;

[0069] Figure 2 Typical buck converter circuit diagram;

[0070] Figure 3 Typical buck converter circuit diagram; Figure 2 Equivalent circuit diagram including parasitic parameters;

[0071] Figure 4 Switching node ringing noise waveform diagram;

[0072] Figure 5 RC snubber circuit access position schematic diagram;

[0073] Figure 6 Buffer circuit energy transfer schematic diagram, wherein (a) is the energy transfer schematic diagram of the buffer circuit when the high side switch is turned on; (b) is the energy transfer schematic diagram of the buffer circuit when the low side switch is turned on;

[0074] Figure 7 Ringing frequency actual waveform diagram;

[0075] Figure 8 Parallel test capacitor Ctest circuit;

[0076] Figure 9 Switching node ringing noise waveform diagram without snubber circuit;

[0077] Figure 10 Switching node ringing noise waveform diagram with RC snubber circuit. DETAILED DESCRIPTION

[0078] The present application will be further described in conjunction with the embodiments below, but the embodiments of the present application are not limited thereto.

[0079] Example 1:

[0080] As shown in the typical buck converter, the equivalent circuit including parasitic parameters is shown in Figure 2 As shown in the typical buck converter, the equivalent circuit including parasitic parameters is shown in Figure 3 As shown in the typical buck converter, the equivalent circuit including parasitic parameters is shown in

[0081] 1. Core elements include:

[0082] Input voltage V IN ;

[0083] Input filter capacitor C IN , providing local high-frequency current path for switching operation;

[0084] SW H : High side (upper tube) switching device (such as MOSFET);

[0085] SW L : Low side (lower transistor) switch device (e.g. MOSFET or synchronous rectifier).

[0086] 2. Distributed parasitic inductance

[0087] including parasitic inductance L P1 ~L P4 , where:

[0088] L P1 : Loop parasitic inductance from source of high side switch SW H to input capacitor C IN .

[0089] L P2 : Loop parasitic inductance from drain of low side switch SW L to ground (or to C IN negative).

[0090] L P3 and L P4 : Commonly represent the parasitic inductance generated by the traces connecting the switch node and the power inductor.

[0091] These inductances are not actual components, but parasitic parameters generated by PCB traces, component leads, etc., and are the main cause of high frequency ringing and EMI problems.

[0092] 3. Node parasitic capacitance

[0093] including node parasitic capacitance C P1 and node parasitic capacitance C P2 , where:

[0094] C P1 : Total parasitic capacitance of switch node (SW H point) to ground.

[0095] C P2 : Parasitic capacitance of drain of low side switch SW L to ground (usually output capacitance Coss of SW L ).

[0096] These capacitances are the parasitic capacitances of the switch node to ground, mainly composed of junction capacitance of the switch device and layout stray capacitance.

[0097] 4. Equivalent model of capacitor

[0098] For a real capacitor, its high frequency behavior is not ideal. ESR (Equivalent Series Resistance) and ESL (Equivalent Series Inductance) are two key parasitic parameters existing in a real capacitor. Together with the ideal capacitance Co, they form the complete equivalent model of a capacitor. ESR causes the capacitor to heat up when passing current and increases voltage ripple, while ESL limits the high frequency performance of the capacitor, making it lose decoupling effect and generate switching noise after exceeding the self-resonant frequency.

[0099] 5. RC snubber circuit

[0100] RSNB: snubber resistor

[0101] CSNB: snubber capacitor

[0102] Circuit working mechanism:

[0103] When the switch tube (SW H or SW L ) is switched at high speed, the rapidly changing current (di / dt) will excite the resonance loop composed of L P1 ~L P4 parasitic inductance and C P1 , C P2 parasitic capacitor, generating strong high-frequency ringing (Ringing) and voltage overshoot (Overshoot) at the switch node (SW). The external RC snubber circuit (RSNB + CSNB) provides a damping path for the resonance loop, consuming its energy, thereby effectively suppressing ringing and overshoot, reducing electromagnetic interference (EMI). However, the parasitic inductance ESL of the snubber capacitor itself will limit the high frequency response capability of the path, so when selecting CSNB, a ceramic capacitor with low ESL (such as NPO / COG material) should be selected, and a compact layout should be adopted to minimize its impact.

[0104] Figure 4 The figure shows the high-frequency ringing (Ringing) phenomenon generated at the moment when the switch node (SW node) of the switch power supply (such as DC-DC converter) is turned off.

[0105] Figure 5 The figure shows the access position of the RC snubber circuit of the present application between the switch node and the ground GND. The energy transfer principle of the RC snubber circuit is shown in Figure 6 .

[0106] Stage one: charging (absorbing energy)

[0107] Timing: at the moment when SW H is turned off and the voltage of the SW node rises sharply.

[0108] Process: The sharp rising voltage (high dv / dt) will charge the buffer capacitor C SNB . The current path is: SW node → R SNB → C SNB → GND, as shown in (a). Figure 6

[0109] Action: The charging process of C SNB absorbs part of the energy that would otherwise excite the LC resonance loop (parasitic inductance and capacitance). This effectively suppresses the voltage overshoot, reducing the voltage peak.

[0110] Phase 2: Resistor energy consumption

[0111] Timing: During the entire charging process of C SNB and the subsequent discharging process.

[0112] Process: Since the charging and discharging loop always has a buffer resistor R SNB in series, the current flowing through R SNB will generate I²R SNB heat loss.

[0113] Core role: This is the most critical step of the RC buffer circuit. R SNB directly consumes the electric field energy absorbed by C SNB in the form of heat. This process damps the resonance, effectively eliminating the ringing. If there is only a capacitor and no resistor, the absorbed energy will be re-released back to the circuit during the resonance process, with limited effect or even worse.

[0114] Phase 3: Discharge (release remaining energy)

[0115] Timing: When SW H is turned on again, the SW node voltage drops from high (close to VIN) to low (close to GND).

[0116] Process: At this time, the buffer capacitor C SNB charged to a high voltage will discharge through R SNB and the conducting SW H . The discharge current path is: C SNB (+) → R SNB → SW H → GND → C SNB (-), as shown in (b). Figure 6

[0117] Action: Complete an energy cycle. The discharge current will also pass through R SNB ​​The energy is dissipated, and the remaining energy is consumed, ready for the next switching cycle.

[0118] Summary:

[0119] The RC snubber circuit is not "eliminating" energy, but a "mover" and "converter" of energy. It absorbs the harmful, potentially oscillatory high-frequency electromagnetic energy through the capacitor C SNB , and then converts it safely into heat energy dissipated through the resistor R SNB . This "charging (absorption) - resistance energy dissipation (conversion) - discharging (resetting)" cycle continuously suppresses voltage spikes and ringing, thereby significantly improving EMI and improving system reliability.

[0120] As Figure 1 shown, the present application provides a design method of a snubber circuit for removing DC-DC switching node noise, determining the parameters of the snubber resistor and the snubber capacitor in the RC snubber circuit, specifically comprising:

[0121] Step S1, measuring the ringing frequency fr of the resonant circuit switching node:

[0122] Using an oscilloscope probe to directly contact the switching node (except for the ground lead, using a ground adapter to minimize inductance), capturing the switching node ringing waveform, and extracting the fundamental frequency, i.e. the ringing frequency fr;

[0123] Step S2, connecting a test capacitor Ctest in parallel between the switching node and the ground, and adjusting the value of the test capacitor Ctest to make the new ringing frequency fr_new satisfy: fr_new=fr / 2;

[0124] According to the test capacitor Ctest, the parasitic capacitor Cp is calculated as: Cp=Ctest / 3;

[0125] The derivation process is as follows:

[0126] Principle: When no snubber circuit is added, the ringing frequency fr of the resonant circuit is: fr=1 / (2π* ).

[0127] After connecting the test capacitor Ctest in parallel, the total capacitance becomes (Cp+Ctest), and the new ringing frequency fr_new is: fr_new=1 / (2π* ).

[0128] Objective: We adjust Ctest to make the new frequency fr_new become half of the original frequency fr, i.e. fr_new=fr / 2.

[0129] Substitute the formula to establish the equation:

[0130] 1 / (2π* )=(1 / (2π* )) / 2;

[0131] Simplify the solution:

[0132] Multiply both sides by 2π, and approximate: 1 / =1 / (2* );

[0133] Take the reciprocal of both sides: =2* ;

[0134] Square both sides: Lp*(Cp+Ctest)=4*Lp*Cp;

[0135] Divide both sides by Lp(Lp≠0): Cp+Ctest=4*Cp;

[0136] Move the term to solve: Ctest=4Cp-Cp, i.e. Ctest=3Cp.

[0137] Therefore: Cp=Ctest / 3.

[0138] Conclusion: When the capacity of the parallel test capacitor Ctest is exactly three times the capacity of the parasitic capacitor Cp, the resonance frequency will be reduced to half of the original frequency. We can find the Ctest that makes the frequency halve through experiments, and then we can deduce the exact value of Cp. The relationship Cp=Ctest / 3 is based on the strict mathematical derivation of the resonance frequency formula, and it is accurate.

[0139] According to the parasitic capacitance Cp and the ringing frequency fr, calculate the characteristic impedance Z0, Z0=1 / (2πfrCp);

[0140] Further determine the buffer resistance Rsn, Rsn=Z0;

[0141] Then calculate the buffer capacitance Csn according to the parasitic capacitance Cp, Csn=2×Cp;

[0142] Finally, according to the buffer capacitance Csn, the input voltage Vin and the switching frequency fsw, determine the rated power PR of the buffer resistance Rsn: PR≥2×(CsnVin 2 fsw / 2)=CsnVin 2 fsw.

[0143] Take the input voltage of the input voltage as an example (switching frequency fsw=500kHz):

[0144] 1. The measured ringing frequency fr=217.4MHz, as Figure 7 shown;

[0145] 2. Parallel test capacitor Ctest=680pF reduces ringing frequency to 108.7MHz; as shown in the dashed box, C Figure 8 P0 .

[0146] 3. Calculate parasitic capacitance Cp: Cp=680 / 3≈227pF;

[0147] 4. Calculate characteristic impedance: Z0=1 / (2π×217.4e 6 ×227e −12 )≈32.1Ω; take Rsn=Z0=33Ω;

[0148] 5. Calculate snubber capacitor Csn: Csn=2×227pF=454pF, take Csn=470pF;

[0149] 6. Resistor power: PR≥470e −12 ×12 2 ×500e 3 =40.3mW, select resistor with rated power PR=100mW.

[0150] Note that the resistor power calculation value 40.3mW is the average power consumed by the resistor calculated theoretically. It represents the minimum power dissipation capability that the resistor needs to withstand under ideal conditions.

[0151] Selected value (100mW): This is the actual rated power of the resistor selected.

[0152] Reasons for differences and advantages:

[0153] 1. Derating: This is a core principle in electronic engineering to ensure reliability and life. It is usually required that the working stress of components (such as power, voltage, temperature) should be 50%-80% lower than the maximum rated value. Let a resistor with rated power 100mW consume 40.3mW of power, the power consumption derating rate is (100-40.3) / 100≈60%, which is a very reasonable and robust design margin.

[0154] 2. Deal with transient impact: The instantaneous power during switching may be much higher than the average power. Selecting a resistor with higher rated power can better withstand these transient thermal shocks and avoid damage due to overheating.

[0155] 3. Tolerance and fluctuations: The input voltage Vin and switching frequency fsw may fluctuate, and load changes will also affect the waveform, resulting in actual power consumption that may be slightly higher than the theoretical value. Reserving a margin is necessary.

[0156] ​The application adopts tests to verify the effect, and compares the circuit without a buffer circuit with the RC buffer circuit (wherein, Rsn = 33 Ω, Csn = 470 pF), and the results are as shown in Figure 9 and Figure 10 .

[0157] After the RC buffer circuit is used, the ringing amplitude is reduced by more than 20 dB; the full load efficiency loss is less than 0.8% (the loss of the traditional trial and error method is about 1.5%).

[0158] The application eliminates hundreds of MHz high-order harmonics through the precise damping resonant loop, effectively suppresses noise, is suitable for Buck, Boost, Buck-Boost and other topologies, and has universality in engineering; only 1 resistor + 1 capacitor are needed, without a magnetic core element, and has a low-cost advantage.

[0159] Embodiment 2

[0160] As shown in Figure 5 , a circuit for removing DC-DC switching node noise includes an input voltage Vin, a switching tube SW H and a switching tube SW L which are connected in series to form a loop, a filter capacitor Cin is connected in parallel across the input voltage Vin, an RC buffer circuit is connected in parallel with the switching tube SW L , the RC buffer circuit includes a buffer resistor Rsn and a buffer capacitor Csn connected in series, an inductor L is connected between the nodes of the switching tube SW H and the switching tube SW L , a load R L is connected to the negative terminal of the input voltage Vin, and a capacitor Co is connected in parallel with the load R L , and the rated power PR of the buffer resistor Rsn and the value of the buffer capacitor Csn are determined as follows:

[0161] Step S1, measure the ringing frequency fr of the resonant loop switching node:

[0162] Use an oscilloscope probe to directly contact the switching node (except for the ground lead, use a ground adapter to minimize inductance), capture the ringing waveform of the switching node, and extract the fundamental frequency, i.e. the ringing frequency fr;

[0163] Step S2, connect a test capacitor Ctest in parallel between the switching node and the ground, and adjust the value of the test capacitor Ctest so that the new ringing frequency fr_new satisfies: fr_new = fr / 2;

[0164] According to the test capacitor Ctest, the parasitic capacitor Cp is calculated as Cp = Ctest / 3;

[0165] The characteristic impedance Z0 is calculated according to the parasitic capacitance Cp and the ringing frequency fr, Z0=1 / (2πfrCp);

[0166] The snubber resistance Rsn is further determined, Rsn=Z0;

[0167] The snubber capacitance Csn is calculated according to the parasitic capacitance Cp, Csn=2xCp;

[0168] Finally, the rated power PR of the snubber resistance Rsn is determined according to the snubber capacitance Csn, the input voltage Vin and the switching frequency fsw, PR≥2×(CsnVin 2 fsw / 2)=CsnVin 2 fsw.

[0169] Although the present application has been described with reference to the explanatory embodiments thereof, the above embodiments are merely the preferred embodiments of the present application, and the embodiments of the present application are not limited to the above embodiments, and it should be understood that those skilled in the art can design many other modifications and embodiments, which will fall within the scope and spirit of the principles disclosed in the present application.

Claims

1. A design method of a buffer circuit for removing DC-DC switching node noise, characterized by, The application comprises the following steps: S1, measuring the ringing frequency fr of the resonant loop switch node; S2, determining the test capacitance Ctest in combination with the ringing frequency fr, calculating the parasitic capacitance Cp according to the test capacitance Ctest, calculating the characteristic impedance Z0 according to the parasitic capacitance Cp and the ringing frequency fr, determining the snubber resistance Rsn, calculating the snubber capacitance Csn according to the parasitic capacitance Cp, and finally determining the rated power PR of the snubber resistance Rsn according to the snubber capacitance Csn, the input voltage Vin and the switching frequency fsw.

2. The design method of a buffer circuit for removing noise at a DC-DC switching node according to claim 1, characterized in that, The method for measuring the ringing frequency fr of the resonant loop switch node is as follows: using an oscilloscope probe to directly contact the switch node, capturing the ringing waveform of the switch node, and extracting the fundamental frequency, i.e. the ringing frequency fr.

3. The design method of a buffer circuit for removing noise at a DC-DC switching node according to claim 2, characterized in that, The oscilloscope removes the ground lead and adopts a ground adapter to minimize inductance.

4. The design method of a buffer circuit for removing noise at a DC-DC switching node according to claim 1, characterized in that, The method for determining the test capacitance Ctest in combination with the ringing frequency fr is as follows: connecting the test capacitance Ctest in parallel between the switch node and the ground, and adjusting the value of the test capacitance Ctest so that the new ringing frequency fr_new satisfies fr_new=fr / 2.

5. The design method of a buffer circuit for removing noise at a DC-DC switching node according to claim 1, wherein The calculation formula for calculating the parasitic capacitance Cp according to the test capacitance Ctest is Cp=Ctest / 3.

6. The method of claim 5, wherein the method further comprises: The calculation formula for calculating the characteristic impedance Z0 according to the parasitic capacitance Cp and the ringing frequency fr is Z0=1 / (2πfrCp).

7. The design method of a buffer circuit for removing noise at a DC-DC switching node according to claim 6, wherein The calculation formula for determining the snubber resistance Rsn is Rsn=Z0.

8. The method of claim 7, wherein the method further comprises: The formula for calculating the snubber capacitance Csn according to the parasitic capacitance Cp is Csn=2xCp.

9. The design method of a buffer circuit for removing noise at a DC-DC switching node according to claim 8, wherein, The calculation formula for determining the rated power PR of the buffer resistor Rsn according to the buffer capacitor Csn, the input voltage Vin and the switching frequency fsw is: PR≥2×(CsnVin 2 fsw / 2)=CsnVin 2 fsw.

10. A circuit for removing DC-DC switching node noise, comprising: This includes the input voltage Vin, which is connected in series to form a circuit, and the switching transistor SW. H and switching transistor SW L A filter capacitor Cin is connected in parallel across the input voltage Vin, and the switching transistor SW L An RC snubber circuit is connected in parallel, the RC snubber circuit including a snubber resistor Rsn and a snubber capacitor Csn connected in series, and the switching transistor SW H and switching transistor SW L The nodes between them are connected by inductor L and load R. L The load R is then connected to the negative terminal of the input voltage Vin. L A capacitor Co is connected in parallel. The rated power PR of the buffer resistor Rsn and the value of the buffer capacitor Csn are determined according to the design method of a buffer circuit for removing noise from DC-DC switching nodes as described in any one of claims 1-9.

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