Calculation method and device based on data flow diagram

Abstract

The embodiment of the invention provides a method for carrying out calculation based on a data flow graph (DFG) and related equipment. The method comprises the steps that a first operator obtains a plurality of data values from a second operator, the data flow diagram comprises the first operator and the second operator, and the data values are stored in a plurality of instruction units corresponding to the second operator in the DFG respectively; the first operator calculates an output result of the first operator according to the plurality of data values in the second operator, and the plurality of data values in the second operator are input of the first operator. By the proposed techniques, cycling or recursion may be performed in the DFG.

Description

Technical Field

[0001] The embodiments of this application relate to the field of data processing, and more specifically, to a method and related apparatus for performing calculations based on a dataflow graph (DFG). Background Technology

[0002] Dataflow architecture is a computer architecture that differs significantly from traditional von Neumann or control flow architectures. The latter execute instructions sequentially, while the former lacks a program counter. Dataflow architecture represents a program as a data flow graph (DFG), where nodes are "operators," and directed edges between them are "channels" through which immutable data values ​​pass. Operators are evaluated when data is available on all input channels. The completion of evaluation makes the resulting data available to operators at the end of the output channels.

[0003] To our knowledge, all existing dataflow architectures maintain a one-to-one relationship between operators and instruction units: the program is loaded into memory as a DFG (Data Flow Group), each operator is mapped to an instruction unit, and their execution produces a computational package. Instruction units, as atomic containers for input and output data, cannot store multiple data values. Therefore, all existing dataflow architectures are unsuitable for loops or recursion.

[0004] Therefore, figuring out how to perform loops or recursion in a DFG is a challenge. Summary of the Invention

[0005] Embodiments of this application provide a method and related apparatus for performing calculations based on a data flow graph (DFG). This technical solution allows for looping or recursion within the DFG.

[0006] According to a first aspect, embodiments of this application provide a method for performing calculations based on DFG, wherein the method includes:

[0007] The first operator obtains multiple data values ​​from the second operator. The data flow graph includes the first operator and the second operator, wherein the multiple data values ​​are respectively stored in multiple instruction units corresponding to the second operator in the DFG.

[0008] The first operator calculates its output based on the plurality of data values ​​in the second operator, wherein the plurality of data values ​​in the second operator are the inputs of the first operator.

[0009] Based on the above method, multiple instruction units are created for an operator, such that each instruction unit can be used to store the operation package during each recursion or each loop.

[0010] In one possible design, before the first operator obtains multiple data values ​​from the second operator, the method further includes: creating the multiple instruction units corresponding to the second operator in the DFG based on whether recursive or cyclic computation exists in the DFG.

[0011] In one possible design, the method further includes destroying the plurality of instruction units when the calculation corresponding to the second operator is completed.

[0012] In one possible design, the second operator is stored in a first memory, and the plurality of instruction units are stored in a second memory, the first memory being different from the second memory.

[0013] In one possible design, the first memory is a fast read / slow write memory, and the second memory has a balanced read and write operation speed.

[0014] In one possible design, the peak capacity of the second memory is determined by the number of operators in the DFG and the number of instruction units corresponding to each operator.

[0015] In one possible design, the DFG is used to calculate the nth Fibonacci number.

[0016] According to a second aspect, embodiments of this application provide a computing device having the function of implementing the method described in the first aspect. The function can be implemented in hardware or by hardware executing corresponding software. The hardware or software includes one or more modules corresponding to the function.

[0017] According to a third aspect, embodiments of this application provide a computer-readable storage medium including instructions. When the instructions are executed on a computer, they cause the computer to perform the methods of the first aspect or any possible design of the first aspect.

[0018] According to a fourth aspect, embodiments of this application provide a computing device including a processor, a memory, and a communication interface. The processor is connected to the memory and the communication interface. The memory is used to store instructions, the processor is used to execute the instructions, and the communication interface is used to communicate with other network elements under the control of the processor. When the processor executes the instructions stored in the memory, it causes the processor to perform the methods described in the first aspect or any possible design of the first aspect.

[0019] According to a fifth aspect, embodiments of this application provide a computing device cluster including at least one computing device, wherein the computing device includes a processor and a memory coupled to the processor, wherein the memory is used to store a computer program, and the processor is used to invoke and run the computer program stored in the memory to cause the computing device to perform the methods of the first aspect or any possible design of the first aspect.

[0020] According to a sixth aspect, a chip system is provided, wherein the chip system includes a memory and a processor, the memory being used to store a computer program, and the processor being used to invoke the computer program from the memory and run the computer program to cause a server on which the chip resides to perform the methods described in the first aspect or any possible design of the first aspect.

[0021] According to a seventh aspect, a computer program product is provided, wherein when the computer program product is run on a server, the server is caused to perform the methods described in the first aspect or any possible design of the first aspect. Attached Figure Description

[0022] One or more embodiments are illustrated by way of example with the accompanying drawings, which are not intended to limit the embodiments. Elements with the same reference numerals in the drawings are shown as similar elements, and the drawings are not limited to scale, wherein:

[0023] Figure 1 This is a schematic diagram of a method for performing calculations based on a data flow graph (DFG) provided in an embodiment of this application;

[0024] Figure 2 An example DFG of the dataflow procedure for calculating factorials is shown;

[0025] Figure 3 A schematic diagram of a primitive architecture similar to a dataflow machine is shown;

[0026] Figure 4 A schematic diagram illustrating the evaluation of the data stream factorial algorithm is shown.

[0027] Figure 5 A schematic diagram is shown for calculating the nth Fibonacci number;

[0028] Figure 6 This is a schematic block diagram of a computing device provided in an embodiment of this application;

[0029] Figure 7 This is a schematic block diagram of a computing device provided in an embodiment of this application. Detailed Implementation

[0030] The technical solutions in the embodiments of this application are clearly and completely described below with reference to the accompanying drawings. It is obvious that the described embodiments are merely some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of this application.

[0031] In the specification, claims, and drawings of this application, the term "comprising" and any other variations thereof are intended to cover a non-exclusive inclusion. For example, a process, method, system, product, or apparatus that comprises a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to the process, method, system, product, or apparatus.

[0032] This application presents various aspects, embodiments, or features within the context of systems comprising multiple devices, components, modules, etc. It should be understood and appreciated that various systems may include additional devices, components, modules, etc., and / or may exclude all devices, components, modules, etc., discussed in conjunction with the accompanying drawings. Furthermore, combinations of these approaches may also be used.

[0033] Furthermore, in the embodiments of this application, the words "exemplary," "for example," etc., are used to indicate examples or illustrations. Any embodiment or design described as "exemplary" in this application should not be construed as a preferred or advantageous embodiment that is superior to other embodiments or designs. Rather, the word "exemplary" is used to present a concept in a specific manner.

[0034] In this application, "related" and "corresponding" can sometimes be used interchangeably. It should be noted that, without emphasizing the distinction, they have the same meaning.

[0035] The business scenarios described in the embodiments of this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided by the embodiments of this application. Even if the architecture evolves and new business scenarios emerge, the technical solutions provided by the embodiments of this application are still applicable to solving similar technical problems.

[0036] For ease of description, the following explains several concepts involved in the embodiments of this application.

[0037] An arithmetic logic unit (ALU) is a combinational digital circuit that performs arithmetic and bitwise operations on integer binary numbers.

[0038] The central processing unit (CPU), also known as a microprocessor or simply a processor, is an electronic circuit that executes instructions, including computer programs.

[0039] A data flow graph (DFG) is a graph that represents the data dependencies between multiple operations.

[0040] Microarchitecture is the way a given instruction set architecture is implemented in a specific processor.

[0041] Random access memory (RAM) is a form of computer memory that can be read and changed in any order, and is typically used to store working data and machine code.

[0042] Recursion is a method for solving computational problems where the solution depends on the solutions of smaller instances of the same problem.

[0043] Garbage collection (GC) is a form of automatic memory management in which the garbage collector attempts to reclaim memory that has been allocated by the program but is no longer referenced; this memory is called garbage.

[0044] Dataflow architecture is a computer architecture that differs significantly from traditional von Neumann or control flow architectures. The latter execute instructions sequentially, while the former lacks a program counter. Dataflow architecture represents a program as a data flow graph (DFG), where nodes are "operators," and directed edges between them are "channels" through which immutable data values ​​pass. Operators are evaluated when data is available on all input channels. The completion of evaluation makes the resulting data available to operators at the end of the output channels.

[0045] To our knowledge, all existing dataflow architectures maintain a one-to-one relationship between operators and instruction units: the program is loaded into memory as a DFG (Data Flow Group), each operator maps to an instruction unit, and their execution produces a computational package. Instruction units, as atomic containers for input and output data, cannot store multiple data values. Therefore, instruction units are unsuitable for loops or recursion.

[0046] To address the aforementioned issues, embodiments of this application provide a method and apparatus for performing calculations based on a data flow graph (DFG), which allows for looping or recursion within the DFG.

[0047] Figure 1This is a schematic diagram of a method for performing computations based on a data flow graph (DFG). The method can be executed by a device for DFG-based computations, or by a module or unit within that device. The method specifically includes the following steps.

[0048] Step 110: The first operator obtains multiple data values ​​from the second operator.

[0049] For example, a data flow graph includes a first operator and a second operator.

[0050] In this embodiment, the first operator obtains multiple data values ​​from the second operator, wherein the multiple data values ​​are respectively stored in multiple instruction units corresponding to the second operator in the DFG. That is, the second operator corresponds to multiple instruction units, one data value is stored in one instruction unit, and the first operator obtains multiple data values ​​from the multiple instruction units corresponding to the second operator.

[0051] In some embodiments, before the first operator obtains multiple data values ​​from the second operator, the first operator creates multiple instruction units corresponding to the second operator based on whether there is recursive or cyclic computation in the DFG.

[0052] In some embodiments, after the first operator creates a plurality of instruction units corresponding to the second operator in the DFG, the first operator destroys the plurality of instruction units when the computation corresponding to the second operator is completed.

[0053] The best way to demonstrate this solution is through examples. Figure 2 A sample DFG (Data Flow Governance Form) is shown, illustrating a data flow procedure for calculating factorials. Nodes are operators, and the arcs between them are channels through which data tags can pass. Each arc has a direction representing the dependency between operators: an operator that arrives at a node is an operator that expects data.

[0054] Figure 2 Represent this code as a DFG, where nodes are atoms and directed edges are channels through which data is transferred. The atom "eq" depends on "x", so the arrow points to "eq". Dashed lines represent recursion. The atom "mul" depends on "if", while the atom "if" depends on "mul". Each node is a potential data source that other nodes may depend on. When all the data in a node is available, the operators inside the node begin to compute new data. The operator "if" is a control flow operator; it does not compute new data but simply uses the data already on its input arcs, copying one of them as the output.

[0055] Therefore, in Figure 2In the case of recursion or loops in the DFG shown, it is understandable that the operator "mul" is executed at least twice.

[0056] In one possible implementation, the following is a recursive dataflow algorithm for calculating factorial 3 in EO, an object-oriented dataflow programming language (assuming atoms "if", "eq", "dec", and "mul" are defined):

[0057]

[0058] Here, the first line creates a copy (or instance) of the "if" object and names it "f," expecting the following three lines to include the three parameters of the copy of the "if" object being created. The second line creates the first parameter of the "if" object, which is a copy of the "eq" object with two parameters: the input object "x" and the integer "1". The third line creates the second parameter of the copy of the "if" object: the integer "1". The fourth line creates the third parameter of the copy of the "if" object, which itself is a copy of the "mul" object with two parameters: "x" and "(f(dec x))".

[0059] In another possible implementation, the same algorithm can be written in Lisp, a functional dataflow programming language:

[0060]

[0061]

[0062] Here, in the first line, the function "f" is defined as having one parameter "x". The following three lines define the body of the function f.

[0063] In another possible implementation, the imperative equivalent of this recursive algorithm can be written in the C programming language:

[0064]

[0065] In the embodiments of this application, for example, in Figure 2 In this context, the first operator is "if", and the second operator is "mul". The operator "mul" corresponds to multiple instruction units. A data value is stored in one instruction unit, and the operator "if" retrieves multiple data values ​​from the multiple instruction units corresponding to the operator "mul".

[0066] In one possible implementation, Figure 3 Multiple instruction units corresponding to operators in DFG were created. Figure 3Similar to the original architecture of the dataflow machine, its extension lies in that the instruction unit pool is maintained between the DFG and the arbitration network. Because of this pool, each operator in the DFG can have multiple instruction units, thus enabling recursion in dataflow programs.

[0067] like Figure 3 As shown, the data flow machine is designed as follows: (1) a set of “instruction units” in memory, wherein one instruction unit corresponds to each node of the DFG; (2) an “arbitration network” that receives “operation packets” from completed instruction units; (3) a set of “operation units” that convert operation packets into “data packets”; and (4) a “distribution network” that puts data (or references to data) into instruction units.

[0068] In one possible implementation, operators in the DFG are retained in memory and never change, while instruction units are retained in a memory pool. These instruction units are created when data is available in the input channels and destroyed when the computational evaluation of the data is complete. Unlike storing operators in memory, which stores instruction units in a memory pool, the memory pool of instruction units and DFG operators can be placed in different types of memory within the CPU to achieve higher performance; this separation may bring additional performance benefits.

[0069] In one possible implementation, since operators in a DFG are only loaded into memory once, while instruction units are created and destroyed throughout the program's lifetime, memory pools are more suitable for memory with balanced read and write operation speeds, while operators in a DFG can use fast read / slow write memory.

[0070] At the start and end of the program, the DFG is full, while the pool is empty. During program evaluation, the pool may reach its peak capacity. In one possible implementation, the peak capacity of the second memory is determined by the number of operators in the DFG and the number of instruction units corresponding to each operator.

[0071] Step 120: The first operator calculates the output result of the first operator based on multiple data values ​​in the second operator.

[0072] In one possible implementation, multiple data values ​​in the second operator are inputs to the first operator.

[0073] Figure 4 The evaluation process of the dataflow factorial algorithm is illustrated using a sequence diagram. There are 5 operators in the DFG and 15 instruction units with different lifetimes (these instruction units are represented by solid black vertical bars on the diagram).

[0074] For example, such as Figure 4As shown, the evaluation begins with the data available at node "x": this data is the positive integer value "3". A first instruction unit is created for "x", which stores the value "3". The presence of data at "x" triggers three operators simultaneously (the dataflow evaluation model is implicitly parallel): "eq", "dec", and "mul". Then, a first instruction unit is created for "eq", which stores the value "3". "eq" compares "3" with "1", and since they are not equal, "eq" sets FALSE as its output arc, outputting to "if". A first instruction unit is created for "if", which stores "FALSE". Then, "eq" sends the value "3" to "dec", creating a first instruction unit for "dec", which stores the value "3". Simultaneously, "dec" changes "3" to "2" and sends this new data to "x". Then, "dec" sends the value "3" to "mul", creating a first instruction unit for "mul", which stores the value "3".

[0075] like Figure 4 As shown, because "dec" sends the value "2" to "x", the evaluation begins with the new data available in the "x" node: the new data is the positive integer value "2". A second instruction unit is created for "x" to store the value "2". The presence of data at "x" triggers three operators simultaneously (the data flow evaluation model is implicitly parallel): "eq", "dec", and "mul". Then, a second instruction unit is created for "eq", which stores the value "2". "eq" compares "2" with "1", and since they are not equal, "eq" sets FALSE as its output arc, outputting to "if". A second instruction unit is created for "if", which stores "FALSE". Then, "eq" sends the value "2" to "dec", and a second instruction unit is created for "dec", which stores the value "2". Simultaneously, "dec" changes "2" to "1" and sends this new data to "x". Then, "dec" sends the value "2" to "mul", creating a second instruction unit for "mul", which is used to store the value "2".

[0076] like Figure 4As shown, because "dec" sends the value "1" to "x", the evaluation begins with the new data available in the "x" node: this new data is the positive integer value "1", and a third instruction unit is created for "x" to store the value "1". The presence of data at "x" triggers three operators simultaneously (the data flow evaluation model is implicitly parallel): "eq", "dec", and "mul". Then, a third instruction unit is created for "eq", which stores the value "1". "eq" compares "1" with "1", and since they are equal, "eq" sets TRUE to its output arc, outputting to "if". A third instruction unit is created for "if", which stores "TRUE". Then, "eq" sends the value "1" to "dec", and a third instruction unit is created for "dec", which stores the value "1". Simultaneously, "dec" changes "1" to "0" and sends this new data to "x". Then, "dec" sends the value "1" to "mul", creating a third instruction unit for "mul", which stores the value "1". "mul" takes the values ​​"1", "2", and "3" from the three instruction units it created, and multiplies them together, resulting in 6. The algorithm with 3 as input produces 6 as the factorial of 3.

[0077] exist Figure 4 In the sequence graph, when new data is available and must reach the receiving node through an edge, there are three types of situations: (1) the receiving node already has an available instruction unit - data arrives unit; (2) the receiving node has no unit - a new unit is born; (3) the receiving node already has a unit, but the edge is orange (it is a recursive edge) - a new unit is born.

[0078] This example demonstrates how the ability to create multiple cells for a single operator can be recursively implemented. During the evaluation of the factorial of 3, three cells are created for the operators “x”, “eq”, “dec”, “mul”, and “if”, respectively.

[0079] In one possible implementation, DFG is used to compute the nth Fibonacci number. A simple recursive algorithm for computing the nth Fibonacci number can be implemented as a dataflow program.

[0080] Figure 5 The algorithm is presented as a set of Φ-calculus expressions. This application implements the algorithm and evaluates it on Phie, a simulator for the ΦPU dataflow architecture. The goal of the experiments is to measure the performance of the instruction unit pool and the required peak capacity of the instruction unit pool.

[0081] Figure 5The symbols used consist of object definitions, which are operators in the data flow graph. The expression "v i (π)|→[...]” represents the vertex “v” in the graph. i The vertex has multiple slots / edges connecting it to other vertices. Edges can represent direct connections, such as "α0|→v6(π)", or dynamically assigned connections, such as "ρ|→ξ.ξ.α0". Some edges point to data, such as "Δ|→0x01", and others point to imperative ALU instructions, such as "λ|→int-add".

[0082] In one possible implementation, this set of Φ calculus expressions represents the following recursive Fibonacci algorithm described in the EO language:

[0083]

[0084] Here, the first line declares an abstract object "fibo" with a single parameter "x" (similar to how functions are declared in functional programming languages). The following lines then declare the object's body. It resembles the factorial program demonstrated earlier. The objects "plus" and "minus" are properties of the integer object (all scalar numbers described by EO are also objects).

[0085] In another possible implementation, a functional version of the algorithm can be rewritten using the C programming language:

[0086]

[0087] By using the scheme of this application in a dataflow microprocessor architecture, the following positive effects can be achieved:

[0088] 1. Because data tagging is eliminated, the complexity of the hardware architecture can be reduced;

[0089] 2. By using RAM relatively simply for the instruction unit pool, the CPU's data bandwidth can be increased;

[0090] 3. Loops and recursion can be used without any restrictions.

[0091] Figure 6 This is a schematic block diagram of a computing device 600 provided in an embodiment of this application. Figure 6 As shown, the computing device 600 includes an acquisition unit 601 and a computing unit 602.

[0092] The acquisition unit 601 is used to: acquire multiple data values ​​from the second operator through the first operator, wherein the data flow graph includes the first operator and the second operator, and the multiple data values ​​are respectively stored in multiple instruction units corresponding to the second operator in the DFG.

[0093] The calculation unit 602 is used for: the first operator to calculate the output result of the first operator based on multiple data values ​​in the second operator, wherein the multiple data values ​​in the second operator are the inputs of the first operator.

[0094] In some embodiments, the computing device 600 further includes a creation unit, configured to create a plurality of instruction units corresponding to the second operator in the DFG, based on whether recursive or cyclic computation exists in the DFG, before the acquisition unit acquires a plurality of data values ​​from the second operator.

[0095] In some embodiments, the computing device 600 further includes a destruction unit for destroying a plurality of instruction units when the calculation corresponding to the second operator is completed.

[0096] In some embodiments, the second operator is stored in the first memory, and a plurality of instruction units are stored in the second memory, wherein the first memory and the second memory are different.

[0097] In some embodiments, the first memory is a fast read / slow write memory, and the second memory has a balanced read and write operation speed.

[0098] In some embodiments, the peak capacity of the second memory is determined by the number of operators in the DFG and the number of instruction units corresponding to each operator.

[0099] In some embodiments, DFG is used to calculate the nth Fibonacci number.

[0100] It should be understood that the computing device 600 provided in this embodiment of the present application can correspond to the computing device in the above embodiments, and the above and other management operations and / or functions of each unit in the computing device are used to implement the corresponding steps of the above method. For the sake of brevity, further details are omitted here.

[0101] like Figure 7 As shown, the computing device 700 may include a transceiver 701, a processor 702, and a memory 703. The memory 703 may be used to store code, instructions, etc., executed by the processor 702.

[0102] It should be understood that the processor 702 can be an integrated circuit chip with signal processing capabilities. In implementation, the various steps of the above method embodiments can be completed by hardware integrated logic circuits in the processor or by software instructions. The processor can be a general-purpose processor, a central processing unit (CPU), a graphics processing unit (GPU), a neural processing unit (NPU), a system-on-chip (SoC), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. The processor can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this application. The general-purpose processor can be a microprocessor, or it can be any common processor. The steps of the methods disclosed in the embodiments of this application can be directly executed by a hardware decoding processor, or executed using a combination of hardware and software modules in the decoding processor. The software modules can be located in storage media that are well-established in the field, such as random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, or registers. The storage medium is located in memory, and the processor reads information from the memory and, in conjunction with the hardware in the processor, completes the steps of the above method.

[0103] It is understood that the memory 703 in the embodiments of this application can be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. Non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. Volatile memory can be random access memory (RAM) used as an external cache. By way of example, but not limitation, many forms of RAM can be used, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM), and direct rambus RAM (DR RAM).

[0104] It should be noted that the memory of the systems and methods described in this specification includes, but is not limited to, these memories and any other suitable types of memory.

[0105] Embodiments of this application also provide a system-on-a-chip (SoC), which includes an input / output interface, at least one processor, at least one memory, and a bus. The at least one memory is used to store instructions, and the at least one processor is used to invoke the instructions from the at least one memory to perform the operations of the methods described above.

[0106] Embodiments of this application also provide a computer storage medium, wherein the computer storage medium can store program instructions to execute any of the methods described above.

[0107] Alternatively, the storage medium may specifically be memory 703.

[0108] Those skilled in the art will recognize that the units and algorithm steps described in conjunction with the embodiments disclosed in this specification can be implemented by electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented by hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0109] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the above-described systems, devices, and units can be referred to the corresponding processes in the above method embodiments. Further details will not be repeated here.

[0110] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the described apparatus embodiments are merely exemplary. For example, the unit division is only a logical functional division, and other division methods may be used in actual implementation. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not performed. Furthermore, the mutual coupling or direct coupling or communication connection shown or discussed can be implemented through some interfaces. Indirect coupling or communication connection between devices or units can be implemented electronically, mechanically, or otherwise.

[0111] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0112] In addition, the functional units in the embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0113] When these functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for instructing a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the embodiments of this application. The aforementioned storage medium includes any medium capable of storing program code, such as a USB flash drive, a removable hard disk, read-only memory (ROM), random access memory (RAM), a magnetic disk, or an optical disk.

[0114] The above description is merely some specific implementations of this application and is not intended to limit the scope of protection of this application. Any variations or substitutions easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method for computing based on a data flow graph (DFG), characterized in that, comprises: a first operator obtains a plurality of data values from a second operator, wherein the dataflow graph comprises the first operator and the second operator, and the plurality of data values are respectively stored in a plurality of instruction units corresponding to the second operator in the DFG; the first operator calculates an output result of the first operator according to the plurality of data values in the second operator, wherein the plurality of data values in the second operator are inputs of the first operator.

2. The method of claim 1, wherein, Before the first operator obtains the plurality of data values from the second operator, the method further comprises: creating the plurality of instruction units corresponding to the second operator in the DFG according to whether there is a recursive calculation or a loop calculation in the DFG.

3. The method according to claim 1 or 2, characterized in that, The method further comprises: destroying the plurality of instruction units when the calculation corresponding to the second operator is completed.

4. The method according to any one of claims 1 to 4, characterized in that, The second operator is stored in a first memory, and the plurality of instruction units are stored in a second memory, and the first memory is different from the second memory.

5. The method of claim 4, wherein, The first memory is a fast read / slow write memory, and the second memory has balanced read / write operation speed.

6. The method according to claim 4 or 5, characterized in that, The peak capacity of the second memory is determined by the number of operators in the DFG and the number of instruction units corresponding to each operator.

7. The method according to any one of claims 1 to 6, characterized in that, The DFG is used to calculate the nth Fibonacci number.

8. A computing device, comprising: comprises: an obtaining unit, configured to: obtain a plurality of data values from a second operator by a first operator, wherein the dataflow graph comprises the first operator and the second operator, and the plurality of data values are respectively stored in a plurality of instruction units corresponding to the second operator in the DFG; a calculating unit, configured to: calculate an output result of the first operator according to the plurality of data values in the second operator by the first operator, wherein the plurality of data values in the second operator are inputs of the first operator.

9. The computing device of claim 8, wherein, The computing device further comprises: a creating unit, configured to: before the obtaining unit obtains the plurality of data values from the second operator, create the plurality of instruction units corresponding to the second operator in the DFG according to whether there is a recursive calculation or a loop calculation in the DFG.

10. The computing device of claim 8 or 9, wherein, The computing device further comprises: a destroying unit, configured to: when the calculation corresponding to the second operator is completed, destroy the plurality of instruction units.

11. The computing device of any of claims 8 to 10, wherein, The second operator is stored in a first memory, and the plurality of instruction units are stored in a second memory, and the first memory is different from the second memory.

12. The computing device of claim 11, wherein, The first memory is a fast read / slow write memory, and the second memory has balanced read / write operation speed.

13. The computing device of claim 11 or 12, wherein, The peak capacity of the second memory is determined by the number of operators in the DFG and the number of instruction units corresponding to each operator.

14. The computing device of any of claims 8 to 13, wherein, The DFG is used to calculate the nth Fibonacci number.

15. A computer-readable storage medium storing instructions, wherein, When the instructions are run on a server, the server is caused to perform the method according to any one of claims 1 to 7.

16. A cluster of computing devices, characterized in that, comprising at least one computing device, wherein the computing device comprises a processor and a memory coupled with the processor, wherein the memory is configured to store a computer program, and the processor is configured to invoke and run the computer program stored in the memory, so that the computing device performs the method according to any one of claims 1 to 7.

17. A computer program product, characterised in that, When the computer program product is run on a server, the server is caused to perform the method according to any one of claims 1 to 7.

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