Chemical nickel-chemical palladium-gold immersion (ENEPIG) as surface finish for embedded die attachment

Abstract

In embodiments herein, a surface finish (SF) is formed on conductive contacts of a package substrate for connection to an embedded interconnect bridge circuit module die. In some embodiments, the SF may be electroless nickel plating and electroless palladium immersion gold (ENEPIG). In other embodiments, SF may be gold leaching electroless palladium leaching (IGEPIG). In other embodiments, the SF may include an electrolytic palladium gold layer on the indium layer or on the ferrocobalt layer.

Description

[0001] Cross-reference to related applications This application claims priority to U.S. Patent Application No. 18 / 400878 (filed December 29, 2023, and entitled “ELECTROLESS NICKEL-ELECTROLESS PALLADIUM-IMMERSION GOLD (ENEPIG) AS ASURFACE FINISH FOR EMBEDDED DIE ATTACHMENTS”), which is incorporated herein by reference in its entirety. Background Technology

[0002] Circuit components, such as power delivery components like inductors and capacitors, can be embedded within the core of the packaging substrate of an integrated circuit package. However, embedding components has proven difficult due to various factors, such as thickness mismatch between the core and the component, which can cause the component to tilt or shift within the cavity. Attached Figure Description

[0003] Figure 1 The illustration shows an example multi-die integrated circuit package with an embedded interconnect bridge circuit module assembly.

[0004] Figures 2A-2E illustrate a first example process of embedding an interconnect bridge circuit module die in a packaging substrate according to an embodiment of the present disclosure.

[0005] Figure 3 The illustration shows an example material stack that can be deposited as a surface finish in the process shown in Figures 2A-2E, according to an embodiment of the present disclosure.

[0006] Figure 4 The illustration shows an example material stack that can be deposited as a surface finish in the process shown in Figures 2A-2E, according to an embodiment of the present disclosure.

[0007] Figure 5 The illustration shows an integrated circuit package that is manufactured according to the process described in Figures 2A-2E. Figure 3 Examples of material stacks.

[0008] Figure 6 The illustration shows an integrated circuit package that is manufactured according to the process described in Figures 2A-2E. Figure 3 Another example of a material stack.

[0009] Figure 7 The illustration shows an integrated circuit package that is manufactured according to the process described in Figures 2A-2E. Figure 4 Examples of material stacks.

[0010] Figures 8A-8E illustrate a second example process of embedding an interconnect bridge circuit module die in a packaging substrate according to an embodiment of the present disclosure.

[0011] Figure 9 The illustration shows an example material stack that can be deposited as a surface finish in the process shown in Figures 8A-8E, according to an embodiment of the present disclosure.

[0012] Figure 10 The illustration shows another example material stack that can be deposited in the process shown in Figures 8A-8E according to an embodiment of the present disclosure.

[0013] Figure 11 The illustration shows an integrated circuit package that is manufactured according to the process described in Figures 8A-8E. Figure 9 Examples of material stacks.

[0014] Figure 12 The illustration shows an integrated circuit package that is manufactured according to the process described in Figures 8A-8E. Figure 10 Examples of material stacks.

[0015] Figures 13A-13B The illustration may include an example system containing the architecture described in this article.

[0016] Figure 14 This is a top view of a wafer and die that may be included in a microelectronic assembly, according to any embodiment of the embodiments disclosed herein.

[0017] Figure 15 This is a cross-sectional side view of an integrated circuit device that may be included in a microelectronic assembly, according to any embodiment of the embodiments disclosed herein.

[0018] Figure 16 It is a block diagram of an example electrical device that may include a microelectronic assembly, based on any embodiment of the embodiments disclosed herein. Detailed Implementation

[0019] Embodiments of this disclosure relate to a process for embedding an interconnect bridge circuit module in a multi-die integrated circuit package. More specifically, embodiments herein pertain to techniques for forming a surface finish (SF) on conductive contacts of a package substrate, such as bumps (cavity-side bumps or CSBs) within a cavity of the package substrate, which will be connected to a die embedded within the cavity. As used herein, a cavity-side bump (CSB) may refer to a conductive contact of the package substrate connected to the bottom side of the interconnect bridge circuit module die embedded within the package substrate, for example, as... Figure 1As shown in the diagram. Due to increasing power delivery requirements, integrated circuit packaging substrates have increasingly incorporated embedded interconnect bridge circuit module dies including through-silicon vias (TSVs), which have conductive contacts on the top and bottom sides to allow power delivery through the embedded interconnect bridge circuit module die to the integrated circuit die coupled to the interconnect bridge circuit module die.

[0020] Typically, surface finishes can be formed using electroless nickel-plated palladium-plated immersion gold (ENEPIG), where nickel is deposited via electroless plating, palladium is also formed via electroless plating, and gold is deposited via immersion plating. In fact, ENEPIG has been used in multiple generations of integrated circuit package designs due to its good solder joint reliability (SJR) and electromigration properties. Surface finishes (SF) can refer to one or more material layers (e.g., metal layers) formed on solderable areas of a circuit board, such as conductive contacts on an integrated circuit package substrate. Some recent process flows have utilized electrolytic (e-lytic or elytic) SF (i.e., the SF is deposited using electroplating) comprising palladium and gold formed on cavity-side bumps (CSBs) of the package substrate for use with TSVs to connect to embedded interconnect bridge circuit module dies. However, for example, omitting nickel in the SF from the CSB can lead to SJR problems because it can potentially allow copper to diffuse into the palladium and gold layers to form uncontrolled copper-tin intermetallic compounds (IMCs). Additionally, to ensure minimal oxidation of the copper CSB, a higher palladium and gold layer may be required (since a nickel layer is absent). This can lead to the formation of PdSn4 and AuSn4 alloys, which are very brittle and cause failure (a condition known as palladium / gold embrittlement). Besides bath life issues from copper-contaminated gold baths, gold plating alone can also lead to porosity (due to the electrochemistry between copper and gold). Similar problems and effects have been observed with PdAu plating.

[0021] The embodiments described herein implement techniques capable of addressing and avoiding such problems. For example, some embodiments implement a process flow that allows the use of ENEPIG as the SF in an integrated circuit package substrate, which avoids potential SJR problems and issues related to the maximum current (Imax) limit caused by the use of ENEPIG SF by introducing Ni. Some embodiments implement a process flow that allows the use of ENEPIG SF in conjunction with a thinner nickel layer. However, other embodiments implement a process flow that allows the use of immersion gold electroless palladium immersion gold (IGEPIG) as the SF in an integrated circuit package substrate. Other embodiments implement a process flow that utilizes an SF that includes an indium layer in addition to palladium and gold layers, while other embodiments implement a process flow that utilizes an SF that includes a cobalt-iron layer in addition to palladium and gold layers.

[0022] Accordingly, embodiments of this disclosure can provide one or more advantages over existing process flows. As an example, the process flows described herein (e.g., those associated with electroless plating) can offer cost reduction opportunities due to the reduction of additional photolithography steps associated with the deposition of e-lytic SF materials. Furthermore, some embodiments can be implemented using existing process flow steps and tooling, thereby allowing for faster and cheaper implementation of such processes. Further, the embodiments herein can provide better SJR and Imax performance due to reduced formation of brittle IMCs and reduced IMC formation kinetics. Additionally, the embodiments involving electroless plating herein have already improved wettability due to complete coverage of the SF (including the pad side), resulting in low copper oxidation and uniform tin core adsorption. Other advantages may be apparent to those skilled in the art, and additional advantages are described below with respect to certain embodiments.

[0023] It will be understood that in the examples further shown and described below, the figures may not be drawn to scale and may not include all possible layers and / or circuit components. Additionally, it will be understood that while some figures illustrate orthogonal (e.g., perpendicular) boundaries between interfaces, the embodiments herein may implement such boundaries in a substantially orthogonal manner (e.g., within + / - 5 or 10 degrees) due to the manufacturing methods used to create such devices or for other reasons.

[0024] Referring now to the accompanying drawings, which are not necessarily drawn to scale, similar or identical numerals may be used in different drawings to represent the same or similar parts. The use of similar or identical numerals in different drawings does not mean that all drawings including similar or identical numerals constitute a single or identical embodiment. Similar numerals with different letter suffixes may represent different instances of similar components. The accompanying drawings are provided as examples and not as limiting illustrations of the various embodiments discussed in this document.

[0025] Figure 1 The illustration shows an example multi-die integrated circuit package 100 with an embedded interconnect bridge circuit module assembly 114. Package 100 includes a die layer 102 and vias 104 through the die layer 102. Accumulation layers 106 are formed on the top and bottom sides of the die layer 102, wherein accumulation layer 106A is on the top side of the die layer 102 and accumulation layer 106B is on the bottom side of the die layer 102. Accumulation layers 106 include metal traces (e.g., 107A-E) in the metallization layers as shown and pillars (e.g., 109) between the metallization layers to electrically couple components at the top of the package 100 to pads 110 at the bottom of the package. For example, layer 106 may provide a connection between an integrated circuit (IC) die 112 coupled to the top side of the package and a circuit board (e.g., motherboard, mainboard, etc.) via the pads 110 at the bottom of the package. Package 100 also includes an interconnect bridge circuit module assembly 114 located in the accumulation layer 106A, which electrically couples the first IC die 112A to the second IC die 112B. The interconnect bridge circuit module assembly 114 may include passive and / or active components to interconnect the IC dies 112. As shown, the interconnect bridge circuit module assembly 114 includes through-silicon vias (TSVs) to connect the top and bottom sides of the assembly 114. In some embodiments, the interconnect bridge circuit module assembly 114 may be an Intel® Embedded Multi-Die Interconnect Bridge (EMIB-T) with TSVs.

[0026] Figures 2A-2E illustrate a first example process 200 of embedding an interconnect bridge circuit module die in a package substrate according to an embodiment of the present disclosure. The process may include additional, fewer, or different operations compared to those shown or described below. In some embodiments, one or more of the illustrated operations include multiple operations, sub-operations, etc.

[0027] Reference Figure 2A, Example process 200 includes forming a dielectric accumulation layer 204 on a core layer 202 as shown. The accumulation layer includes materials related to those described above. Figure 1 The described example uses a similar metallization layer and struts. A laser stop layer 210 is then formed within an opening 208 in a photoresist layer 206 (e.g., a dry film resist (DFR) layer) on the accumulation layer 204. The laser stop layer 210 may comprise nickel or any other suitable material. Then, as shown in FIG2B, the photoresist layer 206 is removed, and an additional accumulation layer 212 is formed on the accumulation layer 204 as shown, including the formation of a dielectric accumulation layer in the region above the laser stop layer 210. Then, as... Figure 2CAs shown, cavity 214 is formed in the region above laser stop layer 210 (e.g., via laser drilling) until laser stop layer 210 is exposed, and then laser stop layer 210 can be removed (e.g., etched) to expose a set of conductive pads 215 in the metallization layer.

[0028] Referring then to FIG2D, a surface finish (SF) 216 is then formed (e.g., deposited) on pad 215. In some embodiments, the SF 216 may include Figure 3 The material stack shown can be an electroless nickel-plated palladium-plated immersion gold (ENEPIG) SF. That is, SF 216 may include: layer 302, comprising nickel on copper pads 215 within the cavity 214 of the package substrate; layer 304, comprising palladium on layer 302; and layer 306, comprising gold on layer 304. Layer 302 may be formed via electroless plating, layer 304 may be formed via electroless plating, and layer 306 may be formed via immersion plating, as implied by the name ENEPIG.

[0029] In some embodiments, the thickness of layer 302 may be between 5-10 μm (e.g., 7 μm), the thickness of layer 304 may be between 0.01-10 μm (e.g., 0.04 μm), and the thickness of layer 306 may be between 0.01-10 μm (e.g., 0.06 μm). Some existing dies 220 have copper pads 221 or 222 that are approximately 15 μm thick; however, because layer 302 in SF can be relatively thick (e.g., 7 μm thick), the embodiments herein instead implement dies 220 with pads 221 or 222 of reduced thickness (e.g., between 5-12 μm, such as approximately 10 μm). This avoids potential chip gap height problems, i.e., problems related to the position of the top surface of the embedded interconnect bridge circuit module die 220 relative to the top surface of the accumulation layer 212. These height mismatches can cause problems with interconnection with integrated circuit dies above die 220 or the top metallization layer of accumulation layer 212. When the interconnect bridge circuit module die 220 is attached to the cavity 214, additional issues related to filling the cavity may also exist. Any potential residual height difference can be adjusted in the additional accumulation layer to be formed or through a thicker non-conductive film (NCF) around the die 220.

[0030] Other embodiments may avoid changes to the pads 221, 222 of the die, and instead may include an SF having a layer 302 with a thickness of less than 500 nm, for example, between 100-200 nm (e.g., 150 nm thick), which avoids the SJR problem by including nickel, and also avoids potential chip gap height problems.

[0031] In other embodiments, SF 216 may includeFigure 4 The material stack shown can be an immersion gold electroless plating (IGEPIG) SF. That is, SF 216 may include: layer 402, comprising gold on copper pads 215 in the cavity 214 of the package substrate; layer 404, comprising palladium on layer 402; and layer 406, comprising gold on layer 404. Layer 402 may be formed by dip plating, layer 404 may be formed by electroless plating, and layer 406 may be formed by dip plating, as implied by the name IGIPG. The thickness of layer 402 may be between 0.01-0.04 μm (e.g., 0.02 μm), the thickness of layer 404 may be between 0.02-0.15 μm (e.g., 0.10 μm), and the thickness of layer 406 may be between 0.03-0.10 μm (e.g., 0.08 μm). As described above for the embodiment with a thinner nickel layer 302, these thicknesses avoid the chip gap height problem of existing interconnect bridge circuit module die 220 implementations (e.g., those with pads ~15µm thick). Additionally, such embodiments avoid the gold embrittlement problem seen with higher gold layer thicknesses in gold-plated-only implementations.

[0032] Now refer to Figure 2E An interconnect bridge circuit module die 220, including TSV 218, is placed within a cavity 214. The die 220 is attached using solder 223 such that at least some of the bottom pads 221 of the die 220 are electrically connected to SF 216 formed on pad 215. Subsequently, dielectric material (e.g., molding or accumulating material) can be placed within the remaining portion of the cavity 214 to secure or encapsulate the interconnect bridge circuit module die 220, and further, electrical contacts can be formed or positioned to contact the top pad 222, for example, to attach one or more integrated circuit dies (e.g., such as...). Figure 1 As shown in 112), they are interconnected or the integrated circuit die is connected to a circuit board (e.g., a motherboard) under the substrate.

[0033] While bridge circuit module dies are described herein, other types of dies may be embedded within cavities of the package substrate as described herein. For example, active circuit dies (e.g., integrated circuit dies) or another type of die (e.g., dies having one or more passive circuit components such as capacitors or inductors) may be embedded according to embodiments herein, instead of interconnect bridge circuit module dies, to interconnect multiple integrated circuit dies.

[0034] Figure 5 The illustration shows an integrated circuit package that is manufactured according to the process described in Figures 2A-2E. Figure 3 Example material stack 500. Specifically, Figure 5The illustration shows a cross-sectional view of an example solder joint between the pad (e.g., 221) of a die (e.g., 220) and the CSB of the package substrate (e.g., 215) when ENEPIG with a relatively thick nickel layer (e.g., ~7µm) is used as a surface finish. The solder 510 used can be tin-silver-copper (SnAgCu or SAC) solder or any other type of solder material, such as tin-silver or tin-copper solder chemistries. In some embodiments, the solder can be flowed / reflowed at 250-270°C.

[0035] Example stack 500 includes an IMC 501 formed between a CSB pad 215 of the package substrate and solder 510 for electrically connecting a die (e.g., 221) to the pad 215. Although shown in a particular layer, IMC 501 can be formed in a manner different from that shown. For example, IMC 501 can be distributed, or other IMCs can also be present in the solder joint, such as Cu-Sn or Cu-Sn-Ni based IMCs.

[0036] IMC 501 is formed on a first layer 502 comprising nickel and phosphorus (Ni-P). Layer 502 may be the same as or similar to layer 302. IMC 501 includes a first IMC 504 further comprising nickel and phosphorus (Ni3P and Ni), a second IMC 506 comprising tin, and a third IMC comprising copper, nickel, tin ((Cu,Ni)6Sn5), and palladium. Layer 502 may comprise approximately 10-35% phosphorus by weight, the first IMC 504 may comprise approximately 15-30% phosphorus by weight, and the third IMC 506 may comprise approximately 20-40% copper, approximately 20-40% nickel, and approximately 30-50% tin by weight.

[0037] Cross-sectional and elemental analysis performed on the solder joint may reveal the presence of (Cu,Ni)6Sn5IMC (and / or other IMCs as shown), and may reveal the presence of nickel and phosphorus in the nickel and palladium layers of ENEPIG (to ensure the use of an electroless technique). Additionally, because e-lytic NiPdAu SF requires a DFR, they can be formed into a stacked cylindrical shape with sharp corners (similar to copper bumps / pads, like 215). However, ENEPIG can be plated without a DFR, and therefore can be conformally plated with rounded corners on all sides of the copper bump 215 (e.g., with...). Figure 2D and Figure 2E (Similar in form to that shown). Accordingly, it will be understood that IMC can be compared with... Figure 5 The different forms / shapes shown are formed in the packaging substrate.

[0038] Figure 6 The illustration shows an integrated circuit package that is manufactured according to the process described in Figures 2A-2E. Figure 3 Another example of a material stack is material stack 600. Specifically, Figure 6 The illustration shows a cross-sectional view of an example solder joint between the pads (e.g., 221) of a die (e.g., 220) and the CSB of a package substrate (e.g., 215) when an ENEPIG with a thin nickel layer (e.g., ~0.15 μm) is used as a surface finish. The example stack 600 includes an IMC 601 formed between copper pads 215 and solder 606 (which can be any suitable solder material, e.g., SAC or another type of solder). Although shown in a particular layer, the IMC 5601 can be formed in a different manner than shown, e.g., dispersed. Furthermore, other IMCs may also be present in the solder joint, e.g., Cu-Sn or Cu-Sn-Ni based IMCs.

[0039] The IMC includes: a first IMC 602, comprising copper and tin (Cu3Sn); and a second IMC 604, comprising copper, nickel, and tin ((Cu,Ni)6Sn5) and palladium. The first IMC 602 may comprise approximately 60-75% copper and approximately 25-40% tin by weight. The second IMC 604 may comprise approximately 30-50% copper, approximately 10-30% nickel, and approximately 30-50% tin by weight.

[0040] Similar to the previous example, cross-sectional and elemental analysis performed on the solder joint may reveal the presence of (Cu,Ni)6Sn5IMC, and may also reveal the presence of nickel from the electroless plating technique used on the ENEPIG. Also similar to the previous example, the ENEPIG can be conformally plated with the fillets on all sides of the copper bump 215 (e.g., with...). Figure 2D and Figure 2E (Similar in form to that shown). Accordingly, it will be understood that IMC can be compared with... Figure 6 The different forms / shapes shown are formed in the packaging substrate.

[0041] Figure 7 The illustration shows an integrated circuit package that is manufactured according to the process described in Figures 2A-2E. Figure 4 Example material stack 700. Specifically, Figure 7The illustration shows a cross-sectional view of an example solder joint between the pads (e.g., 221) of a die (e.g., 220) and the CSB of a package substrate (e.g., 215) when IGIPEIG is used as a surface finish. The example stack 700 includes an IMC 701 formed between copper pads 215 and solder 706 (which can be any suitable solder material, e.g., SAC or another type of solder). Although shown in a particular layer, IMC 701 can be formed in a different manner than shown. The IMC includes: a first IMC 702 comprising copper and tin (Cu3Sn); and a second IMC, also comprising copper and tin, but in a different form (Cu6Sn5). The first IMC 702 may comprise approximately 60-75% copper and approximately 25-40% tin by weight, while the second IMC 704 may comprise approximately 50-70% copper and approximately 30-50% tin by weight.

[0042] Similar to the previous examples, cross-sectional and elemental analysis metrology performed on the cavity-side bump / package substrate may reveal the absence of nickel, for example, in Ni-P or Ni6Sn5IMC in the solder joint. Additionally, similar to the previous examples, IGIPIG can be conformally plated with rounded corners on all sides of the copper bump 215 (e.g., with...). Figure 2D and Figure 2E (Similar in form to that shown). Accordingly, it will be understood that IMC can be compared with... Figure 7 The different forms / shapes shown are formed in the packaging substrate.

[0043] Figures 8A-8E illustrate a second example process 800 of embedding an interconnect bridge circuit module die in a package substrate according to an embodiment of the present disclosure. The process may include additional, fewer, or different operations compared to those shown or described below. In some embodiments, one or more of the illustrated operations include multiple operations, sub-operations, etc.

[0044] Reference Figure 8A, Example process 800 includes forming a dielectric accumulation layer 804 on a core layer 802 as shown. The accumulation layer includes a metallization layer and pillars within the accumulation layer 804, as described above for… Figure 9 The described example is similar. Surface finish (SF) 808 is then formed or deposited on the exposed conductive pads 806 of the substrate (e.g., those in the third metallization layer). SF 808 can be employed as follows: Figure 10 or Figure 9 The material shown and further described below is formed.

[0045] For example, refer to Figure 10SF 808 may include layer 902, which includes indium deposited on pad 806 using electrolytic PdAu deposition on layer 902. Specifically, it may include layer 904 comprising palladium on layer 902 and layer 906 comprising gold on layer 904. In some embodiments, the thickness of layer 902 may be between 0.10-1 μm, the thickness of layer 904 may be between 0.01-0.10 μm (e.g., 0.04 μm), and the thickness of layer 906 may be between 0.01-0.10 μm (e.g., 0.06 μm). Layer 902 may include approximately 2-8% (e.g., 5% by weight) of indium.

[0046] Compared to current process flows, thin indium layers such as 902 can provide a small change in the overall thickness of the SF 808, and therefore may not cause chip gap height issues and can be implemented with relatively minimal impact in current process flows. Additionally, indium layers such as 902 can act as active electromigration suppressors by backfilling the electron voids created by tin during soldering. Thinner 902 layers (e.g., those closer to 100 nm thickness) can provide improved Imax characteristics, while thicker 902 layers (e.g., those closer to 1 μm thickness) can also provide low-temperature solder properties.

[0047] As another example, see Figure 10 SF 808 may include layer 1002, which includes cobalt and iron (CoFe) deposited on pad 806 using electrolytic PdAu deposition on layer 1002. Specifically, it may employ layer 1004 including palladium on layer 1002 and layer 1006 including gold on layer 1004. In some embodiments, the thickness of layer 1002 may be between 2-4 μm (e.g., 3.3 μm), the thickness of layer 1004 may be between 0.01-0.10 μm (e.g., 0.04 μm), and the thickness of layer 1006 may be between 0.01-0.10 μm (e.g., 0.06 μm). Layer 1002 may include approximately 20-35% cobalt and approximately 65-80% iron by weight.

[0048] Layer-pair dopants such as 1002 containing cobalt and iron exhibit little or no change in properties, and are therefore compatible with, for example,... Figure 8C The example shown is deposited with palladium and gold compatibility. Furthermore, cobalt and iron can provide better IMC formation kinetics than those including other materials, e.g., better growth than layers with nickel, thus allowing potentially improved SJRs compared to nickel-containing SF. The overall thickness of the described example (e.g., between 3-4 μm) is consistent with current processes and therefore may not cause chip gap height issues, and can be incorporated into existing process flows with relatively minimal cost or variation.

[0049] Referring now to Figure 8B, the laser stop layer 810 is then formed within an opening 811 in the photoresist layer 812 (e.g., a dry film resist (DFR) layer) on the accumulation layer 804. The laser stop layer 810 may comprise nickel or any other suitable material. Then, as... Figure 8E As shown, the photoresist layer 812 is removed, and an additional accumulation layer 814 is formed on the accumulation layer 804 as shown, including the formation of a dielectric accumulation layer in the region above the laser stop layer 810. Then, as shown in FIG8D, a cavity 816 is formed in the region above the laser stop layer 810 (e.g., via laser drilling) until the laser stop layer 810 is exposed. The laser stop layer 810 can then be removed (e.g., etched) to expose the SF 808 on the conductive pad 806.

[0050] Now refer to Figure 1 An interconnect bridge circuit module die 820, including a TSV 818, is placed within a cavity 816. The die 820 is attached using solder 823 such that at least some of the bottom pads 821 of the die 820 are electrically connected to an SF 808 formed on pad 806. Subsequently, a dielectric (e.g., a mold or accumulation material) can be placed within the remaining portion of the cavity 816 to secure or encapsulate the interconnect bridge circuit module die 820, and further, electrical contacts can be formed or positioned to contact the top pads 822 of the die 820, for example, to attach one or more integrated circuit dies (e.g., such as...). Figure 11 As shown in 112), they are interconnected or the integrated circuit die is connected to a circuit board (e.g., a motherboard) under the substrate.

[0051] While bridge circuit module dies are described herein, other types of dies may be embedded within cavities of the package substrate as described herein. For example, active circuit dies (e.g., integrated circuit dies) or another type of die (e.g., dies having one or more passive circuit components such as capacitors or inductors) may be embedded according to embodiments herein, instead of interconnect bridge circuit module dies, to interconnect multiple integrated circuit dies.

[0052] Figure 9 The illustration shows an integrated circuit package that is manufactured according to the process described in Figures 8A-8E. Figure 11 Example material stack 1100. Specifically, Figure 9 The diagram shows when using Figure 9A cross-sectional view of an example solder joint between the pads (e.g., 821) of a die (e.g., 820) and the CSB of a package substrate (e.g., 806) during surface finishing. Example stack 1100 includes an IMC 1104 formed between an indium-containing layer 1102 and a solder 1106 (which can be any suitable solder material, e.g., SAC or another type of solder). IMC 1104 may comprise approximately 1-5% indium by weight and approximately 95-99% tin by weight. In some embodiments, stack 1100 may have a generally cylindrical shape, as shown in the figure for... Figure 12 The described SF can be formed using a photoresist (e.g., DFR).

[0053] Figure 10 The illustration shows an integrated circuit package that is manufactured according to the process described in Figures 8A-8E. Figure 12 Example material stack 1200. Specifically, Figure 10 The diagram shows when using Figure 10 A cross-sectional view of an example solder joint between the pads (e.g., 821) of a die (e.g., 820) and the CSB of a package substrate (e.g., 806) during surface finishing. Example stack 1200 includes an IMC 1204 formed between a layer 1202 comprising cobalt and iron and solder 1206 (which can be any suitable solder material, e.g., SAC or another type of solder). IMC 1104 may comprise approximately 2-8% cobalt by weight, approximately 10-30% iron by weight, and approximately 65-85% tin by weight. In some embodiments, stack 1200 may have a generally cylindrical shape, as shown for… Figures 13A-13B The described SF can be formed using a photoresist (e.g., DFR).

[0054] Figure 13A The illustrations may include example systems 1300 and 1310 of the architectures described herein. In particular, the package substrate 1304 and the multi-die package 1314 may include conductive contacts with surface finishes as described herein for connection to embedded components, such as interconnect bridge circuit module dies, within the substrate 1304 or within layers of the package 1314.

[0055] Figure 14 Example system 1300 includes a circuit board 1302, which in some embodiments may be implemented as a motherboard or mainboard of a computer system. Example system 1300 also includes a packaging substrate 1304 having integrated circuit dies 1306A and 1306B attached to the packaging substrate 1304. Die 1306 may be a packaged or unpackaged integrated circuit product, which includes one or more integrated circuit dies (e.g.,Figure 15 1402 die, Figure 14 The die 1306 may include one or more computing system components, such as one or more processor units (e.g., system-on-a-chip (SoC), processor core, graphics processing unit (GPU), accelerator, chipset processor), I / O controller, memory, or network interface controller. In some embodiments, the die 1306 may include one or more additional active or passive devices, such as capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. In addition to including one or more processor units, the die 1306 may also include additional components, such as embedded DRAM, stacked high-bandwidth memory (HBM), shared cache memory, input / output (I / O) controllers, or memory controllers. Any of these additional components may be located on the same SoC as the processor unit or on one or more SoCs separate from the SoC including the processor unit. These individual SoCs may be referred to as “chiplets”. The packaging substrate 1304 can provide electrical connection between the die 1306 and the circuit board 1302, and may include an embedded interconnect bridge circuit module die as described above.

[0056] Similar to system 1300, system 1310 also includes a circuit board 1312, which in some embodiments may be implemented as a motherboard or mainboard of a computer system. System 1310 also includes a multi-die package 1314, which includes multiple integrated circuits / dies (e.g., 1306) and interconnections between dies in one or more metallization layers. Multi-die package 1314 may include, for example, one or more silicon interposers, one or more silicon bridges embedded in a package substrate. For example, package 1314 may include embedded interconnect bridge circuit module dies (e.g., the Intel® Embedded Multi-Die Interconnect Bridge (EMIB) as described above).

[0057] Main circuit boards 1302 and 1312 provide electrical connections to other components of the computer system, such as memory, storage devices, network interfaces, peripherals, power supplies, etc. The main circuit boards may include one or more traces and circuit components to provide interconnection between such computer system components.

[0058] Figure 15This is a top view of a wafer 1400 and die 1402, which may include any of the embodiments disclosed herein. The wafer 1400 may be made of semiconductor material and may include one or more dies 1402 having integrated circuit structures formed on the surface of the wafer 1400. Each die 1402 may be a repeating unit of an integrated circuit product including any suitable integrated circuit. After the semiconductor product is fabricated, the wafer 1400 may undergo a dicing process, wherein the dies 1402 are separated from each other to provide discrete “chips” of integrated circuit products. Dies 1402 may include one or more transistors (e.g., those discussed below). Figure 16 The wafer 1400 or die 1402 may include some transistors in transistor 1540, supporting circuit modules that route electrical signals to said transistors, passive components (e.g., signal traces, resistors, capacitors or inductors and / or any other integrated circuit components). In some embodiments, the wafer 1400 or die 1402 may include memory devices (e.g., random access memory (RAM) devices, such as static RAM (SRAM) devices, magnetic RAM (MRAM) devices, resistive RAM (RRAM) devices, conductive bridged RAM (CBRAM) devices, etc.), logic devices (e.g., AND, OR, NAND, or NOR gates) or any other suitable circuit elements. Multiple devices of these devices may be combined on a single die 1402. For example, a memory array formed by multiple memory devices may be integrated with a processor unit (e.g., Figure 15 The processor unit 1602 or other logically identical die 1402 is formed thereon, the other logic being configured to store information in the memory device or to execute instructions stored in the memory array.

[0059] Figure 14 This is a cross-sectional side view of an integrated circuit device 1500 that may be included in any of the embodiments disclosed herein. One or more of the integrated circuit devices 1500 may be included in one or more dies 1402 ( Figure 14 The integrated circuit device 1500 may be formed on the die substrate 1502 (e.g., Figure 14 On a 1400 wafer, and may be included in a die (e.g., Figure 14The die substrate 1502 may be a semiconductor substrate composed of a semiconductor material system, including, for example, an n-type or p-type material system (or a combination of both). The die substrate 1502 may include, for example, a crystalline substrate formed using bulk silicon or silicon-on-insulator (SOI) substructures. In some embodiments, the die substrate 1502 may be formed using alternative materials that may or may not be combined with silicon, including but not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Other materials classified as Group II-VI, III-V, or IV may also be used to form the die substrate 1502. While several examples of materials from which the die substrate 1502 may be formed are described herein, any material that can be used as the basis for the integrated circuit device 1500 may be used. The die substrate 1502 may be a diced die (e.g., Figure 14 The die 1402) or wafer (e.g., Figure 15 Part of the 1400 wafer.

[0060] Integrated circuit device 1500 may include one or more device layers 1504 disposed on a die substrate 1502. Device layer 1504 may include features of one or more transistors 1540 (e.g., metal-oxide-semiconductor field-effect transistors (MOSFETs) or ferroelectric field-effect transistors (FeFETs)) formed on the die substrate 1502. Transistor 1540 may include, for example, one or more source and / or drain (S / D) regions 1520, a gate 1522 controlling the current between S / D regions 1520, and one or more S / D contacts 1524 routing electrical signals to / from the S / D regions 1520. Transistor 1540 may include additional features, such as device isolation regions, gate contacts, and the like, not shown for clarity. Transistor 1540 is not limited to... Figure 15 The types and configurations shown are not limited to those shown, but can include a wide variety of other types and configurations, such as planar transistors, non-planar transistors, or combinations of both. Non-planar transistors can include FinFET transistors such as dual-gate transistors or tri-gate transistors, as well as wraparound or all-around gate transistors such as nanoribbon, nanosheet, and nanowire transistors.

[0061] Back Figure 15 Example transistor 1540 may include a gate 1522, which is formed of at least two layers (i.e., a gate dielectric and a gate electrode). The gate dielectric may include a single layer or a stack of layers. One or more layers may include silicon oxide, silicon dioxide, silicon carbide, and / or a high-k dielectric material.

[0062] High-k dielectric materials may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that can be used in gate dielectrics include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, an annealing process may be performed on the gate dielectric to improve its quality when high-k materials are used.

[0063] The gate electrode may be formed on the gate dielectric and may include at least one p-type work function metal or an n-type work function metal, depending on whether the transistor 1540 is a p-type metal-oxide-semiconductor (PMOS) or an n-type metal-oxide-semiconductor (NMOS) transistor. In some implementations, the gate electrode may consist of a stack of two or more metal layers, wherein one or more metal layers are work function metal layers and at least one metal layer is a fill metal layer. Additional metal layers, such as barrier layers, may be included for other purposes.

[0064] For PMOS transistors, metals that can be used as the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides (e.g., ruthenium oxide), and any metals described below with reference to NMOS transistors (e.g., for work function tuning). For NMOS transistors, metals that can be used as the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide), and any metals described above with reference to PMOS transistors (e.g., for work function tuning).

[0065] In some embodiments, when viewed as a cross-section of the transistor 1540 along the source-channel-drain direction, the gate electrode may be composed of a U-shaped structure including a bottom portion substantially parallel to the surface of the die substrate 1502 and two sidewall portions substantially perpendicular to the top surface of the die substrate 1502. In other embodiments, at least one of the metal layers forming the gate electrode may be simply a planar layer substantially parallel to the top surface of the die substrate 1502 and excluding the sidewall portions substantially perpendicular to the top surface of the die substrate 1502. In other embodiments, the gate electrode may be composed of a combination of a U-shaped structure and a planar non-U-shaped structure. For example, the gate electrode may be composed of one or more U-shaped metal layers formed on top of one or more planar non-U-shaped layers.

[0066] In some embodiments, a pair of sidewall spacers may be formed on opposite sides of the gate stack to support the gate stack. The sidewall spacers may be formed from materials such as silicon nitride, silicon oxide, silicon carbide, carbon-doped silicon nitride, and silicon oxynitride. Processes for forming the sidewall spacers are well known in the art and generally include deposition and etching steps. In some embodiments, multiple pairs of spacers may be used; for example, two, three, or four pairs of sidewall spacers may be formed on opposite sides of the gate stack.

[0067] The S / D region 1520 may be formed adjacent to the gate 1522 of each transistor 1540 within the die substrate 1502. The S / D region 1520 may be formed using, for example, an implantation / diffusion process or an etching / deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorus, or arsenic may be ion-implanted into the die substrate 1502 to form the S / D region 1520. An annealing process, activating the dopants and causing them to diffuse further into the die substrate 1502, may follow the ion implantation process. In the latter process, the die substrate 1502 may first be etched to form a notch at the location of the S / D region 1520. An epitaxial deposition process may then be performed to fill the notch with the material used to fabricate the S / D region 1520. In some implementations, the S / D region 1520 may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some embodiments, the epitaxially deposited silicon alloy may be in-situ doped with dopants such as boron, arsenic, or phosphorus. In some embodiments, the S / D region 1520 may be formed using one or more alternative semiconductor materials such as germanium or group III-V materials or alloys. In other embodiments, one or more layers of metal and / or metal alloys may be used to form the S / D region 1520.

[0068] Electrical signals, such as power and / or input / output (I / O) signals, can be transmitted through one or more interconnect layers disposed on device layer 1504 (in Figure 15 The diagram shows interconnect layers 1506-1510 routed to and / or from devices (e.g., transistor 1540) in device layer 1504. For example, conductive features of device layer 1504 (e.g., gate 1522 and S / D contact 1524) may be electrically coupled to interconnect structures 1528 of interconnect layers 1506-1510. One or more interconnect layers 1506-1510 may form a metallization stack (also referred to as an "ILD stack") 1519 of integrated circuit device 1500.

[0069] Interconnect structure 1528 can be arranged within interconnect layers 1506-1510 to route electrical signals according to a variety of designs; in particular, the arrangement is not limited to... Figure 15 The specific configuration of interconnect structure 1528 shown is illustrated. Although a specific number of interconnect layers 1506-1510 are...Figure 15 While shown in the figures, embodiments of this disclosure include integrated circuit devices having more or fewer interconnect layers than those shown.

[0070] In some embodiments, the interconnect structure 1528 may include lines 1528a and / or vias 1528b filled with a conductive material such as a metal. Lines 1528a may be arranged to route electrical signals in a direction substantially parallel to a plane on which the die substrate 1502, on which the device layer 1504 is formed. For example, lines 1528a may be able to route electrical signals from… Figure 15 The via 1528b routes electrical signals in the direction of entering and leaving the page and / or in the direction across the page. The via 1528b can be arranged to route electrical signals in a direction substantially perpendicular to the surface of the die substrate 1502 on which the device layer 1504 is formed. In some embodiments, the via 1528b can electrically couple lines 1528a of different interconnect layers 1506-1510 together.

[0071] Interconnect layers 1506-1510 may include dielectric material 1526 disposed between interconnect structures 1528, such as Figure 15 As shown in the diagram. In some embodiments, the dielectric material 1526 disposed between interconnect structures 1528 in different interconnect layers 1506-1510 may have different compositions; in other embodiments, the composition of the dielectric material 1526 between different interconnect layers 1506-1510 may be the same. Device layer 1504 may also include dielectric material 1526 disposed between transistor 1540 and the bottom layer of the metallization stack. The dielectric material 1526 included in device layer 1504 may have a different composition than the dielectric material 1526 included in interconnect layers 1506-1510; in other embodiments, the composition of the dielectric material 1526 in device layer 1504 may be the same as the dielectric material included in any of interconnect layers 1506-1510.

[0072] A first interconnect layer 1506 (referred to as metal 1 or "M1") may be formed directly on device layer 1504. In some embodiments, the first interconnect layer 1506 may include lines 1528a and / or vias 1528b, as shown. Lines 1528a of the first interconnect layer 1506 may be coupled to contacts of device layer 1504 (e.g., S / D contacts 1524). Vias 1528b of the first interconnect layer 1506 may be coupled to lines 1528a of a second interconnect layer 1508.

[0073] The second interconnect layer 1508 (referred to as metal 2 or "M2") may be formed directly on the first interconnect layer 1506. In some embodiments, the second interconnect layer 1508 may include vias 1528b to couple lines 1528 of the second interconnect layer 1508 to lines 1528a of the third interconnect layer 1510. Although lines 1528a and vias 1528b are structurally depicted as lines within their respective interconnect layers for clarity, lines 1528a and vias 1528b may be structurally and / or materially adjacent in some embodiments (e.g., simultaneously filled during a dual damascene process).

[0074] The third interconnect layer 1510 (referred to as metal 3 or "M3") (and any additional interconnect layers as needed) may be formed on the second interconnect layer 1508 in conjunction with a similar technique and configuration described in conjunction with the second interconnect layer 1508 or the first interconnect layer 1506. In some embodiments, the interconnect layers "higher up" (i.e., further away from device layer 1504) in the metallization stack 1519 of the integrated circuit device 1500 may be thicker than the lower interconnect layers in the metallization stack 1519, wherein the lines 1528a and vias 1528b in the higher interconnect layers are thicker than those in the lower interconnect layers.

[0075] The integrated circuit device 1500 may include a solder resist 1534 (e.g., polyimide or a similar material) and one or more conductive contacts 1536 formed on interconnect layers 1506-1510. Figure 16 In the illustration, conductive contact 1536 is depicted as taking the form of a bonding pad. Conductive contact 1536 may be electrically coupled to interconnect structure 1528 and configured to route electrical signals from transistor(s) 1540 to an external device. For example, solder joints may be formed on one or more conductive contacts 1536 to mechanically and / or electrically couple an integrated circuit die including integrated circuit device 1500 to another component (e.g., a printed circuit board). Integrated circuit device 1500 may include additional or alternative structures to route electrical signals from interconnect layers 1506-1510; for example, conductive contact 1536 may include other similar features (e.g., posts) for routing electrical signals to external components.

[0076] In some embodiments where the integrated circuit device 1500 is a double-sided die, the integrated circuit device 1500 may include another metallization stack (not shown) on the opposite side of device layer 1504. This metallization stack may include multiple interconnect layers as discussed above with reference to interconnect layers 1506-1510 to provide a conductive path (e.g., including conductive lines and vias) between device layer 1504 and additional conductive contacts (not shown) on the opposite side of the integrated circuit device 1500 to conductive contacts 1536.

[0077] In other embodiments where the integrated circuit device 1500 is a double-sided die, the integrated circuit device 1600 may include one or more through-silicon vias (TSVs) through the die substrate 1502; these TSVs may contact one or more device layers 1504 and provide a conductive path between one or more device layers 1504 and additional conductive contacts (not shown) on the opposite side of the integrated circuit device 1500 to the conductive contacts 1536. In some embodiments, the TSVs extending through the substrate can be used to route power and ground signals from the conductive contacts on the opposite side of the integrated circuit device 1500 to the transistor 1540 and any other components integrated into the die 1500, and the metallization stack 1519 can be used to route I / O signals from the conductive contacts 1536 to the transistor 1540 and any other components integrated into the die 1500.

[0078] Multiple integrated circuit devices 1500 can be stacked, wherein one or more TSVs in each stacked device provide connectivity between one device and any other device in the stack. For example, one or more high-bandwidth memory (HBM) integrated circuit dies can be stacked on top of a substrate integrated circuit die, and TSVs in the HBM die can provide connectivity between a single HBM and the substrate integrated circuit die. Conductive contacts can provide additional connectivity between adjacent integrated circuit dies in the stack. In some embodiments, the conductive contacts can be fine-pitch solder bumps (microbumps).

[0079] Figure 16 This may be a block diagram of an example electrical device 1600 that may include one or more embodiments disclosed herein. For example, any suitable component of the electrical device 1600 may include one or more of the integrated circuit device 1500 or integrated circuit die 1402 disclosed herein. Multiple components in Figure 16 The components are illustrated as being included in electrical device 1600, but any one or more of these components may be omitted or repeated as appropriate for the application. In some embodiments, some or all of the components included in electrical device 1600 may be attached to one or more motherboards or system boards. In some embodiments, one or more of these components are fabricated on a single system-on-a-chip (SoC) die.

[0080] Additionally, in various embodiments, electrical device 1600 may not include... ​The electrical device 1600 may include one or more of the components illustrated in the diagram, but may include interface circuit modules for coupling to one or more components. For example, the electrical device 1600 may not include the display device 1606, but may include a display device interface circuit module (e.g., connector and driver circuit modules) to which the display device 1606 may be coupled. In another set of examples, the electrical device 1600 may not include the audio input device 1624 or the audio output device 1608, but may include an audio input or output device interface circuit module (e.g., connector and support circuit modules) to which the audio input device 1624 or the audio output device 1608 may be coupled.

[0081] Electrical device 1600 may include one or more processor units 1602 (e.g., one or more processor cells). As used herein, the terms "processor cell," "processing unit," or "processor" may refer to any means or part of a means of processing electronic data from registers and / or memory to transform that electronic data into other electronic data that can be stored in registers and / or memory. Processor unit 1602 may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), general-purpose GPUs (GPGPUs), accelerated processing units (APUs), field-programmable gate arrays (FPGAs), neural network processing units (NPUs), data processing units (DPUs), accelerators (e.g., graphics accelerators, compression accelerators, artificial intelligence accelerators), controller cryptographic processors (dedicated processors that execute cryptographic algorithms within hardware), server processors, controllers, or any other suitable type of processor unit. Thus, a processor unit may be referred to as an XPU (or xPU).

[0082] Electrical device 1600 may include memory 1604, which itself may include one or more memory devices, such as volatile memory (e.g., dynamic random access memory (DRAM), static random access memory (SRAM)), non-volatile memory (e.g., read-only memory (ROM), flash memory, chalcogenide-based phase-change non-volatile memory), solid-state memory, and / or hard disk drive. In some embodiments, memory 1604 may include memory located on the same integrated circuit die as processor unit 1602. This memory may be used as cache memory (e.g., level 1 (L1), level 2 (L2), level 3 (L3), level 4 (L4), and last level (LLC)) and may include embedded dynamic random access memory (eDRAM) or spin-transfer torque magnetic random access memory (STT-MRAM).

[0083] In some embodiments, the electrical device 1600 may include one or more processor units 1602, which are heterogeneous or asymmetric to other processor units 1602 in the electrical device 1600. There are a wide variety of differences between the processing units 1602 in the system in terms of a range of quality metrics including architecture, microarchitecture, thermal, power consumption characteristics, and the like. These differences can manifest in practice as asymmetry and heterogeneity between the processing units 1602 in the electrical device 1600.

[0084] In some embodiments, electrical device 1600 may include communication component 1612 (e.g., one or more communication components). For example, communication component 1612 is capable of managing wireless communication for transmitting data to and from electrical device 1600. The term "wireless" and its derivatives can be used to describe circuits, apparatus, systems, methods, techniques, communication channels, etc., that can transmit data via modulated electromagnetic radiation through a non-solid medium. The term "wireless" does not imply that associated devices do not contain any wires, although they may not in some embodiments.

[0085] Communication Component 1612 can implement any of a number of wireless standards or protocols, including but not limited to Institute of Electrical and Electronics Engineers (IEEE) standards, including Wi-Fi (IEEE 802.11 series), IEEE 802.16 standards (e.g., IEEE 802.16-2005 revision), Long Term Evolution (LTE) projects along with any revisions, updates, and / or amendments (e.g., Advanced LTE project, Ultra Mobile Broadband (UMB) project (also known as "3GPP2"), etc.). IEEE 802.16 compliant Broadband Wireless Access (BWA) networks are generally referred to as WiMAX networks, an acronym for Global Microwave Access Interoperability, and are a certification mark for products that have passed conformance and interoperability testing of the IEEE 802.16 standard. Communication Component 1612 can operate under GSM, GPRS, UMTS, HSPA, Evolved HSPA (E-HSPA), or LTE networks. Communication component 1612 may operate according to Enhanced GSM Data Rate (EDGE), namely GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). Communication component 1612 may operate according to Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolved Data Optimization (EV-DO) and its derivatives, as well as any other radio protocol represented as 3G, 4G, 5G, and above. In other embodiments, communication component 1612 may operate according to other radio protocols. Electrical device 1600 may include antenna 1622 to facilitate wireless communication and / or receive other wireless communications (such as AM or FM radio transmissions).

[0086] In some embodiments, communication component 1612 can manage wired communications, such as electrical, optical, or any other suitable communication protocol (e.g., the IEEE 802.3 Ethernet standard). As described above, communication component 1612 may include multiple communication components. For example, a first communication component 1612 may be dedicated to short-range wireless communications such as Wi-Fi or Bluetooth, and a second communication component 1612 may be dedicated to longer-range wireless communications such as Global Positioning System (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, etc. In some embodiments, the first communication component 1612 may be dedicated to wireless communications, and the second communication component 1612 may be dedicated to wired communications.

[0087] Electrical device 1600 may include battery / power circuit module 1614. Battery / power circuit module 1614 may include one or more energy storage devices (e.g., batteries or capacitors) and / or circuit modules for coupling components of electrical device 1600 to an energy source (e.g., AC line power) separate from electrical device 1600.

[0088] Electrical device 1600 may include display device 1606 (or a corresponding interface circuit module, as discussed above). Display device 1606 may include one or more embedded or wired or wirelessly connected external visual indicators, such as head-up displays, computer monitors, projectors, touch screen displays, liquid crystal displays (LCDs), light-emitting diode displays, or flat panel displays.

[0089] Electrical device 1600 may include audio output device 1608 (or a corresponding interface circuit module, as discussed above). Audio output device 1608 may include any embedded or wired or wireless external device that generates an auditory indicator, such as a speaker, headphones, or earbuds.

[0090] Electrical device 1600 may include an audio input device 1624 (or a corresponding interface circuit module, as discussed above). The audio input device 1624 may include any embedded or wired or wirelessly connected device that generates a signal representing sound, such as a microphone, microphone array, or digital instrument (e.g., an instrument with a Music Instrument Digital Interface (MIDI) output). Electrical device 1600 may include a Global Navigation Satellite System (GNSS) device 1618 (or a corresponding interface circuit module, as discussed above), such as a Global Positioning System (GPS) device. GNSS device 1618 may communicate with satellite-based systems and may determine the geographical location of electrical device 1600 based on information received from one or more GNSS satellites, as is known in the art.

[0091] Electrical device 1600 may include other output devices 1610 (or corresponding interface circuit modules, as discussed above). Examples of the other output device 1610 may include audio codecs, video codecs, printers, wired or wireless transmitters for providing information to other devices, or additional storage devices.

[0092] Electrical device 1600 may include another input device 1620 (or a corresponding interface circuit module, as discussed above). Examples of the other input device 1620 may include an accelerometer, gyroscope, compass, image capture device (e.g., a single-image or stereo camera), trackball, track, trackpad, touchpad, keyboard, cursor control device such as a mouse, stylus, touch screen, proximity sensor, microphone, barcode reader, quick-response (QR) code reader, electrocardiogram (ECG) sensor, PPG (photoplethysmography) sensor, skin conductance response sensor, any other sensor, or radio frequency identification (RFID) reader.

[0093] Electrical device 1600 may have any desired form factor, such as a handheld or mobile electrical device (e.g., a cellular phone, smartphone, mobile internet device, music player, tablet computer, laptop computer, 2-in-1 convertible computer, portable all-in-one computer, netbook computer, ultrabook computer, personal digital assistant (PDA), ultra-mobile personal computer, portable game console, etc.), desktop electrical device, server, rack-level computing solution (e.g., blade, tray, or skid-mount computing system), workstation or other networked computing component, printer, scanner, monitor, set-top box, entertainment control unit, fixed game console, smart TV, vehicle control unit, digital camera, digital video recorder, wearable electrical device, or embedded computing system (e.g., a computing system as part of a vehicle, smart home appliance, consumer electronics or device, or manufacturing equipment). In some embodiments, electrical device 1600 may be any other electronic device that processes data. In some embodiments, electrical device 1600 may include multiple discrete physical components. Given the range of devices that can be shown for electrical device 1600 in various embodiments, in some embodiments, electrical device 1600 may be referred to as a computing device or computing system.

[0094] The following provides illustrative examples of the techniques described throughout this disclosure. Embodiments of these techniques may include any one or more and any combination of the examples described below. In some embodiments, at least one of the systems or components presented in one or more of the foregoing figures may be configured to perform one or more operations, techniques, processes, and / or methods as presented in the examples below.

[0095] Example A1 is an integrated circuit packaging substrate comprising: a plurality of metallization layers in a dielectric accumulation layer; a die within the accumulation layer, the die including conductive contacts electrically connected to conductive contacts of the metallization layers; and a conductive material between the conductive contacts of the die and the conductive contacts of the metallization layers, the conductive material comprising nickel, phosphorus, tin, and palladium.

[0096] Example A2 includes the subject matter of Example A1, wherein the conductive material comprises an intermetallic compound comprising nickel and phosphorus.

[0097] Example A3 includes the subject of Example A2, wherein the intermetallic compound comprises phosphorus in the range of 15-30% by weight.

[0098] Example A4 includes the subject matter of any one of Examples A1-A3, wherein the conductive material comprises an intermetallic compound, the intermetallic compound comprising copper, nickel, tin, and palladium.

[0099] Example A5 includes the subject matter of Example A4, wherein the intermetallic compound comprises copper, nickel, and tin in a weight range of 20-40%, nickel, and tin in a weight range of 30-50%.

[0100] Example A6 includes the subject matter of any one of Examples A1-A5, wherein the conductive material comprises an intermetallic compound, the intermetallic compound comprising nickel, tin, and phosphorus.

[0101] Example A7 includes the subject matter of any one of Examples A1-A6, wherein the conductive material comprises a layer on the conductive pads of the metallization layer, the layer comprising nickel and phosphorus.

[0102] Example A8 includes the subject of any one of Examples A1-A7, wherein the die is an interconnect bridge circuit module die.

[0103] Example A9 includes the subject matter of Example A8, wherein the interconnect bridge circuit module die includes a through-silicon via (TSV) to which the conductive contacts are connected.

[0104] Example A10 includes the subject of any one of Examples A1-A9, wherein the die is encapsulated in a cavity or opening in the accumulated layer.

[0105] Example A11 is an integrated circuit package comprising: an integrated circuit package substrate including: a plurality of metallization layers in a dielectric accumulation layer; an interconnect bridge circuit module die embedded in the accumulation layer, the interconnect bridge circuit module die including a through-hole between a first conductive contact connected to a first side of the interconnect bridge circuit module die and a second conductive contact on a second side of the interconnect bridge circuit module die opposite to the first side, the second conductive contact being electrically connected to conductive contacts of the metallization layer; and a conductive material between the second conductive contact of the interconnect bridge circuit module die and the conductive contact of the metallization layer, the conductive material including nickel, phosphorus, tin, and palladium; and an integrated circuit die coupled to the package substrate, wherein at least two integrated circuit dies are interconnected by the interconnect bridge circuit module die.

[0106] Example A12 includes the subject matter of Example A11, wherein the conductive material comprises an intermetallic compound comprising nickel and phosphorus.

[0107] Example A13 includes the subject matter of Example A12, wherein the intermetallic compound comprises phosphorus in the range of 15-30% by weight.

[0108] Example A14 includes the subject matter of any one of Examples A11-A13, wherein the conductive material comprises an intermetallic compound, the intermetallic compound comprising copper, nickel, tin, and palladium.

[0109] Example A15 includes the subject matter of Example A14, wherein the intermetallic compound comprises copper, nickel, and tin in a weight range of 20-40% and 30-50% respectively.

[0110] Example A16 includes the subject matter of any one of Examples A11-A15, wherein the conductive material comprises an intermetallic compound, the intermetallic compound comprising nickel, tin, and phosphorus.

[0111] Example A17 includes the subject matter of any one of Examples A11-A16, wherein the conductive material comprises a layer on the conductive pads of the metallization layer, the layer comprising nickel and phosphorus.

[0112] Example A18 is a method of forming an integrated circuit package substrate, comprising: forming an accumulation layer on a die layer, the accumulation layer including a plurality of metallization layers; forming a cavity in the accumulation layer to expose a subset of conductive contacts of the metallization layers; forming a first surface finish layer on the subset of conductive contacts, the first surface finish layer including nickel and having a thickness greater than 5 μm; forming a second surface finish layer on the first surface finish layer, the second surface finish layer including palladium; forming a third surface finish layer on the second surface finish layer, the second surface finish layer including gold; and placing a die within the cavity such that the conductive contacts of the die are electrically connected to the subset of conductive contacts.

[0113] Example A19 includes the subject matter of Example A18, wherein the first surface finish layer is formed using a chemical plating, the second surface finish layer is formed using a chemical plating, and the third surface finish layer is formed using an immersion plating.

[0114] Example A20 includes the subject matter of Example A18 or A19, wherein the thickness of the first surface finishing layer is between 5 and 10 μm, the thickness of the second surface finishing layer is between 0.01 and 0.10 μm, and the thickness of the third surface finishing layer is between 0.01 and 0.10 μm.

[0115] Example B1 is an integrated circuit packaging substrate comprising: a plurality of metallization layers in a dielectric accumulation layer; a die within the accumulation layer, the die including conductive contacts electrically connected to conductive contacts of the metallization layers; and a conductive material between the conductive contacts of the die and the conductive contacts of the metallization layers, the conductive material including copper, nickel, tin, and palladium.

[0116] Example B2 includes the subject matter of Example B1, wherein the conductive material comprises an intermetallic compound, the intermetallic compound comprising copper and tin.

[0117] Example B3 includes the subject of Example B2, wherein the intermetallic compound comprises copper at a weight of 60-75% and tin at a weight of 25-40%.

[0118] Example B4 includes the subject matter of any one of Examples B1-B3, wherein the conductive material comprises an intermetallic compound, the intermetallic compound comprising copper, nickel, tin, and palladium.

[0119] Example B5 includes the subject matter of Example B4, wherein the intermetallic compound comprises copper at 30-50% by weight, nickel at 10-30% by weight, and tin at 30-50% by weight.

[0120] Example B6 includes the subject of any one of Examples B1-B5, wherein the die is an interconnect bridge circuit module die.

[0121] Example B7 includes the subject of Example B6, wherein the interconnect bridge circuit module die includes a through-silicon via (TSV) to which the conductive contacts are connected.

[0122] Example B8 includes the subject of any of Examples B1-B7, wherein the conductive material conformally surrounds the conductive contact of the metallization layer.

[0123] Example B9 is an integrated circuit package comprising: an integrated circuit package substrate including: a plurality of metallization layers in a dielectric accumulation layer; an interconnect bridge circuit module die embedded in the accumulation layer, the interconnect bridge circuit module die including a through-hole between a first conductive contact connected to a first side of the interconnect bridge circuit module die and a second conductive contact on a second side of the interconnect bridge circuit module die opposite to the first side, the second conductive contact being electrically connected to conductive contacts of the metallization layer; and a conductive material between the second conductive contact of the interconnect bridge circuit module die and the conductive contact of the metallization layer, the conductive material including copper, nickel, tin, and palladium; and an integrated circuit die coupled to the package substrate, wherein at least two integrated circuit dies are interconnected by the interconnect bridge circuit module die.

[0124] Example B10 includes the subject matter of Example B9, wherein the conductive material comprises an intermetallic compound comprising copper and tin.

[0125] Example B11 includes the subject matter of Example B10, wherein the intermetallic compound comprises copper at a weight of 60-75% and tin at a weight of 25-40%.

[0126] Example B12 includes the subject matter of any one of Examples B9-B11, wherein the conductive material comprises an intermetallic compound, the intermetallic compound comprising copper, nickel, tin and palladium.

[0127] Example B13 includes the subject matter of Example B12, wherein the intermetallic compound comprises copper at 30-50% by weight, nickel at 10-30% by weight, and tin at 30-50% by weight.

[0128] Example B14 includes the subject of any one of Examples B9-B13, wherein the second conductive contact of the interconnect bridge circuit module die has a thickness greater than 12 μm.

[0129] Example B15 includes the subject of any one of Examples B9-B14, wherein the conductive material conformally surrounds the conductive contact of the metallization layer.

[0130] Example B16 is a method of forming an integrated circuit package substrate, comprising: forming an accumulation layer on a die layer, the accumulation layer including a plurality of metallization layers; forming a cavity in the accumulation layer to expose a subset of conductive contacts of the metallization layers; forming a first surface finish layer on the subset of conductive contacts, the first surface finish layer including nickel and having a thickness of less than 500 nm; forming a second surface finish layer on the first surface finish layer, the second surface finish layer including palladium; forming a third surface finish layer on the second surface finish layer, the second surface finish layer including gold; and placing a die within the cavity such that the conductive contacts of the die are electrically connected to the subset of conductive contacts.

[0131] Example B17 includes the subject matter of Example B16, wherein the first surface finish layer is formed using a chemical plating, the second surface finish layer is formed using a chemical plating, and the third surface finish layer is formed using an immersion plating.

[0132] Example B18 includes the subject matter of Example B16 or B17, wherein the thickness of the first surface finishing layer is between 100-200 nm, the thickness of the second surface finishing layer is between 0.01-10 μm, and the thickness of the third surface finishing layer is between 0.01-10 μm.

[0133] Example B19 includes the subject of Example B18, wherein the first surface finishing layer is approximately 150 nm thick, the second surface finishing layer is approximately 0.04 μm thick, and the third surface finishing layer is approximately 0.06 μm thick.

[0134] Example B20 includes the subject of any one of Examples B16-B19, wherein the first surface finishing layer is conformally formed around each conductive contact of the subset of conductive contacts.

[0135] Example C1 is an integrated circuit packaging substrate comprising: a plurality of metallization layers in a dielectric accumulation layer; a die within the accumulation layer, the die including conductive contacts electrically connected to conductive contacts of the metallization layers; and a conductive material between the conductive contacts of the die and the conductive contacts of the metallization layers, the conductive material comprising copper and tin.

[0136] Example C2 includes the subject matter of Example C1, wherein the conductive material comprises an intermetallic compound, the intermetallic compound comprising copper and tin.

[0137] Example C3 includes the subject of Example C2, wherein the intermetallic compound comprises copper at a weight of 60-75% and tin at a weight of 25-40%.

[0138] Example C4 includes the subject matter of Example C2, wherein the intermetallic compound is a first intermetallic compound, and the conductive material further includes a second intermetallic compound, the second intermetallic compound comprising copper and tin.

[0139] Example C5 includes the subject of Example C4, wherein the second intermetallic compound comprises copper at a weight of 50-70% and tin at a weight of 30-50%.

[0140] Example C6 includes the subject matter of any one of Examples C1-C5, wherein the conductive material does not include nickel.

[0141] Example C7 includes the subject of any one of Examples C1-C6, wherein the die is an interconnect bridge circuit module die.

[0142] Example C8 includes the subject matter of Example C7, wherein the interconnect bridge circuit module die includes a through-silicon via (TSV) to which the conductive contacts are connected.

[0143] Example C9 is an integrated circuit package comprising: an integrated circuit package substrate including: a plurality of metallization layers in a dielectric accumulation layer; an interconnect bridge circuit module die embedded in the accumulation layer, the interconnect bridge circuit module die including a through-hole between a first conductive contact connected to a first side of the interconnect bridge circuit module die and a second conductive contact on a second side of the interconnect bridge circuit module die opposite to the first side, the second conductive contact being electrically connected to conductive contacts of the metallization layer; and a conductive material between the second conductive contact of the interconnect bridge circuit module die and the conductive contact of the metallization layer, the conductive material including copper and tin; and an integrated circuit die coupled to the package substrate, wherein at least two integrated circuit dies are interconnected by the interconnect bridge circuit module die.

[0144] Example C10 includes the subject matter of Example C9, wherein the conductive material comprises an intermetallic compound comprising copper and tin.

[0145] Example C11 includes the subject matter of Example C10, wherein the intermetallic compound comprises copper at a weight of 60-75% and tin at a weight of 25-40%.

[0146] Example C12 includes the subject matter of Example C10, wherein the intermetallic compound is a first intermetallic compound, and the conductive material further includes a second intermetallic compound, the second intermetallic compound comprising copper and tin.

[0147] Example C13 includes the subject matter of Example C12, wherein the second intermetallic compound comprises copper in a weight range of 50-70% and tin in a weight range of 30-50%.

[0148] Example C14 includes the subject matter of any one of Examples C9-C13, wherein the conductive material does not include nickel.

[0149] Example C15 is a method of forming an integrated circuit package substrate, comprising: forming an accumulation layer on a die layer, the accumulation layer including a plurality of metallization layers; forming a cavity in the accumulation layer to expose a subset of conductive contacts of the metallization layers; forming a first surface finish layer on the subset of conductive contacts, the first surface finish layer including gold; forming a second surface finish layer on the first surface finish layer, the second surface finish layer including palladium; forming a third surface finish layer on the second surface finish layer, the second surface finish layer including gold; and placing a die within the cavity such that the conductive contacts of the die are electrically connected to the subset of conductive contacts.

[0150] Example C16 includes the subject matter of Example C15, wherein the first surface finish layer is formed using dip plating, the second surface finish layer is formed using electroless plating, and the third surface finish layer is formed using dip plating.

[0151] Example C17 includes the subject matter of Example C15 or C16, wherein the thickness of the first surface finishing layer is between 0.01 and 0.04 μm, the thickness of the second surface finishing layer is between 0.02 and 0.15 μm, and the thickness of the third surface finishing layer is between 0.03 and 0.10 μm.

[0152] Example C18 includes the subject of Example C17, wherein the first surface finish layer is about 0.02 μm thick, the second surface finish layer is about 0.10 μm thick, and the third surface finish layer is about 0.08 μm thick.

[0153] Example C19 includes the subject matter of any one of Examples C15-C18, wherein the first surface finish, the second surface finish, and the third surface finish do not contain nickel.

[0154] Example C20 includes the subject of any one of Examples C15-C18, wherein the first surface finishing layer is conformally formed around each conductive contact of the subset of conductive contacts.

[0155] Example D1 is an integrated circuit packaging substrate comprising: a plurality of metallization layers in a dielectric accumulation layer; a die within the accumulation layer, the die including conductive contacts electrically connected to conductive contacts of the metallization layers; and a conductive material between the conductive contacts of the die and the conductive contacts of the metallization layers, the conductive material comprising indium and tin.

[0156] Example D2 includes the subject matter of Example D1, wherein the conductive material comprises an intermetallic compound comprising indium and tin.

[0157] Example D3 includes the subject of Example D2, wherein the intermetallic compound comprises indium at a weight of 1-5% and tin at a weight of 95-99%.

[0158] Example D4 includes the subject matter of Example D2 or D3, wherein the conductive material further includes an indium layer between the conductive contact of the metallization layer and the intermetallic compound.

[0159] Example D5 includes the subject of any one of Examples D1-D4, wherein the die is an interconnect bridge circuit module die.

[0160] Example D6 includes the subject of Example D5, wherein the interconnect bridge circuit module die includes a through-silicon via (TSV) to which the conductive contacts are connected.

[0161] Example D7 includes the subject of any one of Examples D1-D6, wherein the conductive material conformally surrounds the conductive contact of the metallization layer.

[0162] Example D8 includes the subject of any one of Examples D1-D7, wherein the conductive material does not include nickel.

[0163] Example D9 is an integrated circuit package comprising: an integrated circuit package substrate including: a plurality of metallization layers in a dielectric accumulation layer; an interconnect bridge circuit module die embedded in the accumulation layer, the interconnect bridge circuit module die including a through-hole between a first conductive contact connected to a first side of the interconnect bridge circuit module die and a second conductive contact on a second side of the interconnect bridge circuit module die opposite to the first side, the second conductive contact being electrically connected to conductive contacts of the metallization layer; and a conductive material between the second conductive contact of the interconnect bridge circuit module die and the conductive contact of the metallization layer, the conductive material including indium and tin; and an integrated circuit die coupled to the package substrate, wherein at least two integrated circuit dies are interconnected by the interconnect bridge circuit module die.

[0164] Example D10 includes the subject of Example D9, wherein the conductive material comprises an intermetallic compound comprising indium and tin.

[0165] Example D11 includes the subject matter of Example D10, wherein the intermetallic compound comprises indium at a weight of 1-5% and tin at a weight of 95-99%.

[0166] Example D12 includes the subject matter of Example D10 or D11, wherein the conductive material further includes an indium layer between the conductive contact of the metallization layer and the intermetallic compound.

[0167] Example D13 includes the subject of any one of Examples D10-D12, wherein the conductive material conformally surrounds the conductive contact of the metallization layer.

[0168] Example D14 includes the subject of any one of Examples D10-D13, wherein the second conductive contact of the interconnect bridge circuit module die has a thickness greater than 12 μm.

[0169] Example D15 includes the subject matter of any one of Examples D10-D14, wherein the conductive material does not include nickel.

[0170] Example D16 is a method of forming an integrated circuit package substrate, comprising: forming a first accumulation layer on a die layer, the first accumulation layer including a plurality of metallization layers; forming a first surface finish layer including indium on a subset of conductive contacts of the metallization layers of the first accumulation layer; forming a second surface finish layer including palladium on the first surface finish layer; forming a third surface finish layer including gold on the second surface finish layer; forming a second accumulation layer on the first accumulation layer; forming a cavity in the second accumulation layer above the subset of conductive contacts; and placing a die within the cavity such that the conductive contacts of the die are electrically connected to the subset of conductive contacts.

[0171] Example D17 includes the subject of Example D16, wherein the first surface finish layer is formed by electroplating, the second surface finish layer is formed by electroplating, and the third surface finish layer is formed by electroplating.

[0172] Example D18 includes the subject matter of Example D16 or D17, wherein the thickness of the first surface finishing layer is between 0.10-1 μm, the thickness of the second surface finishing layer is between 0.01-0.10 μm, and the thickness of the third surface finishing layer is between 0.01-0.10 μm.

[0173] Example D19 includes the subject of Example D18, wherein the first surface finishing layer is about 1 μm thick, the second surface finishing layer is about 0.04 μm thick, and the third surface finishing layer is about 0.06 μm thick.

[0174] Example D20 includes the subject of any one of Examples D16-D19, wherein the first surface finish layer is not conformally formed around each of the subset of conductive contacts.

[0175] Example E1 is an integrated circuit packaging substrate comprising: a plurality of metallization layers in a dielectric accumulation layer; a die within the accumulation layer, the die including conductive contacts electrically connected to conductive contacts of the metallization layers; and a conductive material between the conductive contacts of the die and the conductive contacts of the metallization layers, the conductive material comprising cobalt, iron, and tin.

[0176] Example E2 includes the subject matter of Example E1, wherein the conductive material comprises an intermetallic compound, which includes cobalt, iron, and tin.

[0177] Example E3 includes the subject matter of Example E2, wherein the intermetallic compound comprises cobalt at a weight of 20-35%, iron at a weight of 10-30%, and tin at a weight of 65-85%.

[0178] Example E4 includes the subject matter of Example E2 or E3, wherein the conductive material further includes a layer comprising cobalt and iron between the conductive contact of the metallization layer and the intermetallic compound.

[0179] Example E5 includes the subject of any one of Examples E1-E4, wherein the die is an interconnect bridge circuit module die.

[0180] Example E6 includes the subject matter of Example E5, wherein the interconnect bridge circuit module die includes a through-silicon via (TSV) to which the conductive contacts are connected.

[0181] Example E7 includes the subject of any of Examples E1-E6, wherein the conductive material conformally surrounds the conductive contact of the metallization layer.

[0182] Example E8 includes the subject matter of any one of Examples E1-E7, wherein the conductive material does not include nickel.

[0183] Example E9 is an integrated circuit package comprising: an integrated circuit package substrate including: a plurality of metallization layers in a dielectric accumulation layer; an interconnect bridge circuit module die embedded in the accumulation layer, the interconnect bridge circuit module die including a through-hole between a first conductive contact connected to a first side of the interconnect bridge circuit module die and a second conductive contact on a second side of the interconnect bridge circuit module die opposite to the first side, the second conductive contact being electrically connected to conductive contacts of the metallization layer; and a conductive material between the second conductive contact of the interconnect bridge circuit module die and the conductive contact of the metallization layer, the conductive material including cobalt, iron, and tin; and an integrated circuit die coupled to the package substrate, at least two integrated circuit dies being interconnected by the interconnect bridge circuit module die.

[0184] Example E10 includes the subject matter of Example E9, wherein the conductive material comprises an intermetallic compound, which includes cobalt, iron, and tin.

[0185] Example E11 includes the subject matter of Example E10, wherein the intermetallic compound comprises cobalt at a weight of 20-35%, iron at a weight of 10-30%, and tin at a weight of 65-85%.

[0186] Example E12 includes the subject matter of Example E10 or E11, wherein the conductive material further includes a layer comprising cobalt and iron between the conductive contact of the metallization layer and the intermetallic compound.

[0187] Example E13 includes the subject of any of Examples E10-E12, wherein the conductive material conformally surrounds the conductive contact of the metallization layer.

[0188] Example E14 includes the subject of any one of Examples E10-E13, wherein the second conductive contact of the interconnect bridge circuit module die has a thickness greater than 12 μm.

[0189] Example E15 includes the subject matter of any one of Examples E10-E14, wherein the conductive material does not include nickel.

[0190] Example E16 is a method of forming an integrated circuit package substrate, comprising: forming a first accumulation layer on a die layer, the first accumulation layer including a plurality of metallization layers; forming a first surface finishing layer on a subset of conductive contacts of the metallization layers of the first accumulation layer, the first surface finishing layer including cobalt and iron; forming a second surface finishing layer on the first surface finishing layer, the second surface finishing layer including palladium; forming a third surface finishing layer on the second surface finishing layer, the second surface finishing layer including gold; forming a second accumulation layer on the first accumulation layer; forming a cavity in the second accumulation layer above the subset of conductive contacts; and placing a die within the cavity such that the conductive contacts of the die are electrically connected to the subset of conductive contacts.

[0191] Example E17 includes the subject matter of Example E16, wherein the first surface finish layer is formed by electroplating, the second surface finish layer is formed by electroplating, and the third surface finish layer is formed by electroplating.

[0192] Example E18 includes the subject matter of Example E16 or E17, wherein the thickness of the first surface finishing layer is between 2-4 μm, the thickness of the second surface finishing layer is between 0.01-0.10 μm, and the thickness of the third surface finishing layer is between 0.01-0.10 μm.

[0193] Example E19 includes the subject of Example E18, wherein the first surface finish layer is approximately 3.3 μm thick, the second surface finish layer is approximately 0.04 μm thick, and the third surface finish layer is approximately 0.06 μm thick.

[0194] Example E20 includes the subject of any one of Examples E16-E19, wherein the first surface finish layer is not conformally formed around each of the subset of conductive contacts.

[0195] In the foregoing description, various aspects of the illustrative implementations have been described using terminology commonly used by those skilled in the art to convey the main points of the work to others skilled in the art. However, those skilled in the art will readily recognize that this disclosure may be practiced using only some of the aspects described. For illustrative purposes, specific quantities, materials, and configurations have been presented to provide a thorough understanding of the illustrative implementations. However, those skilled in the art will readily recognize that this disclosure may be practiced without all the specific details described. In other instances, well-known features have been omitted or simplified so as not to affect the understanding of the illustrative implementations.

[0196] For the purposes of this disclosure, the phrase "A and / or B" means (A), (B), or (A and B). For the purposes of this disclosure, the phrase "A, B, and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C).

[0197] As used herein, the terms “above,” “below,” “between,” “above,” and “on” can refer to the relative position of a material layer or component with respect to other layers or components. For example, a layer disposed above or below another layer may be in direct contact with said other layer, or may have one or more intermediate layers. Furthermore, a layer disposed between two layers may be in direct contact with said two layers, or may have one or more intermediate layers. In contrast, a first layer “on” a second layer is in direct contact with that second layer. Similarly, unless explicitly stated otherwise, a feature disposed between two features may be in direct contact with said adjacent feature, or may have one or more intermediate features.

[0198] The above description may use the phrases "in one embodiment" or "in an embodiment," each referring to one or more of the same or different embodiments. Furthermore, the terms "comprising," "including," "having," and the like, as used with respect to embodiments of this disclosure, are synonymous.

[0199] The term “coupled with” and its derivatives may be used in this document. “Coupled” can mean one or more of the following: “Coupled” can mean two or more elements in direct physical or electrical contact. However, “coupled” can also mean two or more elements in indirect contact with each other, but still cooperating or interacting with each other, and can mean one or more other elements are coupled or connected between the elements said to be coupled. The term “directly coupled” can mean two or more elements in direct contact.

[0200] In various embodiments, the phrase “a first feature formed, deposited or otherwise disposed on a second feature” may mean that a first feature is formed, deposited or disposed on a second feature, and that at least a portion of the first feature may be in direct contact (e.g., direct physical and / or electrical contact) or indirect contact (e.g., having one or more other features between the first and second features) with at least a portion of the second feature.

[0201] In various embodiments, the phrase “on top of” in the context of a first layer or component being on a second layer or component means that the first layer or component is directly and physically attached to the second layer or component (with no layer or component between the first and second layers or components) or that one or more intermediate layers or components are physically attached to the second layer or component.

[0202] In various embodiments, the term "adjacent" refers to layers or components that are physically in contact with each other. That is, there are no layers or components between the stated adjacent layers or components. For example, layer X adjacent to layer Y refers to a layer that is physically in contact with layer Y.

[0203] Where this disclosure refers to an element or a first element or its equivalent, such disclosure includes one or more such elements, neither requiring nor excluding two or more such elements. Furthermore, the sequence indicators (e.g., first, second, or third) used to identify the elements are used to distinguish the elements and do not indicate or imply a required or limited number of such elements, nor do they indicate a particular location or order of such elements unless otherwise specifically stated.

Claims

1. An integrated circuit packaging substrate, comprising: Multiple metallization layers in a dielectric accumulation layer; The die within the accumulation layer includes conductive contacts that are electrically connected to conductive contacts of the metallization layer; as well as The conductive material between the conductive contacts of the die and the conductive contacts of the metallization layer includes nickel, phosphorus, tin, and palladium.

2. The integrated circuit packaging substrate as described in claim 1, wherein, The conductive material includes an intermetallic compound, which includes nickel and phosphorus.

3. The integrated circuit packaging substrate as described in claim 2, wherein, The intermetallic compound comprises phosphorus at a weight of 15-30%.

4. The integrated circuit packaging substrate according to any one of claims 1-3, wherein, The conductive material includes intermetallic compounds, which include copper, nickel, tin, and palladium.

5. The integrated circuit packaging substrate as described in claim 4, wherein, The intermetallic compound comprises 20-40% copper, 20-40% nickel, and 30-50% tin by weight.

6. The integrated circuit packaging substrate according to any one of claims 1-5, wherein, The conductive material includes an intermetallic compound, which includes nickel, tin, and phosphorus.

7. The integrated circuit packaging substrate according to any one of claims 1-6, wherein, The conductive material includes a layer on the conductive pads of the metallization layer, the layer comprising nickel and phosphorus.

8. The integrated circuit packaging substrate according to any one of claims 1-7, wherein, The die is an interconnect bridge circuit module die.

9. The integrated circuit packaging substrate as described in claim 8, wherein, The interconnect bridge circuit module die includes a through-silicon via (TSV) to which the conductive contacts are connected.

10. The integrated circuit packaging substrate according to any one of claims 1-9, wherein, The die is encapsulated in a cavity or opening within the accumulated layer.

11. An integrated circuit package, comprising: Integrated circuit packaging substrate, including: Multiple metallization layers in a dielectric accumulation layer; An interconnect bridge circuit module die embedded in the accumulation layer, the interconnect bridge circuit module die including a through-hole between a first conductive contact on a first side of the interconnect bridge circuit module die and a second conductive contact on a second side of the interconnect bridge circuit module die opposite to the first side, the second conductive contact being electrically connected to a conductive contact of the metallization layer; and The conductive material between the second conductive contact of the interconnect bridge circuit module die and the conductive contact of the metallization layer, the conductive material comprising nickel, phosphorus, tin, and palladium; and The integrated circuit dies are coupled to the packaging substrate, and at least two integrated circuit dies are interconnected by the interconnect bridge circuit module dies.

12. The integrated circuit package as described in claim 11, wherein, The conductive material includes an intermetallic compound, which includes nickel and phosphorus.

13. The integrated circuit package as described in claim 12, wherein, The intermetallic compound comprises phosphorus at a weight of 15-30%.

14. The integrated circuit package according to any one of claims 11-13, wherein, The conductive material includes intermetallic compounds, which include copper, nickel, tin, and palladium.

15. The integrated circuit package as described in claim 14, wherein, The intermetallic compound comprises 20-40% copper, 20-40% nickel, and 30-50% tin by weight.

16. The integrated circuit package as described in any one of claims 11-15, wherein, The conductive material includes an intermetallic compound, which includes nickel, tin, and phosphorus.

17. The integrated circuit package as described in any one of claims 11-16, wherein, The second conductive contact of the interconnect bridge circuit module die has a thickness between 5-12 μm.

18. A method for forming an integrated circuit packaging substrate, comprising: An accumulation layer is formed on the core layer, the accumulation layer comprising a plurality of metallization layers; A cavity is formed in the accumulated layer to expose a subset of the conductive contacts of the metallization layer; A first surface finishing layer is formed on the subset of conductive contacts, the first surface finishing layer comprising nickel and having a thickness greater than 5 μm; A second surface finishing layer is formed on the first surface finishing layer, the second surface finishing layer comprising palladium; A third surface finish layer is formed on the second surface finish layer, wherein the second surface finish layer comprises gold; The die is placed inside the cavity, such that the conductive contacts of the die are electrically connected to the subset of conductive contacts.

19. The method of claim 18, wherein, The first surface finishing layer is formed by chemical plating, the second surface finishing layer is formed by chemical plating, and the third surface finishing layer is formed by dip plating.

20. The method of claim 18 or 19, wherein, The thickness of the first surface finishing layer is between 5-10 μm, the thickness of the second surface finishing layer is between 0.01-10 μm, and the thickness of the third surface finishing layer is between 0.01-10 μm.

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