Method and system for transmitting DMX512-RDM signal on power supply line

Abstract

The invention discloses a method and a system for transmitting a DMX512-RDM signal on a power supply line. The method comprises the following steps: a power supply, a controller, a bus driver respectively connected with the power supply and the controller, a two-wire power supply circuit connected with the bus driver, an impedance matcher connected with the two-wire power supply circuit, and an impedance matching circuit connected with the impedance matcher, the bus driver is connected with the two-wire power supply line, the bus adapter is connected to the two-wire power supply line, and the controlled equipment is connected with the bus adapter. The bus driver takes electricity from the power supply and supplies electricity to the controlled equipment through the two-wire power supply line and the bus adapter. According to the method, the technical cost is low, the reliability is high, the real-time performance is high, a large number of DMX512 signal cables are saved, and much inconvenience brought by the signal cables to installation, debugging, transportation and management of the DMX512-RDM system is avoided.

Description

Technical Field

[0001] This invention pertains to signal transmission systems and methods, specifically relating to a method and system for transmitting DMX512-RDM signals over a power supply line. Background Technology

[0002] DMX512 is a digital communication standard used for stage lighting, sound, and special effects equipment. Its core function is to enable precise control of up to 512 device channels through a single data cable.

[0003] It is the universal "language" in the field of stage technology, ensuring that equipment from different brands (such as lighting consoles, moving lights, and dimmers) can be compatible and communicate with each other.

[0004] The core components of a DMX512 system include: Controller – the “brain” that issues control commands, typically a lighting control console or a computer with DMX output; DMX signal cable – a dedicated cable for transmitting digital signals, requiring shielded twisted-pair cable (such as XLR 3-core / 5-core cable) to avoid interference; Controlled devices – the terminals that execute commands, such as moving head lights, LED PAR lights, smoke machines, etc., which receive and interpret signals through the DMX interface; Signal amplifier / splitter – used to enhance the signal or split the transmission when the transmission distance is too long (over 100 meters) or the number of devices is too large, ensuring signal stability.

[0005] Key features of the DMX512 system are: Number of channels – A single DMX line supports up to 512 independent control channels, each channel can output a value from 0 to 255 (corresponding to different parameters of the controlled device, such as light brightness, color, and angle); Transmission method – It uses differential signal transmission, which has strong anti-interference capabilities and is suitable for the complex electromagnetic environment of the stage; Connection method – It supports “daisy chain” connection, that is, the controlled devices are connected in series, without the need for a complex star topology.

[0006] The DMX512+RDM system is a lighting control system that adds Remote Device Management (RDM) functionality to the DMX512 system. RDM is an extension protocol of DMX512, introducing bidirectional communication capabilities. This means the controller can not only send commands to controlled devices but also receive feedback information from them, such as device model, software version, hardware version, DMX address, operating status, and error reports. Therefore, the DMX512+RDM system is becoming the industry's preferred choice.

[0007] The existing technology has the following drawbacks: DMX512-RDM systems require a large number of DMX512 signal cables to transmit DMX512-RDM signals. These cables, along with the power supply cables necessary for DMX512-RDM systems, become troublesome components in building such systems. DMX512-RDM signal cables and power supply cables belong to the low-voltage and high-voltage domains, respectively. For safety and anti-interference considerations, the two types of cables need to be laid out independently, making wiring complicated. DMX512 cables are thin and easily broken, and have a large number of connection points, resulting in a high probability of signal failure and interference, especially in mobile stage systems, making troubleshooting difficult. Furthermore, a large number of signal distributors / amplifiers are required as auxiliary equipment, making equipment installation and management complicated. Summary of the Invention

[0008] The purpose of this invention is to provide a method and system for transmitting DMX512-RDM signals on a power supply line. By utilizing the power supply line required by the DMX512-RDM system, power and DMX512-RDM signals can be transmitted simultaneously, thereby saving on dedicated DMX512 signal cables and overcoming the shortcomings of existing technologies.

[0009] The technical solution of this invention is implemented as follows: The method for transmitting DMX512-RDM signals on a power supply line provided by the present invention is characterized in that it is implemented in a system consisting of a power supply, a controller, a bus driver connected to the power supply and the controller respectively, a two-wire power supply line connected to the bus driver, an impedance matching device connected to the two-wire power supply line, at least one bus adapter connected to the two-wire power supply line, and a controlled device connected to the bus adapter. The bus driver draws power from the power supply and supplies power to the controlled device through the two-wire power supply line and the bus adapter.

[0010] The controller and the controlled device transmit the DMX512-RDM signal in half-duplex mode via the bus driver, two-wire power supply line, and bus adapter.

[0011] The controller and the controlled device transmit the DMX512-RDM signal in half-duplex mode using a real-time transparent transmission method of logic signals.

[0012] The logic signal is a serial signal composed of logic 1 and logic 0 signals of variable duration, represented by digital levels.

[0013] The real-time transparent transmission of the logic signal means that the logic signal not only maintains its original logic state during transmission, but also controls the transmission delay within the minimum range required by the system, so as to ensure that the signal is "synchronized" with the source.

[0014] The real-time transparent transmission method of the logic signal is as follows: When the controller transmits DMX512-RDM signals to the controlled device, the bus driver and the bus adapter are the signal sender and the signal receiver, respectively. When the controlled device transmits DMX512-RDM signals to the controller, the bus adapter and the bus driver are the signal sender and the signal receiver, respectively.

[0015] The signal transmitter encodes the transmission logic signal into a first narrow pulse code signal, and then converts the first narrow pulse code signal into a second narrow pulse code signal on the two-wire power supply line for transmission. The signal receiver converts the second narrow pulse code signal on the two-wire power supply line into a third narrow pulse code signal, and then decodes the third narrow pulse code signal into a reception logic signal. The logic signal is a DMX512-RDM signal, the transmission logic signal is the input signal of the signal transmitter, and the reception logic signal is the output signal of the signal receiver.

[0016] The first, second, and third narrow pulse code signals are all combinations of several consecutive narrow pulse signals representing the transmission of logic A signal and fixed-level signals representing the transmission of logic B signal, wherein logic A and logic B are mutually exclusive and take values ​​of 0 or 1.

[0017] The value range of the narrow pulse signal width Tp is: less than half of the narrow pulse signal period T, and greater than the minimum width required for the narrow pulse signal to be effectively transmitted and recognized in the system.

[0018] The narrow pulse signal is a unipolar positive narrow pulse signal or a unipolar negative narrow pulse signal, and the fixed level signal is a fixed low level signal or a fixed high level signal.

[0019] The method for encoding the transmitted logic signal into a first narrow pulse code signal is as follows: NA consecutive narrow pulse signals with a period of T represent a transmitted logic A signal with a duration of TA, and the start time of the first narrow pulse signal is consistent with the start time of the transmitted logic A signal; a fixed-level signal with a duration of TB represents a transmitted logic B signal with a duration of TB, and the start and end times of the fixed-level signal are consistent with the start and end times of the transmitted logic B signal; the period T of the narrow pulse signal is not greater than the minimum duration of the transmitted logic A signal.

[0020] When the duration TA of the transmitted logic A signal is divisible by the period T of the narrow pulse signal, the number of consecutive narrow pulses NA is equal to the duration TA of the transmitted logic A signal divided by the period T of the narrow pulse signal. When the duration TA of the transmitted logic A signal is not divisible by the period T of the narrow pulse signal, the number of consecutive narrow pulses NA is equal to the duration TA of the transmitted logic A signal divided by the period T of the narrow pulse signal, rounded down, and then incremented by one.

[0021] The method for decoding the third narrow pulse code signal into a receiving logic signal is as follows: each narrow pulse signal is decoded into a receiving logic A signal with a duration of the narrow pulse signal period T, the start and end times of the receiving logic A signal being consistent with the start and end times of the narrow pulse signal; and fixed-level signals outside the narrow pulse signal period are decoded into receiving logic B signals.

[0022] The present invention provides a system for transmitting DMX512-RDM signals over a power supply line, comprising a power supply, a controller, a bus driver connected to the power supply and the controller respectively, a two-wire power supply line connected to the bus driver, an impedance matching device connected to the two-wire power supply line, at least one bus adapter connected to the two-wire power supply line, and a controlled device connected to the bus adapter; the power supply is used for system power supply; the controller is used for DMX512-RDM system control; the bus driver is used for power supply and transmission of DMX512-RDM signals; the two-wire power supply line is used for simultaneous transmission of power and signals; the bus adapter is used for power supply and transmission of DMX512-RDM signals; the controlled device is used for receiving and transmitting DMX512-RDM signals; and the impedance matching device is used to prevent signal reflection and improve signal transmission quality.

[0023] The bus driver includes: a power isolator that connects both the power supply and the two-wire power line; a first transmitting node and a first receiving node that connect both the controller and the two-wire power line; the power isolator is used for power supply and signal isolation; the first transmitting node is used for encoding and transmitting the controller's DMX512-RDM signal; and the first receiving node is used for receiving and decoding the DMX512-RDM signal.

[0024] The bus adapter includes: a load isolator that simultaneously connects the two-wire power supply line to the controlled device, a second transmitting node, and a second receiving node; the load isolator is used for power supply and signal isolation; the second transmitting node is used for encoding and transmitting the DMX512-RDM signal of the controlled device, and the second receiving node is used for receiving and decoding the DMX512-RDM signal.

[0025] The first and second transmitting nodes include: an encoding circuit, a processing circuit connected to the encoding circuit, and an output coupling circuit connected to the encoding circuit and the processing circuit respectively; the encoding circuit is used to encode the transmitting logic signal into a first narrow pulse code signal and control the working state of the output coupling circuit according to the characteristics of the transmitting logic signal; the processing circuit is used to amplify the first narrow pulse code signal; and the output coupling circuit is used to couple the amplified first narrow pulse code signal to the two-wire power supply line to form a second narrow pulse code signal.

[0026] The first and second receiving nodes include: an input coupling circuit, a shaping circuit connected to the input coupling circuit, and a decoding circuit connected to the shaping circuit; the input coupling circuit is used to extract the second narrow pulse code signal from the two-wire power supply line, the shaping circuit is used to convert the extracted second narrow pulse code signal into a third narrow pulse code signal, and the decoding circuit is used to decode the third narrow pulse code signal into a receiving logic signal. Beneficial effects

[0027] This invention utilizes power lines to transmit DMX512-RDM signals, saving a significant amount of dedicated DMX512 signal cables. The signal transmission effect is consistent with that when using dedicated cables, but with lower cost, higher reliability, and stronger anti-interference capability.

[0028] The technical solution of the present invention will be further described below with reference to the accompanying drawings. Attached Figure Description

[0029] Figure 1 This is a block diagram illustrating the system principle of the present invention.

[0030] Figure 2 This is a block diagram of the system bus driver of the present invention.

[0031] Figure 3 This is a block diagram of the system bus adapter of the present invention.

[0032] Figure 4 This is a schematic diagram of the bus impedance matching circuit of the present invention.

[0033] Figure 5 This is a schematic diagram of the power isolator of the system of this invention.

[0034] Figure 6 This is a schematic diagram of the load isolator of the system of the present invention.

[0035] Figure 7 This is a block diagram of the first and second sending nodes of the system of the present invention.

[0036] Figure 8 This is a block diagram of the first and second receiving nodes of the system of the present invention.

[0037] Figure 9 This is a block diagram of the principle of the first and second transmitting nodes of the system of the present invention.

[0038] Figure 10 This is a block diagram of the first and second receiving nodes of the system of the present invention.

[0039] Figure 11 This is the system signal timing diagram of the present invention.

[0040] Figure 12This is a timing diagram of the DMX512-RDM signal. Detailed Implementation

[0041] The system for transmitting DMX512-RDM signals over a power supply line provided by this invention is as follows: Figure 1 As shown, the system includes a power supply, a controller, a bus driver connected to the power supply and the controller respectively, a two-wire power supply line connected to the bus driver, an impedance matching device connected to the two-wire power supply line, at least one bus adapter connected to the two-wire power supply line, and a controlled device connected to the bus adapter. The power supply is used for system power supply; the controller is used for DMX512-RDM system control; the bus driver draws power from the power supply and supplies power and transmits DMX512-RDM signals to the controlled device through the two-wire power supply line and the bus adapter; the two-wire power supply line transmits power and signals simultaneously; the bus adapter draws power and transmits DMX512-RDM signals; the controlled device is used for receiving and transmitting DMX512-RDM signals; and the impedance matching device is used to prevent signal reflection and improve signal transmission quality.

[0042] The power supply uses either AC or DC power; the controller uses a common DMX512-RDM controller, such as the H0 lighting control console from Leading Flame Technology; the two-wire power supply line uses a common two-core or three-core cable, such as RVV cable.

[0043] The bus driver, such as Figure 2 As shown, it includes: a power isolator that connects both the power supply and the two-wire power line; a first transmitting node and a first receiving node that connect both the controller and the two-wire power line. The power isolator is used for power supply and signal isolation; the first transmitting node is used for encoding and transmitting the controller's DMX512-RDM signal; and the first receiving node is used for receiving and decoding the DMX512-RDM signal.

[0044] The bus adapter, such as Figure 3 As shown, it includes: a load isolator that simultaneously connects the two-wire power supply line to the controlled device, a second transmitting node, and a second receiving node. The load isolator is used for power supply and signal isolation; the second transmitting node is used for encoding and transmitting the DMX512-RDM signal of the controlled device, and the second receiving node is used for receiving and decoding the DMX512-RDM signal.

[0045] The impedance matching device is as follows Figure 4As shown, it includes a resistor R1 and a capacitor C3 connected in series. The resistor R1 is used to prevent signal reflection and improve signal transmission quality, and the capacitor C3 is used for low-frequency signal isolation and high-frequency signal coupling. Both the resistor R1 and the capacitor C3 are commonly used components.

[0046] The controlled equipment uses a commonly used DMX512-RDM device, such as the Jiechuang series stage lights.

[0047] The power isolator, such as Figure 5 As shown, it includes: an inductor L1, used to supply power to the two-wire power supply line and to isolate high-frequency signals between the power supply and the two-wire power supply line; and a capacitor C1, used for high-frequency filtering; both the inductor L1 and the capacitor C1 are commonly used components.

[0048] The load isolator is as follows Figure 6 As shown, it includes an inductor L2 for supplying power to the controlled device and isolating high-frequency signals between the two-wire power supply line and the controlled device; and a capacitor C2 for high-frequency filtering; both inductor L2 and capacitor C2 are commonly used components.

[0049] The power supply principle of the system is as follows: See Figure 1-5 6. The power supply supplies power to the controlled device through the power isolator of the bus adapter, the two-wire power supply line, and the load isolator of the bus adapter. The difference from existing technologies is that the power isolator and the load isolator are connected in series between the power supply and the controlled device. Since the impedance of a high-frequency power inductor to a DC power supply or an AC power supply of approximately 50Hz is negligible, and the DC resistance of the inductor is extremely small, the power supply effect of this invention is no different from that of existing technologies, regardless of whether an AC or DC power supply is used.

[0050] The first and second sending nodes are as follows Figure 7 As shown, it includes: an encoding circuit, a processing circuit connected to the encoding circuit, and an output coupling circuit connected to the encoding circuit and the processing circuit respectively; the encoding circuit is used to encode the transmitted logic signal into a first narrow pulse code signal and control the working state of the output coupling circuit according to the characteristics of the transmitted logic signal; the processing circuit is used to amplify the first narrow pulse code signal; and the output coupling circuit is used to couple the amplified first narrow pulse code signal to the two-wire power supply line to form a second narrow pulse code signal.

[0051] The first and second receiving nodes are as follows Figure 8As shown, it includes: an input coupling circuit, a shaping circuit connected to the input coupling circuit, and a decoding circuit connected to the shaping circuit; the input coupling circuit is used to extract the second narrow pulse code signal from the two-wire power supply line, the shaping circuit is used to convert the extracted second narrow pulse code signal into a third narrow pulse code signal, and the decoding circuit is used to decode the third narrow pulse code signal into a receive logic signal.

[0052] The encoding circuit, processing circuit, and output coupling circuit of the first and second transmitting nodes are as follows: Figure 9 As shown, the encoding circuit is a microprocessor U1, used to encode the transmitted logic signal into the first narrow pulse code signal, and also used to control the operating state of the output coupling circuit according to the characteristics of the logic signal; the processing circuit is an operational amplifier U2, used to amplify the first narrow pulse code signal; the output coupling circuit includes a capacitor C4 and an analog switch U5, used to couple the amplified first narrow pulse code signal to the two-wire power supply line as needed by the encoding circuit, forming the second narrow pulse code signal. The connection relationship of each circuit is as follows: Figure 9 As shown, the VCD is the operating power supply; the microprocessor U1 is an STC8 series or STM32 series microcontroller; the operational amplifier is a general-purpose high-speed operational amplifier such as the OPA2350; the capacitor C4 is a common component; and the analog switch U5 is a solid-state relay GAQY214S. BUSUA and BUSB are the two poles of a two-wire power supply line, with BUSB being the common terminal for all circuits and the power supply VCD.

[0053] The input coupling circuit, shaping circuit, and decoding circuit of the first and second receiving nodes are as follows: Figure 10 As shown, the input coupling circuit includes capacitors C5 and C6 for low-frequency signal isolation and high-frequency signal coupling, resistor R2 for increasing signal input impedance and damping, and transformer T1 for signal isolation coupling. The shaping circuit includes resistors R3 and R4 for setting the signal static operating point voltage, R5 and R6 for setting the comparator reference voltage, and voltage comparator U3 for signal shaping, outputting the third narrow pulse code signal. The decoding circuit is a microprocessor U4 for signal decoding, decoding the third narrow pulse code signal into a receive logic signal. The connection relationships of each circuit are as follows: Figure 9 As shown, the VCD is the operating power supply. The microprocessor U4 is an STC8 series or STM32 series microcontroller, the voltage comparator is a general-purpose high-speed operational amplifier such as OPA2350, and the capacitors C5 and C6, and resistors R3, R4, R5, and R6 are common components. BUSA and BUSB are the two poles of the two-wire power supply line, and BUSB is the common terminal of all circuits and the power supply VCD.

[0054] The power supply VCD for the first transmitting node and the first receiving node is obtained by the power supply conversion, and the operating power supply for the second transmitting node and the second receiving node is obtained by the power supply conversion at the output of the load isolator.

[0055] Based on the above description, industry professionals can independently select relevant devices and, according to the device parameters, define and design the functions and connections of each pin, and then write related software. Further implementation details will not be elaborated upon.

[0056] The logic signal is a serial signal composed of logic 1 signals and / or logic 0 signals of variable duration, represented by digital levels. For example... Figure 11 (a) shows a serial signal consisting of two logic 0 signals with durations of TL1 and TL2 and a logic 1 signal with duration of TH1.

[0057] Although in a specific digital system, the duration of a logic signal is not continuous but an integer multiple of the system clock cycle, the present invention assumes that the duration is continuous, that is, it assumes that the system clock cycle is small enough to be negligible relative to the duration of any logic signal, so as to make the present invention more adaptable.

[0058] The system uses a real-time transparent transmission method for logic signals to transmit the DMX512-RDM signal.

[0059] The real-time transparent transmission of the logic signal means that the logic signal not only maintains its original logic state during transmission, but also controls the transmission delay within the minimum range required by the system, so as to ensure that the signal is "synchronized" with the source.

[0060] The real-time transparent transmission method of the logic signal is as follows: When the controller transmits a DMX512-RDM signal to the controlled device, the bus driver and the bus adapter are the signal sender and the signal receiver, respectively; when the controlled device transmits a DMX512-RDM signal to the controller, the bus adapter and the bus driver are the signal sender and the signal receiver, respectively; the signal sender encodes the transmitted logic signal into a first narrow pulse code signal, and then converts the first narrow pulse code signal into a second narrow pulse code signal on the two-wire power supply line for transmission; the signal receiver converts the second narrow pulse code signal on the two-wire power supply line into a third narrow pulse code signal, and then decodes the third narrow pulse code signal into a received logic signal; wherein, the logic signal is a DMX512-RDM signal, the transmitted logic signal is the input signal of the signal sender, and the received logic signal is the output signal of the signal receiver.

[0061] See Figure 1-11When the controller transmits a DMX5122-RDM signal to the controlled device through the bus driver, the two-wire power supply line, and the bus adapter, the encoding circuit of the first transmitting node of the bus driver treats the DMX512-RDM signal as a downlink transmission logic signal and encodes it into a downlink first narrow pulse code signal. This downlink first narrow pulse code signal is amplified by the processing circuit of the first transmitting node. Simultaneously, the encoding circuit controls the output coupling circuit of the first transmitting node to send the amplified downlink first narrow pulse code signal to the two-wire power supply line, becoming the downlink second narrow pulse code signal. This downlink second narrow pulse code signal then passes through the input coupling circuit and shaping circuit of the second receiving node of the bus adapter, becoming the downlink third narrow pulse code signal. The decoding circuit of the second receiving node then decodes this downlink third narrow pulse code signal to obtain a downlink received logic signal consistent with the downlink transmission logic signal. This downlink received logic signal is the DMX512-RDM signal received by the controlled device from the controller.

[0062] See Figure 1-11 When the controlled device sends a DMX512-RDM signal to the controller via the bus adapter, two-wire power supply line, and bus driver, the encoding circuit of the second transmitting node of the bus adapter treats the DMX512-RDM signal as an uplink transmission logic signal and encodes it into an uplink first narrow pulse code signal. This uplink first narrow pulse code signal is amplified by the processing circuit of the second transmitting node. Simultaneously, the encoding circuit controls the output coupling circuit of the second transmitting node to send the amplified uplink first narrow pulse code signal to the two-wire power supply line, becoming the uplink second narrow pulse code signal. This uplink second narrow pulse code signal then passes through the input coupling circuit and shaping circuit of the first receiving node of the bus driver to become the uplink third narrow pulse code signal. The decoding circuit of the first receiving node then decodes this uplink third narrow pulse code signal to obtain an uplink receiving logic signal that is consistent with the uplink transmission logic signal. This uplink receiving logic signal is the DMX512-RDM signal received by the controller from the controlled device.

[0063] The transmission of the DMX512-RDM signals of the controller and the controlled device is time-division multiplexing. During the transmission of the controller's DMX512-RDM signal, the output coupling circuit of the first transmitting node is closed, and the output coupling circuit of the second transmitting node is open. During the transmission of the controlled device's DMX512-RDM signal, the output coupling circuit of the second transmitting node is closed, and the output coupling circuit of the first transmitting node is open. The purpose of not closing the two output coupling circuits simultaneously is to avoid signal collision and attenuation. The operating state of the output coupling circuit is controlled by the encoding circuit connected to it. The encoding circuit controls the operating state of the output coupling circuit according to the characteristics of its transmitted logic signal. The characteristics of the transmitted logic signal are determined by the DMX512-RDM protocol. According to the protocol and the signal, the encoding circuit can determine whether it is necessary to transmit the received transmitted logic signal, and control the switching circuit of the output coupling circuit to close when necessary, otherwise control the switching circuit to open. Further details are omitted here.

[0064] To prevent the second narrow pulse code signal on the two-wire power supply line from being absorbed and attenuated by the power supply and the controlled device, a power isolator and a load isolator are connected in series between the power supply and the controlled device and the two-wire power supply line, respectively; to prevent the second narrow pulse code signal from being reflected and excessively distorted due to the impedance mismatch of the two-wire power supply line, an impedance matching device is connected in parallel at the end of the two-wire power supply line.

[0065] Due to the combined influence of the impedance characteristics of the first and second transmitting nodes, power isolators, load isolators, two-wire power supply lines, and impedance matching devices, the second narrow pulse code signal on the two-wire power supply line may have a large waveform distortion compared to the first narrow pulse code signal. In particular, the pulse width of the narrow pulse signal is changed, and harmonic signals appear. However, the time at which any fundamental pulse of the second narrow pulse code signal begins to appear is always consistent with the time at which the corresponding narrow pulse signal in the first narrow pulse code signal begins to appear.

[0066] The third narrow pulse code signal output by the shaping circuits of the first and second receiving nodes may have a narrow pulse signal width Tp that differs from the first narrow pulse code signal due to waveform differences between the second and first narrow pulse code signals, and further due to the influence of the input coupling circuit and the shaping circuit. However, proper design of the circuit parameters can ensure that the start time difference of each corresponding narrow pulse signal is negligible. Therefore, it can be considered that the first and third narrow pulse code signals are synchronized, but the narrow pulse signal widths may have slight differences.

[0067] The first, second, and third narrow pulse code signals are all combinations of several consecutive narrow pulse signals representing the transmission of logic A signal and fixed-level signals representing the transmission of logic B signal, wherein logic A and logic B are mutually exclusive and take values ​​of 0 or 1.

[0068] like Figure 11 The narrow pulse code signals shown in (b)-(c) are a combination of NL1 consecutive narrow pulse signals representing a transmitted logic 0 (logic A = logic 0) signal with a duration of TL1, a fixed-level signal with a duration of TH1 representing a transmitted logic 1 (logic B = logic 1) signal with a duration of TH1, and NL2 narrow pulse signals representing a transmitted logic 0 (logic A = logic 0) signal with a duration of TL2. Figure 11 The narrow pulse code signals shown in (d)-(e) are combination signals representing a fixed-level signal with a duration of TL1 for transmitting logic 0 (logic B = logic 0), NH1 narrow pulse signals with a duration of TH1 for transmitting logic 1 (logic A = logic 1), and a fixed-level signal with a duration of TL2 for transmitting logic 0 (logic B = logic 0).

[0069] The value range of the narrow pulse signal width Tp is: less than, and preferably much less than, half of the pulse signal period T, and greater than the minimum width required for effective transmission and recognition of the narrow pulse signal in the system. On the one hand, the smaller the ratio of the narrow pulse signal width Tp to the narrow pulse signal period T, the less inter-symbol interference (ISI) there is, which is more conducive to signal transmission. On the other hand, the smaller the narrow pulse signal width Tp, the smaller the pulse signal period T can be, and the higher the logic signal transmission rate can be. Therefore, the narrow pulse signal width Tp should be as small as possible. However, if the narrow pulse signal width Tp is too small, the pulse signal becomes weak, and after system attenuation and absorption, it may be difficult for the receiving node to extract and recognize it, leading to poor signal transmission reliability. Therefore, the narrow pulse signal width must be greater than a certain minimum value. The determination of the minimum value is related to the specific parameters of the system and needs to be tested and determined after the system design is completed. The optimized parameters that have been tested and passed are: when T=4µs, Tp=250ns, the transmission rate is 250Kbps; when T=800ns, Tp=100ns, the transmission rate is 1250Kbps. The narrow pulse signal is a unipolar positive narrow pulse signal or a unipolar negative narrow pulse signal, and the fixed level signal is a fixed low level signal or a fixed high level signal. (See Figure 911.) Figure 11 (b) and Figure 11 The narrow pulse signal in (e) is a unipolar negative narrow pulse signal, and the fixed level signal is a fixed high level signal. The narrow pulse signals in Figures 911(c) and 911(d) are unipolar positive narrow pulse signals. The fixed level signal is a fixed low level signal.

[0070] The method for encoding the transmitted logic signal into a first narrow pulse code signal is as follows: NA consecutive narrow pulse signals with a period of T represent a transmitted logic A signal with a duration of TA, and the start time of the first narrow pulse signal coincides with the start time of the transmitted logic A signal. A fixed-level signal with a duration of TB represents a transmitted logic B signal with a duration of TB, and the start and end times of the fixed-level signal coincide with the start and end times of the transmitted logic B signal. Logic A and logic B are mutually exclusive and take values ​​of 0 or 1, and the period T of the narrow pulse signal is not greater than the minimum duration of the transmitted logic A signal.

[0071] When the duration TA of the transmitted logic A signal is divisible by the period T of the narrow pulse signal, the number of consecutive narrow pulses NA is equal to the duration TA of the transmitted logic A signal divided by the period T of the narrow pulse signal. When the duration TA of the transmitted logic A signal is not divisible by the period T of the narrow pulse signal, the number of consecutive narrow pulses NA is equal to the duration TA of the transmitted logic A signal divided by the period T of the narrow pulse signal, rounded down, and then incremented by one.

[0072] Because transmitting a logic A signal is either transmitting a logic 0 signal or a logic 1 signal, a narrow pulse signal is either a unipolar positive narrow pulse signal or a unipolar negative narrow pulse signal, and a fixed-level signal is either a fixed high-level signal or a fixed low-level signal, there are four different encoding methods for transmitting logic signals. Among them, The first encoding method is as follows: in the method of encoding the transmitted logic signal into a first narrow pulse code signal, the transmitted logic A signal is the transmitted logic 0 signal, the transmitted logic B signal is the transmitted logic 1 signal, the narrow pulse signal is the unipolar negative narrow pulse signal, and the fixed level signal is the fixed high level signal.

[0073] The second encoding method is as follows: in the method of encoding the transmitted logic signal into a first narrow pulse code signal, the transmitted logic A signal is the transmitted logic 0 signal, the transmitted logic B signal is the transmitted logic 1 signal, the narrow pulse signal is a unipolar positive narrow pulse signal, and the fixed level signal is a fixed low level signal.

[0074] The third encoding method is as follows: in the method of encoding the transmitted logic signal into a first narrow pulse code signal, the transmitted logic A signal is the transmitted logic 1 signal, the transmitted logic B signal is the transmitted logic 0 signal, the narrow pulse signal is a unipolar positive narrow pulse signal, and the fixed level signal is a fixed low level signal.

[0075] The fourth encoding method is as follows: in the method of encoding the transmitted logic signal into a first narrow pulse code signal, the transmitted logic A signal is the transmitted logic 1 signal, the transmitted logic B signal is the transmitted logic 0 signal, the narrow pulse signal is a unipolar negative narrow pulse signal, and the fixed level signal is a fixed high level signal.

[0076] The first narrow pulse code signal varies depending on the encoding method. Figure 11 (b)-(e) are Figure 11 (a) shows the first narrow pulse code signal obtained by using the first, second, third, and fourth encoding methods, respectively. TL1 and TL2 represent the durations of two segments of transmitting logic 0 signals, and TH1 represents the duration of one segment of transmitting logic 1 signals. The period of the narrow pulse signal is T.

[0077] Figure 11 (b) The narrow pulse code signal is represented by NL1 consecutive unipolar negative narrow pulse signals to represent a transmission logic 0 signal with a duration of TL1, and the start time of the first narrow pulse signal is consistent with the start time of the transmission logic 0 signal. The fixed high-level signal with a duration of TH1 is used to represent the transmission logic 1 signal with a duration of TH1, and the start and end times of the fixed high-level signal are consistent with the start and end times of the transmission logic 1 signal. Figure 11 (c) shows a narrow pulse code signal where NL1 consecutive unipolar positive narrow pulses represent a transmission logic 0 signal of duration TL1, with the start time of the first narrow pulse signal coinciding with the start time of the transmission logic 0 signal. A fixed low-level signal of duration TH1 represents a transmission logic 1 signal of duration TH1, with the start and end times of the fixed low-level signal coinciding with the start and end times of the transmission logic 1 signal. During the transmission logic 0 signal period of duration TL1, if the transmission logic 0 signal duration TL1 is divisible by the narrow pulse signal period T, the number of consecutive narrow pulses NL1 is equal to the transmission logic 0 signal duration TL1 divided by the narrow pulse signal period T. If the transmission logic 0 signal duration TL1 is not divisible by the narrow pulse signal period T, the number of consecutive narrow pulses NL1 is equal to the transmission logic 0 signal duration TL1 divided by the narrow pulse signal period T, rounded down, and then incremented by one. The number of narrow pulses NL2 during the transmission logic 0 signal period of duration TL2 can be calculated using this method.

[0078] Figure 11 (d) The narrow pulse code signal represents a transmission logic 1 signal with a duration of TH1 by several consecutive unipolar positive narrow pulse signals, and the start time of the first narrow pulse signal is consistent with the start time of the transmission logic 1 signal. A fixed low level signal with a duration of TL1 represents a transmission logic 0 signal with a duration of TL1, and the start and end times of the fixed low level signal are consistent with the start and end times of the transmission logic 0 signal with a duration of TL1. A fixed low level signal with a duration of TL2 represents a transmission logic 0 signal with a duration of TL2, and the start and end times of the fixed low level signal are consistent with the start and end times of the transmission logic 0 signal with a duration of TL2. Figure 11(e) The narrow pulse code signal represents a transmission logic 1 signal with a duration of TH1 by a number of consecutive unipolar negative narrow pulse signals, and the start time of the first narrow pulse signal is consistent with the start time of the transmission logic 1 signal. A fixed high-level signal with a duration of TL1 represents a transmission logic 0 signal with a duration of TL1, and the start and end times of the fixed high-level signal are consistent with the start and end times of the transmission logic 0 signal with a duration of TL1. A fixed high-level signal with a duration of TL2 represents a transmission logic 0 signal with a duration of TL2, and the start and end times of the fixed high-level signal are consistent with the start and end times of the transmission logic 0 signal with a duration of TL2. During the transmission of a logic 1 signal with a duration of TH1, when the transmission duration TH1 is divisible by the narrow pulse signal period T, the number of consecutive narrow pulses NH1 is equal to the transmission duration TH1 divided by the narrow pulse signal period T. When the transmission duration TH1 is not divisible by the narrow pulse signal period T, the number of consecutive narrow pulses NH1 is equal to the transmission duration TH1 divided by the narrow pulse signal period T, rounded down, and then incremented by one.

[0079] The method for decoding the third narrow pulse code signal into a receiving logic signal is as follows: each narrow pulse signal is decoded into a receiving logic A signal with a duration of the narrow pulse signal period T. The start and end times of the receiving logic A signal are consistent with the start and end times of the narrow pulse signal. Fixed level signals outside the narrow pulse signal period are decoded into receiving logic B signals. Logic A and logic B are mutually exclusive and take values ​​of 0 or 1.

[0080] Since the narrow pulse signal of the third narrow pulse code signal is a unipolar positive narrow pulse code signal and a unipolar negative narrow pulse code signal, the fixed level signal is a fixed low level signal or a fixed high level signal, and the received logic A signal is a received logic 0 signal or a received logic 1 signal, the decoding method of the third narrow pulse code signal varies depending on the encoding method of the transmitted logic signal used.

[0081] Although the width of the narrow pulse signal in the third narrow pulse code signal may differ slightly from the width Tp of the narrow pulse signal in the first narrow pulse code signal due to transmission and recognition errors, its decoding result is independent of the narrow pulse signal width, and the third and first narrow pulse code signals are synchronized. Therefore, for ease of description below, the third narrow pulse code signal is regarded as the first narrow pulse code signal. Figure 11 The narrow pulse code signals shown in (b)-(e) can be regarded as timing diagrams of the first or third narrow pulse code signals.

[0082] The decoding method using the first encoding method is as follows: each unipolar negative narrow pulse signal is decoded into a received logic 0 signal with a duration equal to the narrow pulse signal period T, the start and end times of which coincide with the start and end times of the unipolar negative narrow pulse signal; fixed high-level signals outside the unipolar negative narrow pulse signal period are decoded into received logic 1 signals, such as... Figure 11 As shown in (f), it is composed of Figure 11 (b) shows the timing diagram of the received logic signals obtained by decoding the unipolar negative narrow pulse code signal. The start time of each received logic 0 signal segment coincides with the start time of the first unipolar negative narrow pulse signal in that segment, and the end time coincides with the end time of the last unipolar negative narrow pulse signal in that segment. The duration is equal to the number of unipolar negative narrow pulses in that segment multiplied by the narrow pulse signal period T. For example, the duration of the first received logic 0 signal segment is NL1xT. The start time of the received logic 1 signal following this received logic 0 signal is the end time of that received logic 0 signal segment, and the end time is the start time of the next received logic 0 signal segment.

[0083] The decoding method using the second encoding method is as follows: each unipolar positive narrow pulse signal is decoded into a receive logic 0 signal with a duration equal to the narrow pulse signal period T, the start and end times of which coincide with the start and end times of the unipolar positive narrow pulse signal; fixed low-level signals outside the unipolar positive narrow pulse signal period are decoded into receive logic 1 signals, such as... Figure 11 As shown in (f), it is composed of Figure 11 (c) shows the timing diagram of the received logic signals obtained by decoding the unipolar negative narrow pulse code signal. The start time of each received logic 0 signal segment coincides with the start time of the first unipolar positive narrow pulse signal in that segment, and the end time coincides with the end time of the last unipolar positive narrow pulse signal in that segment. The duration is equal to the number of unipolar positive narrow pulses in that segment multiplied by the narrow pulse signal period T. For example, the duration of the first received logic 0 signal segment is NL1xT. The start time of the received logic 1 signal following this received logic 0 signal is the end time of that received logic 0 signal segment, and the end time is the start time of the next received logic 0 signal segment.

[0084] The decoding method using the third encoding method is as follows: each unipolar positive narrow pulse signal is decoded into a receive logic 1 signal with a duration equal to the narrow pulse signal period T, the start and end times of which coincide with the start and end times of the unipolar positive narrow pulse signal; fixed low-level signals outside the unipolar positive narrow pulse signal period are decoded into receive logic 0 signals, such as... Figure 11 As shown in (g), Figure 11(d) shows the timing diagram of the received logic signals obtained by decoding the unipolar positive narrow pulse code signal. The start time of each received logic 1 signal segment coincides with the start time of the first unipolar positive narrow pulse signal in that segment, and the end time coincides with the end time of the last unipolar positive narrow pulse signal in that segment. The duration is equal to the number of unipolar positive narrow pulses in that segment multiplied by the narrow pulse signal period T. For example, the duration of the first received logic 1 signal segment is NH1xT. The start time of the received logic 0 signal following this received logic 1 signal is the end time of that received logic 1 signal segment, and the end time is the start time of the next received logic 1 signal segment.

[0085] The decoding method using the fourth encoding method is as follows: each unipolar negative narrow pulse signal is decoded into a receive logic 1 signal with a duration equal to the narrow pulse signal period T, the start and end times of which coincide with the start and end times of the unipolar negative narrow pulse signal; fixed high-level signals outside the unipolar negative narrow pulse signal period are decoded into receive logic 0 signals, such as... Figure 11 As shown in (g), Figure 11 (e) shows the timing diagram of the received logic signals obtained by decoding the unipolar negative narrow pulse code signal. The start time of each received logic 1 signal segment coincides with the start time of the first unipolar negative narrow pulse signal in that segment, and the end time coincides with the end time of the last unipolar negative narrow pulse signal in that segment. The duration is equal to the number of unipolar negative narrow pulses in that segment multiplied by the narrow pulse signal period T. For example, the duration of the first received logic 1 signal segment is NH1xT. The start time of the received logic 0 signal following this received logic 1 signal is the end time of that received logic 1 signal segment, and the end time is the start time of the next received logic 1 signal segment.

[0086] See Figure 11 (a)-(c) and Figure 11 (f) When the duration of all logic 0 signals is divisible by the period T of the narrow pulse signal, the decoded received logic signal is the same as and synchronized with the transmitted logic signal. Figure 11(a) can be viewed as a timing diagram of both transmitted and received logic signals. When the duration TL1 of a certain logic 0 signal cannot be divided evenly by the period T of the narrow pulse signal, since the number of narrow pulses NL1 is equal to the duration TL1 divided by the period T of the narrow pulse signal, rounded down and then added by 1, the duration TLJ of the decoded received logic 0 signal is equal to NL1 multiplied by T. TLJ is greater than TL1, and the difference between the two is DL1 = TLJ - TL1, and the maximum difference is one period T of the narrow pulse signal. However, the start time of the received logic 0 signal is consistent with the start time of the corresponding transmitted logic 0 signal, and the duration of the received logic 1 signal after the received logic 0 signal will be shortened by DL1. The start time of the received logic 1 signal lags behind the start time of the corresponding transmitted logic 1 signal by one time DL1, while the end time is still consistent with the end time of the corresponding transmitted logic 1 signal.

[0087] See Figure 11 (a), Figure 11 (d)-(e) and Figure 11 (g) When the duration of all logic 1 signals is divisible by the period T of the narrow pulse signal, the decoded received logic signal is the same as and synchronized with the transmitted logic signal. Figure 11 (a) This can be viewed as a timing diagram for both transmitted and received logic signals. When the duration TH1 of a certain logic 1 signal is not divisible by the period T of the narrow pulse signal, since the number of narrow pulses NH1 is equal to the duration TH1 divided by the period T, rounded down, and then incremented by 1, the decoded duration THJ of the received logic 1 signal is equal to NH1 multiplied by T. THJ is greater than TH1, and the difference between the two is DH1 = THJ - TH1, with a maximum difference of one narrow pulse signal period T. However, the start time of this received logic 1 signal is consistent with the start time of the corresponding transmitted logic 1 signal. The duration of the received logic 0 signal following this received logic 1 signal will be shortened by DH1, and the start time of this received logic 0 signal will lag behind the start time of the corresponding transmitted logic 0 signal by one time DH1, while the end time is still consistent with the end time of the corresponding transmitted logic 0 signal.

[0088] In the above diagram and text, 'x' represents a multiplication sign. The method for encoding the transmitted logic signal into a first narrow pulse code signal further includes: using NA consecutive narrow pulse signals with a period of T to represent a transmitted logic A signal of duration TA, where the start time of the first narrow pulse signal coincides with the start time of the transmitted logic A signal; and using a fixed-level signal of duration TC to represent a transmitted logic B signal of duration TB, where the start time of the fixed-level signal coincides with the end time of the last narrow pulse signal among the NA narrow pulse signals representing the preceding transmitted logic A signal, and the end time coincides with the end time of the transmitted logic B signal. The difference between this method and the aforementioned method for encoding the transmitted logic signal into a first narrow pulse code signal is that when the duration TA of the transmitted logic A signal is not divisible by the period T of the narrow pulse signal, the transmitted logic A signal is extended until the end of the last narrow pulse signal, while the duration TC of the subsequent transmitted logic B signal is shortened to begin from the end of the last narrow pulse signal representing the preceding transmitted logic A signal, and the extension and shortening durations are equal. Based on the foregoing analysis and introduction, those skilled in the art can easily understand and implement this method. Meanwhile, the decoding result of the third narrow pulse code signal obtained by this method is completely consistent with the decoding result of the third narrow pulse code signal obtained by the aforementioned method, and the relevant details of this method will not be described in detail.

[0089] In summary: When the duration TA of all transmitted logic A signals represented by the narrow pulse signal is divisible by the period T of the narrow pulse signal, the transmitted logic signals can be transmitted in real time without errors, meaning the received logic signals are logically identical and synchronized with the transmitted logic signals. When the duration of a segment of transmitted logic A signals represented by the narrow pulse signal is not divisible by the period T of the narrow pulse signal, the duration of the received logic A signal corresponding to that segment of transmitted logic A signals will be extended by a time TD, while the duration of the received logic B signal corresponding to the subsequent transmitted logic B signal will be shortened by a time TD, and the maximum value of TD is... In a narrow pulse signal period T, the start time of the received logic A signal coincides with the start time of the transmitted logic A signal, and the end time of the received logic B signal coincides with the end time of the transmitted logic B signal. Whether the transmitted logic B signal is divisible by the narrow pulse signal period T does not affect the transmission error. The transmission error does not accumulate; that is, the transmission error of a segment of transmitted logic A signal only affects the transmission error of the immediately following transmitted logic B signal and will not affect the real-time transmission of subsequent transmitted logic signals starting from the next segment of transmitted logic A signal. The first narrow pulse signal can be used as a synchronization signal for the received logic A signal.

[0090] Clearly, the minimum length of the transmittable logic signal, i.e., the transmittable data bit width Tw, is equal to the narrow pulse signal period T. This means the maximum transmittable data rate is 1 / T. Other transmittable rates are: 1 / (2T) when the data bit width Tw is twice the narrow pulse signal period T, 1 / (3T) when the data bit width is three times the narrow pulse signal period T, and so on. Furthermore, it can be deduced that when the narrow pulse signal period T is less than half the asynchronous serial data bit width Tw, asynchronous serial data at any rate of 1 / Tw can be transmitted.

[0091] The DMX512-RDM signal timing is as follows: Figure 12 As shown, 1 is the reset signal, 2 is the reset marker, 3 is the field, 4 is the start bit, 5 is the least significant data bit, 6 is the most significant data bit, 7 is the stop bit, 8 is the stop bit, 9 is the idle time between fields, 10 is the pre-reset marker, 11 is the interval between reset signals, 12 is the reset sequence, 13 is the DMX512-RDM data packet, 14 is the start code (field 0 data), 15 is field 1, and 16 is field n (maximum 512). The DMX512-RDM signal includes several parts: the reset signal, fields, pre- and post-reset markers, and the idle time between fields. The reset signal is a logic 0 signal with a duration greater than 88µs, the field is an asynchronous serial signal with a bit width of 4µs (rate of 250Kbps), and the others are logic 1 signals of varying durations. Currently, a dedicated line is used to transmit DMX512-RDM signals. This invention directly transmits DMX512-RDM signals on the two-wire power supply line of stage lighting equipment, thereby reducing material costs and installation and debugging expenses by saving on dedicated DMX512 signal transmission lines.

[0092] The method for transparently transmitting the DMX512-RDM signal is as described above. The narrow pulse signal width Tp is 250 ns, and the narrow pulse signal period T is 4 μs, equal to the data bit width of the DMX512-RDM signal. A unipolar negative narrow pulse signal is selected for encoding. During this process, the errors between the received DMX512-RDM signal and the transmitted DMX512-RDM signal are as follows: field error is 0, reset signal duration error is 4 μs (negligible relative to the protocol-specified length), and other logic 1 signal duration errors are also 4 μs (negligible relative to the protocol-specified length). Furthermore, when the narrow pulse signal width Tp is 100 ns, the narrow pulse signal period T is 0.8 μs (one-fifth of the DMX512-RDM signal data bit width), and a unipolar negative narrow pulse signal is selected for encoding, the aforementioned field error is 0, the reset signal duration error is 0.8 μs, and the duration error of other logic 1 signals is 0.8 μs. The error is smaller, and the real-time performance is stronger.

[0093] The beneficial effects of the method and system described in this invention are analyzed in summary as follows: 1. Because a power isolator and a load isolator are connected in series between the power supply and the second-wire power supply line, and between the second-wire power supply line and the controlled equipment, the narrow pulse code signal on the second-wire power supply line is theoretically completely free from the interference of fixed or random signals from the power supply and the controlled equipment. The signal transmission quality is only related to the impedance characteristics of the designable second-wire power supply line, the transmitting node, and the receiving node. That is, through the system of the present invention, the second narrow pulse code signal is transmitted in a closed environment with controllable parameters, and the signal transmission quality can be fully guaranteed. This is the fundamental reason why the system of the present invention has a low bit error rate and high reliability.

[0094] 2. The encoding and decoding methods described in this invention are extremely simple and can be implemented using ordinary microprocessors or sequential logic circuits. Furthermore, the transmitted signal is a narrow pulse signal, and the only requirement during transmission is to preserve the timing accuracy of the pulse occurrence, while allowing for a relatively large degree of waveform distortion. The transmission objective can be achieved using simple circuits. Therefore, compared to existing technologies that rely on complex algorithms and modulation / demodulation processes to transmit logic signals, the circuitry of this invention is extremely simple and the cost is extremely low.

[0095] 3. The system of this invention creates a relatively ideal environment for narrow pulse signal transmission. By rationally designing the parameters of each circuit, the narrow pulse signal width Tp can be significantly reduced, thereby reducing the logic signal bit width Tw and improving the communication rate. Theoretically, this rate can reach over 10Mbps.

[0096] 4. The system of the present invention achieves the goal of real-time bit-by-bit transmission of logic signals. No matter how many bits the logic signal is, the time lag between receiving the logic signal and sending the logic signal is at most one narrow pulse signal period T, thus achieving extremely high real-time performance. In implementing bit-by-bit transmission of logic signals, the system of the present invention can not only use a simple microprocessor, but also directly use a simple sequential logic circuit, thus achieving extremely low cost and extremely high reliability.

[0097] 5. The significant features of the system of this invention are: a high speed of over 1Mbps and a low cost of less than 5 yuan. The high speed characteristic allows it to be applied to systems with high speed requirements, such as DMX512 systems and digital broadcasting systems, while the low cost characteristic gives it a very high cost-performance advantage in any applicable field.

[0098] 6. Ben's invention technology has the characteristic of high speed, and can transmit data at any speed when the maximum speed is below 40%.

[0099] 7. The technology of this invention provides a cost-effective solution for transmitting DMX512-RDM signals over a two-line power supply line, which is of great significance for the upgrade of stage lighting systems.

[0100] 8. The transmission rate of this technology reaches over 1Mbps, while the rate of DMX512-RDM signal is only 250Kbps. Therefore, multiple DMX512-RDM signals can be transmitted simultaneously on a single two-wire power supply line, solving the problem of sufficient power supply but insufficient DMX512-RDM channels.

Claims

1. A method for transmitting DMX512-RDM signals over a power supply line, characterized in that: Implemented in a system comprising a power supply, a controller, a bus driver connected to the power supply and the controller respectively, a two-wire power supply line connected to the bus driver, an impedance matching device connected to the two-wire power supply line, at least one bus adapter connected to the two-wire power supply line, and a controlled device connected to the bus adapter: The bus driver draws power from the power supply and supplies power to the controlled device through the two-wire power supply line and the bus adapter. The controller and the controlled device transmit the DMX512-RDM signal in half-duplex mode via the bus driver, two-wire power supply line, and bus adapter.

2. The method for transmitting DMX512-RDM signals on a power supply line according to claim 1, characterized in that: The controller and the controlled device transmit the DMX512-RDM signal in half-duplex mode using a real-time transparent transmission of logic signals. The logic signal is a serial signal composed of logic 1 and logic 0 signals of variable duration, represented by digital levels; The real-time transparent transmission of the logic signal means that the logic signal not only maintains its original logic state during transmission, but also controls the transmission delay within the minimum range required by the system, so as to ensure that the signal is "synchronized" with the source.

3. The method for transmitting DMX512-RDM signals on a power supply line according to claim 2, characterized in that: The real-time transparent transmission method of the logic signal is as follows: When the controller transmits DMX512-RDM signals to the controlled device, the bus driver and the bus adapter are the signal sender and the signal receiver, respectively. When the controlled device transmits DMX512-RDM signals to the controller, the bus adapter and the bus driver are the signal sender and the signal receiver, respectively. The signal transmitter encodes the transmission logic signal into a first narrow pulse code signal, and then converts the first narrow pulse code signal into a second narrow pulse code signal on the two-wire power supply line for transmission. The signal receiver converts the second narrow pulse code signal on the two-wire power supply line into a third narrow pulse code signal, and then decodes the third narrow pulse code signal into a reception logic signal. The logic signal is a DMX512-RDM signal, the transmission logic signal is the input signal of the signal transmitter, and the reception logic signal is the output signal of the signal receiver. The first, second, and third narrow pulse code signals are all combinations of several consecutive narrow pulse signals representing the transmission of logic A signal and fixed-level signals representing the transmission of logic B signal, wherein logic A and logic B are mutually exclusive and take values ​​of 0 or 1.

4. The method for transmitting DMX512-RDM signals on a power supply line according to claim 3, characterized in that: The value range of the narrow pulse signal width Tp is: less than half of the narrow pulse signal period T, and greater than the minimum width required for the narrow pulse signal to be effectively transmitted and recognized in the system.

5. The method for transmitting DMX512-RDM signals on a power supply line according to claim 3. Law, its characteristics are The narrow pulse signal is a unipolar positive narrow pulse signal or a unipolar negative narrow pulse signal, and the fixed level signal is a fixed low level signal or a fixed high level signal.

6. The method for transmitting DMX512-RDM signals on a power supply line according to claim 3, characterized in that: The method for encoding the transmitted logic signal into a first narrow pulse code signal is as follows: A transmission logic A signal with a duration of TA is represented by NA consecutive narrow pulse signals with a period of T, and the start time of the first narrow pulse signal is the same as the start time of the transmission logic A signal. A transmission logic B signal with a duration of TB is represented by a fixed-level signal with a duration of TB, and the start and end times of the fixed-level signal are the same as the start and end times of the transmission logic B signal. The period T of the narrow pulse signal is not greater than the minimum duration of the transmission logic A signal. When the duration TA of the transmitted logic A signal is divisible by the period T of the narrow pulse signal, the number of consecutive narrow pulses NA is equal to the duration TA of the transmitted logic A signal divided by the period T of the narrow pulse signal. When the duration TA of the transmitted logic A signal is not divisible by the period T of the narrow pulse signal, the number of consecutive narrow pulses NA is equal to the duration TA of the transmitted logic A signal divided by the period T of the narrow pulse signal, rounded down, and then incremented by one.

7. The method for transmitting DMX512-RDM signals on a power supply line according to claim 3, characterized in that: The method for decoding the third narrow pulse code signal into a receiving logic signal is as follows: each narrow pulse signal is decoded into a receiving logic A signal with a duration of the narrow pulse signal period T, the start and end times of the receiving logic A signal being consistent with the start and end times of the narrow pulse signal; and fixed-level signals outside the narrow pulse signal period are decoded into receiving logic B signals.

8. A system for transmitting DMX512-RDM signals over a power supply line, characterized in that: The system includes a power supply, a controller, a bus driver connected to the power supply and the controller respectively, a two-wire power supply line connected to the bus driver, an impedance matching device connected to the two-wire power supply line, at least one bus adapter connected to the two-wire power supply line, and a controlled device connected to the bus adapter. The power supply is used for system power supply; the controller is used for DMX512-RDM system control; the bus driver is used for power supply and transmission of DMX512-RDM signals; the two-wire power supply line is used for simultaneous transmission of power and signals; the bus adapter is used for power supply and transmission of DMX512-RDM signals; the controlled device is used for receiving and transmitting DMX512-RDM signals; and the impedance matching device is used to prevent signal reflection and improve signal transmission quality.

9. The system for transmitting DMX512-RDM signals on a power supply line according to claim 8, characterized in that: The bus driver includes: a power isolator that connects both the power supply and the two-wire power line; a first transmitting node and a first receiving node that connect both the controller and the two-wire power line; the power isolator is used for power supply and signal isolation; the first transmitting node is used for encoding and transmitting the controller's DMX512-RDM signal; and the first receiving node is used for receiving and decoding the DMX512-RDM signal.

10. The system for transmitting DMX512-RDM signals on a power supply line according to claim 9, characterized in that: The bus adapter includes: a load isolator that simultaneously connects the two-wire power supply line to the controlled device, a second transmitting node, and a second receiving node; the load isolator is used for power supply and signal isolation; the second transmitting node is used for encoding and transmitting the DMX512-RDM signal of the controlled device, and the second receiving node is used for receiving and decoding the DMX512-RDM signal.

11. The system for transmitting DMX512-RDM signals over a power supply line according to claim 10, characterized in that: The first and second transmitting nodes include: an encoding circuit, a processing circuit connected to the encoding circuit, and an output coupling circuit connected to the encoding circuit and the processing circuit respectively; the encoding circuit is used to encode the transmitting logic signal into a first narrow pulse code signal and control the working state of the output coupling circuit according to the characteristics of the transmitting logic signal; the processing circuit is used to amplify the first narrow pulse code signal; and the output coupling circuit is used to couple the amplified first narrow pulse code signal to the two-wire power supply line to form a second narrow pulse code signal.

12. The system for transmitting DMX512-RDM signals on a power supply line according to claim 10, characterized in that: The first and second receiving nodes include: an input coupling circuit, a shaping circuit connected to the input coupling circuit, and a decoding circuit connected to the shaping circuit; the input coupling circuit is used to extract the second narrow pulse code signal from the two-wire power supply line, the shaping circuit is used to convert the extracted second narrow pulse code signal into a third narrow pulse code signal, and the decoding circuit is used to decode the third narrow pulse code signal into a receiving logic signal.

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