Programmable low-temperature-drift under-voltage locking circuit

Abstract

The invention discloses a programmable low-temperature-drift under-voltage locking circuit, and the circuit comprises a reference current generation module which is used for outputting an initial reference current, and the input end of the reference current generation module is connected with a first reference voltage; the zero-temperature-drift current source array is used for generating reference current according to the initial reference current and the second reference voltage and mirroring the reference current to a plurality of parallel branches; the trimming module is used for adjusting the total current of the parallel branches by using a programmable resistor and a capacitor; the sampling module is used for sampling the total current and the power supply voltage of the parallel branches output by the trimming module; and the comparison output module is used for comparing the power supply voltage with a sampling voltage generated according to the programmable resistor and the total current of the parallel branches, and outputting a pair of differential signals. Through the reference current generation module, the zero-temperature-drift current source array, the trimming module, the sampling network and the voltage comparator, the problems that in an existing resistance voltage division type undervoltage locking scheme, a threshold value is fixed and cannot be adjusted, and the scheme is sensitive to temperature changes are solved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of electronic circuit, in particular to a programmable low temperature drift under voltage lockout circuit. BACKGROUND

[0002] Under voltage lockout (UVLO) is a protection circuit used in electronic devices to shut off the power supply when the supply voltage is below a predetermined threshold. This technology is widely used in embedded systems, ballasts and power management chips to prevent system failure or component damage by monitoring the supply voltage.

[0003] The under voltage lockout circuit is composed of a voltage sampling module, a comparator, an output buffer and a hysteresis feedback loop. Different protection thresholds can be set by adjusting the voltage dividing resistors. Some DC / DC converters integrate this function to maintain standby state before the input voltage reaches a safe value to reduce power consumption. The circuit design based on bandgap reference voltage source structure uses high-order temperature compensation technology. The maximum lockout voltage drift is 0.3V when the temperature is-30~140℃, which improves the system stability. Some low voltage and low power design can control the static power consumption below 2μW, which is suitable for battery powered devices.

[0004] The existing resistance voltage division type UVLO scheme mainly relies on fixed resistance voltage division ratio to set the under voltage protection threshold, such as Figure 1 Once this design is determined, the threshold cannot be changed, which lacks flexibility. In addition, the temperature coefficient of the resistance will cause the voltage division ratio to drift with temperature, which will affect the stability of the threshold point. This temperature drift phenomenon is particularly evident in wide temperature range applications, which seriously affects the performance and reliability of the circuit. SUMMARY

[0005] In view of the above problems of the prior art, the technical problem to be solved by the present application is to solve the problems of fixed threshold and sensitivity to temperature changes in the existing resistance voltage division type under voltage lockout (UVLO) scheme by using a reference current generation module, a zero temperature drift current source array, a trimming module, a sampling network and a voltage comparator.

[0006] One of the technical solutions adopted by the present application is to provide a programmable low temperature drift under voltage lockout circuit, comprising: a reference current generation module, which is connected to a first reference voltage at the input end, and is used to output an initial reference current according to the first reference voltage, a bipolar transistor and a matching resistance; a zero temperature drift current source array, which is used to generate a reference current according to the initial reference current and a second reference voltage, and mirror the reference current to a plurality of parallel branches; a trimming module, configured to adjust the total current of the parallel branches by using programmable resistance and capacitance; a sampling module, configured to sample the total current of the parallel branches and the voltage of the power supply output by the trimming module; a comparison output module, configured to compare the voltage of the power supply and the sampling voltage generated according to the programmable resistance and the total current of the parallel branches, and output a pair of differential signals.

[0007] Further, the reference current generation module comprises a first PMOS tube, a second PMOS tube, a first NPN transistor, a second NPN transistor, a first resistor and a second resistor; wherein the source of the first PMOS tube is connected to a reference voltage V1, the drain of the first PMOS tube is electrically connected to the source of the second PMOS tube, the gates of the first PMOS tube and the second PMOS tube are electrically connected and grounded, and the drain of the second PMOS tube is electrically connected to the collector of the first NPN transistor. The base of the first NPN transistor is short-circuited to the collector, the collector is electrically connected to the drain of the second PMOS tube, and the emitter is grounded; the base of the second NPN transistor is electrically connected to the base of the first NPN transistor, and the emitter is connected to the ground through the first resistor and the second resistor in series.

[0008] Further, the zero-temperature drift current source array comprises a main branch and bias generation module and a trimmable current mirror array, wherein the main branch and bias generation module is configured to generate a reference current according to an initial reference current and a second reference voltage, and the trimmable current mirror array is configured to mirror the reference current to a plurality of parallel branches.

[0009] Further, the main branch and bias generation module comprises a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube and a sixth PMOS tube; wherein the source of the third PMOS tube is connected to a second reference voltage V2, the gate and the drain of the third PMOS tube are connected to each other; the source of the fourth PMOS tube is electrically connected to the drain of the third PMOS tube, the gate and the drain of the fourth PMOS tube are connected to each other, and further connected to the collector of the second NPN transistor; the gate of the fifth PMOS tube is electrically connected to the gate of the third PMOS tube, constituting a current mirror; the drain of the fifth PMOS tube is electrically connected to the source of the sixth PMOS tube; and the gate of the sixth PMOS tube is connected to the gate of the fourth PMOS tube, constituting a current mirror.

[0010] Further, the trimmable current mirror array comprises a plurality of series branches composed of seventh to twenty-first PMOS tubes; wherein the sources of the seventh PMOS tube, the tenth PMOS tube, the thirteenth PMOS tube, the sixteenth PMOS tube and the nineteenth PMOS tube are all connected to the second reference voltage V2, and the gates are all electrically connected to the gate of the third PMOS tube. The source of the eighth PMOS, the eleventh PMOS, the fourteenth PMOS, the seventeenth PMOS, the twentieth PMOS is electrically connected with the drain of the seventh PMOS, the tenth PMOS, the thirteenth PMOS, the sixteenth PMOS, the nineteenth PMOS respectively, and the gate is electrically connected with the gate of the fourth PMOS; The gate of the sixth PMOS, the eighth PMOS, the eleventh PMOS, the fourteenth PMOS, the seventeenth PMOS, the twentieth PMOS is electrically connected with the gate of the fourth PMOS, forming a common source and common gate structure. The drain of the ninth PMOS, the twelfth PMOS, the fifteenth PMOS, the eighteenth PMOS, the twenty-first PMOS is electrically connected with the anode of the first diode, and the gate of the eighteenth PMOS, the twenty-first PMOS is grounded.

[0011] Further, the adjustment module adjusts the total current size of the parallel branch through OPT adjustment; the gate of the ninth PMOS, the twelfth PMOS, the fifteenth PMOS is connected with the output end of the adjustment module, and the conduction or turn-off of the ninth PMOS, the twelfth PMOS, the fifteenth PMOS is controlled through the adjustment module, so as to change the total current size of the parallel branch.

[0012] Further, the sampling module includes a first diode, a first capacitor, a fourth resistor, a fifth resistor and a programmable resistor; the cathode of the first diode is electrically connected with the sampling node through the fifth resistor; the programmable resistor and the first capacitor are connected in series, and the two ends of the series connection are connected in parallel between the sampling node and the ground; the first end of the fourth resistor is electrically connected with the power supply, for sampling the power supply voltage.

[0013] Further, the comparison output module is a COMP comparator; the non-inverting input end of the COMP comparator is electrically connected with the second end of the fourth resistor; the inverting input end of the COMP comparator is electrically connected with the sampling node through the fifth resistor.

[0014] Further, the COMP comparator outputs a pair of differential signals, wherein the positive phase differential signal is used as an under-voltage lock signal.

[0015] Further, the feedback module comprises a twenty-second PMOS tube and a first NMOS tube, a gate of the twenty-second PMOS tube is connected to the inverted differential signal, a gate of the first NMOS tube is connected to the non-inverted differential signal; a source of the twenty-second PMOS tube and a drain of the first NMOS tube are both connected to the reference current mirror of the zero temperature drift current source array output; the drain of the twenty-second PMOS tube and the source of the first NMOS tube are both connected to the non-inverted input terminal of the COMP comparator, and are both connected to the ground through a third resistor.

[0016] The programmable low temperature drift under-voltage lockout circuit has at least the following beneficial effects: 1. A temperature-independent under-voltage protection threshold is provided. By adopting the technology of combining a zero-temperature-coefficient current source with a matching resistance value, a high-stability reference voltage is generated to overcome the defect that the threshold point drifts with temperature in the traditional resistance voltage division scheme, thereby realizing under-voltage detection in the full working temperature range.

[0017] 2. A programmable under-voltage protection threshold is realized. By introducing an external programmable resistance and an internal adjustable current source array, the protection threshold can be flexibly set and calibrated according to the specific application requirements, thereby solving the problem of limited applicability of the traditional fixed threshold circuit.

[0018] 3. The consistency and reliability of the under-voltage protection circuit are provided. By integrating a one-time programmable trimming module, the threshold deviation caused by the process angle deviation of the integrated circuit is compensated, thereby ensuring the consistency of the protection threshold between different chips and improving the production yield and product reliability.

[0019] 4. The stability of the under-voltage judgment process is enhanced. By introducing a transient enhancement mechanism with hysteresis characteristics, the comparison output oscillation caused by noise or fluctuations near the critical point of the power supply voltage is effectively suppressed, thereby improving the robustness of the system in complex working environments. BRIEF DESCRIPTION OF DRAWINGS

[0020] The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiments of the application and serve to explain the application without, however, to limit it improperly. In the drawings: Figure 1 FIG. 1 is a typical under-voltage protection circuit structure schematic diagram.

[0021] Figure 2 FIG. 2 is a programmable low temperature drift under-voltage lockout circuit structure schematic diagram of the present application.

[0022] Figure 3 FIG. 3 is a working simulation waveform diagram of power supply voltage SVDD power-on and power-off of the gate drive circuit of the embodiment of the present application. DETAILED DESCRIPTION

[0023] The application will be further described below with reference to the drawings.

[0024] Please refer to Figure 2 , the schematic diagram of the programmable low temperature drift under-voltage lockout circuit structure of the application. The programmable low temperature drift under-voltage lockout circuit comprises: The reference current generation module is connected to a first reference voltage at the input end, and is used for outputting an initial reference current according to the first reference voltage, a bipolar transistor and a matching resistance. The conventional under-voltage protection circuit adopts resistance direct voltage division, and the threshold value will drift due to the temperature coefficient of the voltage division resistance. In order to overcome this defect, one of the core innovations of the application is to introduce a zero temperature coefficient reference current.

[0025] In some embodiments, the reference current generation module comprises a first PMOS tube (MP1), a second PMOS tube (MP2), a first NPN transistor (NPN1), a second NPN transistor (NPN1), a first resistance (R1) and a second resistance (R2); wherein the source of the first PMOS tube is connected to a reference voltage V1, the drain of the first PMOS tube is electrically connected to the source of the second PMOS tube, the gates of the first PMOS tube and the second PMOS tube are electrically connected and grounded, and the drain of the second PMOS tube is electrically connected to the collector of the first NPN transistor; The base of the first NPN transistor is short-circuited to the collector, the collector is electrically connected to the drain of the second PMOS tube, and the emitter is grounded; the base of the second NPN transistor is electrically connected to the base of the first NPN transistor, and the emitter is connected to the ground through the first resistance and the second resistance in series. The initial reference current generation mechanism is based on the cooperative work of the first reference voltage, the bipolar transistor and the matching resistance. Specifically, the negative temperature coefficient of the base-emitter voltage V_BE of the bipolar transistor (the first NPN transistor NPN1 and the second NPN transistor NPN2) and the positive temperature coefficient of the difference ΔV_BE between the V_BE of the two transistors under different current densities are weighted and synthesized by the carefully designed matching resistance pair (the first resistance R1 and the second resistance R2). The temperature coefficients of the matching resistance pair are selected to be able to compensate each other, so as to finally generate a high stability reference current I_REF which changes little with temperature.

[0026] The zero temperature drift current source array comprises a main branch and a bias generation module and a tunable current mirror array, wherein the main branch and the bias generation module are used for generating a reference current according to the initial reference current and a second reference voltage, and the tunable current mirror array is used for mirroring the reference current to a plurality of parallel branches.

[0027] In some embodiments, the zero-temperature-drift current source array is the core of the present invention for achieving low-temperature-drift characteristics, and it consists of a main branch and multiple mirror branches.

[0028] Main branch and bias generation module: The main branch includes a third PMOS transistor (MP3), a fourth PMOS transistor (MP4), a fifth PMOS transistor (MP5), and a sixth PMOS transistor (MP6). The source of MP3 is connected to another fixed reference voltage V2, and its gate and drain are connected to each other. The source of MP4 is connected to the drain of MP3, and its gate and drain are connected to each other, and further connected to the collector of the second NPN transistor (NPN2). The gate of MP5 is connected to the gate of MP3, forming a current mirror, and the drain of MP5 is connected to the source of MP6. The gate of MP6 is connected to the gate of MP4, forming a current mirror, and the drain of MP6 is connected to the source of MP22 and the drain of MN1.

[0029] Adjustable current mirror array: The current source array also includes multiple series branches consisting of the seventh to twenty-first PMOS transistors (MP7~MP21). These branches are configured to precisely mirror the main branches (MP3, MP4).

[0030] Specifically, the sources of MP7, MP10, MP13, MP16, and MP19 are all connected to the fixed reference voltage V2, and their gates are all connected to the gate of MP3 to form the input side of the current mirror.

[0031] The sources of MP8, MP11, MP14, MP17, and MP20 are connected to the drains of MP7, MP10, MP13, MP16, and MP19, respectively, and their gates are all connected to the gate of MP4, forming the input side of the cascode current mirror.

[0032] Each mirror branch consists of three PMOS transistors connected in series, for example: First mirror branch: MP7 (source connected to V2), MP8, MP9.

[0033] Second mirror branch: MP10 (source connected to V2), MP11, MP12.

[0034] Third mirror branch: MP13 (source connected to V2), MP14, MP15.

[0035] Fourth mirror branch: MP16 (source connected to V2), MP17, MP18.

[0036] Fifth mirror branch: MP19 (source connected to V2), MP20, MP21.

[0037] The gates of MP6, MP8, MP11, MP14, MP17 and MP20 are connected with the gate of MP4, forming a common source and common gate structure, so as to improve the precision of the current mirror and the output impedance.

[0038] The end transistors in the branch, including MP9, MP12, MP15, MP18, MP21, have their drains connected to the anode of diode D1. The gates of MP18 and MP21 are connected to ground, and the gates of MP9, MP12 and MP15 are connected to the trimming module.

[0039] The trimming module is used to adjust the total current of the parallel branch by using programmable resistance and capacitance. The trimming module is used to fine-tune the under-voltage lock threshold. The gates of some end transistors (such as MP9, MP12 and MP15) are connected to the output of the trimming module, and the conduction or turn-off of the end transistors is controlled by the trimming module, so as to change the total current flowing into the output node and realize digital programming of the threshold.

[0040] The sampling module is used to sample the total current of the parallel branch output by the trimming module and the power supply voltage.

[0041] Specifically, the sampling module is connected to the sampling node (CMP-) through the cathode of the first diode D1 and the fifth resistance (R5). A programmable resistance (Ruv) and a capacitance (Cuv) are connected in series and then connected in parallel between the sampling node (CMP-) and ground, which is used to generate a reference voltage for under-voltage detection and play a filtering role.

[0042] The fourth resistance (R4) is connected between the power supply (SVDD) and the sampling node (CMP-), which is used to sample the power supply voltage.

[0043] The comparison output module is used to compare the power supply voltage and the sampling voltage generated according to the programmable resistance and the total current of the parallel branch, and output a pair of differential signals. The sampling node (CMP-) and another comparison node (CMP+) are connected to the two input terminals of the voltage comparator (COMP). The voltage comparator (COMP) outputs a pair of differential signals (VOUT+, VOUT-). Among them, the VOUT+ signal is the final under-voltage lock signal. The differential output also acts on the circuit through the feedback network composed of MP22 and MN1, so as to enhance the decision speed and stability of the comparator.

[0044] In combination Figure 1 , the under-voltage lock circuit of the present application realizes accurate and stable monitoring of the power supply voltage SVDD in the working process by using the unique zero temperature drift current source and programmable sampling network. The complete working process is described in chronological order as follows: First stage: SVDD power-up and circuit initialization 1. Power supply setup: When the power supply voltage SVDD starts to rise from 0V, the internal reference voltage module starts to work and generates the required reference voltages V1 and V2.

[0045] 2. Zero temperature drift current source startup: Under the bias of the reference voltages V1 and V2, the (zero temperature coefficient) current source composed of MP1, MP2, NPN1, NPN2 and matching resistors R1 and R2 is first started. The current is mirrored to the main branch of the cascode current mirror composed of MP3, MP4, MP5, MP6, etc. MP3 and MP4 generate a stable initial reference current I_REF.

[0046] 4. Programmable threshold voltage generation: The stable I_REF current is mirrored to the binary weighted current branches (MP7~MP21) controlled by the OTP trimming logic. The total current I_TOTAL after all branches are merged flows through the programmable resistor R_UV, generating an accurate, low temperature drift, undervoltage lockout threshold voltage V_THRESHOLD (i.e. the voltage of the CMP- node), V_THRESHOLD = I_TOTAL * R_UV.

[0047] This threshold can be externally programmed by selecting different R_UV resistance values, and the error caused by process deviation can be calibrated by trimming I_TOTAL through OTP.

[0048] Second stage: normal operation and monitoring state 5. Power supply sampling and comparison: The power supply voltage SVDD generates a power supply sampling voltage at the CMP+ node through resistor R4.

[0049] 6. Undervoltage judgment: The voltage comparator COMP continuously compares the power supply sampling voltage at the CMP+ node with the threshold voltage V_THRESHOLD.

[0050] When SVDD is normal (higher than the set threshold): the power supply sampling voltage at the CMP+ node is higher than V_THRESHOLD, and the comparator output VOUT+ is high, indicating that the power supply is normal and the system can work normally.

[0051] Transient enhancement standby during SVDD power-up (less than threshold voltage): In this state, the NMOS transistor MN1 in the transient enhancement module is in the off state.

[0052] Vcmp-= VDD * R3 / (R3+R24) Transient enhancement starts when SVDD power-up approaches less than threshold voltage: in this state, VOUT+ is high, and the NMOS transistor MN1 in the transient enhancement module is in the on state.

[0053] Vcmp = VDD * R3 / (R3+R24) + Ihys" * R3 Third stage: SVDD power down and UVLO trigger 7. Threshold detection: As SVDD starts to drop, the sampled voltage at CMP- node also drops through R4.

[0054] 8. Critical point comparison: When SVDD drops to the point that its sampled voltage equals (or slightly lower than) V_THRESHOLD set by zero temperature drift current and R_UV, the output state of voltage comparator COMP flips.

[0055] 9. Protection signal output: The comparator output VOUT+ jumps from high to low. This low level signal is the valid UVLO signal, which will inform the following logic control circuit that the system is about to enter UVLO state.

[0056] 10. Hysteresis and transient enhancement: At the same time, the low level of VOUT+ turns off NMOS MN1 in transient enhancement module, and the high level of VOUT- turns off MP22. This injected current is equivalent to a transient drop in the voltage of CMP- node, which introduces a hysteresis window for the comparator. This hysteresis ensures that once the UVLO is triggered, even if there are small fluctuations or noise in SVDD due to load changes, it will not cause the comparator output to oscillate, making the protection state stable and reliable until SVDD is completely powered down or rises significantly above the threshold voltage.

[0057] Fourth stage: SVDD power up and exit protection 11. Power recovery: When SVDD starts to power up from zero, the circuit repeats the initialization process of the first stage.

[0058] 12. Exit protection: Only when SVDD continues to rise, so that its sampled voltage not only exceeds the fixed V_THRESHOLD, but also overcomes the hysteresis voltage introduced by the transient enhancement module, will the comparator output VOUT+ flip from low to high, releasing the UVLO state, and the system returns to normal operation.

[0059] The simulation results of power up and down are shown in the following waveform diagram Figure 3 .

[0060] In summary, compared with the prior art, the present scheme has significant technical advantages and improvements, mainly reflected in the following aspects: 1. Threshold fixed and non-adjustable problem: Traditional resistance voltage division under-voltage lockout circuit adopts fixed resistance voltage division ratio. Once the circuit design is finalized and the chip is manufactured, the under-voltage protection threshold becomes fixed and cannot be adjusted according to actual application requirements. This limits the adaptability and flexibility of the circuit in different application environments. This scheme introduces a programmable interface, allowing the threshold of the under-voltage lockout circuit to be flexibly set. Users can adjust the threshold of the under-voltage protection according to different application scenarios and requirements. This innovative design greatly improves the adaptability and practicality of the circuit, enabling it to function in a wider range of applications.

[0061] 2. Sensitive to temperature changes: In traditional resistance voltage division under-voltage lockout circuits, due to the influence of the temperature coefficient of resistance, the voltage division ratio will change with temperature, causing the under-voltage protection threshold to drift with temperature. This temperature drift not only reduces the accuracy of the under-voltage lockout circuit, but also may affect the stability and reliability of the circuit. This scheme uses a zero-temperature drift current source array and a trimming module to carefully select matching resistors for the current source array, effectively reducing the impact of temperature drift on threshold accuracy. The positive and negative temperature coefficient resistors compensate for each other at different temperatures, generating a zero-temperature current that ensures the stability of the under-voltage protection trigger point. In addition, by precisely controlling the current ratio, the threshold drift caused by process angle changes is further offset, achieving high stability within the operating temperature range.

[0062] 3. Lack of systematic compensation scheme: Existing under-voltage lockout circuit designs often lack a systematic compensation scheme, especially for BCD (Bipolar / CMOS / DMOS) process resistance matching characteristics and temperature coefficient optimization circuit architecture. This scheme uses an innovative zero-temperature drift current architecture and matching resistor design, not only solving the threshold fixed and non-adjustable and sensitive to temperature changes problems, but also introducing a systematic temperature compensation mechanism. This mechanism is specifically optimized for BCD process resistance matching characteristics and temperature coefficients, providing a complete circuit architecture that is adjustable and not affected by temperature drift. This not only improves the accuracy and stability of the under-voltage lockout circuit, but also enhances its adaptability and reliability under different process conditions.

[0063] This scheme is an under-voltage lockout solution with high flexibility, high stability and high accuracy. Compared with existing resistance voltage division under-voltage lockout circuits, the design of this scheme significantly improves the adaptability and reliability of the circuit in different application scenarios and process conditions, bringing important innovations and breakthroughs to the development of under-voltage protection technology.

[0064] The application prospect of the present scheme is wide, especially in electronic devices and systems that require high precision and stability. For example, in automotive electronics, industrial automation, communication equipment and portable electronic devices, the under-voltage lockout circuit is a key component to ensure the stable operation of the system. By providing programmable under-voltage protection thresholds, the present scheme allows device manufacturers to flexibly adjust the under-voltage protection settings according to specific application requirements, thereby optimizing system performance. In addition, its low temperature drift characteristic enables it to maintain stable working performance in environments with large temperature variations, such as outdoor or industrial environments. The design of matching resistance pairs and the temperature compensation mechanism further enhance its reliability under different environmental conditions. Therefore, the present scheme is not only suitable for current high-performance electronic applications, but also provides a solid foundation for future technological innovation.

[0065] The above only expresses the preferred embodiments of the present application, which are described in detail and specifically, but cannot be understood as limiting the scope of the patent. It should be noted that for ordinary skilled in the art, without departing from the concept of the present application, several modifications and improvements can be made, which are within the scope of protection of the present application. Therefore, the scope of protection of the present application patent should be subject to the appended claims.

Claims

1. A programmable low temperature drift under voltage lockout circuit, characterized by, The application relates to a zero-temperature-drift current source array, which comprises the following modules: a reference current generation module, the input end of which is connected to a first reference voltage, and which is used for outputting an initial reference current according to the first reference voltage, a bipolar transistor and a matching resistor; a zero-temperature-drift current source array, which is used for generating a reference current according to the initial reference current and a second reference voltage, and mirroring the reference current to a plurality of parallel branches; a trimming module, which is used for adjusting the total current of the parallel branches by using programmable resistors and capacitors; a sampling module, which is used for sampling the total current of the parallel branches output by the trimming module and a power supply voltage; a comparison output module, which is used for comparing the power supply voltage with a sampling voltage generated according to the programmable resistors and the total current of the parallel branches, and outputting a pair of differential signals.

2. The programmable low drift dropout latching circuit of claim 1, wherein, The reference current generation module comprises a first PMOS tube, a second PMOS tube, a first NPN transistor, a second NPN transistor, a first resistor and a second resistor; wherein the source of the first PMOS tube is connected to a reference voltage V1, the drain of the first PMOS tube is electrically connected to the source of the second PMOS tube, the gates of the first PMOS tube and the second PMOS tube are electrically connected and grounded, and the drain of the second PMOS tube is electrically connected to the collector of the first NPN transistor. The base of the first NPN transistor is short-circuited to the collector, the collector is electrically connected to the drain of the second PMOS tube, and the emitter is grounded; the base of the second NPN transistor is electrically connected to the base of the first NPN transistor, and the emitter is connected to the ground through the first resistor and the second resistor in series.

3. The programmable low drift brownout lockout circuit of claim 1, wherein, The zero-temperature-drift current source array comprises a main branch and bias generation module and a trimmable current mirror array; the main branch and bias generation module is used for generating a reference current according to the initial reference current and the second reference voltage; and the trimmable current mirror array is used for mirroring the reference current to a plurality of parallel branches.

4. The programmable low drift brownout lockout circuit of claim 3, wherein, The main branch and bias generation module comprises a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube and a sixth PMOS tube; wherein the source of the third PMOS tube is connected to a second reference voltage V2, the gate and the drain of the third PMOS tube are connected to each other; the source of the fourth PMOS tube is electrically connected to the drain of the third PMOS tube, the gate and the drain of the fourth PMOS tube are connected to each other, and the gate and the drain are further connected to the collector of the second NPN transistor; the gate of the fifth PMOS tube is electrically connected to the gate of the third PMOS tube, and the fifth PMOS tube and the sixth PMOS tube constitute a current mirror.

5. The programmable low drift brownout lockout circuit of claim 4, wherein, The trimmable current mirror array comprises a plurality of series branches composed of seventh to twenty-first PMOS tubes; wherein the sources of the seventh PMOS tube, the tenth PMOS tube, the thirteenth PMOS tube, the sixteenth PMOS tube and the nineteenth PMOS tube are all connected to the second reference voltage V2, and the gates are all electrically connected to the gate of the third PMOS tube. The source of the eighth PMOS, eleventh PMOS, fourteenth PMOS, seventeenth PMOS and twentieth PMOS is electrically connected with the drain of the seventh PMOS, tenth PMOS, thirteenth PMOS, sixteenth PMOS and nineteenth PMOS respectively, and the gate is electrically connected with the gate of the fourth PMOS; The gate of the sixth PMOS, eighth PMOS, eleventh PMOS, fourteenth PMOS, seventeenth PMOS and twentieth PMOS is electrically connected with the gate of the fourth PMOS, forming a common source and common gate structure; The drain of the ninth PMOS, twelfth PMOS, fifteenth PMOS, eighteenth PMOS and twenty-first PMOS is electrically connected with the anode of the first diode; the gate of the eighteenth PMOS and twenty-first PMOS is grounded.

6. The programmable low drift brownout lockout circuit of claim 5, wherein, The tuning module adjusts the total current size of the parallel branch through OPT tuning; the gate of the ninth PMOS, twelfth PMOS and fifteenth PMOS is connected with the output end of the tuning module, and the conduction or turn-off of the tuning module is controlled, so as to change the total current size of the parallel branch.

7. The programmable low drift brownout lockout circuit of claim 1, wherein, The sampling module includes a first diode, a first capacitor, a fourth resistor, a fifth resistor and a programmable resistor; the cathode of the first diode is electrically connected with the sampling node through the fifth resistor; the programmable resistor and the first capacitor are connected in series, and the two ends of the series connection are connected in parallel between the sampling node and the ground; the first end of the fourth resistor is electrically connected with the power supply, for sampling the power supply voltage.

8. The programmable low drift brownout lockout circuit of claim 7, wherein, The comparison output module is a COMP comparator; the non-inverting input end of the COMP comparator is electrically connected with the second end of the fourth resistor; the inverting input end of the COMP comparator is electrically connected with the sampling node through the fifth resistor.

9. The programmable low drift brownout lockout circuit of claim 8, wherein, The COMP comparator outputs a pair of differential signals, in which the positive phase differential signal is used as an under-voltage lock signal.

10. The programmable low drift brownout lockout circuit of claim 9, wherein, The feedback module includes a twenty-second PMOS and a first NMOS, the gate of the twenty-second PMOS is connected with the inverted differential signal, and the gate of the first NMOS is connected with the positive phase differential signal; the source of the twenty-second PMOS and the drain of the first NMOS are connected with the reference current mirror output by the zero temperature drift current source array; the drain of the twenty-second PMOS and the source of the first NMOS are electrically connected with the non-inverting input end of the COMP comparator, and are connected with the ground through a third resistor.

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