Data prefetching method and device based on PSRAM, medium and program product
By pre-reading data in PSRAM and storing it in a first-in-first-out queue, the problem of limited data transmission rate in the prior art is solved, and uninterrupted data reading and improved bus bandwidth are achieved.
Patent Information
- Application Number
- CN202511333709.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-09-18
- Publication Date
- 2026-01-30
AI Technical Summary
In the prior art, accessing PSRAM data requires repeatedly performing the steps of enabling the current page, reading data, and disabling the current page, which limits the data transfer rate. Furthermore, existing methods increase time and space consumption by recombining PSRAM data into SRAM.
Before the bus sends a request, the controller sends a second request message to the register of the first-in-first-out queue. Data is read from the PSRAM in advance and stored in the register-controlled first-in-first-out queue until a preset length threshold is reached. Then, when a bus request is received, the data is directly transmitted from the queue to the bus.
By eliminating the time required for the controller to read data from the PSRAM, uninterrupted data reading is achieved, improving data transmission efficiency and bus bandwidth.
Smart Images
Figure CN121434112A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of data storage, and particularly relates to a data prefetching method and device based on PSRAM, a storage medium, an electronic device and a computer program product. BACKGROUND
[0002] As a commonly used peripheral storage device, PSRAM (pseudo static random access memory) combines the high density of DRAM (dynamic random access memory) and the ease of use of SRAM (static random access memory), and provides an efficient and stable data storage solution for many embedded systems, consumer electronics and industrial control devices.
[0003] However, when accessing data in the PSRAM, reading the next page of data in the PSRAM, or reading data again after the PSRAM is closed, the three steps of opening the current page enable, reading data and closing the current page enable need to be repeatedly performed, which seriously limits the data transmission rate of the PSRAM.
[0004] The prior art recombines the data read from the PSRAM, and then stores the recombined data in the SRAM to obtain continuous page data from the SRAM, but this method needs to increase the time and address space for carrying to recombine the data, and still limits the transmission rate, so this method cannot fundamentally solve the limitation of the PSRAM in transmitting data. That is, in the prior art, in order to reduce the time for reading data from the PSRAM, the data in the PSRAM is read in advance, recombined and arranged, and then placed in the SRAM.
[0005] Therefore, the method of the prior art needs to waste a lot of time and space before the bus can read the data in the PSRAM. SUMMARY
[0006] In view of the problem in the prior art that a large amount of time and storage space needs to be consumed to obtain data in the PSRAM, the present application mainly provides a data prefetching method and device based on PSRAM, a storage medium, an electronic device and a computer program product.
[0007] In order to achieve the above object, the first technical scheme of the present application is: a data prefetching method based on PSRAM, comprising: before a bus sends a first request for reading data stored in a pseudo-static random memory, sending second request information to a register for controlling a first-in-first-out queue by a controller, wherein the first request and the second request both include a start address for reading data and a reading length; the register for controlling the first-in-first-out queue reads data stored in the pseudo-static random memory from the second start address as a starting point according to the second request information, and stores the read data in the first-in-first-out queue controlled by the register until the length of the data stored in the first-in-first-out queue controlled by the register is the second reading length; when the register for controlling the first-in-first-out queue receives the first request sent by the bus, the data is transmitted from the first-in-first-out queue controlled by the register to the bus according to the first start address and the first reading length corresponding to the first request in the first-in-first-out reading rule.
[0008] Optionally, the register for controlling the first-in-first-out queue reads data stored in the pseudo-static random memory from the second start address as a starting point according to the second request information, and stores the read data in the first-in-first-out queue controlled by the register until the length of the data stored in the first-in-first-out queue controlled by the register is the second reading length, comprising: setting a storage length threshold of data in the first-in-first-out queue controlled by the register; and when the length of the data stored in the first-in-first-out queue controlled by the register is less than the storage length threshold, reading data from the pseudo-static random memory according to the second request information to supplement into the first-in-first-out queue controlled by the register, so that the length of the data stored in the first-in-first-out queue controlled by the register is equal to the storage length threshold.
[0009] Optionally, when the length of the data stored in the first-in-first-out queue controlled by the register is less than the storage length threshold, reading data from the pseudo-static random memory according to the second request information to supplement into the first-in-first-out queue controlled by the register, comprising: taking the difference between the length of the data stored in the first-in-first-out queue controlled by the register and the storage length threshold as the second reading length of the second request information; and taking the address corresponding to the last data obtained from the register for controlling the first-in-first-out queue as the second start address of the second request information.
[0010] Optionally, when the register for controlling the first-in-first-out queue receives the first request sent by the bus, the data is transmitted from the first-in-first-out queue controlled by the register to the bus according to the first start address and the first reading length corresponding to the first request in the first-in-first-out reading rule, comprising: if the current first start address of the current first request and the first end address of the last first request are continuous addresses, the data is continuously transmitted from the first-in-first-out queue controlled by the register to the bus in the first-in-first-out reading rule.
[0011] Optionally, the storage length threshold of the register is configured through the bus.
[0012] The second technical solution adopted by the present application is a data prefetching device based on PSRAM, comprising: an access information acquisition module, configured to issue a second request information to a register controlling a first-in-first-out queue through a controller before a first request for reading data stored in a pseudo-static random access memory is issued through a bus, wherein the first request and the second request both include a start address of reading data and a reading length; a data reading module, configured to control the register controlling the first-in-first-out queue to read data stored in the pseudo-static random access memory from the second start address as a starting point according to the second request information and store the read data in the first-in-first-out queue controlled by the register until the length of the data stored in the first-in-first-out queue controlled by the register is the second reading length; and a data transmission module, configured to transmit data from the first-in-first-out queue controlled by the register to the bus according to the first start address and the first reading length corresponding to the first request in a first-in-first-out reading rule when the register controlling the first-in-first-out queue receives the first request issued through the bus.
[0013] The third technical solution adopted by the present application is a computer readable storage medium storing a computer program / instruction, wherein the computer program / instruction is operated to execute the data prefetching method based on PSRAM in the first technical solution.
[0014] The fifth technical solution adopted by the present application is a computer program product comprising a computer program / instruction, wherein the computer program / instruction is executed by a processor to realize the data prefetching method based on PSRAM in the first technical solution.
[0015] The present application saves the time for the controller to read data from the PSRAM when the bus acquires data, improves the data transmission efficiency, and when the requested data is continuous, the present application can realize uninterrupted data reading, greatly improving the bus bandwidth. BRIEF DESCRIPTION OF DRAWINGS
[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or prior art description will be briefly introduced. Obviously, the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.
[0017] Figure 1 is a schematic diagram of one specific embodiment of the data prefetching method based on PSRAM of the present application;
[0018] Figure 2is a schematic diagram of one specific embodiment of a data prefetching device based on PSRAM.
[0019] The specific embodiments of the present application have been shown and described in the above-described drawings and text. These drawings and text are not meant to limit the scope of the present application in any way but are merely meant to illustrate the present application to one of ordinary skill in the art by reference to a particular embodiment. DETAILED DESCRIPTION
[0020] The preferred embodiments of the present application will be described in detail below with reference to the drawings, so that the advantages and features of the present application can be more easily understood by those skilled in the art, and the scope of protection of the present application can be more clearly defined.
[0021] It should be noted that, in this text, relational terms such as first and second are used merely to distinguish one entity or action from another, and do not necessarily require or imply any actual such relationship or order between or among the entities or actions. Also, the terms "comprises", "comprising", or any other variations thereof are intended to cover non-exclusive inclusions, so that a process, method, article, or apparatus that comprises a list of elements does not only include those elements, but can also include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without more limitations, the elements defined by the phrase "comprises" do not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes the elements.
[0022] In view of the technical problems existing in the prior art, a method is needed that can fetch data from PSRAM on demand without increasing the data transfer time and address space. The present application modifies the control logic of the controller between the PSRAM and the bus, and reads data from the PSRAM in advance when the controller has not yet received a bus request for PSRAM data access, and stores the read data in the FIFO (First-In First-Out queue) of the controller. When a read request arrives, the data is directly fetched from the FIFO and delivered to the bus. Moreover, when the data stored in the FIFO is less than a preset length threshold, the FIFO automatically supplements data from the PSRAM using consecutive data addresses. This method directly omits the time for the controller to read data from the PSRAM when data transmission begins, and when the requested data is consecutive, the data can be read uninterruptedly, greatly improving the bandwidth of the system.
[0023] The technical solutions of the present application and how the technical solutions solve the above technical problems will be described in detail below with specific embodiments. The specific embodiments described below can be combined with each other to form new embodiments. For the same or similar ideas or processes described in one embodiment, they can not be described again in other embodiments.
[0024] Figure 1 An embodiment of the PSRAM-based data prefetching method is shown.
[0025] Figure 1 The PSRAM-based data prefetching method shown includes: step S101, before a first request for reading data stored in a pseudo-static random memory is issued on a bus, issuing second request information to a register controlling a first-in-first-out queue through a controller, wherein the first request and the second request both include a start address of reading data and a reading length; step S102, the register controlling the first-in-first-out queue reads data stored in the pseudo-static random memory from the second start address as a starting point according to the second request information, and stores the read data in the first-in-first-out queue controlled by the register, until the length of the data stored in the first-in-first-out queue controlled by the register is the second reading length; step S103, when the register controlling the first-in-first-out queue receives the first request issued on the bus, the data is transmitted from the first-in-first-out queue controlled by the register to the bus according to the first start address and the first reading length corresponding to the first request according to the first-in-first-out reading rule. This specific embodiment saves the time for the controller to read data from the PSRAM when the bus acquires data, improves the data transmission efficiency, and when the requested data is continuous, the present application can realize uninterrupted data reading, greatly improving the bus bandwidth.
[0026] Specifically, in the prior art, in order to reduce the time for reading data from the PSRAM, the data in the PSRAM is usually read in advance, and then the read data is rearranged and placed in the SRAM (static random access memory) after being rearranged. When the data needs to be read again, the data is read from the SRAM. Such an operation mode needs to occupy a large amount of time and space, therefore the present application proposes a PSRAM-based data prefetching method, which directly omits the time for the controller to read data from the PSRAM when starting transmission, and when the requested data is continuous, uninterrupted data reading can be realized, thereby improving the bandwidth of the bus.
[0027] In one specific embodiment of the present application, the storage length threshold of the register is configured through the bus.
[0028] To achieve the aforementioned data reading from PSRAM, this application utilizes the coordinated operation of four modules: a bus interface, a register module, a controller, and a FIFO, to achieve the purpose of pre-fetching data from PSRAM. Specifically, the bus interface detects data read operations from the PSRAM via the bus, i.e., it detects whether the bus has issued a data read request and whether the bus has successfully read the required data; the register is configured by the bus, and the length and initial address of the prefetched data are set in the register; the controller judges the information received from the bus interface, modifies the length of the prefetched data, determines the starting address of the read data, and also determines whether the addresses of the data read requests issued by the bus are consecutive; and the FIFO reads data from the PSRAM.
[0029] exist Figure 1 In the embodiment shown, the PSRAM-based data prefetching method includes step S101, in which a second request is sent by the controller to the register controlling the first-in-first-out queue before the bus issues a first request to read the data stored in the pseudo-static random access memory. Both the first request and the second request include the starting address and the length of the data to be read.
[0030] Specifically, before the bus issues the first request to read data from the PSRAM, the controller pre-stores the data to be read from the PSRAM into a register-controlled FIFO (First-In-First-Out) queue. The length of data read from the FIFO queue depends on the prefetch length configured in the register, i.e., the read length of the second request. The starting address of the read depends on the prefetch initial address, i.e., the second starting address. When the bus accesses the PSRAM, the first request information, including the first starting address and the first read length, is transmitted to the controller through the bus interface. Simultaneously, the controller compares the current request information with the previous request information to determine if the addresses are consecutive. If they are consecutive, the register no longer issues a read request to the PSRAM, and automatic data filling is performed; that is, the FIFO automatically replenishes data from the PSRAM, and the bus directly reads data from the FIFO. This ensures the continuity of data reading and improves data reading efficiency.
[0031] exist Figure 1 In the embodiment shown, the PSRAM-based data prefetching method includes step S102, which controls the register of the first-in-first-out queue to read the data stored in the pseudo-static random access memory starting from the second starting address according to the second request information, and stores the read data in the first-in-first-out queue controlled by the register until the length of the data stored in the first-in-first-out queue controlled by the register is the second read length.
[0032] In one specific embodiment of this application, step S102 includes: setting a data storage length threshold in the register; and when the length of the data stored in the register-controlled first-in-first-out queue is less than the storage length threshold, reading data from the pseudo-static random access memory to supplement the register-controlled first-in-first-out queue according to the second request information, so that the length of the data stored in the controlled first-in-first-out queue register is equal to the storage length threshold.
[0033] exist Figure 1 In the embodiment shown, the PSRAM-based data prefetching method includes step S103, whereby when the register controlling the first-in-first-out queue receives a first request from the bus, data is transmitted from the register-controlled first-in-first-out queue to the bus according to the first starting address and the first read length corresponding to the first request.
[0034] Specifically, the second starting address information is stored in the register of the control FIFO (First-In-First-Out queue) through the data register. The control FIFO register sends the second starting address information and the second read length information to the PSRAM interface in sequence according to the corresponding control signal. After waiting for several clock cycles, the FIFO completes data reading and buffering. At this time, the FIFO will buffer the data read from the PSRAM. When the FIFO receives the first request information, it sends the data to the bus interface through the data register according to the corresponding control signal, thereby completing the data reading.
[0035] In one specific embodiment of this application, step S103 includes: if the current first start address of the current first request is a continuous address with the first end address of the previous first request, then data is continuously transferred from the register to the bus according to the first-in-first-out reading rule.
[0036] Furthermore, the difference between the length of the stored data in the first-in-first-out queue controlled by the register and the storage length threshold is used as the second read length of the second request information; the address corresponding to the last data obtained by the register controlling the first-in-first-out queue is used as the second starting address of the second request information.
[0037] Specifically, if the current data read address and the previous data read address are consecutive, the bus will directly read data from the FIFO, while the PSRAM will transfer data to the FIFO until the bus data read operation stops. At the same time as the data read operation is completed, the FIFO is in a fully loaded state, and the PSRAM will stop transferring data.
[0038] In one specific embodiment of this application, the storage length threshold is a fixed value that does not change with the size of the data read.
[0039] Specifically, changing the size of the data stored in PSRAM does not affect the prefetched data; in other words, the length of the prefetched data can be modified according to the settings.
[0040] Before issuing a first request from the bus to read data stored in the pseudo-static random access memory (PSRAM), this application first sends a second request message to the register controlling the first-in-first-out (FIFO) queue via the controller. This causes the FIFO queue to pre-read data from the PSRAM. Upon receiving the second request message, the register controlling the FIFO queue reads the data stored in the PSRAM starting from the second starting address of the second request message and stores the read data in the register-controlled FIFO queue. The FIFO queue continues to read data from the PSRAM until the length of the data stored in the register-controlled FIFO queue equals the second read length. Through data pre-reading and storage, this application transfers a portion of the data in the PSRAM to the register-controlled FIFO queue for storage. Then, when the register controlling the FIFO queue receives the first request from the bus, it transfers the data required by the bus to the bus from the register-controlled FIFO queue according to the first starting address and the first read length corresponding to the first request, following the FIFO read rule. This process avoids direct data access to the PSRAM by the bus, thereby improving data access efficiency.
[0041] Figure 2 This paper illustrates a specific embodiment of a PSRAM-based data prefetching device according to this application.
[0042] exist Figure 2 In the specific embodiment shown, the PSRAM-based data prefetching device mainly includes: an access information acquisition module 201, used to send a second request message to the register controlling the first-in-first-out queue via the controller before the bus issues a first request to read the data stored in the pseudo-static random access memory, wherein both the first request and the second request include the starting address and the reading length of the data; a data reading module 202, used to control the register controlling the first-in-first-out queue to read the data stored in the pseudo-static random access memory starting from the second starting address according to the second request message, and store the read data in the register-controlled first-in-first-out queue until the length of the data stored in the register-controlled first-in-first-out queue is the second reading length; and a data transmission module 203, used to transmit data from the register-controlled first-in-first-out queue to the bus according to the first starting address and the first reading length corresponding to the first request, according to the first-in-first-out reading rule, when the register controlling the first-in-first-out queue receives the first request issued by the bus.
[0043] The PSRAM-based data prefetching apparatus provided in this application can be used to execute the PSRAM-based data prefetching method described in any of the above embodiments. Its implementation principle and technical effect are similar, and will not be repeated here.
[0044] In one specific embodiment of this application, the functional modules of the PSRAM-based data prefetching device may be directly in hardware, in software modules executed by a processor, or in a combination of both.
[0045] Software modules may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disks, removable disks, CD-ROMs, or any other form of storage medium known in this art. An exemplary storage medium is coupled to the processor, enabling the processor to read information from and write information to the storage medium.
[0046] The processor can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic, discrete hardware components, or any combination thereof. A general-purpose processor can be a microprocessor, but alternatively, it can be any conventional processor, controller, microcontroller, or state machine. The processor can also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors incorporating a DSP core, or any other such configuration. Alternatively, the storage medium can be integrated with the processor. The processor and storage medium can reside in an ASIC. The ASIC can reside in the user terminal. Alternatively, the processor and storage medium can reside as discrete components in the user terminal.
[0047] In another specific embodiment of this application, a computer-readable storage medium is provided, which stores a computer program / instructions that are operated to perform the PSRAM-based data prefetching method described in the above embodiments.
[0048] In one specific embodiment of this application, a computer program product includes a computer program / instruction that, when executed by a processor, implements the PSRAM-based data prefetching method described in the above embodiments.
[0049] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.
[0050] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.
[0051] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.
Claims
1. A method for data prefetching based on PSRAM, characterized in that, The method comprises: Before a first request for reading data stored in the pseudo-static random memory is sent by a bus, a second request information is sent by a controller to a register for controlling a first-in-first-out queue, wherein the first request and the second request both comprise a start address for reading data and a reading length; The register for controlling the first-in-first-out queue reads data stored in the pseudo-static random memory from the second start address according to the second request information and stores the read data in the first-in-first-out queue controlled by the register until the length of the data stored in the first-in-first-out queue controlled by the register is the second reading length; When the register for controlling the first-in-first-out queue receives the first request sent by the bus, the data is transmitted from the first-in-first-out queue controlled by the register to the bus according to the first start address and the first reading length corresponding to the first request according to the first-in-first-out reading rule.
2. The method of claim 1, wherein the PSRAM-based data prefetching is performed by a processor. The register for controlling the first-in-first-out queue reads data stored in the pseudo-static random memory from the second start address according to the second request information and stores the read data in the first-in-first-out queue controlled by the register until the length of the data stored in the first-in-first-out queue controlled by the register is the second reading length, comprising: Setting a storage length threshold of the data in the first-in-first-out queue controlled by the register; and When the length of the data stored in the first-in-first-out queue controlled by the register is less than the storage length threshold, the data is read from the pseudo-static random memory according to the second request information to supplement the register, so that the length of the data stored in the register is equal to the storage length threshold.
3. The method of claim 2, wherein the PSRAM-based data prefetching is performed by a prefetch engine. When the length of the data stored in the first-in-first-out queue controlled by the register is less than the storage length threshold, the data is read from the pseudo-static random memory according to the second request information to supplement the first-in-first-out queue controlled by the register, comprising: The difference between the length of the data stored in the first-in-first-out queue controlled by the register and the storage length threshold is taken as the second reading length of the second request information; The address corresponding to the last data obtained by the register for controlling the first-in-first-out queue is taken as the second start address of the second request information.
4. The method of claim 1, wherein the PSRAM-based data prefetching is performed by a processor. When the register for controlling the first-in-first-out queue receives the first request sent by the bus, the data is transmitted from the first-in-first-out queue controlled by the register to the bus according to the first start address and the first reading length corresponding to the first request according to the first-in-first-out reading rule, comprising: If the current first start address of the current first request and the first end address of the last first request are continuous addresses, the data is continuously transmitted from the first-in-first-out queue controlled by the register to the bus according to the first-in-first-out reading rule.
5. The method of claim 2, wherein the PSRAM-based data prefetching is performed by a prefetch engine. The storage length threshold of the first-in-first-out queue controlled by the register is configured by the bus.
6. A data prefetching apparatus based on PSRAM, characterized by, The method comprises: The access information acquisition module is configured to, before a first request for reading data stored in the pseudo-static random access memory is sent by the bus, send second request information to a register controlling a first-in-first-out queue through a controller, wherein the first request and the second request both include a start address of the data to be read and a reading length; The data reading module is configured to control the register controlling the first-in-first-out queue to read the data stored in the pseudo-static random access memory from a second start address according to the second request information and store the read data in the first-in-first-out queue controlled by the register until the length of the data stored in the first-in-first-out queue controlled by the register is a second reading length. The data transmission module is configured to, when the register controlling the first-in-first-out queue receives the first request sent by the bus, transmit the data from the first-in-first-out queue controlled by the register to the bus according to a first start address and a first reading length corresponding to the first request according to a first-in-first-out reading rule.
7. The PSRAM-based data prefetching apparatus of claim 6, wherein, The data transmission module includes: If the current first start address of the current first request is a continuous address with a first end address of a previous first request, the data transmission module is configured to continuously transmit the data from the first-in-first-out queue controlled by the register to the bus according to the first-in-first-out reading rule.
8. The PSRAM-based data prefetching apparatus of claim 6, wherein, The data reading module includes a module configured to set a storage length threshold of the data in the register and, when the length of the data stored in the first-in-first-out queue controlled by the register is less than the storage length threshold, read the data from the pseudo-static random access memory according to the second request information and supplement the data into the first-in-first-out queue controlled by the register, so that the length of the data stored in the first-in-first-out queue controlled by the register is equal to the storage length threshold.
9. A computer readable storage medium storing computer programs / instructions, characterized in that, The computer program / instruction is operated to perform the PSRAM-based data prefetching method according to any one of claims 1-5.
10. A computer program product comprising computer programs / instructions, characterized in that, The computer program / instruction is operated to perform the PSRAM-based data prefetching method according to any one of claims 1-5.