Task scheduling methods, apparatus, and electronic devices for a fully fair scheduler

Abstract

This disclosure provides a task scheduling method, apparatus, and electronic device for a Completely Fair Scheduler (CFS), relating to the fields of artificial intelligence and cloud computing technologies, and particularly to operating system scheduling technology. The implementation scheme includes: determining the waiting time of ready tasks in the processor's run queue; updating the processor's latency information based on the waiting time of a ready task leaving the run queue when the ready task leaves; comparing the maximum waiting time of ready tasks in the run queue with a latency threshold, wherein the latency threshold is based on the processor's latency information; and scheduling the ready task corresponding to the maximum waiting time in response to the maximum waiting time exceeding the latency threshold. Using embodiments of this disclosure, the latency threshold for prioritizing task scheduling is dynamically determined by utilizing the processor's latency, thus achieving dynamic scheduling based on system operating conditions on top of CFS.

Description

Technical Field

[0001] This disclosure relates to the fields of artificial intelligence and cloud computing technologies, and in particular to operating system scheduling technologies, specifically to a task scheduling method, apparatus, electronic device, computer-readable storage medium, and computer program product for a Completely Fair Scheduler. Background Technology

[0002] Multi-core operating systems typically employ various scheduling strategies, including real-time scheduling (RT), deadline scheduling, and Completely Fair Scheduler (CFS).

[0003] The methods described in this section are not necessarily methods that had been previously conceived or adopted. Unless otherwise specified, no method described in this section should be assumed to be prior art simply because it is included in this section. Similarly, unless otherwise specified, the issues mentioned in this section should not be considered to be accepted in any prior art. Summary of the Invention

[0004] This disclosure provides a task scheduling method, apparatus, electronic device, computer-readable storage medium, and computer program product for a Completely Fair Scheduler.

[0005] According to one aspect of this disclosure, a task scheduling method for a Fully Fair Scheduler is provided, comprising: determining the waiting time of ready tasks in a processor's run queue; updating the processor's latency information based on the waiting time of the ready task when the ready task leaves the run queue; comparing a maximum waiting time of ready tasks in the run queue with a latency threshold, wherein the latency threshold is based on the processor's latency information; and scheduling the execution of a ready task corresponding to the maximum waiting time in response to the maximum waiting time exceeding the latency threshold.

[0006] According to another aspect of this disclosure, a task scheduling apparatus for a Completely Fair Scheduler is provided, comprising: a waiting time determination unit configured to determine the waiting time of a task in a processor's run queue; a delay information determination unit configured to update the processor's delay information based on the waiting time of the task when the task leaves the run queue; a comparison unit configured to compare a maximum waiting time of ready tasks in the run queue with a delay threshold, wherein the delay threshold is based on the processor's delay information; and a delay-priority scheduling unit configured to schedule the execution of a ready task corresponding to the maximum waiting time in response to the maximum waiting time exceeding the delay threshold.

[0007] According to another aspect of this disclosure, an electronic device is provided, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform a method according to an embodiment of this disclosure.

[0008] According to another aspect of this disclosure, a non-transitory computer-readable storage medium is provided storing computer instructions, wherein the computer instructions are used to cause a computer to perform a method according to an embodiment of this disclosure.

[0009] According to another aspect of this disclosure, a computer program product is provided, comprising a computer program, wherein the computer program, when executed by a processor, implements a method according to an embodiment of this disclosure.

[0010] According to one or more embodiments of this disclosure, a latency threshold for prioritizing task scheduling is dynamically determined by utilizing processor latency, thereby enabling dynamic scheduling based on system operation on top of CFS.

[0011] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this disclosure, nor is it intended to limit the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0012] The accompanying drawings exemplify embodiments and form part of the specification, serving together with the textual description to explain exemplary implementations of the embodiments. The illustrated embodiments are for illustrative purposes only and do not limit the scope of the claims. Throughout the drawings, the same reference numerals refer to similar but not necessarily identical elements.

[0013] Figure 1 An exemplary flowchart of a task scheduling method for a fully fair scheduler according to an embodiment of the present disclosure is shown.

[0014] Figure 2 An exemplary process for task scheduling according to embodiments of the present disclosure is illustrated.

[0015] Figure 3 The process of dynamic scheduling according to an embodiment of the present disclosure is illustrated.

[0016] Figure 4 An exemplary process for task scheduling according to embodiments of the present disclosure is illustrated.

[0017] Figure 5 An exemplary block diagram of a task scheduling apparatus for a fully fair scheduler according to embodiments of the present disclosure is shown.

[0018] Figure 6 A structural block diagram of an exemplary electronic device that can be used to implement embodiments of the present disclosure is shown. Detailed Implementation

[0019] The exemplary embodiments of this disclosure are described below with reference to the accompanying drawings, including various details of the embodiments to aid understanding, and should be considered merely exemplary. Therefore, those skilled in the art will recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope of this disclosure. Similarly, for clarity and brevity, descriptions of well-known functions and structures are omitted in the following description.

[0020] In this disclosure, unless otherwise stated, the use of terms such as "first," "second," etc., to describe various elements is not intended to limit the positional, temporal, or importance relationships of these elements; such terms are merely used to distinguish one element from another. In some examples, the first element and the second element may refer to the same instance of that element, while in other cases, based on the context, they may refer to different instances.

[0021] The terminology used in the description of the various examples described in this disclosure is for the purpose of describing particular examples only and is not intended to be limiting. Unless the context explicitly indicates otherwise, an element may be one or more unless the number of elements is specifically limited. Furthermore, the term "and / or" as used in this disclosure covers any one of the listed items and all possible combinations thereof.

[0022] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0023] While schedulers in related technologies each possess different advantages, they all have limitations in maintaining the controllability of latency for user-space tasks. For example, the CFS scheduler is designed to achieve fair scheduling of all tasks on the CPU. CFS determines the execution order by maintaining the virtual runtime of tasks (vruntime). Current CFS only focuses on fairness as its core metric and cannot reflect the latency behavior of tasks from "ready" to "actually running." For instance, CFS cannot provide observability of task queuing time, does not guarantee strict scheduling latency, may exhibit significant tail latency in high-load scenarios, cannot maintain consistency of waiting latency information after task migration, and lacks a latency-based proactive intervention mechanism.

[0024] To address the aforementioned problems in related technologies, this disclosure provides a novel task scheduling method for a CFS scheduler. Embodiments of this disclosure are used to solve the following technical problems.

[0025] 1. How to accurately record the queuing delay from task readiness to execution, so that the scheduler can perceive the scheduling delay of each CPU in real time.

[0026] 2. If the delay of a task exceeds a threshold, the scheduler will be triggered to prioritize scheduling that task, thereby controlling the tail delay.

[0027] 3. How to ensure that multi-core load balancing and latency information are consistent and correctly inherited during task migration, and how to prioritize load balancing for delayed tasks.

[0028] 4. How to provide a user interface for reading, controlling, and adjusting delay parameters.

[0029] Figure 1 An exemplary flowchart of a task scheduling method for a fully fair scheduler according to an embodiment of the present disclosure is shown.

[0030] In step S102, the waiting time of ready tasks in the processor's run queue is determined.

[0031] In step S104, when a ready task leaves the run queue, the processor's latency information is updated based on the task's waiting time.

[0032] In step S106, the maximum waiting time of ready tasks in the run queue is compared with a latency threshold, where the latency threshold is based on the processor's latency information.

[0033] In step S108, in response to the maximum waiting time exceeding the delay threshold, the ready task corresponding to the maximum waiting time is scheduled for execution.

[0034] By utilizing embodiments of this disclosure, the waiting time of tasks can be determined by recording the enqueue time of tasks in the run queue. This allows for accurate latency calculation of tasks in the run queue, and the overall latency of the processor can be statistically analyzed based on the latency of each task leaving the run queue. By utilizing the processor's latency, a latency threshold for prioritizing task scheduling is dynamically determined, thus enabling dynamic scheduling based on system operating conditions on top of CFS.

[0035] The principles of this disclosure will be described in detail below. The methods disclosed herein can be applied to operating system kernels that support multi-core processors.

[0036] In step S102, the waiting time of ready tasks in the processor's run queue is determined.

[0037] A ready task can refer to a task located in the ready queue of the processor's run queue.

[0038] In some embodiments, step S102 may include: when a task is added to the ready queue in the processor's run queue, recording the task's enqueue time information; reading the current system time, calculating the difference between the current system time and the enqueue time information, to obtain the waiting time of the task in the ready queue.

[0039] In other embodiments, a timer can be used to record the waiting time of ready tasks in the run queue. For example, the timer can be started when a task is added to the run queue. The waiting time of the task can be determined by the length of time recorded in the timer.

[0040] Step S102 enables the scheduler to obtain accurate and real-time single-task waiting data, thereby providing a basis for the delay-first scheduling strategy.

[0041] In step S104, when a ready task leaves the run queue, the processor's latency information is updated based on the task's waiting time.

[0042] When a ready task leaves the run queue, its waiting time can be determined as its total waiting time. The processor's latency information can include statistics on the total waiting time of ready tasks that have left at least one queue in the run queue.

[0043] In some embodiments, the processor's latency information can be updated each time a ready task leaves the run queue. In other embodiments, the processor's latency information can be updated based on a predetermined time period.

[0044] In some embodiments, updating the processor latency information based on task waiting time includes: employing an exponential moving average (EMA) statistical method, and using a weighting factor to weight the waiting time of tasks currently leaving the ready queue with the historical average latency to obtain the updated processor latency information. Using this method, the influence of real-time task latency information and historical task latency information on processor latency information can be effectively balanced by the weighting factor, enabling the processor latency information to dynamically and sensitively reflect recent system state changes, while effectively suppressing transient fluctuations through historical data smoothing. In some examples, the weighting factor may be predetermined. In other examples, the weighting factor is dynamically adjusted based on the processor's system load. Exemplary system load may include CPU utilization, the number of ready tasks, etc. The higher the system load, the lower the weight of the waiting time of tasks currently leaving the ready queue, thus meeting the higher requirements for system stability when the system load is high. Conversely, the lower the system load, the higher the weight of the waiting time of tasks currently leaving the ready queue, thus enabling the processor latency information to effectively reflect system fluctuations. Without departing from the principles of this disclosure, those skilled in the art can use any suitable function to determine the specific way in which the weighting factor changes with the system load.

[0045] In step S106, the maximum waiting time of ready tasks in the run queue is compared with a latency threshold, where the latency threshold is based on the processor's latency information.

[0046] In some embodiments, a delay management queue is provided in the processor's run queue. The delay management queue is used to store ready tasks(s) in the processor's run queue in a manner ordered by wait duration, such that the task at the head of the delay management queue has the longest wait duration.

[0047] By maintaining a dedicated data structure in the run queue to manage task delay information, the task that has not been scheduled for the longest time can be quickly identified, thus enabling delay-first scheduling.

[0048] An exemplary delay management queue can support the following functionalities: inserting new tasks by time (from the tail of the queue), removing already running or migrated tasks, organizing tasks in order of waiting time, and quickly locating the task with the longest waiting time (i.e., the task at the head of the queue). This delay management queue can be implemented using any suitable data structure, such as a red-black tree, a min-heap, a max-heap, etc.

[0049] In other embodiments, any suitable data structure can be used to manage the waiting time of ready tasks in the run queue, as long as the waiting time of ready tasks can be read from it.

[0050] In step S108, in response to the maximum waiting time exceeding the delay threshold, the ready task corresponding to the maximum waiting time is scheduled for execution.

[0051] When the maximum waiting time of a task in the processor run queue exceeds a preset threshold, the scheduler will trigger preemption and will prioritize the task that has been waiting the longest in the next task selection, instead of selecting tasks according to the virtual runtime sorting of the traditional Completely Fair Scheduler.

[0052] Accordingly, in response to the maximum waiting time not exceeding the delay threshold, the next task to run is selected based on the virtual runtime according to the scheduling policy of the Fully Fair Scheduler.

[0053] The aforementioned latency threshold can be preset or dynamically adjusted. In some examples, the latency threshold can be dynamically adjusted within a predetermined range. The initial value and / or range of the latency threshold can be preset by the user via a configuration interface. In some embodiments, the latency threshold can be dynamically adjusted based on at least one of the following: the system load of the processor; the changing trend of the processor's latency information.

[0054] For example, when the system load is high (e.g., the number of tasks exceeds a threshold or CPU utilization exceeds a threshold), the latency threshold can be increased to improve system stability and reduce frequent system interventions. When the system load is low (e.g., the number of tasks does not exceed a threshold or CPU utilization does not exceed a threshold) or processor latency information indicates an increase in system latency, the latency threshold can be decreased to schedule tasks with longer waiting times in a timely manner, thereby reducing the overall system latency. Without departing from the principles of this disclosure, those skilled in the art can utilize any suitable function to determine the specific manner in which the latency threshold changes with system load and / or latency trends.

[0055] In the CFS scheduling strategy, load balancing can be achieved by pulling tasks from the busiest processor queue and migrating them to a relatively idle processor. This load balancing can be based on minimizing system overhead. In some embodiments, a latency-first strategy can also be applied during the load balancing process of the CFS scheduler. This mechanism can promptly distribute pressure when severe tail latency occurs locally in the system, preventing the continuous accumulation of latency in a single processor queue, thereby improving the scheduling balance and response efficiency at the system-wide level. By proactively intervening when tail latency deteriorates, task response time is reduced, allowing the system to maintain better interactivity and real-time experience under medium-to-high load scenarios.

[0056] In some embodiments, ready tasks with the longest waiting time in the run queue can be selected for migration to the target processor to achieve load balancing. In other embodiments, tasks with a waiting time exceeding a latency threshold in the run queue can be selected for migration to the target processor to achieve load balancing. The latency threshold used in the load balancing strategy and the latency threshold used to schedule task execution in step S108 can be the same or different.

[0057] For ready tasks migrated to the target processor according to a load balancing strategy, their waiting time can include the waiting time in the run queue before migration and the waiting time in the run queue of the target processor. For example, the waiting time can be determined based on the sum of the first waiting time experienced before migration and the second waiting time experienced in the processor's run queue after migration. Alternatively, the waiting time can be determined based on the weighted sum of the first waiting time experienced before migration and the second waiting time experienced after migration.

[0058] In some embodiments, the Fully Fair Scheduler provided by the present disclosure may also have a configurable user-space interface, enabling users to directly set fixed latency thresholds or limit the dynamic adjustment range of latency thresholds through system parameters or control groups. This achieves a latency management mechanism that combines automatic adjustment and manual control, improving the adaptability and controllability of the scheduling strategy. The user-space interface provided by the embodiments of the present disclosure can also provide observability support for users. In some embodiments, the processor's run queue may also include latency statistics fields, including the current processor's average latency, maximum latency, and latency threshold. Information such as the average latency, latency threshold, and maximum latency of the run queue can be read via the user-space interface through system files or a debug interface. In some embodiments, the user-space interface can also be used to enable / disable latency scheduling capabilities, configure average latency statistics, configure latency thresholds, and output task latency changes through tracking points. This facilitates real-time monitoring of scheduling latency by system administrators, performance analysis tools, or business-side programs, enabling performance optimization.

[0059] Figure 2 An exemplary process for task scheduling according to embodiments of the present disclosure is illustrated.

[0060] The task enqueue module 210 is used to record the enqueue time information of a task when it is enqueued, which serves as the starting point for scheduling waiting time and provides basic data for subsequent delay calculation.

[0061] CPU ready queue 220 integrates a dedicated data structure for managing task delay information. This data structure supports inserting tasks by time, removing running / migrating tasks, organizing tasks in order by waiting time, and quickly locating the longest-waiting task (the task at the head of the queue).

[0062] The task dequeue module 230 is used to read the current system time when a task is dequeued (or selected to run), subtract the enqueue time from the actual waiting time, and include this time in the delay data statistics.

[0063] The latency data statistics module 240 is used to maintain latency statistics information of the CPU ready queue. It uses the exponential moving average (EMA) algorithm to calculate the average latency of a single CPU and balances the newly observed latency with the historical average latency. It can also be used to output latency data (average latency, maximum latency, etc.) to the user interface.

[0064] The delay scheduling decision module 250 is used to determine whether to trigger delay-first scheduling based on the waiting time provided by the delay data statistics module 240, combined with a dynamically adjusted delay threshold or a fixed delay threshold configured by the administrator. If the longest waiting time exceeds the threshold, the delay-first scheduling logic is triggered (prioritizing the task that has been waiting the longest), while also guiding the cross-processor migration strategy.

[0065] User interface module 260 provides a user-mode interface that supports: reading latency statistics (average latency, threshold, etc.); enabling / disabling latency scheduling capabilities; configuring latency thresholds and average latency statistics parameters; and also supports administrator-configurable interface functions, allowing manual setting of thresholds or adjustment ranges.

[0066] use Figure 2 The task scheduling process shown in the diagram involves the task enqueue module 210 recording the time when a task is enqueued. Then, the task is stored in the latency management structure of the CPU ready queue 220. When a task is dequeued, the task dequeue module 230 calculates the waiting time and sends it to the latency data statistics module 240. The latency data statistics module 240 generates information such as average latency and maximum latency, which is simultaneously provided to the user interface module 260 for observation and passed to the latency scheduling decision module 250 to determine whether to trigger priority scheduling based on thresholds. Finally, the decision result is fed back to the CPU ready queue 220 to guide task selection / migration.

[0067] Figure 3 The process of dynamic scheduling according to an embodiment of the present disclosure is illustrated.

[0068] Initialization can be performed at position 301 to prepare the basic data for the latency statistics module. This includes reading the historical EMA average latency and setting the initial weighting factor.

[0069] At position 302, the system load status can be determined, and the current CPU load level (such as the number of ready tasks and CPU utilization) can be collected to provide a basis for subsequent weight adjustment.

[0070] At point 303, weighting factors can be dynamically adjusted, for example, the weighting factors of the EMA algorithm can be dynamically adjusted based on the system load status (e.g., reducing weights under high load and increasing weights under low load). Simultaneously, manual weight configuration via user interface 310 is supported, achieving a combination of automatic adjustment and manual control.

[0071] At position 304, the EMA calculation of average latency can be performed: using an adjusted weighting factor, the new observed latency is fused with the historical mean through an exponential moving average algorithm to obtain the current CPU latency average.

[0072] The delay threshold can be calculated at point 305. Based on the EMA average delay result and combined with the system load status, the trigger threshold for delay scheduling is dynamically generated. It also supports configuring the threshold range or a fixed value through the user interface at point 310, enhancing policy controllability.

[0073] Tasks can be scheduled for execution at position 306. The calculated latency threshold can be passed to the latency scheduling decision module. If the task latency exceeds the threshold, it will be scheduled first; otherwise, CFS scheduling will be used. This completes the task scheduling and execution.

[0074] use Figure 3 The process shown in the figure realizes a closed loop of "load perception → weight adaptation → latency statistics → dynamic threshold generation → scheduling decision", which ensures the accuracy of latency statistics and the adaptability of scheduling strategy, and effectively supports the latency-first scheduling mechanism provided in this disclosure.

[0075] Figure 4 An exemplary process for task scheduling according to embodiments of the present disclosure is illustrated.

[0076] At position 401, scheduling begins: the task selection process of the Completely Fair Scheduler (CFS) is triggered, which is the starting point of the scheduling logic.

[0077] At position 402, it checks if the current latency exceeds a threshold: the scheduler reads the task's current waiting time and combines it with... Figure 3 The comparison of the dynamically adjusted delay threshold described herein serves as the triggering decision node for the delay-first scheduling strategy.

[0078] At point 403, delay-first scheduling can be performed: if the delay exceeds the threshold (the result is "Y"), the delay-first scheduling logic is triggered, that is, the scheduler skips the typical CFS virtual runtime sorting and directly selects the task that has been waiting the longest.

[0079] At 404, the CFS scheduling logic can be invoked: if the delay does not exceed the threshold (the result is "N"), then the task selection logic of the typical Completely Fair Scheduler is used.

[0080] Task execution can be achieved at point 405: regardless of whether the task is selected through "Latency First Scheduling" or "CFS Scheduling", it will eventually enter the processor's execution phase. At the same time, the latency information of the processor's run queue will be updated.

[0081] The embodiments of this disclosure achieve the following technical effects by accurately sensing task scheduling latency, dynamically calculating the average latency, and tail latency in the CFS scheduler, and prioritizing the scheduling of the task with the highest latency when the latency exceeds a threshold:

[0082] Reduce tail latency and improve interactive responsiveness: For user-mode latency-sensitive tasks, it can significantly shorten the scheduling time of long-waiting tasks and improve system response, making it particularly suitable for interactive applications and high-concurrency scenarios.

[0083] Dynamically adapt to system load: The latency threshold can be automatically adjusted according to the CPU load, and a user-configurable interface is provided to maintain a reasonable scheduling strategy under high load, ensuring system stability and performance.

[0084] Visualization and controllability of scheduling strategies: By providing a latency statistics interface, system monitoring, performance analysis and strategy optimization can be realized, enabling users to quickly respond to performance bottlenecks.

[0085] Therefore, the embodiments of this disclosure significantly improve the shortcomings of the CFS scheduler in user-mode task latency control in related technologies, enabling the product to have better performance in scenarios with high concurrency, multi-tasking, and low latency requirements, and achieving a better user experience and system response efficiency.

[0086] Figure 5 An exemplary block diagram of a task scheduling apparatus for a fully fair scheduler according to embodiments of the present disclosure is shown.

[0087] like Figure 5 As shown, the device 500 may include a waiting time determination unit 510, a delay information determination unit 520, a comparison unit 530, and a delay priority scheduling unit 540.

[0088] The waiting time determination unit 510 can be configured to determine the waiting time of a task in the processor's run queue.

[0089] The delay information determination unit 520 can be configured to update the processor's delay information based on the task's waiting time when the task leaves the run queue.

[0090] The comparison unit 530 can be configured to compare the maximum waiting time of ready tasks in the run queue with a latency threshold, wherein the latency threshold is based on processor latency information;

[0091] The delay-first scheduling unit 540 can be configured to schedule and execute ready tasks corresponding to the maximum waiting time in response to the maximum waiting time exceeding the delay threshold.

[0092] In some embodiments, determining the waiting time of a task in the processor's run queue includes: recording the enqueue time information of the task when it is added to the ready queue in the processor's run queue; reading the current system time and calculating the difference between the current system time and the enqueue time information to obtain the waiting time of the task in the ready queue.

[0093] In some embodiments, the processor's run queue includes a delay management queue, which stores ready tasks in the processor's run queue in a sorted manner by waiting time, such that the task at the head of the delay management queue has the longest waiting time.

[0094] In some embodiments, updating the processor's latency information based on the task's waiting time includes: using an exponential moving average (EMA) statistical method, and employing weighting factors to perform a weighted calculation on the task's waiting time and the historical average latency to obtain the updated processor latency information.

[0095] In some embodiments, the weighting factor is dynamically adjusted based on the processor's system load.

[0096] In some embodiments, the latency threshold is dynamically adjusted based on at least one of the following: the processor's system load; the trend of changes in the processor's latency information.

[0097] In some embodiments, the delay threshold is dynamically adjusted within a predetermined range.

[0098] In some embodiments, the apparatus 500 further includes a fully fair scheduling unit configured to select the next task to run based on the virtual runtime in response to the maximum waiting time not exceeding a delay threshold, according to the scheduling policy of the fully fair scheduler.

[0099] In some embodiments, the apparatus 500 further includes a migration unit configured to select ready tasks in the run queue that have the longest wait time or whose wait time exceeds a latency threshold for migration to a target processor to achieve load balancing.

[0100] In some embodiments, the waiting time of a task migrated to the target processor in the target processor's run queue includes the waiting time in the run queue it was in before being migrated and the waiting time in the target processor's run queue.

[0101] In some embodiments, the processor's run queue also includes a latency statistics field, which includes the current processor's average latency, maximum latency, and latency threshold.

[0102] In some embodiments, the device 500 is applied to an operating system kernel that supports multi-core processors.

[0103] It should be understood that Figure 5 The various modules or units of the device 500 shown can be connected to the reference. Figure 1 The steps in method 100 described correspond to each other. Therefore, the operations, features, and advantages described above for method 100 also apply to apparatus 500 and its included modules and units. For the sake of brevity, some operations, features, and advantages will not be repeated here.

[0104] Although specific functions have been discussed with reference to specific modules above, it should be noted that the functions of the various units discussed in this article can be divided into multiple units, and / or at least some functions of multiple units can be combined into a single unit.

[0105] The collection, storage, use, processing, transmission, provision, and disclosure of user personal information involved in the technical solution disclosed herein comply with the provisions of relevant laws and regulations and do not violate public order and good morals.

[0106] According to embodiments of the present disclosure, an electronic device is also provided, including: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform a method according to embodiments of the present disclosure.

[0107] According to embodiments of the present disclosure, a non-transitory computer-readable storage medium storing computer instructions is also provided, wherein the computer instructions are used to cause a computer to perform a method according to embodiments of the present disclosure.

[0108] According to embodiments of the present disclosure, a computer program product is also provided, comprising a computer program, wherein the computer program, when executed by a processor, implements the method according to embodiments of the present disclosure.

[0109] refer to Figure 6The present invention describes a structural block diagram of an electronic device 600 that can serve as a server or client of the present disclosure, which is an example of a hardware device that can be applied to various aspects of the present disclosure. The electronic device is intended to represent various forms of digital electronic computer devices, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the present disclosure described and / or claimed herein.

[0110] like Figure 6 As shown, the electronic device 600 includes a computing unit 601, which can perform various appropriate actions and processes based on a computer program stored in a read-only memory (ROM) 602 or a computer program loaded from a storage unit 608 into a random access memory (RAM) 603. The RAM 603 may also store various programs and data required for the operation of the electronic device 600. The computing unit 601, ROM 602, and RAM 603 are interconnected via a bus 604. An input / output (I / O) interface 605 is also connected to the bus 604.

[0111] Multiple components in electronic device 600 are connected to I / O interface 605, including: input unit 606, output unit 607, storage unit 608, and communication unit 609. Input unit 606 can be any type of device capable of inputting information to electronic device 600. Input unit 606 can receive input digital or character information and generate key signal inputs related to user settings and / or function control of electronic device, and can include, but is not limited to, a mouse, keyboard, touchscreen, trackpad, trackball, joystick, microphone, and / or remote control. Output unit 607 can be any type of device capable of presenting information, and can include, but is not limited to, a monitor, speaker, video / audio output terminal, vibrator, and / or printer. Storage unit 608 can include, but is not limited to, disk and optical disk. Communication unit 609 allows electronic device 600 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks, and can include, but is not limited to, modems, network cards, infrared communication devices, wireless communication transceivers, and / or chipsets, such as Bluetooth devices, 802.11 devices, WiFi devices, WiMax devices, cellular communication devices, and / or the like.

[0112] The computing unit 601 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of the computing unit 601 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 601 performs the various methods and processes described above, such as method 100. For example, in some embodiments, method 100 may be implemented as a computer software program tangibly contained in a machine-readable medium, such as storage unit 608. In some embodiments, part or all of the computer program may be loaded and / or installed on the electronic device 600 via ROM 602 and / or communication unit 609. When the computer program is loaded into RAM 603 and executed by the computing unit 601, one or more steps of method 100 described above may be performed. Alternatively, in other embodiments, the computing unit 601 may be configured to perform method 100 by any other suitable means (e.g., by means of firmware).

[0113] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), complex programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0114] The program code used to implement the methods of this disclosure may be written in any combination of one or more programming languages. This program code may be provided to a processor or controller of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus, such that when executed by the processor or controller, the program code causes the functions / operations specified in the flowcharts and / or block diagrams to be implemented. The program code may be executed entirely on a machine, partially on a machine, as a standalone software package partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0115] In the context of this disclosure, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0116] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device for displaying information to the user (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor); and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the computer. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0117] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as data servers), or middleware components (e.g., application servers), or frontend components (e.g., user computers with graphical user interfaces or web browsers through which users can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., communication networks). Examples of communication networks include local area networks (LANs), wide area networks (WANs), the Internet, and blockchain networks.

[0118] Computer systems can include clients and servers. Clients and servers are generally located far apart and typically interact via communication networks. Client-server relationships are created by computer programs running on the respective computers and having a client-server relationship with each other. Servers can be cloud servers, servers in distributed systems, or servers incorporating blockchain technology.

[0119] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this disclosure can be performed in parallel, sequentially, or in a different order, as long as the desired result of the technical solution disclosed in this disclosure can be achieved, and this is not limited herein.

[0120] While embodiments or examples of this disclosure have been described with reference to the accompanying drawings, it should be understood that the methods, systems, and devices described above are merely exemplary embodiments or examples, and the scope of the invention is not limited by these embodiments or examples, but only by the granted claims and their equivalents. Various elements in the embodiments or examples may be omitted or replaced by their equivalents. Furthermore, the steps may be performed in a different order than that described in this disclosure. Further, various elements in the embodiments or examples may be combined in various ways. Importantly, as the technology evolves, many elements described herein can be replaced by equivalents that appear after this disclosure.

Claims

1. A task scheduling method for a fully fair scheduler, comprising: Determine the waiting time of ready tasks in the processor's run queue; When the ready task leaves the running queue, the processor's latency information is updated according to the task's waiting time; The maximum waiting time of ready tasks in the run queue is compared with a latency threshold, wherein the latency threshold is based on the processor's latency information; In response to the maximum waiting time exceeding the delay threshold, the ready task corresponding to the maximum waiting time is scheduled for execution. The step of updating the processor's latency information based on the task's waiting time includes: An exponential moving average statistical method is used to calculate the latency of the task by weighting it with a weighted factor and the historical average latency, so as to obtain the updated latency information of the processor.

2. The method according to claim 1, wherein, The determination of the waiting time of tasks in the processor's run queue includes: When a task is added to the ready queue in the processor's run queue, the enqueue time information of the task is recorded. Read the current system time and calculate the difference between the current system time and the enqueue time information to obtain the waiting time of the task in the ready queue.

3. The method according to claim 1, wherein, The processor's run queue includes a delay management queue, which stores ready tasks in the processor's run queue in a sorted manner by waiting time, so that the task at the head of the delay management queue has the maximum waiting time.

4. The method according to claim 1, wherein, The weighting factor is dynamically adjusted based on the system load of the processor.

5. The method according to claim 1, wherein, The delay threshold is dynamically adjusted based on at least one of the following: The system load of the processor; The trend of the processor's latency information.

6. The method according to claim 5, wherein, The delay threshold is dynamically adjusted within a predetermined range.

7. The method according to claim 1, further comprising: In response to the maximum waiting time not exceeding the delay threshold, the next task to run is selected based on the virtual runtime according to the scheduling policy of the Fully Fair Scheduler.

8. The method according to claim 1, further comprising: Select ready tasks from the run queue that have the longest waiting time or whose waiting time exceeds the latency threshold to migrate to the target processor for execution in order to achieve load balancing.

9. The method according to claim 8, wherein, The waiting time of a task migrated to the target processor in the target processor's run queue includes the waiting time in the run queue it was in before being migrated and the waiting time in the target processor's run queue.

10. The method according to claim 1, wherein, The processor's run queue also includes a latency statistics field, which includes the current processor's average latency, maximum latency, and latency threshold.

11. The method according to claim 1, wherein, The method is applied to operating system kernels that support multi-core processors.

12. A task scheduling apparatus for a fully fair scheduler, comprising: The waiting time determination unit is configured to determine the waiting time of a task in the processor's run queue. The delay information determination unit is configured to update the processor's delay information based on the waiting time of the task when the task leaves the run queue; The comparison unit is configured to compare the maximum waiting time of ready tasks in the run queue with a latency threshold, wherein the latency threshold is based on the processor's latency information; A delay-first scheduling unit is configured to schedule and execute a ready task corresponding to the maximum waiting time in response to the maximum waiting time exceeding the delay threshold. The step of updating the processor's latency information based on the task's waiting time includes: An exponential moving average statistical method is used to calculate the latency of the task by weighting it with a weighted factor and the historical average latency, so as to obtain the updated latency information of the processor.

13. An electronic device, comprising: At least one processor; as well as A memory that is communicatively connected to the at least one processor; in The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform the method of any one of claims 1-11.

14. A non-transitory computer-readable storage medium storing computer instructions, wherein, The computer instructions are used to cause the computer to perform the method according to any one of claims 1-11.

15. A computer program product comprising a computer program, wherein, When the computer program is executed by a processor, it implements the method of any one of claims 1-11.

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