Novel memristor Baplov associative memory circuit
By simplifying the structure of the memristor Pavlovian associative memory circuit, using only one memristor and basic electronic components, and combining it with a learning and forgetting module, three forgetting modes of the memristor device are realized. This solves the problems of complexity and high power consumption of existing circuits, and is suitable for low-power neuromorphic chips and brain-like intelligent sensors.
Patent Information
- Application Number
- CN202511623767.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-07
- Publication Date
- 2026-02-03
AI Technical Summary
Existing memristor Pavlovian associative memory circuits rely on multi-memristor arrays or complex peripheral circuits, resulting in large circuit area overhead, high power consumption, and a lack of efficient learning and forgetting regulation modules, making it difficult to realize the natural fading and recovery process of biological memory.
Design a novel memristor Pavlovian associative memory circuit that uses only a memristor and a small number of basic electronic components such as resistors and transistors, combined with a learning and forgetting module, to achieve three forgetting modes: food forgetting, bell forgetting, and natural forgetting.
It simplifies the circuit structure, reduces power consumption, and realizes the full functionality of Pavlovian associative memory. It is suitable for low-power neuromorphic chips and brain-like intelligent sensors, and supports applications in miniaturized and portable devices.
Smart Images
Figure CN121457541A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of memristor neural networks, and more particularly to a novel memristor Pavlov associative memory circuit. Background Technology
[0002] In the fields of artificial intelligence and neuromorphic computing, simulating the learning and memory functions of biological nervous systems has always been one of the core research directions. Memristors, as a novel nanodevice with "memory" characteristics, have become a key hardware foundation for building efficient memristor neural networks due to their advantages of dynamic historical changes in resistance value with applied electrical signals and high compatibility with biological synaptic weight regulation mechanisms. They are widely used in scenarios such as associative memory, pattern recognition, and deep learning, driving the development of neural networks towards low power consumption, high integration, and brain-like characteristics. Pavlovian associative memory, as a classic model of conditioned reflexes, is an important paradigm for simulating biological learning and memory behavior. Its core requirement is to achieve full-function simulation of the establishment, reinforcement, extinction, and recovery of associations between unconditioned stimuli (US) and conditioned stimuli (CS). However, current circuit designs for implementing Pavlovian associative memory based on memristor devices still face significant technical bottlenecks: on the one hand, most solutions rely on multi-memristor arrays or complex peripheral circuits to construct synaptic units, which not only increases the circuit's area overhead, power consumption, and wiring complexity, but also makes it difficult to meet the practical application requirements of highly integrated neuromorphic chips; on the other hand, existing circuits generally lack dedicated learning-forgetting regulation modules, resulting in insufficient dynamic regulation capabilities of "learning-reinforcement-forgetting" during the associative memory process. They can either only achieve a single association establishment function and cannot simulate the natural extinction and recovery process of biological memory, or they need to achieve forgetting through complex signal timing control, which reduces the circuit's response speed and stability. Furthermore, with the surge in demand for low-power smart hardware in fields such as the Internet of Things and edge computing, the application of traditional memristor associative memory circuits based on multiple devices or complex control is severely restricted in miniaturized and portable devices. Therefore, developing a circuit that can simplify the circuit structure with a single memristor while integrating an efficient learning and forgetting module to achieve the full functionality of Pavlovian associative memory has become a key breakthrough direction for solving current technical pain points and promoting memristor neural networks from theoretical research to practical applications. It has significant academic value and promising prospects for industrial applications. Summary of the Invention
[0003] Purpose of the invention: Existing circuits that realize the full functions of Pavlovian associative memory are too complex. In order to optimize the circuit structure and reduce power consumption and cost, this invention proposes a novel memristor Pavlovian associative memory circuit. This circuit, through the combination of various module circuits, can still realize the three forgetting functions of Pavlovian associative memory with only one memristor in the total circuit.
[0004] Technical solution: A novel memristor Pavlov associative memory circuit includes a memristor M1, an operational amplifier U1, four resistors, a voltage source Vk, an input Vin, and an output Vout, wherein the four resistors are resistors R2, R3, R4, and R5.
[0005] Furthermore, the voltage source Vk is connected to the negative input of the operational amplifier U1 through the resistor R3; the input Vin is connected to the positive input of the operational amplifier U1 and grounded through the resistor R2; one end of the resistor R4 is connected to the negative input of the operational amplifier U1, and the other end is connected to the output of the operational amplifier U1.
[0006] Furthermore, the positive terminal of the memristor M1 is grounded, and the negative terminal is connected to the output terminal of the operational amplifier U1 through the resistor R5. The other end of the resistor R5 is the output Vout.
[0007] Furthermore, a novel memristor Pavlovian associative memory circuit includes a control module composed of NMOS transistors T1 and T2, diodes D1 and D2, and resistor R11; a neuron module composed of NMOS transistor T3, voltage source VDD, and resistor R12; an absolute value circuit composed of operational amplifiers A2 and A3, diodes D3 and D4, and resistors R6, R7, R8, R9, and R10; a voltage follower operational amplifier A1; the aforementioned learning and forgetting module; a first voltage source Vfood; and a second voltage source Vring.
[0008] Furthermore, the first voltage source Vfood is connected to the input terminal of the diode D2 and the gate of the NMOS transistor T2, and the output terminal of the diode D2 is connected to the gate of the NMOS transistor T3 and the output terminal of the diode D1.
[0009] Furthermore, the drain of the NMOS transistor T3 is connected to the voltage source VDD, and the source is grounded through the resistor R12.
[0010] Furthermore, the second voltage source Vring is connected to the drain of the NMOS transistor T2, and the source of the NMOS transistor T2 is connected to the input voltage V1, which serves as the learning-forgetting module.
[0011] Furthermore, the output voltage V2 of the learning-forgetting module is connected to the positive input of the operational amplifier A1, the negative input of the operational amplifier A1 is connected to the output terminal, the output terminal of the operational amplifier A1 is connected to the resistor R6, and the other end of the operational amplifier A1 is connected to the absolute value circuit composed of the operational amplifiers A2 and A3, the resistors R7, R8, R9, R10, and the diodes D3 and D4. The output voltage V3 of the absolute value circuit is connected to the drain of the NMOS transistor T1.
[0012] Furthermore, the source of the NMOS transistor T1 is connected to the input terminal of the diode D1 and the resistor R11, the other end of the resistor R11 is grounded, the gate of the NMOS transistor T1 is connected to the positive terminal of the second voltage source Vring, and the negative terminals of the second voltage source Vring and the first voltage source Vfood are both grounded.
[0013] Beneficial effects: This invention addresses the technical bottleneck of current Pavlov associative memory circuits, which rely on multiple memristor arrays, have complex structures, and are difficult to implement multiple types of forgetting functions. It innovatively proposes a minimalist hardware architecture design that uses only one memristor as the core memory unit and combines it with a small number of basic electronic components such as resistors, capacitors, and transistors to build the circuit system, which can efficiently realize the three key forgetting modes in the Pavlov associative memory process. Among them, "food forgetting" only provides food signals, and the previously established conditioned reflex association will gradually weaken; "ringing forgetting" refers to the repeated application of conditioned stimuli (such as electrical signals simulating "ringing") without reinforcement signals, leading to the gradual fading of established associations; "natural forgetting" simulates the instinctive decay characteristics of biological memory, that is, in the absence of any external stimulus intervention, the circuit achieves the natural fading of associated memories through the slow recovery mechanism of the resistance value of the memristor itself. This invention simplifies the hardware structure, reduces power consumption and integration costs, and provides key technical support for applications such as low-power neuromorphic chips and brain-like intelligent sensors. Attached Figure Description
[0014] Figure 1 This is the learning-forgetting module circuit of the present invention; Figure 2 This is the total circuit of the present invention that realizes all the functions of Pavlov; Figure 3 This is a demonstration of the simulation test results of the present invention. Detailed Implementation
[0015] To make the technical solution of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.
[0016] Example This invention uses the HP memristor model to construct a memristor Pavlov associative memory circuit, and the memristor Pavlov associative memory circuit is tested in actual operation. The parameters of the memristor are set as M(0)=8KΩ, ROFF=18KΩ, RON=100Ω, and k=105; The resistance value Rj (j=1,2,...,12) = 6KΩ; The threshold voltages VT of NMOS transistors T1 and T2 are 2.5V, and the threshold voltage VT of NMOS transistor T3 is 1.5V. The voltage values of voltage sources Vfood and Vring during testing are... Figure 3 As shown; Voltage source Vk=2.5V, VDD=5V.
[0017] like Figure 1 and Figure 2 As shown, a novel memristor Pavlov associative memory circuit is provided, including one memristor M1; four resistors R2, R3, R4 and R5; one operational amplifier U1; and one voltage source Vk. When learning the forgotten module circuit test, Vk always remains at 2.5V, so only Vin determines the circuit state; When Vin < 2.5V, the output Vout is negative, the resistor M1 decreases, the weight decreases, resulting in a decrease in the actual voltage drop of Vout. When Vin > 2.5V, the output Vout is positive. The resistance of M1 increases, the weight increases, and the actual voltage drop of Vout increases.
[0018] like Figure 1 and Figure 2 As shown, the memristor Pavlovian associative memory circuit that implements learning and three types of forgetting functions includes a control module composed of NMOS transistors T1 and T2, diodes D1 and D2, and resistor R11; a neuron module composed of NMOS transistor T3, voltage source VDD, and resistor R12; an absolute value circuit composed of operational amplifiers A2 and A3, diodes D3 and D4, and resistors R6, R7, R8, R9, and R10; A1 as a voltage follower; and the aforementioned learning and forgetting modules. The control module determines the Vin of the learning and forgetting module and the output Vout of the neuron module. Diodes D1 and D2 are used to prevent backflow, which affects the input voltage and the control module. The output Vout of the neuron module indicates whether the dog is drooling. The output V2 of the learning and forgetting module only takes the specific value of the weight and feeds it back to the control module to determine the output Vout of the neuron module, thereby achieving the purpose of associative memory learning and forgetting functions; the function of voltage follower A1 is to prevent the absolute value circuit from affecting the output voltage V2 of the learning and forgetting module.
[0019] like Figure 3 As shown, the circuit operation can be divided into 7 stages, including the initial test stage, the first learning stage, the food forgetting stage, the second learning stage, the bell forgetting stage, the third learning stage, and the natural forgetting stage. 1) In the initial testing phase, 0-0.10s: input voltage Vfood=0V, Vring=0V, Vout has no output, indicating that the dog will not drool when there is neither a bell signal nor food; 0.10-0.20s: Vfood=0V, Vring=5V, Vout has no output, indicating that the dog will not drool when given a bell signal alone without associative memory learning; 0.20-0.30s: Vfood=5V, Vring=0V, Vout has an output signal, indicating that the dog will drool when given a food signal, which is a manifestation of unconditioned stimulus.
[0020] 2) First learning, 0.30-0.90s: Vfood=5V, Vring=5V. At this time, T1, T2, and T3 are turned on, V1=Vring=5V, input to the learning and forgetting module, which increases the resistance of M1, increases the weight, and causes the actual voltage division of V2 to increase. V3 will receive the specific voltage division value of V2. When T1 is turned on, the value of V3 can also determine whether T3 is turned on, thus controlling whether Vout has an output signal. At the same time, the dog is given a bell signal and a food signal, and the dog will gradually establish an associative memory between the two, achieving the purpose of learning. 0.90-1.05s: Vfood=0V, Vring=5V. At this time, T1 is turned on, T2 is turned off. Because V3>the threshold voltage VT of NMOS transistor T3, T3 is turned on, and Vout has an output. After the learning is completed, the bell signal is given again alone. It is found that the dog still drools. This indicates that the dog has established an associative memory between food and bell.
[0021] 3) During the food forgetting phase, from 1.05 to 1.45 seconds: Vfood = 5V, Vring = 0V. At this time, T1 is off, and T2 and T3 are on. V1 = Vring = 0V, and the input is sent to the learning and forgetting module. The resistance of M1 decreases, and the weight decreases, causing the actual voltage division of V2 and V3 to gradually decrease. The control over Vout also gradually weakens. When the food signal is given again, although Vout has an output signal, the weight of M1 keeps decreasing, indicating that the dog is slowly forgetting the association between the bell and the food. From 1.45 to 1.60 seconds: Vfood = 0V, Vring = 5V. T1 is on, and T2 and T3 are off. There is no output from Vout. After forgetting, the bell signal is given again for testing. It is found that the dog does not drool, indicating that the dog has forgotten the association between the bell and the food.
[0022] 4) The second learning process is the same as 2), with a learning period of 1.60-2.20 seconds. The dog re-establishes the associative memory between food and the bell.
[0023] 5) During the ringing forgetting stage, 2.20-2.60s: Vfood=0V, Vring=5V. At this time, T1 is turned on and T2 is turned off, V1=Vring=5V, but it cannot be input to the learning and forgetting module. Due to the existence of Vk, the output V2 of the learning and forgetting module is negative, which causes the resistance of M1 to decrease, the weight to decrease, and the actual voltage division V3 to gradually decrease. Figure 3 The Vout waveform also shows that the Vout signal output disappears at 2.36s. At this time, V3 < 1.5V, and T3 changes from being on to being off. This indicates that after learning is complete, if a bell signal is given alone, the dog will initially drool, but it will gradually forget the associative memory between food and bell, and eventually will no longer drool over the bell.
[0024] 6) The third learning process is the same as the previous two; the time period from 2.60 to 3.10 seconds is the learning phase, and from 3.10 to 3.25 seconds is the detection phase to see if the learning phase is completed. As can be seen in the figure, the dog drools at the bell signal, indicating that the associative memory between food and bell has been re-established.
[0025] 7) Natural forgetting stage, 3.25s-3.55s: Vfood=0V, Vring=0V. At this time, T1, T2, and T3 are cut off, and Vout has no signal output. The learning and forgetting module output V2 is negative, so the resistance of M1 decreases, the weight decreases, and the actual voltage division V3 also gradually decreases. 3.55s-end: Vfood=0V, Vring=5V. At this time, T1 is on, T2 and T3 are cut off, and Vout has no signal output. During the natural forgetting process, if nothing is given, the dog does not drool. However, as time goes by, the dog will still forget the association between the bell and food. After a period of time, if the bell signal is given again, the dog will not drool, indicating that the dog has forgotten this conditioned reflex.
[0026] In simulation testing, the weight changes and output signals throughout the entire training process are analyzed. Figure 3 The circuit is clearly demonstrated, with a simple overall structure and the number of memristors reduced to one, effectively reducing the circuit overhead cost and replication difficulty in implementing Pavlovian associative memory.
[0027] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention. Therefore, the scope of protection of this patent should be determined by the appended claims.
Claims
1. A novel memristor Pavlovian associative memory circuit, comprising a memristor M1, an operational amplifier U1, four resistors, a voltage source Vk, an input Vin, and an output Vout, characterized in that: The four resistors are resistor R2, resistor R3, resistor R4 and resistor R5.
2. The novel memristor Pavlov associative memory circuit according to claim 1, characterized in that: The voltage source Vk is connected to the negative input of the operational amplifier U1 through the resistor R3; the input Vin is connected to the positive input of the operational amplifier U1 and grounded through the resistor R2; one end of the resistor R4 is connected to the negative input of the operational amplifier U1 and the other end is connected to the output of the operational amplifier U1.
3. A novel memristor Pavlovian associative memory circuit according to claim 1, characterized in that: The positive terminal of the memristor M1 is grounded, and the negative terminal is connected to the output terminal of the operational amplifier U1 through the resistor R5. The other end of the resistor R5 is the output Vout.
4. A novel memristor Pavlov associative memory circuit according to claim 1, comprising a control module composed of NMOS transistors T1 and T2, diodes D1 and D2 and resistor R11, a neuron module composed of NMOS transistor T3, voltage source VDD and resistor R12, an absolute value circuit composed of operational amplifiers A2 and A3, diodes D3 and D4 and resistors R6, R7, R8, R9 and R10, a voltage follower operational amplifier A1, the aforementioned learning and forgetting module, a first voltage source Vfood and a second voltage source Vring.
5. A novel memristor Pavlovian associative memory circuit according to claim 4, characterized in that: The first voltage source Vfood is connected to the input terminal of the diode D2 and the gate of the NMOS transistor T2, and the output terminal of the diode D2 is connected to the gate of the NMOS transistor T3 and the output terminal of the diode D1.
6. A novel memristor Pavlovian associative memory circuit according to claim 4, characterized in that: The drain of the NMOS transistor T3 is connected to the voltage source VDD, and the source is grounded through the resistor R12.
7. A novel memristor Pavlovian associative memory circuit according to claim 4, characterized in that: The second voltage source Vring is connected to the drain of the NMOS transistor T2, and the source of the NMOS transistor T2 is connected to the input voltage V1, which serves as the learning and forgetting module.
8. A novel memristor Pavlovian associative memory circuit according to claim 4, characterized in that: The output voltage V2 of the learning and forgetting module is connected to the positive input of the operational amplifier A1, the negative input of the operational amplifier A1 is connected to the output terminal, the output terminal of the operational amplifier A1 is connected to the resistor R6, and the other end of the operational amplifier A1 is connected to the absolute value circuit composed of the operational amplifiers A2 and A3, the resistors R7, R8, R9, R10, and the diodes D3 and D4. The output voltage V3 of the absolute value circuit is connected to the drain of the NMOS transistor T1.
9. A novel memristor Pavlovian associative memory circuit according to claim 8, characterized in that: The source of the NMOS transistor T1 is connected to the input terminal of the diode D1 and the resistor R11. The other end of the resistor R11 is grounded. The gate of the NMOS transistor T1 is connected to the positive terminal of the second voltage source Vring. The negative terminals of the second voltage source Vring and the first voltage source Vfood are both grounded.