Layout splicing method and computer equipment

Abstract

The invention provides a layout splicing method. The layout splicing method comprises the following steps: acquiring a list of vertexes and a list of edges of a plurality of slices of a layout; according to the list of the vertexes of the multiple slices, a list of the vertexes of the layout is obtained, and the list of the vertexes of the layout comprises the vertexes of the multiple slices; according to a vertex of a first graph of the first slice, determining a tangency point of the first slice, the first graph being a graph with at least one edge overlapping with at least one boundary of the first slice in the first slice, and the tangency point being a vertex located on the boundary of the first slice in the first graph; according to the tangent points of the multiple slices, a cross-slice edge of the layout is determined, and the cross-slice edge comprises a first tangent point and a second tangent point which are located on a first boundary and a second boundary which are overlapped of the adjacent slices respectively; and determining a list of edges of the layout according to the list of the cross-slice edges and the plurality of slice edges. According to the method, the number of vertexes and the number of edges involved in a scanning line algorithm in the layout splicing process can be reduced, so that the layout splicing efficiency is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of chip design, in particular to a layout splicing method and a computer device. BACKGROUND

[0002] In the process of chip layout processing, it is usually necessary to analyze, modify or optimize the entire layout. This process involves a large amount of graphic data, and therefore may consume a large amount of computing resources and time. Parallel technology in chip layout processing can divide a large task into multiple small tasks, and distribute these small tasks to multiple parallel processing units (such as multiple processor cores, multiple computing nodes or graphics processing units GPU, etc.) for simultaneous processing. In this way, a large amount of data that would otherwise need to be processed in series can be processed simultaneously by multiple processing units, thereby significantly improving processing speed. This process usually involves steps such as data synchronization, data integration and data verification. Polygon Boolean OR operation is a common data integration method.

[0003] In the process of chip layout processing, the vector graphics of the layout are usually divided into multiple original slices, a plurality of processing units are used to respectively and in parallel process a part of the original slices to obtain multiple target slices, and then the polygon Boolean OR operation is used to combine these scattered target slices into a unified layout. The above process can be referred to as splicing of the chip layout. In some cases, the polygon Boolean OR operation in the process of splicing multiple target slices, especially the process of boundary segmentation by scan line algorithm, consumes a lot of time, resulting in low efficiency of chip layout processing. SUMMARY

[0004] The present application provides a layout splicing method and a computer device to improve the efficiency of layout splicing.

[0005] In a first aspect, a layout splicing method is provided, which includes: obtaining a list of vertices and a list of edges of multiple slices of a layout; obtaining a list of vertices of the layout according to the list of vertices of the multiple slices, the list of vertices of the layout including the vertices of the multiple slices; determining a cut point of a first slice according to a vertex of a first graph of the first slice, wherein the first graph is a graph in the first slice that has at least one edge overlapping at least one boundary of the first slice, the cut point is a vertex in the first graph that is located on the boundary of the first slice, and the first slice is any slice in the multiple slices; determining a cross-slice edge of the layout according to the cut points of the multiple slices, wherein the cross-slice edge includes a first cut point and a second cut point located on a first boundary and a second boundary, respectively, of adjacent slices, and the first cut point and the second cut point are cut points at the same position in the first boundary and the second boundary, respectively, in order of coordinate values; and determining a list of edges of the layout according to the cross-slice edge and the list of edges of the multiple slices.

[0006] The layout splicing method provided by the embodiments of the present application can obtain the cut point of a graph located at a boundary according to the graph related to the slice boundary, reduce the number of vertices and edges involved in the scan line algorithm in the layout splicing process, thereby reducing the time complexity of the layout splicing, and improving the efficiency of the layout splicing.

[0007] In some implementations of the first aspect, the list of edges of the layout includes the cross-slice edges and the edges obtained after the coincident cut edges are deleted from the list of edges of the plurality of slices; wherein the cut edge is an edge of the first graph that overlaps with one boundary of the first slice.

[0008] In such implementations, deleting the coincident cut edges can reduce unnecessary redundant data in the graph, and improve the reliability of graph storage and representation.

[0009] In some implementations of the first aspect, determining the list of edges of the layout according to the cross-slice edges and the list of edges of the plurality of slices includes: in a case where a plurality of first graphs form a composite polygon, determining a plurality of edge frames of a second graph according to the cut points of the plurality of slices, wherein the second graph is the composite polygon formed by the plurality of first graphs, the edge frame includes a graph identifier of the second graph, an edge frame type of the edge frame, and a plurality of cut points of the edge frame; determining a self-intersecting edge of the second graph according to a first edge frame and at least one second edge frame, wherein the graph identifier of the first edge frame and the graph identifier of the at least one second edge frame correspond to the same second graph, the edge frame type of the first edge frame is an outer edge frame, the edge frame type of the second edge frame is an inner edge frame, and the two vertices of the self-intersecting edge are cut points in different edge frames, and the two vertices of at least one self-intersecting edge of the second graph are a cut point in the first edge frame and a cut point in one second edge frame, respectively; and determining the list of edges of the layout according to the cross-slice edges, the self-intersecting edges, and the list of edges of the plurality of slices, wherein the list of edges of the layout includes the cross-slice edges, the self-intersecting edges, and the edges obtained after the coincident cut edges are deleted from the list of edges of the plurality of slices.

[0010] Such implementations can efficiently and accurately process the vertices and edges of the composite polygon related to the slice boundary, and improve the efficiency of the composite polygon splicing.

[0011] In some implementations of the first aspect, determining the plurality of edge frames of the second graph according to the cut points of the plurality of slices includes: determining a list of cut point pairs of the plurality of slices according to the cut points of the plurality of slices, wherein the cut point pair includes a pair of adjacent cut points in the cut points of the second slice, and the second slice is any slice in the plurality of slices; and determining the plurality of edge frames according to the cross-slice edges and the list of cut point pairs of the plurality of slices.

[0012] In such implementations, the cut point pair is used to represent the positional relationship and connection relationship between the cut points, and the properties of the graph can be analyzed according to the cut point pair, thereby improving the efficiency of the composite polygon splicing.

[0013] In some implementations of the first aspect, the arrangement order of the cut points of the second slice is a clockwise or counterclockwise order with the geometric center of the second slice as the center, and adjacent cut points are adjacent cut points in the arrangement order.

[0014] In such implementations, the bounding box can accurately represent the properties of the composite polygon, and generating the bounding box according to the ordered list of cut point pairs can reduce the implementation complexity of the stitching algorithm and improve the reliability of the graphic storage and representation.

[0015] In some implementations of the first aspect, determining the list of edges of the layout according to the list of cross-slice edges, the list of self-intersecting edges, and the list of edges of the plurality of slices includes: using the list of cross-slice edges, the list of self-intersecting edges, and the list of edges of the plurality of slices as inputs of a multi-way merge algorithm to obtain the list of edges of the layout.

[0016] In such implementations, the multi-way merge algorithm has a lower time complexity, which can improve the efficiency of determining the list of edges of the layout.

[0017] In some implementations of the first aspect, determining the plurality of bounding boxes according to the list of cross-slice edges and the list of cut point pairs of the plurality of slices includes: using the list of cross-slice edges and the list of cut point pairs of the plurality of slices as inputs of a simple ring detection algorithm to determine the plurality of bounding boxes.

[0018] In such implementations, the simple ring detection algorithm has a lower time complexity, which can improve the efficiency of determining the plurality of bounding boxes.

[0019] In some implementations of the first aspect, the time complexity of determining the list of edges of the layout according to the list of cross-slice edges and the list of edges of the plurality of slices is O(PQ)+O(P log P), where the average number of first graphics in the plurality of slices is P, and the average number of vertices included in the first graphics is Q, and P and Q are positive integers.

[0020] The time complexity of the main steps of the layout stitching method of the embodiment is O(PQ)+O(P log P), while the time complexity of the conventional polygon Boolean operation is O(PQ log PQ). The time complexity of the layout stitching algorithm of the present application is less than that of the conventional stitching algorithm.

[0021] In a second aspect, a computer device is provided, which includes at least one processor and at least one memory; the at least one memory stores at least one computer program including instructions, when the instructions are executed by the at least one processor, the method as described in any implementation of the first aspect is executed.

[0022] In a third aspect, a chip is provided, the chip comprising a processor and a communication interface, the communication interface configured to receive a signal and transmit the signal to the processor, and the processor configured to process the signal such that the method according to any implementation form of the first aspect is performed.

[0023] In a fourth aspect, a computer-readable storage medium is provided, the computer-readable storage medium storing computer instructions, when the computer instructions are run on a computer device, causing the method according to any implementation form of the first aspect to be performed.

[0024] In a fifth aspect, a computer program product is provided, the computer program product comprising instructions, when the instructions are run on a computer device, causing the computer device to perform the method according to any implementation form of the first aspect. BRIEF DESCRIPTION OF DRAWINGS

[0025] Figure 1 is a schematic block diagram of a layout provided by an embodiment of the present application.

[0026] Figure 2 is a flowchart of a layout splicing method provided by an embodiment of the present application.

[0027] Figures 3 to 5 is a schematic block diagram of a layout provided by an embodiment of the present application.

[0028] Figure 6 is a schematic block diagram of a chip system provided by an embodiment of the present application.

[0029] Figure 7 is a schematic block diagram of a computer device provided by an embodiment of the present application.

[0030] Figure 8 is a schematic block diagram of a computer program product provided by an embodiment of the present application. DETAILED DESCRIPTION

[0031] First, the related technical terms in the present application are explained.

[0032] A list is an abstract data structure that can store and traverse elements in a specific order. The main feature of a list is that elements have an order relationship, and each element can be accessed by index or iteration. Lists include linked lists, arrays, stacks, and queues. A linked list is a data structure linked together by pointers or references, where each element contains a value and a pointer to the next element. An array is a data structure that stores elements of the same type in contiguous memory, and elements are accessed by index. In the above data structures that can implement lists, the time complexity of insertion and deletion operations is O(1) regardless of the number of elements in the list.

[0033] A queue is a first-in, first-out (FIFO) data structure commonly used to process tasks in a specific order. It has two endpoints, the front and the back, and elements can only be inserted (enqueued) from the back and deleted (dequeued) from the front. A priority queue is similar to a regular queue, but each element has an associated priority. In a priority queue, elements with higher priority are processed earlier than those with lower priority. Specifically, an element can be inserted into a priority queue with a specified priority, which is usually a non-negative integer calculated based on the element's data or attributes. Therefore, the priority can be considered as the key of the element in the queue, and the combination of the priority and the element can be considered as a key-value pair. That is, the priority queue actually stores elements, but logically stores multiple key-value pairs, and the size relationship of the keys determines the order in which the values of the key-value pairs are processed. In addition, priority queues are usually implemented using binary heaps (such as max heaps or min heaps), and the time complexity of insertion and deletion operations in a binary heap with N elements is O(log N). Therefore, the time complexity of insertion and deletion operations in a priority queue is O(log N).

[0034] A hash table, also known as a hash table, is a data structure that uses key-value pairs for efficient data storage and retrieval. In a hash table, data is not organized in order or hierarchical relationships, but through a hash function, each key is mapped to a location in the table to access the record, which is called a hash value or index. The average time complexity of hash table lookup, insertion, and deletion operations can reach O(1), i.e. constant time.

[0035] A simple polygon is a closed figure formed by a sequence of edges. These edges are connected end-to-end to form a closed boundary; and, the boundary of a simple polygon does not intersect itself. Furthermore, the boundary of a simple polygon is a sequence of consecutive line segments, each edge connecting two vertices, and each vertex being the common endpoint of exactly two edges.

[0036] A self-intersecting polygon is a polygon whose at least one edge intersects with other edges inside the polygon, that is, the boundary of the polygon does not simply enclose an area, but at least part of the boundary crosses other parts inside the polygon. A typical self-intersecting polygon is a five-pointed star formed by five straight lines drawn in succession.

[0037] A compound polygon is a polygon composed of an outer frame and at least one inner frame, the inner frame is completely surrounded by the outer frame, and the inner and outer frames do not intersect directly. The outer frame defines the outer contour of the compound shape, while the inner frame is used to define the area that needs to be excluded from the compound shape. A typical compound polygon is a square frame with a small rectangular blank area inside, which is usually called a hole.

[0038] In chip layout processing, it is often necessary to analyze, modify or optimize the entire layout. This process involves a large amount of graphic data, and therefore may consume a large amount of computing resources and time. Parallel technology in chip layout processing can divide a large task into multiple small tasks and distribute these small tasks to multiple parallel processing units (such as multiple processor cores, multiple computing nodes or graphics processing units GPU, etc.) for simultaneous processing. In this way, a large amount of data that would otherwise need to be processed in series can be processed simultaneously by multiple processing units, significantly improving processing speed. This process usually involves steps such as data synchronization, data integration and data verification. Polygon Boolean or operation is a common data integration method.

[0039] Polygon Boolean or operation (Boolean OR) is also known as union operation, which can perform set operation based on two or more polygons to generate a new shape, where the new shape contains all the areas covered by the polygons participating in the operation, and the overlapping parts are not repeated. That is, the area of all polygons is merged, and the internal overlapping part is removed. This process is highly abstract, and there are actually multiple algorithms for implementing union operation, such as Weiler-Atherton algorithm, Vatti clipping algorithm or Greiner-Hormann algorithm, etc., which include different details and optimization measures to handle special cases and improve efficiency. The general steps are as follows:

[0040] First, the input polygon data needs to be parsed into a form that can be processed by a computer. For a polygon, its vertex list and edge list can be stored, where the vertex list stores the coordinate information of all vertices, and the edge list stores the information of edges that constitute the polygon (each edge is defined by two vertices). Further, a half-edge data structure is used, based on the edge list, each edge is represented as a directed edge (i.e. half-edge), and all polygons follow the same ordering rule to store multiple edges, improving the processing efficiency of the subsequent process. Then, the boundary segmentation is performed by the scan line algorithm, and a horizontal (or vertical) scan line is set to move step by step from the lowest point to the top, which is used to detect the intersection of polygon edges. As the scan line moves, an active edge table (AET) is maintained to record the polygon edges cut by the current scan line. When the scan line encounters the intersection of polygon edges, these events need to be handled, the active edge table is updated, and the intersection information is recorded. Then, the union operation is performed, and during the scanning process, the continuous "true" interval (i.e. the area belonging to any polygon) is recorded. When the scan line moves, it will find that some intervals belong to the union area of one or more polygons. Based on the recorded interval information, the polygons after the union operation can be reconstructed, for example, the adjacent interval endpoints are connected to form the edges of the output polygon. Finally, the polygon simplification and optimization are performed, and there may be redundant vertices or edges in the generated polygon, which need to be simplified, such as removing approximately collinear vertices by comparing the threshold of floating-point numbers. The merged polygon may be self-intersecting, and in some cases further processing is needed to ensure the validity of the output polygon.

[0041] In some graphic design rules, each inner edge frame of a composite polygon must have at least one edge connected to the outer edge frame and / or other inner edge frames, i.e. the composite polygon in the chip needs to be designed as a self-intersecting polygon, so that from any vertex in the vertex list, all vertices can be traversed according to a specific order, to improve the reliability of the scan line algorithm.

[0042] In the chip layout processing process, the vector graphics of the layout are usually divided into multiple original slices, a plurality of processing units are used to process a part of the original slices in parallel to obtain multiple target slices, and then the polygon Boolean operation is used to combine the scattered target slices into a unified layout. The above process can be referred to as chip layout splicing. In some cases, the polygon Boolean operation in the process of splicing multiple target slices, especially the boundary segmentation process by the scan line algorithm, takes a lot of time, resulting in low efficiency of chip layout processing.

[0043] Therefore, the present application provides a layout splicing method, which comprises: obtaining a list of vertices and a list of edges of a plurality of slices of a layout;

[0044] A list of vertices for the layout is obtained based on a list of vertices for multiple slices. The list of vertices for the layout includes the vertices of the multiple slices. The tangent points of the first slice are determined based on the vertices of the first graphic of the first slice, where the first graphic is a graphic whose at least one edge overlaps with at least one boundary of the first slice, and the tangent points are vertices of the first graphic located on the boundary of the first slice. The first slice is any one of the multiple slices. Cross-slice edges of the layout are determined based on the tangent points of the multiple slices, where the cross-slice edges include first tangent points and second tangent points located on the overlapping first and second boundaries of adjacent slices, respectively. The first tangent points and second tangent points are tangent points at the same position on the first and second boundaries, ordered by coordinate values. A list of edges for the layout is determined based on the cross-slice edges and the list of edges for the multiple slices.

[0045] The layout stitching method provided in this application embodiment can obtain the tangent point of the graphic located on the boundary based on the graphic related to the slice boundary in the layout, thereby reducing the number of vertices and edges involved in the scan line algorithm in the layout stitching process, thus reducing the time complexity of layout stitching and improving the efficiency of layout stitching.

[0046] The technical solutions in this application will now be described with reference to the accompanying drawings.

[0047] It should be understood that the slice in the layout stitching method provided in this application refers to the target slice obtained after processing the original slice. In subsequent embodiments, unless otherwise specified, "slice" refers to "target slice".

[0048] It should be understood that the overlap of vertices or edges in a vector graphic or slice, as referred to in this application, means that the difference between the coordinates of two or more vertices expressed in floating-point numbers is less than a preset threshold, or the difference between the coordinates of two vertices of two or more edges expressed in floating-point numbers is less than a preset threshold. In other words, the overlap referred to in this application refers to overlap in the sense of computer data processing, not overlap in the mathematical sense. Similarly, the overlap of edges and boundaries in a vector graphic and slice refers to overlap in the sense of computer data processing, that is, the difference between the x-coordinates of two vertices of an edge and the x-coordinate of the boundary is less than a preset threshold, or the difference between the y-coordinates of two vertices of an edge and the y-coordinate of the boundary is less than a preset threshold.

[0049] In the chip layout stitching process, taking a target slice as an example, let P be the average number of boundary-related graphics in each slice, and Q be the average number of vertices contained in each boundary-related graphic. Then, the average number of vertices in each slice is R = PQ. In one embodiment, such as... Figure 1 The chip layout shown includes four slices, each slice comprising multiple rectangular shapes. Figure 1The shaded rectangles shown each have at least one side that overlaps with at least one boundary of their respective slice; that is, the shaded rectangle represents a graphic associated with the boundary of the slice. For example... Figure 1 As shown, there are 16 graphics related to the boundaries of the slices in the 4 slices, so P is calculated as 16 / 4 = 4. Figure 1 If the average number of rectangles in the figure includes 4 vertices, then Q = 4.

[0050] It should be understood that, for ease of demonstration, Figure 1 Rectangles are used to represent graphics in the layout, but this should not be interpreted as a restriction on P or Q. Some chip layouts have more graphics, such as 200 to 2000; each boundary-related graphic includes an average of 100 to 1000 vertices, meaning P can range from 200 to 2000, and Q can range from 100 to 1000. Furthermore, the spaces between slices are used to more clearly show the vertices and edges on the slice boundaries; the actual slices are closely packed, for example... Figure 1 The lower boundary of slice #1 coincides with the upper boundary of slice #2. Figure 1 The right boundary of slice #1 coincides with the left boundary of slice #4.

[0051] In chip layout processing, even if the original data is already ordered in some sense, the reordering step in the scanline algorithm is still necessary. Specifically, taking horizontal scanlines as an example, the scanline algorithm typically moves horizontally, so it needs to be sorted according to the intersection positions of the scanlines. Even if the original data is sorted along a certain dimension, it may be necessary to reorder the intersections or edges based on the direction of the scanline and the current scanline position. Secondly, the core of the scanline algorithm is maintaining an Active Edge Table (AET), which contains all edges intersecting with the current scanline and needs to be sorted according to the x-coordinate of the intersection points. Even if the original data is ordered, this order may not meet the requirements of the AET, thus requiring reordering. Furthermore, scanline algorithms are often event-driven, meaning the algorithm needs to process events in the order they occur, including the start and end events of edges. Even if the data is ordered in some way, reordering ensures that events are processed in the correct order. Finally, for complex polygons with internal "holes" or complex geometries, the scanline algorithm needs to correctly identify and process these structures, which may require specific sorting of edges and vertices to ensure the accuracy of fill and clipping operations.

[0052] In some embodiments, the Boolean OR operation merges multiple scattered slices into a unified layout. The total number of vertices processed by the scanline operation in the Boolean OR operation is R. Similarly, the average number of edges in each graph to be operated on is related to Q; for example, the average number of edges in a simple polygon is Q or linearly related to Q. Therefore, the total number of edges processed by the scanline operation is linearly related to R. Considering that the sorting step in the scanline algorithm is the main source of its time complexity, for major sorting algorithms (such as quicksort, mergesort, etc.), in the worst case, the time complexity of sorting all R vertices is O(R logR), i.e., O(PQ logPQ). Similarly, the time complexity of sorting all edges is O(PQ logPQ), and the time complexity of the scanline operation is O(PQ logPQ). Since the scanline operation is the most important and time-consuming operation in the Boolean OR operation, the time complexity of the Boolean OR operation can be considered to be O(PQ log PQ).

[0053] In chip layout, the number of edges and vertices of a graph are usually linearly related. Therefore, the following embodiments will only illustrate the time complexity of the scanline algorithm by the number of vertices involved in the scanline algorithm.

[0054] In some embodiments, each slice stores a list of vertices for all shapes and a list of edges for all shapes. For example, a slice may include two rectangles ABCD and EFGH. In one possible implementation, the vertex list may be {A,B,C,D,E,F,G,H}, and the edge list may be {(A,B),(B,C),(C,D),(D,A),(E,F),(F,G),(G,H),(H,E)}. The edge list may store directed edges, and the vertex and edge lists may be stored in a different order than in the example above. In another possible implementation, each shape corresponds to a vertex list and an edge list. In this case, the slice may include combinations of {A,B,C,D} and {(A,B),(B,C),(C,D),(D,A)}, as well as combinations of {E,F,G,H} and {(E,F),(F,G),(G,H),(H,E)}. Clearly, regardless of the representation used, the number of vertices and edges in a slice is always the same.

[0055] For ease of explanation, the storage format used in the subsequent embodiments of this application is as follows: each slice stores the vertex list of all graphics in a list and the edge list of all graphics in a list.

[0056] In one embodiment, combined Figure 2 The flowchart shown and Figure 3The schematic block diagram of the chip layout shown illustrates the layout splicing method provided in this application.

[0057] S210, retrieves a list of vertices and a list of edges for multiple slices of the map.

[0058] As mentioned earlier, in some embodiments, each slice stores a list of vertices of all graphs in a list and a list of edges of all graphs in a list.

[0059] S220: Obtain a list of vertices of the map based on a list of vertices of multiple target slices.

[0060] In some embodiments, the vertex lists of multiple slices are sorted according to the x-coordinate and / or y-coordinate of the vertices. When the layout includes W slices, this embodiment is essentially a multiway merge algorithm, which merges W sorted vertex lists, each containing an average of R elements, into a single sorted list. This merge algorithm can be implemented using a priority queue. First, the first element of each vertex list is inserted into a priority queue. The time complexity of this step is O(W log W). Next, the smallest element is taken from the priority queue and added to the result list. Then, the next element in the list containing that element (if it exists) is inserted into the priority queue. Since there are WR elements in the priority queue, the time complexity of each retrieval is O(log W), so the total time complexity is O(WR log W). The time complexity of the above steps is O(W log W + WR log W). In this embodiment, W is considered a constant, so the time complexity of S220 is O(R), or O(PQ).

[0061] S230, determine the tangent point of the first slice based on the vertices of the first graphic of the first slice.

[0062] For ease of explanation, the first figure is a figure in the first slice where at least one edge overlaps with at least one boundary of the first slice, the first figure has at least two vertices located on at least one boundary of the first slice, and the first slice is any slice among a plurality of slices. The vertices in the first figure located on the boundaries of the slice are called tangent points.

[0063] According to the definitions of P and Q in the foregoing embodiments, the average number of first graphics in multiple slices is P, and the average number of vertices included in all first graphics is Q.

[0064] In some embodiments, the vertex list of each first shape in the multiple slices is traversed. The traversal process is used to determine whether PQ points are located on the slice boundary in turn. Therefore, the time complexity of this step is O(PQ). Since the number of cutting points in each first shape is independent of the average number of vertices Q in each first shape, the number of cutting points in the resulting cutting point list is only related to P.

[0065] In one embodiment, such as Figure 3 As shown, taking slice #1 as an example, figure ABCD is the first figure, and the whole is L-shaped. Vertices {A, B, C, D} are located on the boundary of slice #1, and are therefore also called tangent points {A, B, C, D}, which is the list of tangent points for slice #1. There are 298 vertices between vertices A and C, and 198 vertices between vertices D and B. Therefore, figure ABCD includes vertices Q = 500, and slice #1 includes 1 figure related to the boundary. Similarly, the figures in slices #2, #3, and #4 also include 500 vertices.

[0066] It should be understood that Figure 3 The slices shown are closely spaced in real-world applications; please refer to the previous section for details. Figure 1 The explanation of slicing is omitted here. Secondly, the figure ABCD is in... Figure 3 The shape shown is only a general illustration; its actual shape is not a graphic composed of six straight, long line segments. Furthermore, for ease of explanation, let P = 1 be the number of boundary-related graphics in slice #1. However, in the main application scenarios of this application, the value of P is typically between 200 and 2000 or a larger number.

[0067] In summary, the total time complexity of S230 is O(PQ).

[0068] S240, determine the cross-slice edges of the layout based on the tangent points of multiple slices.

[0069] In some embodiments, a scan-line algorithm is used to obtain a list of cross-slice edges from the list of tangent points of multiple slices. The cross-slice edges include first and second tangent points located on the overlapping first and second boundaries of adjacent slices, respectively. The first and second tangent points are tangent points at the same position on the first and second boundaries, sorted by coordinate values. For example, as... Figure 3 As shown, the tangent point C in slice #1 and the tangent point E in slice #2 are located on the overlapping boundary of slice #1 and slice #2. Tangent point C is the first tangent point from left to right on the lower boundary of slice #1, that is, the first tangent point arranged in ascending order of x-coordinate values. Tangent point E is the first tangent point from left to right on the upper boundary of slice #2. Then (C, E) is Figure 3 The chip layout shown represents one side of the final composite rectangle.

[0070] In one embodiment, such as Figure 3 As shown, the cross-slice edges that can be obtained according to the scan line algorithm include {(C,E),(H,K),(M,N),(Z,A),(F,D),(B,Y),(X,L),(J,G)}. Since the number of elements in the tangent list is related to P, the time complexity of the scan line algorithm is O(P log P).

[0071] In one possible implementation, the sorting method in the scanline algorithm differs from the clockwise or counterclockwise sorting method in this embodiment. Therefore, using the center of all slice positions as the center, the edges across slices are sorted counterclockwise to obtain {(C,E),(H,K),(M,N),(Z,A),(F,D),(B,Y),(X,L),(J,G)}, with a time complexity of O(P log P).

[0072] In summary, the total time complexity of S240 is O(P log P).

[0073] S250, determine the list of edges of the layout based on the list of edges across slices and multiple slices.

[0074] S251, determine multiple borders of the second graphic based on the tangent points of multiple slices.

[0075] In this embodiment, the second graphic is a composite polygon formed by multiple first graphics, and the border includes a graphic identifier of the second graphic, a border type of the border, and multiple tangent points of the border. In some embodiments, tangent point pairs of multiple slices are determined based on the tangent points of the multiple slices. A tangent point pair includes a pair of adjacent tangent points from a list of tangent points of the second slice, and the second slice is any one of the multiple slices.

[0076] In one possible implementation, the tangents of the second slice are arranged in a clockwise or counterclockwise order centered on the geometric center of the second slice, with adjacent tangents being those that are adjacent in the arrangement. For example, Figure 3The slice #1 shown is rectangular in shape. Cutting points A and B are located on the right boundary of slice #1, and cutting points C and D are located on the lower boundary. Polar coordinates are established at the geometric center of slice #1. The x and y coordinates of all cutting points are converted to their distances from the geometric center and angles relative to the coordinate axes in polar coordinates. The clockwise or counterclockwise order of the cutting points can then be determined based on the magnitude of the angles. In this embodiment, a standard polar coordinate system is established in slice #1, and the list of cutting points in slice #1 is sorted counterclockwise, resulting in a list of cutting points {B,A,C,D}. A further list of cutting point pairs is {(B,A),(A,C),(C,D),(D,B)}. It should be understood that, similar to edges and directed edges in a graph, a pair of cutting points can represent a direction, i.e., the first cutting point in a pair points to the second cutting point; alternatively, the order of the cutting points may not indicate a direction.

[0077] The number of pointcuts in the pointcut list is related to P. Therefore, the time complexity of traversing the pointcut list to obtain the pointcut pair list is O(P), and the time complexity of sorting the pointcut list is O(P log P).

[0078] In this implementation, tangent pairs are used to represent the positional and connectivity relationships between tangent points. The properties of the graphics can be analyzed based on tangent pairs, thereby improving the efficiency of splicing composite polygons.

[0079] In some embodiments, the list of edges of the layout includes edges across slices, and edges obtained by deleting overlapping cut edges from the list of edges of multiple slices; wherein a cut edge is an edge of the first graphic that overlaps with a boundary of the first slice.

[0080] In one possible implementation, overlapping cut point pairs are removed from the list of cut point pairs for multiple slices. Specifically, as shown below... Figure 3 As shown, vertices C and D in slice #1 are both vertices and tangent points, so (C,D) is an edge of shape ABCD. Since (C,D) coincides with the lower boundary of slice #1, it is a tangent edge of shape ABCD. Similarly, (F,E) can be considered a tangent edge of shape EFGH, so (C,D) and (F,E) coincide. Using the scanline algorithm on tangent edges (C,D) and (F,E), considering that edges (C,E) and (F,D) have already been established, they are self-intersecting edges within the layout, and the tangent point pair (C,D) and (F,E) should be deleted.

[0081] In another embodiment, such as Figure 4As shown, the cut edges in slice #1 are (C,S) and (T,D), and the cut edges in slice #2 are (F,V) and (U,E). According to the scan-line algorithm, the cut edges {(C,S),(T,D),(F,V),(U,E)} are all self-intersecting edges within the layout, and their corresponding cut points should be deleted. Similarly, when there are multiple pairs of overlapping cut edges on the boundary between two overlapping slices, the corresponding cut point pairs should all be deleted.

[0082] It should be understood that the specific implementation of the scan line algorithm in the above embodiments refers to related technologies and will not be elaborated here. The number of elements in the cut-point list is related to P, therefore the time complexity of this embodiment is O(P log P).

[0083] Furthermore, iterate through the list of edges of multiple slices, and delete overlapping edges in the list of edges of multiple slices based on the tangent to be deleted. Obviously, the time complexity of this step is O(PQ).

[0084] In this implementation, removing overlapping edges can reduce unnecessary redundant data in the graphics and improve the reliability of graphics storage and representation.

[0085] In some embodiments, multiple borders of the second graphic are determined based on a list of cut point pairs across slice edges and multiple slices. According to the foregoing embodiments, the layout already includes W lists of cut point pairs and a list of slice edges, where W is the number of slices. Further, these W+1 lists can be concatenated end-to-end to form a larger original list of cut point pairs, where each element in the original list is of the form (cut point #1, cut point #2).

[0086] In one possible implementation, a simple cycle detection algorithm is used to determine multiple bounding boxes. First, a hash table is set up where the key is a cutoff point and the value is a list of cutoff point pairs. Specifically, the original list of cutoff point pairs is traversed once, mapping the starting point (first point) of each cutoff point pair to a list of all cutoff point pairs starting from that first point. Let P1 be the number of elements in the original list of cutoff point pairs; then the time complexity of this step is O(P1), where P1 is linearly dependent on P, therefore the time complexity of this step is O(P).

[0087] Secondly, for each cut point in the hash table, check if there is an edge starting from it. If so, insert the starting point of the current cut point pair into the current border, and use the ending point (the second point) as the starting point of the next cut point pair to be searched. Recursively search for cut point pairs and delete the searched ones until no cut point pair starting from the current cut point can be found, thus obtaining the current border. Then, repeat the above steps for the remaining cut point pairs to obtain another border. This step involves searching the hash table, with a time complexity of O(1). Since each cut point and edge is visited once, the overall time complexity is still O(P1), and further, O(P).

[0088] In this implementation, the simple ring detection algorithm has low time complexity and can improve the efficiency of determining multiple bounding boxes.

[0089] In some embodiments, the graphic identifier of the border and the border type are further described. For example, such as Figure 3 As shown, for a composite polygon in the layout, based on the list of edges across slices and the list of tangent pairs of multiple slices, we can obtain two borders corresponding to the shape. The border type of {A,C,E,H,K,M,N,Z} is the outer border, and the border type of {B,Y,X,L,J,G,F,D} is the inner border.

[0090] In summary, the time complexity of S251 is O(P log P) + O(PQ).

[0091] In this implementation, the border can accurately represent the attributes of the composite polygon. Generating borders based on an ordered list of tangent points can reduce the implementation complexity of the splicing algorithm and improve the reliability of graphics storage and representation.

[0092] S252, determine the self-intersecting edges of the second graphic based on the first border and at least one second border.

[0093] In some embodiments, a scanline algorithm is used on the first border and at least one second border of the second graphic to determine a list of self-intersecting edges of the second graphic. The graphic identifier of the first border and the graphic identifiers of all second borders correspond to the same second graphic. The border type of the first border is an outer border, and the border type of the second border is an inner border. The two vertices of a self-intersecting edge are tangent points in different borders. The two vertices of at least one self-intersecting edge of the second graphic are a tangent point in the first border and a tangent point in one of the second borders, respectively.

[0094] It should be understood that the second shape is a composite polygon, which has one and only one outer border and may have one or more inner borders. Correspondingly, the second shape has one and only one first border and may have one or more second borders. In one possible implementation, such as... Figure 3As shown, {A,C,E,H,K,M,N,Z} is the first border, and {B,Y,X,L,J,G,F,D} is the second border. When the self-intersecting edges are directed edges, the list of self-intersecting edges contains exactly two self-intersecting edges: {(C,D),(F,E)}. Taking (C,D) as an example, vertex C is the tangent point in the first border, and D is the tangent point in the second border. Of course, the list of self-intersecting edges can also be {(X,N) and (M,L)}, which can achieve the same result. Figure 3 The inner and outer borders of the compound polygon shown are connected. When the self-intersecting edges do not indicate direction, the list of self-intersecting edges may contain only one self-intersecting edge from (C,D) and (F,E).

[0095] In one possible implementation, a second shape includes two inner borders, where the two vertices of one of the self-intersecting edges can be the tangent points in two different second borders, i.e., the two inner borders are connected by the self-intersecting edge, and one of the inner borders is connected to the outer border by the self-intersecting edge.

[0096] In the first and second borders of the second graphic, the number of tangent points is related to P, so the time complexity of the scan line algorithm of S252 is O(P log P).

[0097] It should be understood that in related technologies, the Boolean OR algorithm performs a scanline algorithm based on all points of the second graphic, and the resulting self-intersecting edge is usually an edge formed by extending a vertex of the inner border horizontally or vertically until it contacts a point of the outer border. For example... Figure 5 As shown, the self-intersecting edges obtained by the Boolean OR algorithm are usually edges (A, B). In this application, both vertices of the self-intersecting edge are tangent points, for example... Figure 5 The edge (C,D) in the middle.

[0098] S253, determine the list of edges of the layout based on the list of edges across slices, self-intersecting edges, and edges of multiple slices.

[0099] In one possible implementation, the edge lists of multiple slices are sorted according to the x-coordinates and / or y-coordinates of the start and / or end points of the edges. Therefore, firstly, the P2 self-intersecting edge lists, each containing a constant number of elements and linearly related to P, are merged into a single self-intersecting edge list containing P3 elements. The time complexity of this step is O(P). Then, the cross-slice edge list and the self-intersecting edge list, each containing P4 elements and linearly related to P, are sorted in the same way as the slice edge lists. The time complexity of this step is O(P log P). Secondly, when the layout includes W slices, this embodiment essentially uses a multi-way merge algorithm, merging the W sorted edge lists, each containing an average of PQ elements, and the two sorted edge lists, each containing an average of P elements, into a single sorted list. According to the aforementioned embodiment, the time complexity of this step is O(PQ) + O(P log P).

[0100] In this implementation, the multi-way merge algorithm has low time complexity and can improve the efficiency of determining the edge list of the map.

[0101] In summary, S251-S253 provided in this application can efficiently and accurately process the vertices and edges of composite polygons related to slice boundaries, improving the efficiency of composite polygon stitching. In all embodiments and possible implementations of the layout stitching method in this example, the time complexity of the main steps is one of O(PQ), O(P log P), or O(PQ) + O(P log P), therefore the time complexity is O(PQ) + O(P log P), while the time complexity of conventional polygon Boolean OR operations is O(PQ log PQ). The time complexity of the layout stitching algorithm in this application is less than that of conventional stitching algorithms.

[0102] It should be understood that time complexity is a concept used to describe the relationship between the running time of an algorithm and the size of the input data. "Algorithm #1 has a greater time complexity than Algorithm #2" usually means that in the worst case, as the input size increases, the time required by Algorithm #1 increases at a faster rate than that of Algorithm #2. However, this does not mean that Algorithm #1 will be slower than Algorithm #2 in all cases. For example, the notation of time complexity ignores the constant factor in the algorithm. Even if the time complexity of Algorithm #1 is higher than that of Algorithm #2, if the constant factor of Algorithm #1 is smaller, Algorithm #1 may be faster than Algorithm #2 for small datasets. Furthermore, Big O notation ignores lower-order terms in polynomials; when the input size is small, the impact of lower-order terms on speed and time cannot be ignored. In summary, it is usually difficult to reflect the time complexity of an algorithm by statistically analyzing its specific time usage. Generally, logical analysis is used to compare the merits of different algorithms under different conditions.

[0103] It should be understood that the time complexity of determining the target slice based on the original slice is obviously related to P and Q, and the time taken in this step increases as P and Q increase. For algorithms executed in specific layout processing software, it is usually impossible to separately calculate the time corresponding to the above steps and the time corresponding to the layout stitching steps. Furthermore, calculating the time of the complete layout processing process usually does not reflect the time taken in the layout stitching steps; therefore, the time of the complete layout processing process can only serve as a reference for algorithm performance.

[0104] In summary, for a specific chip layout, the duration of each embodiment or step described in this application is statistically analyzed and compared with the duration of steps or the total duration of an algorithm that implements a similar function. The resulting numerical values ​​should not be considered as a limitation on the technical solution of this application.

[0105] In one embodiment, to compare the time taken for the complete layout processing process of the embodiments of this application and related technologies, a chip layout processing method in the related technologies is used as a comparative example. The comparative method specifically involves: dividing the layout into multiple original slices; processing the multiple original slices in parallel to obtain multiple target slices; performing a polygon Boolean OR operation based on the list of edges of the multiple target slices to determine the list of edges of the layout; and determining the list of vertices of the layout based on the list of vertices of the multiple target slices. The chip layout processing method corresponding to the method of the embodiments of this application further includes: before obtaining the list of vertices and the list of edges of the multiple slices of the layout, dividing the layout into multiple original slices; and processing the multiple original slices in parallel to obtain multiple slices.

[0106] The comparative examples and the embodiments of this application are implemented using the same programming language (e.g., C++), executed in the same operating environment (e.g., the same computer device), and process the same multiple chip layouts, with each layout processed three times. For each layout, the average processing time for three processing runs in both the comparative examples and the embodiments of this application is statistically analyzed, and the results are shown in Table 1.

[0107] Table 1

[0108] Numbering Comparative Example Time t1(s) Example time t2 (s) [t2 / t1] 1 170 192 112％ 2 218 136 63％ 3 382 226 60％ 4 445 482 108％ 5 862 164 22％ 6 1144 192 17％ 7 3745 506 14％ 8 6859 248 4％

[0109] As shown in Table 1, for 6 out of the 8 layouts, the processing time of this embodiment is shorter than that of the comparative example. Furthermore, the processing time of the comparative example is positively correlated with the value of PQ. As the processing time t1 of the comparative example increases, the ratio t2 / t1 of the processing time t2 of this embodiment to the processing time t1 of the comparative example decreases, indicating that the time complexity of this embodiment is less than that of the comparative example.

[0110] The foregoing mainly describes the solutions provided by the embodiments of this application from a methodological perspective. To achieve the above functions, it includes corresponding hardware structures and / or software modules for executing each function. Those skilled in the art should readily recognize that, based on the units and algorithm steps of the examples described in conjunction with the embodiments disclosed herein, this application can be implemented in hardware or a combination of hardware and computer software. Whether a function is executed in hardware or by computer software driving hardware depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0111] This application also provides a chip system 800, such as... Figure 6 As shown, the chip system 800 includes at least one processor and at least one interface circuit, and the processor includes multiple processing units. As an example, when the chip system 800 includes one processor and one interface circuit, the processor can be... Figure 6 The processor 810 shown in the solid box (or the processor 810 shown in the dashed box) can have an interface circuit that is... Figure 6 The interface circuit 820 is shown in the solid box (or the interface circuit 820 is shown in the dashed box).

[0112] When the chip system 800 includes two processors and two interface circuits, then the two processors include Figure 6 The processor 810 shown in the solid box and the processor 810 shown in the dashed box, these two interface circuits include Figure 6 Interface circuit 820 is shown in both solid and dashed boxes. This is not a limitation. Processor 810 and interface circuit 820 can be interconnected via lines. For example, interface circuit 820 can be used to receive signals (e.g., instructions stored in memory). As another example, interface circuit 820 can be used to send signals to other devices (e.g., processor 810).

[0113] For example, interface circuit 820 can read instructions stored in memory and send those instructions to processor 810. When the instruction is executed by processor 810, it can cause a device for accessing memory or a device for accessing memory to perform the steps in the above embodiments. Of course, the chip system 800 may also include other discrete devices, and this application embodiment does not specifically limit this.

[0114] This application also provides a computing device 900. For example... Figure 7As shown, the computing device 900 includes a bus 902, a processor 904, a memory 906, and a communication interface 908. The processor 904, memory 906, and communication interface 908 communicate via the bus 902. The processor 904 includes multiple processing units. The computing device 900 can be a server or a terminal device. It should be understood that this application does not limit the number of processors and memories in the computing device 900.

[0115] The 902 bus can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc. For ease of representation, Figure 7 The bus 904 is represented by a single line, but this does not mean that there is only one bus or one type of bus. The bus 904 may include a path for transmitting information between various components of the computing device 900 (e.g., memory 906, processor 904, communication interface 908).

[0116] Processor 904 may include any one or more processors such as a central processing unit (CPU), a graphics processing unit (GPU), a microprocessor (MP), or a digital signal processor (DSP).

[0117] The memory 906 may include volatile memory, such as random access memory (RAM). The processor 904 may also include non-volatile memory, such as read-only memory (ROM), flash memory, hard disk drive (HDD), or solid state drive (SSD).

[0118] The memory 906 stores executable program code, which the processor 904 executes to implement the aforementioned data management methods. That is, the memory 906 stores instructions for executing the data management methods.

[0119] The communication interface 908 uses transceiver modules, such as, but not limited to, network interface cards and transceivers, to enable communication between the computing device 900 and other devices or communication networks.

[0120] Another embodiment of this application provides a computer-readable storage medium storing instructions that, when executed on a means for accessing memory, perform the various steps of the method flow shown in the above-described method embodiments. In some embodiments, the disclosed method can be implemented as computer program instructions encoded in a machine-readable format on a computer-readable storage medium or on other non-transitory media or articles of art.

[0121] Figure 8 A conceptual partial view of a computer program product provided in an embodiment of this application is shown schematically. The computer program product includes a computer program for executing computer processes on a computing device.

[0122] In one embodiment, a computer program product is provided using a signal bearer medium 1000. The signal bearer medium 1000 may include one or more program instructions that, when run by one or more processors, can execute the data management methods provided in this application embodiment.

[0123] In some examples, the signal carrying medium 1000 may include a computer-readable medium 1001, such as, but not limited to, a hard disk drive, a compact disc (CD), a digital video disc (DVD), a digital magnetic tape, a memory, a read-only memory (ROM), or a random access memory (RAM), etc.

[0124] In some implementations, the signal carrying medium 1000 may include a computer recordable medium 1002, such as, but not limited to, a memory, a read / write (R / W) CD, an R / W DVD, and the like.

[0125] In some implementations, the signal-bearing medium 1000 may include a communication medium 1003, such as, but not limited to, digital and / or analog communication media (e.g., fiber optic cables, waveguides, wired communication links, wireless communication links, etc.). The signal-bearing medium 1000 may be transmitted by a wireless communication medium 1003 (e.g., a wireless communication medium conforming to the IEEE 1502.11 standard or other transmission protocols). One or more program instructions may be, for example, computer-executable instructions or logical implementation instructions.

[0126] In some examples, the apparatus for data management can be configured to provide various operations, functions, or actions in response to one or more program instructions in a computer-readable medium 1001, a computer-recordable medium 1002, and / or a communication medium 1003.

[0127] It should be understood that the arrangements described herein are for illustrative purposes only. Therefore, those skilled in the art will understand that other arrangements and other elements (e.g., machines, interfaces, functions, sequences, and functional groups, etc.) can be used instead, and some elements may be omitted depending on the desired outcome. Furthermore, many of the described elements are functional entities that can be implemented as discrete or distributed components, or in any suitable combination and location with other components.

[0128] In the above embodiments, implementation can be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented using software programs, it can be implemented, in whole or in part, in the form of a computer program product. This computer program product includes one or more computer instructions. When executed on a computer and when the computer execution instructions are executed, all or part of the processes or functions according to the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device.

[0129] Computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, computer instructions can be transmitted from one website, computer, server, or data center to another via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. A computer-readable storage medium can be any available medium that a computer can access, or it can contain one or more data storage devices such as servers or data centers that can be integrated with that medium. Available media can be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., DVDs), or semiconductor media (e.g., solid-state drives (SSDs)).

[0130] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A method for stitching together a map, characterized in that, include: Get a list of vertices and a list of edges for multiple slices of the map; Based on the list of vertices of the plurality of slices, a list of vertices of the layout is obtained, wherein the list of vertices of the layout includes the vertices of the plurality of slices; The tangent point of the first slice is determined based on the vertices of the first graphic of the first slice, wherein the first graphic is a graphic in the first slice whose at least one edge overlaps with at least one boundary of the first slice, the tangent point is a vertex in the first graphic located on the boundary of the first slice, and the first slice is any slice among the plurality of slices. Based on the tangent points of the plurality of slices, the cross-slice edge of the layout is determined, wherein the cross-slice edge includes a first tangent point and a second tangent point located on the first boundary and the second boundary of adjacent slices, respectively, and the first tangent point and the second tangent point are tangent points at the same position on the first boundary and the second boundary, respectively, sorted by coordinate value. The list of edges of the layout is determined based on the list of cross-slice edges and the list of edges of the plurality of slices.

2. The map splicing method according to claim 1, characterized in that, The list of edges of the layout includes the cross-slice edges, and the edges obtained by deleting overlapping cut edges from the list of edges of the plurality of slices; wherein the cut edge is an edge of the first graphic that overlaps with a boundary of the first slice.

3. The layout stitching method according to claim 1 or 2, characterized in that, Determining the list of edges of the layout based on the list of edges across slices and the list of edges of the plurality of slices includes: In the case where multiple first graphics form a composite polygon, multiple borders of a second graphic are determined based on the tangent points of the multiple slices, wherein the second graphic is a composite polygon formed by multiple first graphics, and the borders include a graphic identifier of the second graphic, a border type of the borders, and multiple tangent points of the borders. Based on a first border and at least one second border, a self-intersecting edge of the second graphic is determined, wherein the graphic identifier of the first border and the graphic identifier of the at least one second border correspond to the same second graphic, the border type of the first border is an outer border, the border type of the second border is an inner border, the two vertices of the self-intersecting edge are tangents in different borders, and the two vertices of at least one self-intersecting edge of the second graphic are tangents in the first border and tangents in a second border, respectively. The list of edges of the layout is determined based on the list of cross-slice edges, the list of self-intersecting edges, and the list of edges of the plurality of slices, wherein the list of edges of the layout includes the cross-slice edges, the self-intersecting edges, and the edges obtained by deleting overlapping cut edges from the list of edges of the plurality of slices.

4. The map splicing method according to claim 3, characterized in that, Determining multiple borders of the second graphic based on the tangent points of the multiple slices includes: Based on the tangents of the plurality of slices, a list of tangent pairs of the plurality of slices is determined, wherein the tangent pair includes a pair of adjacent tangents of the tangents of the second slice, and the second slice is any one of the plurality of slices; The plurality of borders are determined based on the list of cross-slice edges and the list of tangent pairs of the plurality of slices.

5. The map splicing method according to claim 4, characterized in that, The cutting points of the second slice are arranged in a clockwise or counterclockwise order centered on the geometric center of the second slice, and the adjacent cutting points are the adjacent cutting points in the arrangement order.

6. The map splicing method according to any one of claims 3 to 5, characterized in that, Determining the list of edges of the layout based on the list of cross-slice edges, the list of self-intersecting edges, and the list of edges of the plurality of slices includes: The list of cross-slice edges, the list of self-intersecting edges, and the list of edges of the multiple slices are used as inputs to a multi-way merge algorithm to obtain the edge list of the layout.

7. The map splicing method according to any one of claims 4 to 6, characterized in that, Determining the plurality of borders based on the list of cross-slice edges and the plurality of slice point pairs includes: The list of cross-slice edges and the list of tangent pairs of the multiple slices are used as input to a simple loop detection algorithm to determine the multiple bounding boxes.

8. The layout splicing method according to any one of claims 1 to 7, characterized in that, The time complexity of determining the list of edges of the layout based on the list of cross-slice edges and the list of edges of the multiple slices is O(PQ) + O(Plog P), where the average number of the first graphs in the multiple slices is P, the average number of vertices in the first graphs is Q, and P and Q are both positive integers.

9. A computer device, characterized in that, It includes one or more processors; one or more memories; said one or more memories storing one or more computer programs, said one or more computer programs including instructions that, when executed by said one or more processors, cause the method of any one of claims 1 to 8 to be performed.

10. A chip, characterized in that, The chip includes a processor and a communication interface, the communication interface being used to receive signals and transmit the signals to the processor, the processor processing the signals such that the method as described in any one of claims 1 to 8 is executed.

11. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions that, when executed on a computer device, cause the method as described in any one of claims 1 to 8 to be performed.

12. A computer program product containing instructions, characterized in that, When the instructions are executed by a computer device, the computer device performs the method as described in any one of claims 1 to 8.

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