Cooperative etching compensation method and device based on multilayer layout and CMP morphology prediction, medium, program product and terminal

Abstract

According to the collaborative etching compensation method and device based on the multi-layer layout and CMP morphology prediction, the medium, the program product and the terminal provided by the invention, the layout data of the current layer layout and the adjacent upper and lower layouts are acquired and associated, interlayer features are extracted based on the layout data, and the three-dimensional contour height data after CMP is predicted through morphology simulation; then the three-dimensional contour height data and the graphic effect of the upper layer layout and the lower layer layout are jointly integrated into an imaging model and an etching process simulation model, the simulation environment is optimized, iterative compensation is carried out in the environment, and the final mask graph and process parameters of the current layer layout are generated. According to the method, multi-layer layout information and CMP morphology prediction are deeply fused, the process coupling effect between multi-layer layouts and chemical mechanical polishing morphology changes are comprehensively considered, an accurate simulation model is established, collaborative optimization of cross-process links is achieved, and the etching compensation precision is remarkably improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing technology, and in particular to a collaborative etching compensation method, apparatus, medium, process product and terminal based on multilayer layout and CMP topography prediction. Background Technology

[0002] Currently, as integrated circuit process nodes continue to shrink, the process coupling effect in semiconductor manufacturing is becoming increasingly significant. Traditional single-layer etching compensation methods face the following technical bottlenecks:

[0003] First, due to the pattern density effect, chemical mechanical polishing (CMP) generates nanoscale undulations on the wafer surface related to the underlying pattern layout. This unevenness can lead to problems such as uneven photoresist thickness, photolithography focal plane deviation, and inconsistent etching depth. Second, multilayer process interaction effects include the influence of the underlying pattern density distribution on the surface flatness after CMP, the complex interactions between masks in multiple patterning techniques within the same layer, and the potential impact of the upper layer pattern on the current layer process. Furthermore, the traditional OPC method based on the "ideal flat surface" assumption cannot accurately predict CMP morphology effects, single-layer compensation strategies ignore interlayer process coupling, and existing technologies have failed to effectively address the physical coupling problem.

[0004] These factors collectively lead to significant critical dimension variations and edge placement errors, with errors reaching the nanometer level in advanced processes, severely limiting chip manufacturing yield and performance. This problem will become even more pronounced as process nodes shrink further. Therefore, traditional compensation methods based solely on current layer information are no longer sufficient to meet the accuracy requirements of advanced processes, resulting in a non-negligible edge placement error (EPE) between the final silicon wafer pattern and the design target, causing electrical short circuits, open circuits, or performance failures. Summary of the Invention

[0005] In view of the shortcomings of the prior art, the present invention provides a collaborative etching compensation method, apparatus, medium, program product and terminal based on multilayer layout and CMP topography prediction, which is used to solve the pattern distortion problem caused by interlayer process coupling and chemical mechanical polishing topography effect in advanced processes.

[0006] To achieve the above and other related objectives, the first aspect of this application provides a collaborative etching compensation method based on multi-layer layout and CMP topography prediction, comprising: acquiring layout data of the current layer layout, the previous layer layout, and the next layer layout in the multi-layer layout; extracting features from the layout data of the multi-layer layout to obtain feature data of the multi-layer layout; performing computational fluid dynamics and mechanical wear simulation using a CMP process topography simulation model based on the feature data of the multi-layer layout to obtain three-dimensional contour height data of the wafer surface after CMP; inputting the three-dimensional contour height data of the wafer surface after CMP and the feature data of the multi-layer layout into a lithography imaging model and an etching process simulation model to iteratively optimize and compensate the mask pattern of the current layer layout to generate an optimized and compensated mask pattern of the current layer layout.

[0007] In some embodiments of the first aspect of this application, the process of extracting features from the layout data of a multi-layer layout to obtain feature data of the multi-layer layout includes: identifying key features of the layout data of the multi-layer layout to obtain key feature identification results for each layer; establishing an inter-layer alignment mapping relationship based on the key feature identification results of each layer; extracting inter-layer feature data between the multi-layer layouts based on the inter-layer alignment mapping relationship; and using the key feature identification results of each layer and the inter-layer feature data between the multi-layer layouts as feature data of the multi-layer layout.

[0008] In some embodiments of the first aspect of this application, the key feature identification results of each layer layout include: the initial line width and spacing of the graphics in the current layer layout, the graphic density distribution of the next layer layout, and the graphic density distribution of the overlapping area of ​​the projection of the previous layer layout onto the current layer layout.

[0009] In some embodiments of the first aspect of this application, the process of inputting the three-dimensional contour height data of the wafer surface after CMP and the feature data of the multi-layer layout into a lithography imaging model and an etching process simulation model, and iteratively optimizing and compensating the mask pattern of the current layer layout to generate the optimized and compensated mask pattern of the current layer layout includes: establishing a focal plane compensation function based on the three-dimensional contour height data of the wafer surface after CMP and the photoresist thickness; performing dynamic focal plane compensation according to the focal plane compensation function during the lithography simulation of the current layer layout in the lithography imaging simulation model to obtain a compensated lithography imaging simulation image; inputting the compensated lithography imaging simulation image and the feature data of the next layer layout into the etching process simulation model to obtain the etching simulation layout of the current layer layout; calculating the error between the etching simulation layout of the current layer layout and the mask pattern of the current layer layout based on a preset optimization function, and performing iterative optimization and compensation operations based on the error to generate the optimized and compensated mask pattern of the current layer layout.

[0010] In some embodiments of the first aspect of this application, the formula for the focal plane compensation function is: ;in, Let be the coordinates of any position on the wafer surface. To compensate for the back focal plane, As the reference focal plane, The height of the CMP morphology at any location on the wafer surface. This refers to the thickness of the photoresist.

[0011] In some embodiments of the first aspect of this application, the preset optimization function includes: edge placement error.

[0012] To achieve the above and other related objectives, a second aspect of this application provides a collaborative etching compensation device based on multi-layer layout and CMP topography prediction, comprising: a layout data acquisition module for acquiring layout data of the current layer, the previous layer, and the next layer in a multi-layer layout; a feature extraction module for extracting features from the layout data of the multi-layer layout to obtain feature data of the multi-layer layout; a CMP topography simulation module for performing computational fluid dynamics and mechanical wear simulations based on the feature data of the multi-layer layout using a CMP process topography simulation model to obtain three-dimensional contour height data of the wafer surface after CMP; and an optimization compensation module for inputting the three-dimensional contour height data of the wafer surface after CMP and the feature data of the multi-layer layout into a lithography imaging model and an etching process simulation model to iteratively optimize and compensate the mask pattern of the current layer layout to generate an optimized and compensated mask pattern of the current layer layout.

[0013] To achieve the above and other related objectives, a third aspect of this application provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the collaborative etching compensation method based on multi-layer layout and CMP topography prediction.

[0014] To achieve the above and other related objectives, a fourth aspect of this application provides a computer program product comprising computer program code that, when executed on a computer, causes the computer to implement the collaborative etching compensation method based on multi-layer layout and CMP topography prediction.

[0015] To achieve the above and other related objectives, a fifth aspect of this application provides an electronic terminal, including a memory, a processor, and a computer program stored in the memory; the processor executes the computer program to implement the collaborative etching compensation method based on multi-layer layout and CMP topography prediction.

[0016] As described above, the collaborative etching compensation method, apparatus, medium, program product, and terminal based on multi-layer layout and CMP topography prediction provided in this application have the following beneficial effects:

[0017] (1) Higher accuracy: By introducing upper and lower layer layout information, the process model is closer to reality, which greatly improves the accuracy of prediction and compensation of etching load effect and optical proximity effect, and effectively reduces EPE.

[0018] (2) Global optimization: It solves the problem of inter-layer process coupling, avoids the limitation of traditional methods that only consider the current layer layout, and realizes cross-layer collaborative optimization.

[0019] (3) Improved yield: More accurate compensation means lower risk of short circuits and open circuits, especially at advanced process nodes, which can significantly improve the manufacturing yield and reliability of chips. Attached Figure Description

[0020] Figure 1 The diagram shown is a flowchart illustrating a collaborative etching compensation method based on multi-layer layout and CMP topography prediction in one embodiment of this application.

[0021] Figure 2 The diagram shown is a structural schematic of a collaborative etching compensation device based on multi-layer layout and CMP topography prediction in one embodiment of this application.

[0022] Figure 3 The diagram shown is a structural schematic of an electronic terminal according to an embodiment of this application. Detailed Implementation

[0023] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. This application can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application. It should be noted that, unless otherwise specified, the following embodiments and features in the embodiments can be combined with each other.

[0024] Before providing a further detailed description of the present invention, the nouns and terms used in the embodiments of the present invention are explained, and the nouns and terms used in the embodiments of the present invention are subject to the following interpretations:

[0025] <1> EPE (Edge Placement Error) refers to the deviation between the actual position of the edge of a pattern and its designed position during photolithography. EPE is an important indicator of photolithography accuracy and directly affects device performance and yield.

[0026] <2> Chemical Mechanical Planarization (CMP): also known as chemical mechanical polishing, is an important step in the fine surface processing of semiconductor manufacturing technology. It has become the most widely used planarization technology in the era of very large-scale integrated circuits. By combining chemical etching of polishing fluid and mechanical removal of polishing particles, excess material on the wafer surface is removed, so that the polished surface achieves a nanometer-level smoothness, ensuring the accuracy of subsequent photolithography, deposition and other processes.

[0027] <3> OPC (Optical Proximity Correction): Optical proximity correction is a technique used to improve the quality of lithography patterns on semiconductor chips. It makes tiny corrections to the original design pattern to compensate for optical near-field effects and chemical effects during the lithography process, thereby improving the precision and reliability of chip manufacturing.

[0028] <4> Etching Loading Effect: The loading effect refers to the influence of pattern density on the etching process. In chip etching, different pattern densities affect parameters such as etching rate and depth, thereby affecting the structure and performance of the final product.

[0029] <5> Line width and spacing: Line width is the width of lines or graphics in the chip design and manufacturing layout, while spacing is the width of different graphics.

[0030] This application provides a collaborative etching compensation method based on multi-layer layout and CMP topography prediction. By deeply fusing multi-layer layout information and CMP topography prediction, and comprehensively considering the process coupling effect between multi-layer layouts and the changes in chemical mechanical polishing topography, an accurate simulation model is established to achieve collaborative optimization across process stages, significantly improving etching compensation accuracy. This application is applicable to advanced process technologies and can effectively solve the pattern distortion problem caused by inter-layer interactions and chemical mechanical polishing topography effects, significantly improving chip manufacturing accuracy and yield.

[0031] To facilitate understanding of the embodiments of this application, firstly, in conjunction with Figure 1 Detailed explanation. Figure 1 This document illustrates a flowchart of a collaborative etching compensation method based on multi-layer layout and CMP topography prediction, as described in an embodiment of the present invention. The method in this embodiment includes:

[0032] Step S11: Obtain the layout data of the current layer, the previous layer, and the next layer in the multi-layer layout.

[0033] It should be noted that layout files are a core file type in the field of electronic design automation (EDA), used to describe the physical structure information of integrated circuits or microelectronic devices, including the size, shape, location, and interconnection methods of components in the circuit. Layout files are a crucial bridge from abstract logic to actual manufacturing in chip design, directly determining the chip's functionality, performance, and reliability. Layout files contain multiple layers of layout. In this embodiment, when performing etch compensation on the current layer layout, considering the multi-layer layout information, it is necessary to obtain the layout data of the current layer layout, as well as the layout data of the adjacent upper and lower layers. For example, obtaining the layout data of the current layer (… ) map, upper layer ( ) map and the next layer ( )version Figure 3 Layered layout, from top to bottom, the order is the next layer ( ) map, current layer ( ) map, next layer ( )territory.

[0034] Step S12: Extract features from the layout data of the multi-layer layout to obtain the feature data of the multi-layer layout.

[0035] In one embodiment of this application, the process of extracting features from the layout data of a multi-layer layout to obtain feature data of the multi-layer layout includes: identifying key features of the layout data of the multi-layer layout to obtain key feature identification results for each layer; establishing an inter-layer alignment mapping relationship based on the key feature identification results of each layer; extracting inter-layer feature data between the multi-layer layouts based on the inter-layer alignment mapping relationship; and using the key feature identification results of each layer and the inter-layer feature data between the multi-layer layouts as feature data of the multi-layer layout.

[0036] In one embodiment of this application, the key feature identification results of each layer of the layout include: the initial line width and spacing of the graphic in the current layer of the layout, the graphic density distribution of the next layer of the layout, and the graphic density distribution of the overlapping area of ​​the projection of the previous layer of the layout onto the current layer of the layout.

[0037] It should be noted that feature extraction algorithms are used to extract features from the layout data of multi-layer layouts. Specifically, feature extraction is performed on the layout data of the current layer, the layout data of the previous layer, and the layout data of the next layer, respectively, to extract key feature identification results such as graphic density distribution and key size statistical features of each layer.

[0038] The feature extraction algorithms include, but are not limited to, edge detection algorithms, shape feature extraction algorithms, and deep learning extraction algorithms. Edge detection algorithms include, but are not limited to, the Canny algorithm, Laplacian algorithm, Roberts algorithm, Prewitt algorithm, and Sobel algorithm. Shape feature extraction algorithms include, but are not limited to, Fourier algorithms, Zernike moment algorithms, grid algorithms, and shape description matrix algorithms. Deep learning extraction algorithms include, but are not limited to, convolutional neural networks and graph neural networks.

[0039] The graphic density distribution includes the proportion of line width or spacing per unit area in the layout. The key dimensional statistical features include statistical distribution data for line width and spacing. For example, obtaining the current layer ( ) map, upper layer ( ) map and the next layer ( After obtaining the layout data of the layout, feature extraction is performed on the three layers of layout data to obtain the current layer ( The initial line width and spacing of the map, the next layer ( The graphic density distribution of the map, the upper layer ( The graphic density distribution of the overlapping area of ​​the projection of the map onto the current layer map.

[0040] Furthermore, after obtaining the key feature recognition results of each layer of the layout, an inter-layer alignment mapping relationship is established to ensure coordinate accuracy, thereby obtaining the layout topology information between each layer of the layout as inter-layer feature data. The layout topology information includes the adjacency relationships and network structure between graphics in each layer of the layout. For example, matching the spatial positions of graphics in a three-layer layout ensures that the current layer ( The layer directly below a certain graphic on the map is the next layer. Which structure of the layout? After extracting the density distribution, key dimension statistical features, and layout topology information of each layer, the format is uniformly converted into a standardized data format for subsequent simulation to obtain the final multi-layer layout feature data.

[0041] Step S13: Based on the feature data of the multi-layer layout, the CMP process topography simulation model is used to perform computational fluid dynamics and mechanical wear simulation to obtain the three-dimensional contour height data of the wafer surface after CMP.

[0042] In this embodiment, key feature data affecting the flatness and etching load effect after CMP are extracted from the feature data of the multi-layer layout. The key feature data affecting the flatness after CMP includes the pattern density distribution of the current layer layout, the pattern geometry parameters of the current layer layout, the pattern density distribution of the next layer layout, and the pattern density distribution of the overlapping area of ​​the projection of the previous layer layout onto the current layer layout. The key feature data affecting the etching load effect includes the local pattern density, pattern spacing, and pattern edge density of the current layer layout.

[0043] It should be noted that the CMP process topography simulation in this embodiment predicts the wafer surface topography before the current layer layout undergoes processing. First, the layout data of the current layer layout and its adjacent upper and lower layers (the upper layer and the lower layer layout) are associated. Then, based on the layout data of the multi-layer layout, the feature data of the multi-layer layout is obtained. Using the key feature data affecting the flatness and etching load effect after CMP, a CMP process topography simulation model is constructed using CMP simulation tools. Simultaneously, the geometric features of the current layer layout (such as pattern density distribution, linewidth, etc.) and CMP process parameters (such as pressure, slurry characteristics, etc.) are input into this CMP process topography simulation model. Computational fluid dynamics and mechanical wear simulations are performed, and finally, the three-dimensional contour height data of the wafer surface after CMP is output. This three-dimensional contour height data records the height of each position on the wafer surface of the current layer layout relative to the reference plane before processing. In this embodiment, the CMP process topography simulation of the current layer layout before the process takes into account the correlation characteristics between the current layer layout and the adjacent layouts above and below, thus achieving more accurate prediction of the surface topography after CMP and improving the accuracy of the prediction of the wafer surface topography after CMP.

[0044] Step S14: Input the three-dimensional contour height data of the wafer surface after CMP and the feature data of the multi-layer layout into the lithography imaging model and the etching process simulation model, and iteratively optimize and compensate the mask pattern of the current layer layout to generate the optimized and compensated mask pattern of the current layer layout.

[0045] In one embodiment of this application, the process of inputting the three-dimensional contour height data of the wafer surface after CMP and the feature data of the multi-layer layout into a lithography imaging model and an etching process simulation model, and iteratively optimizing and compensating the mask pattern of the current layer layout to generate the optimized and compensated mask pattern of the current layer layout includes: establishing a focal plane compensation function based on the three-dimensional contour height data of the wafer surface after CMP and the photoresist thickness; performing dynamic focal plane compensation according to the focal plane compensation function during the lithography simulation of the current layer layout in the lithography imaging simulation model to obtain the compensated lithography imaging simulation image; inputting the compensated lithography imaging simulation image and the feature data of the next layer layout into the etching process simulation model to obtain the etching simulation layout of the current layer layout; calculating the error between the etching simulation layout of the current layer layout and the mask pattern of the current layer layout based on a preset optimization function, and performing iterative optimization and compensation operations based on the error to generate the optimized and compensated mask pattern of the current layer layout.

[0046] It should be noted that in this embodiment, CMP process topography simulation is used to obtain the three-dimensional contour height data of the wafer surface after CMP before the current layer layout is processed, i.e., to predict the CMP topography height. Dynamic focal plane compensation based on the CMP topography height allows subsequent photolithography simulation to accurately reflect the in-plane defocusing variation caused by the CMP topography. This is based on the CMP topography height at any position on the wafer surface. and photoresist thickness A focal plane compensation function (as shown in Formula 1) is constructed using the compensation values. The focal plane compensation value is obtained based on the focal plane compensation function to perform compensation during the lithography simulation of the current layer layout.

[0047] In this embodiment, the formula for the focal plane compensation function is:

[0048] ;(Formula 1)

[0049] in, Let be the coordinates of any position on the wafer surface. To compensate for the back focal plane, As the reference focal plane, The height of the CMP morphology at any location on the wafer surface. This refers to the thickness of the photoresist.

[0050] Specifically, for any location within the photolithography simulation area (i.e., the wafer surface) Its compensated focal plane is used for lithographic imaging calculations. Not the reference focal plane This location The focal plane is affected by the CMP topography height at the current location. and photoresist thickness Impact. Therefore, at the reference focal plane. Based on the CMP topography height at the current location and photoresist thickness Perform appropriate focal length compensation to obtain the compensated focal plane. Among them, the thickness of the photoresist This refers to the change in photoresist thickness calculated based on the layout data of the next layer. Photolithography simulation based on the compensated focal plane can realistically reflect the in-plane defocusing variation caused by CMP morphology, thus improving simulation accuracy.

[0051] In one embodiment of this application, the preset optimization function includes: edge placement error.

[0052] Furthermore, when the preset optimization function used is edge placement error, after obtaining the compensated lithography imaging simulation image, the compensated lithography imaging simulation image and the feature data of the next layer layout are input into the etching process simulation model to obtain the etching simulation layout of the current layer layout. Then, based on the edge placement error, the error between the etching simulation layout of the current layer layout and the mask pattern of the current layer layout is calculated. Then, the error is compared with the preset error threshold. If the error is greater than or equal to the preset error threshold, iterative optimization and compensation operations are performed on the etching simulation layout of the current layer layout until the error between the lithography simulation result and the mask pattern of the current layer layout after multiple iterations of optimization and compensation operations is less than the preset error threshold. Finally, the optimized and compensated mask pattern of the current layer layout is output.

[0053] The error is typically represented by the edge placement error (EPE) between the simulated graphic and the mask graphic of the current layer layout. The specific iterative optimization and compensation process is as follows: based on the EPE value, adjust the edge movement of the mask graphic of the current layer layout or add sub-resolution assist features (SRAF) to generate an optimized and compensated mask graphic. Then, iteratively execute the simulation-compensation loop until the EPE value is less than a preset error threshold, and output the final optimized and compensated mask graphic.

[0054] During iterative optimization and compensation operations, multi-level convergence criteria are set up, and a rapid feedback mechanism is established to provide reference for process parameter configuration and design optimization. This enables efficient iterative optimization and allows for adjustments to CMP process parameters and etching processes. Furthermore, a complete verification system can be established to perform rigorous manufacturability design checks, process window verification, generate detailed manufacturing guidance documents, and provide manufacturability assessment reports.

[0055] To facilitate understanding of the collaborative etching compensation method based on multi-layer layout and CMP topography prediction in this application, the following specific embodiments are provided for illustration.

[0056] Example 1: Fabricating a metal layer at a nanometer-scale process node ( For example, ( ).

[0057] Current layer layout ( The layer density varies drastically, and the adjacent immediate lower layer is a complex FinFET active region (AA) with an extremely complex surface morphology. When using conventional methods, EPE > 6nm.

[0058] This application will include AA layer, The layout of the layers and via layers (V0) is used as input. Data processing is performed on the input layout, and inter-layer alignment calibration is executed to ensure coordinate accuracy. The bumps on the transistor array and the depressions on the isolation region (difference of 15nm) are accurately predicted using a CMP process morphology simulation model. The photolithography imaging model shows that in the depression region, even at the optimal dose, the linewidth is 3nm thinner; the etching process simulation model shows that the etching rate is 8% slower in dense line regions than in isolated lines. After five iterations, asymmetrical curve thickening is applied to isolated lines in the depression region, while the designed linewidth is slightly tightened in the dense region. Simultaneously, fine-tuning of the CMP process parameters (pressure distribution optimization) is recommended. The final result is... The layered mask data is plotted, and adjustments to the CMP and etching processes are suggested. Simulation data shows that the global root mean square EPE value decreases from 7.2nm to 2.1nm, resulting in a significant improvement in the yield of the relevant structures.

[0059] This application acquires and associates layout data of the current layer layout and its adjacent upper and lower layers, extracts interlayer features based on the layout data, and predicts the 3D contour height data after CMP through topography simulation. Then, this 3D contour height data, along with the graphic effects of the upper and lower layers, is integrated into the imaging model and etching process simulation model. The simulation environment is optimized, and iterative compensation is performed within this environment to generate the final mask pattern and process parameters for the current layer layout. This application achieves a paradigm shift from "single-layer local compensation" to "multi-layer collaborative optimization," significantly improving etching contour accuracy and chip manufacturing yield.

[0060] It should be emphasized that the collaborative etching compensation method based on multi-layer layout and CMP topography prediction provided in this application has the following beneficial effects:

[0061] (1) Higher accuracy: By introducing upper and lower layer layout information, the process model is closer to reality, which greatly improves the accuracy of prediction and compensation of etching load effect and optical proximity effect, and effectively reduces EPE.

[0062] (2) Global optimization: It solves the problem of inter-layer process coupling, avoids the limitation of traditional methods that only consider the current layer layout, and realizes cross-layer collaborative optimization.

[0063] (3) Improved yield: More accurate compensation means lower risk of short circuits and open circuits, especially at advanced process nodes, which can significantly improve the manufacturing yield and reliability of chips.

[0064] In the embodiments of this application, the terms "first" and "second" are used to distinguish identical or similar items with essentially the same function and effect, without limiting their order. Those skilled in the art will understand that the terms "first" and "second" do not limit the quantity or execution order, and that the terms "first" and "second" do not necessarily imply that they are different.

[0065] It should be noted that, in the embodiments of this application, the words "exemplary" or "for example" indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in this application should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0066] In this application embodiment, "at least one" refers to one or more, and "more than one" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can represent: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or multiple.

[0067] Figure 2 This application provides a schematic block diagram of a collaborative etching compensation device based on multi-layer layout and CMP topography prediction, as shown in the embodiments below. Figure 2 As shown, the device 200 includes:

[0068] The layout data acquisition module 201 is used to acquire layout data of the current layer layout, the previous layer layout, and the next layer layout in a multi-layer layout;

[0069] The feature extraction module 202 is used to extract features from the layout data of the multi-layer layout to obtain the feature data of the multi-layer layout.

[0070] CMP morphology simulation module 203 is used to perform computational fluid dynamics and mechanical wear simulation based on the feature data of multi-layer layout using the CMP process morphology simulation model, and obtain the three-dimensional contour height data of the wafer surface after CMP.

[0071] The optimization and compensation module 204 is used to input the three-dimensional contour height data of the wafer surface after CMP and the feature data of the multi-layer layout into the lithography imaging model and the etching process simulation model, and to iteratively optimize and compensate the mask pattern of the current layer layout to generate the optimized and compensated mask pattern of the current layer layout.

[0072] It should be understood that the specific process of each module performing the above-mentioned steps has been described in detail in the above method embodiments, and will not be repeated here for the sake of brevity.

[0073] It should also be understood that the module division in the embodiments of this application is illustrative and only represents a logical functional division; in actual implementation, there may be other division methods. Furthermore, the functional modules in the various embodiments of this application can be integrated into a single processor, exist as separate physical entities, or be integrated into a single module. The integrated modules described above can be implemented in hardware or as software functional modules.

[0074] Figure 3 This is a schematic block diagram of the electronic terminal provided in an embodiment of this application. Figure 3 As shown, the electronic terminal includes at least one processor 301, a memory 302, at least one network interface 303, and a user interface 305. The various components in the device are coupled together via a bus system 304. It is understood that the bus system 304 is used to implement communication between these components. In addition to a data bus, the bus system 304 also includes a power bus, a control bus, and a status signal bus. However, for clarity, in… Figure 3 The general will label all buses as bus systems.

[0075] The user interface 305 may include a monitor, keyboard, mouse, trackball, clicker, button, touchpad, or touch screen.

[0076] It is understood that memory 302 can be volatile memory or non-volatile memory, or both. Non-volatile memory can be read-only memory (ROM) or programmable read-only memory (PROM), which serves as an external cache. By way of example, but not limitation, many forms of RAM are available, such as static random access memory (SRAM) and synchronous static random access memory (SSRAM). The memories described in the embodiments of this invention are intended to include, but are not limited to, these and any other suitable categories of memory.

[0077] In this embodiment of the invention, the memory 302 is used to store various types of data to support the operation of the electronic terminal 300. Examples of this data include: any executable program for operation on the electronic terminal 300, such as the operating system 3021 and application programs 3022; the operating system 3021 contains various system programs, such as the framework layer, core library layer, driver layer, etc., for implementing various basic services and handling hardware-based tasks. The application program 3022 may contain various applications, such as a media player, browser, etc., for implementing various application services. The collaborative etching compensation method based on multi-layer layout and CMP topography prediction provided in this embodiment of the invention can be included in the application program 3022.

[0078] The methods disclosed in the above embodiments of the present invention can be applied to processor 301, or implemented by processor 301. Processor 301 may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method can be completed by the integrated logic circuit of the hardware in processor 301 or by instructions in the form of software. The processor 301 may be a general-purpose processor, a digital signal processor (DSP), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. Processor 301 can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of the present invention. General-purpose processor 301 may be a microprocessor or any conventional processor, etc. The steps of the accessory optimization method provided in the embodiments of the present invention can be directly reflected as being executed by a hardware decoding processor, or being executed by a combination of hardware and software modules in the decoding processor. The software module may be located in a storage medium, which is located in memory. The processor reads the information in the memory and combines it with its hardware to complete the steps of the aforementioned method.

[0079] In an exemplary embodiment, the electronic terminal 300 may be used to execute the aforementioned method by one or more application-specific integrated circuits (ASICs), DSPs, programmable logic devices (PLDs), or complex programmable logic devices (CPLDs).

[0080] According to the method provided in the embodiments of this application, this application also provides a computer program product, which includes: computer program code, which, when run on a computer, causes the computer to execute the collaborative etching compensation method based on multi-layer layout and CMP topography prediction in any of the embodiments shown.

[0081] According to the method provided in the embodiments of this application, this application also provides a computer-readable storage medium storing program code, which, when run on a computer, causes the computer to execute the collaborative etching compensation method based on multi-layer layout and CMP topography prediction in any of the embodiments shown.

[0082] As used in this specification, the terms "component," "module," "system," etc., are used to refer to computer-related entities, hardware, firmware, combinations of hardware and software, software, or software in execution. For example, a component can be, but is not limited to, a process running on a processor, a processor, an object, an executable file, an execution thread, a program, and / or a computer. As illustrated, applications running on computing devices and computing devices can both be components. One or more components may reside in a process and / or an execution thread, and components may be located on a single computer and / or distributed among two or more computers. Furthermore, these components can be executed from various computer-readable media on which various data structures are stored. Components can communicate, for example, via local and / or remote processes based on signals having one or more data packets (e.g., data from two components interacting with another component between a local system, a distributed system, and / or a network, such as the Internet interacting with other systems via signals).

[0083] Those skilled in the art will recognize that the various illustrative logical blocks and steps described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this application.

[0084] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0085] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0086] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0087] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0088] In the above embodiments, the functions of each functional unit can be implemented entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially in the form of a computer program product. A computer program product includes one or more computer instructions (programs). When the computer program instructions (programs) are loaded and executed on a computer, all or part of the flow or function according to the embodiments of this application is generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. Computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available media can be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., high-density digital video discs, DVDs), or semiconductor media (e.g., solid-state disks, SSDs, etc.).

[0089] If a function is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0090] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

[0091] In summary, the collaborative etching compensation method, apparatus, medium, program product, and terminal based on multi-layer layout and CMP topography prediction provided in this application include: acquiring layout data of the current layer layout, the previous layer layout, and the next layer layout in a multi-layer layout; extracting features from the layout data of the multi-layer layout to obtain feature data of the multi-layer layout; performing computational fluid dynamics and mechanical wear simulation using a CMP process topography simulation model based on the feature data of the multi-layer layout to obtain three-dimensional contour height data of the wafer surface after CMP; inputting the three-dimensional contour height data of the wafer surface after CMP and the feature data of the multi-layer layout into a lithography imaging model and an etching process simulation model to iteratively optimize and compensate the mask pattern of the current layer layout to generate an optimized and compensated mask pattern of the current layer layout.

[0092] This application, by deeply integrating multi-layer layout information and CMP morphology prediction, comprehensively considers the process coupling effect between multi-layer layouts and the morphology changes caused by chemical mechanical polishing (CMP), and establishes an accurate simulation model to achieve collaborative optimization across process stages, significantly improving etching compensation accuracy. This application is applicable to advanced process technologies and can effectively solve the pattern distortion problem caused by inter-layer interactions and CMP morphology effects, significantly improving chip manufacturing precision and yield. Therefore, this application effectively overcomes the various shortcomings of existing technologies and has high industrial applicability.

[0093] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this application. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this application should still be covered by the claims of this application.

Claims

1. A collaborative etching compensation method based on multi-layer layout and CMP topography prediction, characterized in that, include: Retrieve layout data for the current layer, the previous layer, and the next layer in a multi-layer layout; Feature extraction is performed on the layout data of multi-layer layouts to obtain the feature data of multi-layer layouts; Based on the feature data of the multi-layer layout, the CMP process topography simulation model is used to perform computational fluid dynamics and mechanical wear simulation to obtain the three-dimensional contour height data of the wafer surface after CMP. The three-dimensional contour height data of the wafer surface after CMP and the feature data of the multi-layer layout are input into the lithography imaging model and the etching process simulation model. The mask pattern of the current layer layout is iteratively optimized and compensated to generate the optimized and compensated mask pattern of the current layer layout.

2. The collaborative etching compensation method based on multi-layer layout and CMP topography prediction according to claim 1, characterized in that, The process of extracting features from multi-layer layout data to obtain multi-layer layout feature data includes: Key features are identified in the layout data of multi-layer layouts to obtain the key feature identification results of each layer of the layout; Based on the key feature identification results of each layer of the layout, establish the inter-layer alignment mapping relationship, and extract the inter-layer feature data between multiple layers of the layout based on the inter-layer alignment mapping relationship; The key feature identification results of each layer of the map and the inter-layer feature data between the multiple layers of the map are used as the feature data of the multiple layers of the map.

3. The collaborative etching compensation method based on multi-layer layout and CMP topography prediction according to claim 2, characterized in that, The key feature identification results of each layer of the layout include: the initial line width and spacing of the graphics in the current layer, the graphic density distribution of the next layer, and the graphic density distribution of the overlapping area of ​​the projection of the previous layer onto the current layer.

4. The collaborative etching compensation method based on multi-layer layout and CMP topography prediction according to claim 1, characterized in that, The process of inputting the 3D contour height data of the wafer surface after CMP and the feature data of the multilayer layout into the lithography imaging model and the etching process simulation model, iteratively optimizing and compensating the mask pattern of the current layer layout, and generating the optimized and compensated mask pattern of the current layer layout includes: Based on the three-dimensional contour height data of the wafer surface after CMP and the photoresist thickness, a focal plane compensation function is established. During the photolithography simulation of the current layer layout in the photolithography imaging simulation model, dynamic focal plane compensation is performed according to the focal plane compensation function to obtain the compensated photolithography imaging simulation image. The compensated lithography imaging simulation image and the feature data of the next layer layout are input into the etching process simulation model to obtain the etching simulation layout of the current layer layout. Based on a preset optimization function, the error between the etch simulation layout of the current layer and the mask pattern of the current layer is calculated, and the error is used to perform iterative optimization and compensation operations to generate the optimized and compensated mask pattern of the current layer.

5. The collaborative etching compensation method based on multi-layer layout and CMP topography prediction according to claim 4, characterized in that, The formula for the focal plane compensation function is: ； in, Let be the coordinates of any position on the wafer surface. To compensate for the back focal plane, As the reference focal plane, The height of the CMP morphology at any location on the wafer surface. This refers to the thickness of the photoresist.

6. The collaborative etching compensation method based on multi-layer layout and CMP topography prediction according to claim 4, characterized in that, The preset optimization function includes: edge placement error.

7. A collaborative etching compensation device based on multi-layer layout and CMP topography prediction, characterized in that, include: The layout data acquisition module is used to acquire layout data of the current layer, the previous layer, and the next layer in a multi-layer layout. The feature extraction module is used to extract features from the layout data of multi-layer layouts to obtain feature data of multi-layer layouts. The CMP morphology simulation module is used to perform computational fluid dynamics and mechanical wear simulations based on the feature data of multi-layer layout using the CMP process morphology simulation model, and obtain the three-dimensional contour height data of the wafer surface after CMP. The optimization and compensation module is used to input the three-dimensional contour height data of the wafer surface after CMP and the feature data of the multi-layer layout into the lithography imaging model and the etching process simulation model, and to iteratively optimize and compensate the mask pattern of the current layer layout to generate the optimized and compensated mask pattern of the current layer layout.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the collaborative etching compensation method based on multi-layer layout and CMP topography prediction as described in any one of claims 1 to 6.

9. A computer program product, characterized in that, The computer program product includes computer program code, which, when run on a computer, causes the computer to implement the collaborative etching compensation method based on multi-layer layout and CMP topography prediction as described in any one of claims 1 to 6.

10. An electronic terminal, comprising a memory, a processor, and a computer program stored in the memory, characterized in that, The processor executes the computer program to implement the collaborative etching compensation method based on multi-layer layout and CMP topography prediction as described in any one of claims 1 to 6.

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