Communication method and communication device based on LDPC code

Abstract

A communication method and a communication apparatus in which a device may perform encoding or decoding based on an LDPC matrix, the LDPC matrix being determined based on an LDPC basis matrix, Zc, a, and b, a first region of the basis matrix including L types of elements, 2 < = L < = 2a * b, a and b not being 1 at the same time, Zc, a, and b being used to lift the elements in the first region to a (a * Zc) * (b * Zc) matrix, the matrix including (a * b) (Zc * Zc) matrices, each Zc * Zc matrix is an all-zero matrix or a cyclic shift matrix, the first sub-matrixes of the L elements are different, and the first sub-matrixes are matrixes formed by replacing the cyclic shift matrixes in (a * b) (Zc * Zc) matrixes of the matrix with the lifted corresponding elements with Zc * Zc unit matrixes. According to the method, the decoding performance of the LDPC code can be improved.

Description

Technical Field

[0001] This application relates to the field of coding, and more specifically, to a communication method and communication device based on LDPC codes. Background Technology

[0002] In the field of channel coding, low-density parity check (LDPC) codes are one of the most mature and widely used channel coding schemes. Quasi-cyclic low-density parity check (QC-LDPC) codes are a type of structured LDPC codes. Due to the unique structure of their parity check matrix, they can be encoded using simple feedback shift registers, reducing the coding complexity of LDPC codes.

[0003] Currently, the decoding threshold and decoding complexity of QC-LDPC codes are mainly determined by the base graph (BG) (i.e., the base matrix). Small-scale base matrices support relatively large limitations on the degree distribution of LDPC codes, and the decoding threshold cannot reach the optimal level. New radio (NR) LDPC suffers severe performance degradation at extremely high code rates. The degree distribution of LDPC codes is used to indicate the column redistribution of the parity check matrix. One possible implementation is to increase the decoding threshold by expanding the base matrix. However, large-scale base matrices have low parallelism and complex hardware implementation without good orthogonality. Summary of the Invention

[0004] The embodiments of this application provide a communication method and communication device based on LDPC codes, which helps to improve the decoding performance of LDPC codes.

[0005] In the first aspect, a communication method based on LDPC code is provided. This method can be executed by a transmitting device. Unless otherwise specified, the term "transmitting device" in this application can refer to the transmitting device itself (e.g., a network device, a terminal device), a component in the transmitting device (e.g., a processor, a chip, or a chip system), or a logic module or software that can implement all or part of the functions of the transmitting device.

[0006] The method includes: acquiring an information bit sequence; determining an LDPC matrix, wherein the LDPC matrix is ​​based on an LDPC basis matrix and a boost value Z. c The values ​​a and b are determined, where the first region of the basis matrix includes L types of elements, which include 0 elements and L-1 non-zero elements, where the L-1 non-zero elements are 1 to 2. a*b -1 contains L-1 distinct integers, where L is greater than or equal to 2 and less than or equal to 2.a*b The L elements are integers, where a and b are both positive integers and not both 1. The first region is part or all of the base matrix. The L first submatrices corresponding to the L elements are all different. The first submatrices of each element in the L elements include (a*b) (Zc*Zc) matrices. The Zc*Zc matrix is ​​either an all-zero matrix or an identity matrix. Zc, a, and b are used to promote each element in the first region to a (a*Zc)*(b*Zc) matrix. The (a*Zc)*(b*Zc) matrix is ​​determined based on the first submatrices corresponding to each element. The (a*Zc)*(b*Zc) matrix is ​​obtained by cyclically shifting the identity matrix in the first submatrices. Alternatively, the (a*Zc)*(b*Zc) matrix is ​​an all-zero matrix. The information bit sequence is encoded according to the LDPC matrix to obtain the codeword sequence. The codeword sequence is output.

[0007] It can be understood that if each of the (a*b) (Zc*Zc) matrices in the first submatrix of element #1 in the first region is a matrix of all zeros, then the promoted (a*Zc)*(b*Zc) matrix of element #1 is also a matrix of all zeros. If at least one of the (a*b) (Zc*Zc) matrices in the first submatrix corresponding to element #1 contains a Zc*Zc identity matrix, then the promoted (a*Zc)*(b*Zc) matrix of element #1 can be seen as a matrix obtained by keeping the Zc*Zc matrix of all zeros in the first submatrix unchanged and cyclically shifting the Zc*Zc identity matrix in the first submatrix.

[0008] For example, an LDPC matrix can be an LDPC parity-check matrix or an LDPC generator matrix. The LDPC parity-check matrix or generator matrix is ​​a matrix obtained by boosting the elements of all regions of the base matrix according to the corresponding boosting method. There is a one-to-one correspondence between the LDPC generator matrix and the LDPC parity-check matrix.

[0009] Based on the above technical solution, the improved LDPC matrix can support a wider degree distribution while maintaining orthogonality. In addition, it does not require expanding the size of the basis matrix while optimizing the decoding threshold, thereby reducing the complexity of hardware implementation.

[0010] Secondly, a communication method is provided, which can be executed by a receiving device. Unless otherwise specified, the term "receiving device" in this application can refer to the receiving device itself (e.g., a network device, a terminal device), a component in the receiving device (e.g., a processor, a chip, or a chip system), or a logic module or software that can implement all or part of the functions of the receiving device.

[0011] The method includes: obtaining a symbol sequence; determining an LDPC matrix, the LDPC matrix being based on an LDPC basis matrix and a boosting value Z.c The values ​​a and b are determined, where the first region of the basis matrix includes L types of elements, which include 0 elements and L-1 non-zero elements, where the L-1 non-zero elements are 1 to 2. a*b -1 contains L-1 distinct integers, where L is greater than or equal to 2 and less than or equal to 2. a*b The integers a and b are both positive integers and not both 1. The first region is part or all of the base matrix. The L first submatrices corresponding to the L elements are all different. The first submatrices of each of the L elements include (a*b) (Zc*Zc) matrices. The Zc*Zc matrix is ​​either an all-zero matrix or an identity matrix. Zc, a, and b are used to promote each element in the first region to a (a*Zc)*(b*Zc) matrix. The (a*Zc)*(b*Zc) matrix is ​​determined based on the first submatrices corresponding to each element. The (a*Zc)*(b*Zc) matrix is ​​obtained by cyclically shifting the identity matrix in the first submatrices. Alternatively, the (a*Zc)*(b*Zc) matrix is ​​an all-zero matrix. According to the LDPC matrix, the symbol sequence is decoded to obtain the information bit sequence.

[0012] For the beneficial effects of the second aspect, please refer to the description of the first aspect, which will not be repeated here.

[0013] In some implementations of the first or second aspect, determining the LDPC matrix includes: replacing each element in the first region with an a*b matrix, where any element in the a*b matrix is ​​either a 0 element or a 1 element, and the a*b matrices corresponding to the L types of elements are all different; replacing the 0 elements in the a*b matrix corresponding to each element with a Zc*Zc matrix of all 0s; and replacing the 1 elements in the a*b matrix with a Zc*Zc cyclic shift matrix to obtain the LDPC matrix.

[0014] The above technical solution presents a possible two-stage boosting method. First, each element in the first region is boosted to a matrix of row a and column b. Then, each element in the matrix of row a and column b is further boosted based on the boosting value Zc. Although this solution involves multiple stages of boosting, its hardware implementation is simple, its parallelism is high, and its computational complexity can be reduced.

[0015] In some implementations of the first or second aspect, determining the LDPC matrix includes: replacing each element in the first region with the (a*Zc)*(b*Zc) matrix corresponding to each element to obtain the LDPC matrix.

[0016] It is understandable that this lifting method yields the same result as the two lifting methods mentioned above, namely, the LDPC matrix obtained after lifting is the same. The difference lies in that lifting method one is an indirect lifting method, while lifting method two is a direct lifting method.

[0017] In some implementations of the first or second aspect, if the first region is a partial region of the base matrix, then the base matrix also includes a second region, which is the region remaining in the base matrix excluding the first region, and the elements in the second region are 0 elements or 1 elements. Determining the LDPC matrix includes: promoting the 0 elements in the second region to an all-zero matrix of Zc*Zc, and promoting the 1 elements in the second region to a cyclic shift matrix of Zc*Zc.

[0018] The above technical solution provides a possible specific way to improve the elements in the remaining region (i.e., the second region) of the base matrix when the first region is a partial region of the base matrix.

[0019] In some implementations of the first or second aspect, the first element corresponds to a*b translation values, the first element is a non-zero element in the first region, the a*b translation values ​​correspond one-to-one with the (a*b) (Zc*Zc) matrices of the first submatrix of the first element, wherein the translation value corresponding to the identity matrix of Zc*Zc in the (a*b) (Zc*Zc) matrices is a natural number, and the translation value corresponding to the all-zero matrix of Zc*Zc in the (a*b) (Zc*Zc) matrices is the first character, and the first character is not equal to a natural number.

[0020] In the above technical solution, the same number of translation values ​​can be configured for all non-zero elements in the first region. It is simple to implement, the hardware design is relatively uniform, the parallelism resources to be allocated are consistent, and there is no waste of parallelism.

[0021] For example, the a*b translation values ​​corresponding to the first element correspond one-to-one with the (a*b) (Zc*Zc) matrices of the first submatrix of the first element in the order of row first then column, or the a*b translation values ​​corresponding to the first element correspond one-to-one with the (a*b) (Zc*Zc) matrices of the first submatrix of the first element in the order of column first then row.

[0022] In some implementations of the first or second aspect, the first element corresponds to M translation values, the first element is a non-zero element in the first region, the M translation values ​​correspond one-to-one with the M Zc*Zc identity matrices in the first submatrix of the first element, wherein each of the M translation values ​​is a natural number, and M is greater than or equal to 1 and less than or equal to a*b.

[0023] In the above technical solution, different numbers of translation values ​​can be configured based on the type of non-zero elements in the first region, supporting flexible degree distribution and improving decoding performance.

[0024] For example, the M translation values ​​corresponding to the first element correspond one-to-one with the M Zc*Zc identity matrices in the first submatrix of the first element in the order of row first and column second, or the M translation values ​​corresponding to the first element correspond one-to-one with the M Zc*Zc identity matrices in the first submatrix of the first element in the order of column first and row second.

[0025] In some implementations of the first or second aspect, the first element corresponds to t translation values, the first element is a non-zero element in the first region, and the translation value corresponding to the (Zc*Zc) identity matrix in the (a*b) (Zc*Zc) matrices of the first submatrix of the first element is determined based on the t translation values ​​corresponding to the first element and the element type of the first element, where t is an integer greater than or equal to 0 and less than Q, and Q is the number of Zc*Zc identity matrices contained in the (a*b) (Zc*Zc) matrices of the first submatrix of the first element.

[0026] The above technical solution allows for flexible configuration of translation values ​​for the first element, is simple to implement in hardware, and has good decoding performance.

[0027] In some implementations of the first or second aspect, the basis matrix consists of five parts: part A, part B, part C, part D, and part E. The basis matrix comprises X rows and Y columns. Part A is the region consisting of rows 1 to x1 and columns 1 to y1 of the basis matrix; part B is the region consisting of rows 1 to x1 and columns y1+1 to y2 of the basis matrix, and the matrix corresponding to part B is a square matrix; part C is the region consisting of rows 1 to x1 and columns y2+1 to Y of the basis matrix, and the matrix corresponding to part C is a matrix of all zeros; part D is the region consisting of rows x1+1 to X and columns 1 to y2 of the basis matrix; and part E is the region consisting of rows x1+1 to X and columns y2+1 to Y of the basis matrix, and the matrix corresponding to part E is an identity matrix.

[0028] The characteristics of the regions formed by the rows and columns of the basis matrix have been described above. Below, based on these described characteristics, examples are given to illustrate the specific locations of the first and second regions. The first region uses the lifting method proposed in this application, and the second region uses the lifting method corresponding to the second region described above.

[0029] Example 1: The first region is the region consisting of rows 1 to X and columns 1 to y2 of the basis matrix (i.e., the A+B+D part of the basis matrix), and the second region is all the remaining regions of the basis matrix except for the first region (i.e., the C+E part of the basis matrix).

[0030] The advantage of this example is that part E supports hybrid automatic repeat request (HARQ) and has a lower triangular structure. The diagonal elements are always non-zero. Using the lifting method proposed in this application, the first lifting matrix corresponding to the diagonal elements is a matrix that is neither all zeros nor all ones, which will cause some additional complexity. Therefore, part E can be lifted based on the lifting method corresponding to the second region.

[0031] Example 2: The first region is the region consisting of rows 1 to x1 and columns 1 to y1 of the base matrix and the region consisting of rows x1+1 to X and columns 1 to y2 of the base matrix (i.e., part A+D). The second region is all the remaining regions in the base matrix except for the first region (i.e., part B+C+E of the base matrix).

[0032] The advantage of this example is that part B can have a more flexible coding structure, simple hardware coding, and optimized trap set in this region, while regions A+D can fully utilize the enhancement method proposed in this application.

[0033] Example 3: The first region is the region consisting of all rows of the base matrix and all columns of the base matrix except for at least one column from the y1+1 to y2 columns (i.e., the core check columns) and the y2+1 to Y columns (i.e., the extended check columns). The second region is all regions remaining in the base matrix except for the first region.

[0034] The advantage of this example is that it achieves easy coding with as few mixed structures as possible, resulting in high hardware utilization.

[0035] Optionally, at least one column from column y1+1 to y2 is all columns from column y1+1 to y2.

[0036] Optionally, at least one of the columns from y1+1 to y2 includes the first column, wherein the column weight of the first column in the region formed by rows 1 to x1 and columns y1+1 to y2 of the base matrix (i.e., part B of the base matrix) is an odd number greater than 1. It should be emphasized that the column weight of the first column in part B is the number of non-zero elements among all elements in the first column in part B.

[0037] In some implementations of the first or second aspect, the first region is the region consisting of rows 1 to X and columns 1 to y2 of the base matrix. The first region includes a second element, which is an element of type L other than the first and second elements. In this case, each Zc*Zc matrix in the first submatrix of the first element is an all-zero matrix, and each Zc*Zc matrix in the first submatrix of the second element is an identity matrix.

[0038] In some implementations of the first or second aspect, the first region corresponds to at least one punched column, and each element in the at least one punched column contains at least one second element. More specifically, at least one row in the region consisting of rows 1 to x1 of the base matrix and at least one fixed punched column includes a second element.

[0039] The advantage of the above design rule is that, since the structure of element x is compatible with the punched structure (LDPC cannot decode if each row contains 0 or more punched nodes), at least one element x is required when working at the code rate corresponding to the core array.

[0040] In some implementations of the first or second aspect, each line in part A contains at most one element x.

[0041] The advantages of this design rule are high hardware utilization, support for arbitrary row redistribution, and good decoding performance.

[0042] In some implementations of the first or second aspect, part A does not contain element x.

[0043] The advantage of this design rule is that it maximizes hardware utilization and simplifies the decoding architecture design.

[0044] In some implementations of the first or second aspect, the B part (which is an m*m matrix) contains at most m x's, and each row of the B part contains at most 2 x's.

[0045] The advantage of this design rule is that it can achieve easy coding properties with as few mixed structures as possible, resulting in high hardware utilization.

[0046] In some implementations of the first or second aspect, as the row number of the extended row increases (i.e., as the bit rate decreases), the number of elements x contained in the corresponding row in part D decreases.

[0047] The advantage of this design rule is that as the bitrate decreases, there is more design space for the degree distribution, thus resulting in higher hardware utilization.

[0048] In some implementations of the first or second aspect, the number of second elements contained in each row of part D is less than the threshold corresponding to each row. The threshold corresponding to each row is determined based on the first information corresponding to each row. The first information includes at least one of the following: the bitrate corresponding to each row, the row weight corresponding to each row in the base matrix, the row weight corresponding to each row when the base matrix does not include the punched column, and the connection structure between the second element contained in each row and the punched column of the base matrix.

[0049] In some implementations of the first or second aspect, all rows in part D correspond to S sets of rows, where each of the S sets of rows includes at least one row, at least one row is a row with consecutive row numbers, all rows in each set of rows contain the same number of second elements, and the larger the row number of the first row in the first set of the S sets of rows, the fewer the number of second elements contained in the rows in the first set of rows, the first row is the row with the smallest row number in the first set of rows, and S is an integer greater than 1.

[0050] The advantage of this design rule is that it provides a larger design space for degree distribution, resulting in higher hardware utilization.

[0051] In some implementations of the first or second aspect, L = 2, and the L elements include the first element and the second element, wherein each Zc*Zc matrix in the first submatrix of the first element is an all-zero matrix, and each Zc*Zc matrix in the first submatrix of the second element is an identity matrix.

[0052] Thirdly, a communication apparatus is provided for performing the method provided by any of the above aspects or their implementations. Specifically, the apparatus may include units and / or modules for performing the method provided by any of the above aspects or their implementations, such as processing units and / or transceiver units.

[0053] In one implementation, the device is either a transmitting device or a receiving device. When the device is a transmitting device or a receiving device, the transceiver unit can be a transceiver, an input / output interface, or a communication interface; the processing unit can be at least one processor. Optionally, the transceiver is a transceiver circuit. Optionally, the input / output interface is an input / output circuit.

[0054] In another implementation, the device is a chip, chip system, or circuit used in a transmitting or receiving device. When the device is a chip, chip system, or circuit used in a transmitting or receiving device, the transceiver unit can be an input / output interface, interface circuit, output circuit, input circuit, pin, or related circuit on the chip, chip system, or circuit; the processing unit can be at least one processor, processing circuit, or logic circuit.

[0055] Fourthly, a communication device is provided, comprising: a memory for storing a program; and at least one processor for executing the computer program or instructions stored in the memory to perform the method provided in any of the foregoing aspects or their implementations.

[0056] In one implementation, the device is either a transmitting device or a receiving device.

[0057] In another implementation, the device is a chip, chip system, or circuit used in a transmitting or receiving device.

[0058] Fifthly, a communication device is provided, comprising: at least one processor and a communication interface, wherein the at least one processor is configured to obtain a computer program or instructions stored in a memory via the communication interface to execute the method provided in any of the foregoing aspects or their implementations. The communication interface may be implemented in hardware or software.

[0059] In one implementation, the device further includes the memory.

[0060] Sixthly, a processor is provided for executing the methods provided in the above aspects.

[0061] Unless otherwise specified, or if it does not contradict its actual function or internal logic in the relevant description, the transmission and acquisition / reception operations involved in the processor can be understood as processor output and reception, input and other operations, or as transmission and reception operations performed by radio frequency circuits and antennas. This application does not limit them in this regard.

[0062] In a seventh aspect, a computer-readable storage medium is provided that stores program code for execution by a device, the program code including methods for performing any of the foregoing aspects or their implementations.

[0063] Eighthly, a computer program product containing instructions is provided, which, when run on a computer, causes the computer to perform the method provided in any of the foregoing aspects or their implementations.

[0064] Ninthly, a chip is provided, comprising a processor and a communication interface. The processor reads instructions stored in a memory through the communication interface and executes the methods provided in any of the above aspects or their implementations. The communication interface can be implemented in hardware or software.

[0065] Optionally, as one implementation, the chip also includes a memory that stores computer programs or instructions. The processor is used to execute the computer programs or instructions stored in the memory. When the computer programs or instructions are executed, the processor is used to perform the methods provided by any of the above aspects or their implementations.

[0066] When the method provided in this application is executed by a chip, this application does not limit the specific number of chips implementing the method. For example, it can be executed by one chip, or by two or more chips. Furthermore, when the number of chips implementing the method is two or more, the chip manufacturers are not limited; they can be from the same manufacturer or different manufacturers.

[0067] In a tenth aspect, a computer program is provided that, when run on a computer, causes the methods provided by any of the foregoing aspects or their implementations to be executed.

[0068] Eleventhly, a communication system is provided, including at least one of the transmitting end device or receiving end device described above. Attached Figure Description

[0069] Figure 1 This is a schematic diagram of a network architecture that can be applied to embodiments of this application.

[0070] Figure 2 This is a schematic diagram of the parity check matrix H of an LDPC.

[0071] Figure 3 This is a Tanner plot of the parity-check matrix H of an LDPC.

[0072] Figure 4 This is a schematic diagram of the structure of the parity check matrix.

[0073] Figure 5 This is a schematic diagram of the information transmission process.

[0074] Figure 6 This is a schematic flowchart of a communication method 600 based on LDPC code provided in this application.

[0075] Figures 7 to 9 This is a schematic diagram of the translation value acquisition method proposed in this application.

[0076] Figure 10 This is a schematic block diagram of the communication device 1000 provided in the embodiments of this application.

[0077] Figure 11 A schematic block diagram of a communication device 1100 provided in an embodiment of this application. Detailed Implementation

[0078] To facilitate understanding of the embodiments of this application, the following points will be explained before introducing the embodiments of this application.

[0079] The terms "for indicating" or "instruction" can include both direct and indirect indication, or they can be explicit and / or implicit. The various numerical designations such as "first," "second," etc., are merely for descriptive convenience and are not intended to limit the scope of the embodiments of this application, such as distinguishing different messages or different information. "Predefined" can be implemented by pre-storing corresponding codes, tables, or other methods that can be used to indicate relevant information in the device; this application does not limit the specific implementation method. The "protocol" involved can refer to standard protocols in the field of communication, such as the Long Term Evolution (LTE) protocol, the New Radio (NR) protocol, and related protocols applied to future communication systems; this application does not limit this. The words "exemplary," "for example," "exemplary," "as another example," etc., are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as an "example" in this application should not be construed as being more preferred or advantageous than other embodiments or designs. The terms "comprising," "including," "having," and variations thereof all mean "including but not limited to," unless otherwise specifically emphasized. "At least one" means one or more, while "more" means two or more. "At most one" means one or zero. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can mean: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, and c can mean: a, or, b, or, c, or, a and b, or, a and c, or, b and c, or, a, b, and c. Here, a, b, and c can be single or multiple. Descriptions relating to network element A sending messages, information, or data to network element B, and network element B receiving messages, information, or data from network element A, aim to specify which network element the message, information, or data is intended for, without specifying whether the transmission is direct or indirect via other network elements. Descriptions such as "when…", "in the case of…", "if", and "if" indicate that the device will take corresponding action under certain objective circumstances, not a time limit, nor requiring the device to perform a judgment action during implementation, nor implying any other limitations. Phrases such as "corresponding to…", "correspondingly", and equivalent expressions indicate a correspondence between the preceding and following elements, which may include indirect correspondence. For example, corresponding to a certain objective situation, the device will directly or indirectly take corresponding action, without requiring the corresponding action to immediately follow that objective situation.

[0080] Furthermore, the network architecture and business scenarios described in the embodiments of this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided in the embodiments of this application. As those skilled in the art will know, with the evolution of network architecture and the emergence of new business scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0081] The following describes a communication system to which embodiments of this application can be applied.

[0082] The embodiments of this application can be applied to various communication systems, including but not limited to: 5th generation (5G) systems, LTE systems, long term evolution-advanced (LTE-A) systems, LTE frequency division duplex (FDD) systems, LTE time division duplex (TDD) systems, etc. They can also be applied to future communication systems, such as 6th generation mobile communication systems. Furthermore, they can be applied to device-to-device (D2D) communication, vehicle-to-everything (V2X) communication, machine-to-machine (M2M) communication, machine-type communication (MTC), Internet of Things (IoT) communication systems, narrowband Internet of Things (NB-IoT) systems, or other communication systems. Furthermore, it can be extended to similar wireless communication systems, such as Wireless-Fidelity (WiFi), Worldwide Interoperability for Microwave Access (WIMAX), and communication systems related to the 3rd Generation Partnership Project (3GPP), without limitation.

[0083] The communication system applicable to embodiments of this application may include one or more transmitting devices and one or more receiving devices. Optionally, one of the transmitting device and the receiving device may be a terminal device, and the other may be a network device. Optionally, both the transmitting device and the receiving device may be terminal devices. Optionally, both the transmitting device and the receiving device may be network devices.

[0084] Figure 1 This is a schematic diagram of a network architecture applicable to embodiments of this application. For example... Figure 1 As shown, the embodiments of this application can be applied to both uplink and downlink data transmission. Figure 1 This document uses only uplink or downlink data transmission between one network device and two terminal devices (such as terminal device 1 and terminal device 2) as examples. In uplink data transmission, the sending device is the terminal device and the receiving device is the network device; conversely, in downlink data transmission, the sending device is the network device and the receiving device is the terminal device. Furthermore, the applicability of the embodiments of this application to other communication scenarios is not limited; for example, they can also be applied to sidelink communication.

[0085] The terminal equipment in this application can also be referred to as user equipment (UE), access terminal, user unit, user station, mobile station, mobile station, mobile terminal (MT), remote station, remote terminal, mobile device, user terminal, terminal, drone, wireless communication equipment, user agent, or user device, etc. The terminal equipment in the embodiments of this application can be a device that provides voice and / or data connectivity to a user, and can be used to connect people, objects, and machines, such as handheld devices with wireless connectivity, vehicle-mounted devices, etc. The terminal devices in the embodiments of this application may be mobile phones, tablets, laptops, handheld computers, mobile internet devices (MIDs), wearable devices, virtual reality (VR) devices, augmented reality (AR) devices, wireless terminals in industrial control, wireless terminals in self-driving, wireless terminals in remote medical surgery, wireless terminals in smart grids, wireless terminals in transportation safety, wireless terminals in smart cities, wireless terminals in smart homes, etc.

[0086] The network equipment in this application can be a device with wireless transceiver capabilities, which can be a device that provides wireless communication services. It is usually located on the network side, including but not limited to next-generation base stations (gNodeB, gNB) in 5G systems, base stations in sixth-generation mobile communication systems, base stations in future mobile communication systems, or access nodes in wireless fidelity (WiFi) systems, evolved node B (eNB), radio network controller (RNC), node B (NB), base station controller (BSC), home base station (e.g., home-evolved NodeB or home Node B, HNB), base band unit (BBU), transmission reception point (TRP), transmitting point (TP), base transceiver station (BTS), satellites, drones, etc. in long term evolution (LTE) systems. In a network architecture, network equipment may include centralized unit (CU) nodes, distributed unit (DU) nodes, RAN equipment including CU and DU nodes, RAN equipment including control plane CU nodes, user plane CU nodes, and DU nodes, or, in a cloud radio access network (CRAN) scenario, radio controllers, relay stations, vehicle-mounted equipment, and wearable devices. Furthermore, a base station may be a macro base station, micro base station, relay node, donor node, or a combination thereof. A base station may also refer to a communication module, modem, or chip installed within the aforementioned equipment or apparatus. A base station may also be a mobile switching center and equipment performing base station functions in D2D, V2X, and M2M communications, network-side equipment in 6G networks, and equipment performing base station functions in future communication systems. A base station can support networks with the same or different access technologies, without limitation.

[0087] Unless otherwise specified, the means for implementing the functions of a terminal device or network device in this application can refer to the terminal device or network device itself, or it can refer to a means that enables the terminal device or network device to implement the functions, such as a chip system or chip, specifically a system-on-a-chip (SoC) or a modem. This means can be installed in the terminal device or network device. In the embodiments of this application, the chip system can be composed of chips, or it can include chips and other discrete devices.

[0088] It should also be noted that some embodiments in this article use a 5G system as an example to introduce specific solution details. It is understood that when this solution is used in other communication systems, such as LTE systems, or future communication systems, the messages, channels, or information in the solution can be replaced with messages, channels, or information in other communication systems that can achieve the corresponding functions, and this application does not limit this.

[0089] Furthermore, the embodiments of this application can be applied to various application scenarios, such as high-throughput scenarios, high-reliability scenarios, low-latency scenarios, high-reliability low-latency scenarios, or low-power scenarios. Among them, high-throughput scenarios can be, for example, enhanced mobile broadband (eMBB) scenarios, high-reliability low-latency scenarios can be, for example, URLLC (ultrareliable low-latency communication) scenarios, and low-power scenarios can be, for example, M2M scenarios, MTC scenarios, or IoT scenarios.

[0090] To facilitate understanding of the embodiments of this application, several concepts or terms involved in the embodiments of this application are briefly described. The concepts or terms described below are based on the concepts or terms specified in the agreement, but do not mean that the embodiments of this application can only be applied to existing systems. The concepts or terms involved in the embodiments of this application can be applied to future systems. Furthermore, the specific names of the concepts or terms (e.g., concepts or terms involving functional descriptions) can be adjusted as the system develops in the future.

[0091] 1. LDPC code

[0092] LDPC codes are a type of linear block code. Linear block codes divide the information sequence to be encoded into groups of q bits each. The encoder then performs linear operations on these q information bits to obtain m parity bits. These q information bits are then combined with the m parity bits to obtain a codeword of length n = q + m. The mapping from q information bits to an n-bit codeword is typically represented by a parity check matrix H. Based on the parity check matrix H, a codeword sequence can be generated to complete the encoding process. After the codeword sequence is transmitted through the channel, the receiving equipment decodes the received signal to determine the original information bits.

[0093] The parity-check matrix H of an LDPC is a sparse matrix. The number of zero elements in the parity-check matrix H is far greater than the number of non-zero elements; in other words, the row weight (or column weight) of the parity-check matrix is ​​far less than the number of elements in each row (or column) of the LDPC matrix. Specifically, an LDPC code with an information bit sequence length of q and a code length of n can be uniquely determined by its parity-check matrix H.

[0094] Tanner represented the parity-check matrix H graphically in 1981; this type of graph is now called a Tanner graph. There is a one-to-one correspondence between Tanner graphs and parity-check matrices. A Tanner graph consists of two types of vertices: one type represents codeword bits and is called variable nodes; the other type consists of parity nodes, representing parity constraints. Each parity node represents a parity constraint. The following section will discuss this in conjunction with... Figure 2 and Figure 3 Please provide an explanation.

[0095] Figure 2 This is a schematic diagram of the parity check matrix H of an LDPC.

[0096] Figure 2 In the middle, {V i} represents the set of variable nodes (VN), {C i} represents the set of check nodes (CN). Each row of the check matrix H represents a check equation, and each check equation corresponds to a check node. Each column represents a codeword bit, and each codeword bit corresponds to a variable node. Figure 2 In the diagram, there are 8 variable nodes and 4 check nodes. If a codeword bit is included in the corresponding check equation, a line is used to connect the involved variable nodes and check nodes to obtain the Tanner diagram.

[0097] Figure 3 The Tanner plot of the parity-check matrix H of an LDPC.

[0098] like Figure 3As shown, the Tanner graph represents the parity-check matrix of the LDPC. For example, for a parity-check matrix H of size m rows and n columns, the Tanner graph contains two types of nodes: n variable nodes and m parity nodes. The n variable nodes correspond to the n columns of the parity-check matrix H, and the m parity nodes correspond to the m rows of the parity-check matrix H. A cycle in the Tanner graph consists of interconnected vertices. The cycle starts and ends at one vertex in this group of vertices and passes through each node only once. The length of a cycle is defined as the number of edges it contains, while the perimeter of the graph, also known as the circumference, is defined as the minimum cycle length in the graph. Figure 3 In the middle, the circumference is 4, such as Figure 3 The diagram shows the black lines connecting the variable nodes in the Tanner graph. Variable nodes in the Tanner graph correspond to each column of the parity-check matrix H, which is equivalent to each codeword bit in the LDPC. Parity nodes in the Tanner graph correspond to each row of the parity-check matrix H, which is equivalent to the parity bits in the LDPC. The connection between two types of nodes corresponds to the value of an element in the H matrix. If there is a connection between the i-th parity node and the j-th variable node, the element (i, j) in the H matrix has a value of 1; otherwise, the corresponding element is 0. The connection between a variable node and a parity node can also be called an edge. A connection between a parity node and a variable node can also be described as: there is a connection or an edge between the parity node and the variable node. The edge relationship between a parity node and a variable node can include either the presence of an edge or the absence of an edge. Furthermore, in the Tanner graph, a cycle is a closed loop formed by connecting variable nodes, parity nodes, and edges end-to-end.

[0099] 2. QC-LDPC code

[0100] QC-LDPC codes are a type of structured LDPC codes. Due to the unique structure of their parity-check matrix, encoding can be implemented using a simple feedback shift register, reducing the encoding complexity of LDPC codes. In practice, QC-LDPC codes are represented using a base graph (BG), where elements are either 0 or 1. Expanding the 1s and 0s in the BG yields a parity-check matrix H, which can be used for encoding or decoding. In the embodiments of this application, the BG can be written in matrix form, which can be referred to as the base matrix H in this application. BG Basis matrix H BGAn element of 0 indicates that there are no edges in the base graph, while a value of 1 indicates that there are edges in the base graph (or that the corresponding check is associated with the corresponding variable). NR LDPC codes involve multiple base graph selection; currently, the standard stores two base graphs, BG1 and BG2. BG2 is used when the information length is less than or equal to 292, or when the information length is less than or equal to 3824 and the code rate is less than or equal to 2 / 3, or when the code rate is less than or equal to 0.25; otherwise, BG1 is used. The expansion process of the base matrix is ​​described below.

[0101] Based on the basis matrix and the boosting value Z c (Lifting size) allows the basis matrix to be expanded into a complete parity-check matrix for encoding or decoding. In this application, Z... c It can also be called the expansion factor, lifting factor, expansion value, expansion coefficient, lifting size, etc. The expansion process involves lifting all elements in the basis matrix to a Z-shape. c ×Z c A square matrix, in which 0 is promoted to Z. c ×Z c The zero matrix is ​​promoted to an identity matrix, and then cyclically shifted based on the shifting value (SV) corresponding to the 1. This cyclic shift can be to the left or right, which is not limited in this application. It can be understood that each 1 in the base matrix corresponds to a shifting value. Taking a 4*4 identity matrix as an example, if the shifting values ​​are 0, 1, and 3, the cyclically shifted matrix after shifting to the right is as follows:

[0102] (1) When the translation value is 0 (i.e., remains unchanged), the corresponding cyclically shifted matrix is:

[0103] (2) When the translation value is 1, the corresponding cyclically shifted matrix is:

[0104] (3) When the translation value is 3, the corresponding cyclically shifted matrix is:

[0105] Alternatively, it can be understood that the complete parity check matrix H can be derived from an exponential matrix H. b H indicates b Each element in the array corresponds to a Z. c ×Z c The submatrix is ​​represented by an exponential matrix H, where each element indicates the number of times the corresponding submatrix has been cyclically shifted by the identity matrix. This significantly reduces the storage space required for the complete parity check matrix H. b The elements in it can also be called QC blocks.

[0106] For example, the exponent matrix H of the QC-LDPC code b As shown below:

[0107]

[0108] It can be seen that the exponent matrix H b The size is 4 rows and 24 columns, and the exponent matrix H b Each element i in the array represents a Z. c Square matrix of order Let represent a cyclic shift matrix, where i represents the cyclic shift value of the cyclic shift matrix, and i is an integer. Additionally, the exponent matrix H... b In this context, "-1" represents a zero matrix and "0" represents the identity matrix.

[0109] For example, As shown below:

[0110]

[0111] Optional, exponent matrix H b In addition to "-1", zero elements in the matrix can also be represented in other ways, such as using "-" or null values ​​to represent a matrix of all zeros.

[0112] It is understandable that the above exponent matrix H b The matrix corresponding to the positions greater than or equal to 0 that are changed to 1 and the positions of -1 that are changed to 0 is the base matrix. The 1s in the base matrix are then expanded into a cyclic shift matrix based on the corresponding elements of the exponent matrix, and the 0s are expanded into a 0 matrix of the corresponding size. After expansion, the parity check matrix is ​​obtained.

[0113] Next, the information bit sequence c can be encoded based on the parity-check matrix H to obtain a codeword sequence. The codeword sequence includes (N+2*Zc-K) parity bits w, where N is the length of the codeword sequence, K = Kb*Zc, Kb is the number of columns corresponding to the information column in the base map, and Zc is the boost value. For details on Zc, please refer to the explanation in Terminology 3. Specifically, the parity bits w are determined based on the information bit sequence c and the parity-check matrix H, where the parity bits are w = [w0, w1, w2, ..., w...]. N+2*Zc-K-1 ] T c = [c0, c1, c2, ..., c K-1 ] T The encoding process is solving equations The process of obtaining w.

[0114] 3. Increase value Z c (Lifting Size) and (Shifting Value)

[0115] The storage content of the 5G LDPC code regarding shift values ​​includes: (1) a list of lifting sizes; and (2) a list of shift values ​​that correspond one-to-one with the rows of the lifting size list.

[0116] For example, the list of Lifting Sizes is shown in Table 1.

[0117] Table 1

[0118]

[0119]

[0120] The j-th row of the Lifting Size list includes Where a j ∈{2,3,5,7,9,11,13,15}, max(k j )∈{7,7,6,5,5,5,4,4}; The row index of Lifting Size corresponds one-to-one with the column index of Shifting Value, that is, the lifting size in each row of the Lifting Size list corresponds to a set of Shifting Values.

[0121] For example, the list of Shifting Values ​​is shown in Table 2.

[0122] Table 2

[0123]

[0124] For a fixed lift index, a non-zero position in the base matrix corresponds to one translation value. For example, H... BG The shift value corresponding to row 0, column 0 when the promotion index is 0 is 211, H BG The shift value corresponding to the 6th column of the 1st row in the middle when the lifting index is 3 is 66, H BG The shift value corresponding to the second row and ninth column of the middle column when the lifting value index is 7 is 206.

[0125] It's understandable that LDPC encoding requires first determining the lift value, and then constructing a parity check matrix based on the corresponding shift value. For example, if the determined lift value is 40, and the lift value index corresponding to 40 in Table 1 is 2, then the parity check matrix can be constructed based on the shift value in the column corresponding to lift value index = 2 in Table 2.

[0126] 4. Column weight and row weight

[0127] For a column of a matrix, column weight refers to the number of non-zero elements contained in that column. For a row of a matrix, row weight refers to the number of non-zero elements contained in that row. For example, a matrix can be a basis matrix, a parity matrix, or a generator matrix.

[0128] 5. Structure of the basis matrix

[0129] Figure 4 This is a schematic diagram of the structure of the parity check matrix.

[0130] like Figure 4 As shown in (a), the parity-check matrix can include a high-rate region, an all-zero region, an incremental redundancy region, and a raptor-like region. The high-rate region can include... Figure 4 Parts A and B are shown in (b) above. Part A corresponds to information bits (or information digits, system bits, etc.), and part B is a square matrix corresponding to core parity bits (or core parity digits). The core parity can be the parity corresponding to the highest bit rate, or a parity where all degrees are greater than or equal to 2, or a parity node corresponding to the set of rows with the highest row weight (row weight significantly higher than other rows). A region of all zeros can correspond to... Figure 4 In (b) of the matrix, part C is an all-zero matrix. The incremental redundancy region can correspond to... Figure 4 Part D of (b) in the diagram. The Laptian-like region can correspond to... Figure 4 In (b), part E can be an identity matrix corresponding to the parity bits of the low-rate extension. Parts B and E are both parity parts. Part B is defined as the core parity region, and its features can be either a non-lower triangular encoded part (i.e., values ​​above the diagonal are not all 0) or an encoded part with column weights greater than 1. Part E is defined as the extended parity region, and its features can be either a lower triangular encoded part (i.e., values ​​above the diagonal are all 0) or a diagonal matrix.

[0131] Figure 4 The parity-check matrix of the LDPC code shown adopts a "raptor-like" structure, which can be gradually extended to low code rates from a high-rate core matrix. In practical use, such as... Figure 4 As shown in (a), the first X rows and first Y columns of the parity check matrix can be extracted. As the bitrate decreases, X and Y gradually increase, and the area of ​​the matrix used also gradually expands.

[0132] It should be noted that the parity check matrix can be represented by the LDPC basis matrix. Therefore, the structure of the LDPC basis matrix is ​​similar to that of the parity check matrix, and will not be described in detail here.

[0133] 6. Information column and validation column

[0134] The columns of the LDPC base matrix consist of information columns and check columns.

[0135] Information column: Corresponding to information bits (or information bits, system bits, etc.), it is the column corresponding to part A.

[0136] Check columns: Corresponding to check bits (or check digits, etc.), these are the columns corresponding to parts B and C, and can include core check columns and extended check columns. The core check columns are those corresponding to part B, while the extended check columns are those corresponding to parts C or E. Extended check columns can also be called raptor-like columns. Alternatively, the core check columns are the check columns in part B with a column weight greater than 1 (part B has 1 elements both above and below its diagonal), and the extended check columns are the remaining check columns excluding the core check columns.

[0137] 7. Core rows, core columns, and core matrix

[0138] Core rows: The core rows of the LDPC base matrix correspond to the core parity bits. In other words, the core rows are the rows corresponding to high bitrate regions, or the rows corresponding to parts A, B, or C.

[0139] Core columns: These can include all information columns and all core check columns. In other words, core columns are the columns corresponding to high bitrate areas, or the columns corresponding to part A plus part B.

[0140] The kernel matrix is ​​a matrix region consisting of all the kernel rows and columns of the LDPC base matrix. In other words, the kernel matrix is ​​the high-rate region of the LDPC base matrix, or the part composed of part A and part B.

[0141] 8. Message length, code length, and code rate

[0142] The information length is the length of the bit sequence of information to be sent (i.e., the number of bits contained therein). This length can be the length of the payload information bits, or the length of the payload information bits after adding cyclic redundancy check (CRC) bits. This application does not impose any specific restrictions.

[0143] Code length refers to the length of the bit sequence to be transmitted, which can be the transmitted bit sequence corresponding to the modulated symbol.

[0144] Code rate refers to the ratio of the length of the bit sequence of information to be transmitted to the code length.

[0145] Optionally, the above three values ​​can be pre-configured by higher-layer signaling, media access control (MAC) layer, or downlink physical layer signals, or they can be directly obtained and calculated by the transceiver. For example, the code length can be determined by the frame structure, number of layers, and modulation scheme of the encoded and transmitted information bit sequence; the code rate can be indicated in the above manner or given in the modulation and coding scheme (MCS).

[0146] 9. Information Transmission Process

[0147] Figure 5 This is a schematic diagram illustrating the information transmission process applicable to this application. For example... Figure 5 As shown, information is sent from the source, undergoes source coding, channel coding, modulation, air interface transmission, demodulation, channel decoding, and source recovery before reaching the destination, completing the transmission of information from the source to the destination. Among these processes, Figure 5 The upper-layer processing (including source coding, channel coding, and modulation) is performed at the transmitting end device, while the lower-layer processing (including demodulation, channel decoding, and source recovery) is performed at the receiving end device. The embodiments of this application mainly relate to... Figure 5 The diagram shows source coding, channel coding, channel decoding, and source recovery.

[0148] Based on the description in the background section, this application proposes a communication method based on LDPC codes, which can effectively solve the aforementioned technical problems. The method proposed in this application is described in detail below.

[0149] Figure 6 This is a schematic flowchart of a communication method 600 based on LDPC codes provided in this application. The method includes the following steps.

[0150] It is understood that method 600 can be executed by both the sending device and the receiving device. Unless otherwise specified, "sending device" or "receiving device" can refer to the sending device or receiving device itself, or it can refer to a device that enables the sending device or receiving device to implement this function. For ease of description, the following text will use "sending device" and "receiving device" to describe it. Among them, the sending device can be a terminal device or a network device, and the receiving device can be a terminal device or a network device.

[0151] S610, the transmitting device obtains the information bit sequence.

[0152] It is understandable that if the sending device needs to communicate with the receiving device, that is, if the sending device needs to send a signal to the receiving device, then the sending device needs to first obtain the information bit sequence corresponding to the signal to be sent to the receiving device.

[0153] The process of the transmitting device acquiring the information bit sequence can refer to: the transmitting device performing source encoding on the source symbols to generate the information bit sequence; or, the transmitting device acquiring the information bit sequence can also refer to: the transmitting device receiving the information bit sequence from other communication devices. This application does not limit the method of acquiring the information bit sequence.

[0154] S620, the transmitting device determines the LDPC matrix.

[0155] The LDPC matrix is ​​determined based on the LDPC basis matrix (hereinafter referred to as the basis matrix), the lifting value Zc, the value a, and the value b. The characteristics of each parameter used to determine the LDPC matrix are explained in detail below.

[0156] (1) Basis matrix

[0157] The first region of the basis matrix contains L distinct elements, which include 0 elements and L-1 distinct non-zero elements, where the L-1 non-zero elements are 1 to 2. a*b The set contains L-1 integers, where L is greater than or equal to 2 and less than or equal to 2. a*b The integers a and b are both positive integers and not both equal to 1.

[0158] For example, if a = 1 and b = 2, then the first region can include a maximum of 4 types of elements: 0, 1, 2, and 3. Here, 0 represents the zero element, and 1, 2, and 3 represent non-zero elements. Based on this example, let's illustrate with L types of elements. For example, the first region can include L = 2 types of elements. These two elements can be {0, 1}, {0, 2}, or {0, 3}. If the two elements are {0, 2}, it means the element in the first region is either 0 or 2. For example, the first region can include L = 3 types of elements. These three elements can be {0, 1, 2}, {0, 2, 3}, or {0, 1, 3}. If the three elements are {0, 1, 3}, it means the element in the first region is either 0, 1, or 3.

[0159] Optionally, the first region can be part or all of the base matrix.

[0160] For example, if the first region is a part of the basis matrix, the basis matrix also includes a second region. The second region can be the remaining region in the basis matrix excluding the first region, and the elements in the second region are either 0 or 1.

[0161] For example, if the first region is the entire region of the basis matrix, the positions of the non-zero elements in the basis matrix can be the same as the positions of the non-zero elements in BG1 or BG2 of NR.

[0162] For example, a table can be used to store all the rows of the base matrix and the columns associated with each row. If an associated column exists, the element at that position in the base matrix is ​​a non-zero element; otherwise, it is a zero element. For example, the base matrix can be stored as shown in the first two rows of Table 2.

[0163] (2) Lift value Zc, value a and value b

[0164] Zc, a, and b are used to promote each element in the first region to a (a*Zc)*(b*Zc) matrix (hereinafter referred to as the promoted (a*Zc)*(b*Zc) matrix). The (a*Zc)*(b*Zc) matrix is ​​determined based on the first submatrix corresponding to each element. The L first submatrices corresponding to the L types of elements in the first region are all different. The first submatrix of each type of element includes (a*b) (Zc*Zc) matrices. The Zc*Zc matrix is ​​either an all-zero matrix or an identity matrix. The (a*Zc)*(b*Zc) matrix is ​​obtained by cyclically shifting the identity matrix in the first submatrix, or the (a*Zc)*(b*Zc) matrix is ​​an all-zero matrix.

[0165] It is understood that the A*B matrix described in this application refers to a matrix with A rows and B columns.

[0166] The above description can also be replaced with "Zc, a, and b are used to promote each element in the first region to a (a*Zc)*(b*Zc) matrix. This promoted (a*Zc)*(b*Zc) matrix consists of (a*b) (Zc*Zc) matrices. One of these (a*b) (Zc*Zc) matrices is either a Zc*Zc matrix with all zeros or a Zc*Zc cyclic shift matrix (the row weight of all rows and the column weight of all columns of this cyclic shift matrix are both 1). The L types of first sub-matrices corresponding to the L types of elements are all different. The first sub-matrice for each type of element is a matrix formed by replacing the Zc*Zc cyclic shift matrix in the (a*b) (Zc*Zc) matrices of the promoted (a*Zc)*(b*Zc) matrix with a Zc*Zc identity matrix."

[0167] It can be understood that the first submatrix of each of the L elements is also a (a*Zc)*(b*Zc) matrix (hereinafter referred to as the (a*Zc)*(b*Zc) matrix of the first submatrix). This (a*Zc)*(b*Zc) matrix of the first submatrix also includes (a*b) (Zc*Zc) matrices, one of which is a Zc*Zc matrix that is either an all-zero Zc*Zc matrix or a Zc*Zc identity matrix.

[0168] It can also be understood that if each of the (a*b) (Zc*Zc) matrices in the first submatrix of element #1 in the first region is a matrix of all zeros, then the promoted (a*Zc)*(b*Zc) matrix of element #1 is also a matrix of all zeros. If at least one of the (a*b) (Zc*Zc) matrices in the first submatrix corresponding to element #1 contains a Zc*Zc identity matrix, then the promoted (a*Zc)*(b*Zc) matrix of element #1 can be seen as a matrix obtained by keeping the Zc*Zc matrix of all zeros in the first submatrix unchanged and cyclically shifting the Zc*Zc identity matrix in the first submatrix.

[0169] It can also be understood that the cyclic shift matrix of Zc*Zc is obtained by cyclically shifting the identity matrix of Zc*Zc based on the translation value. The method of obtaining the translation value will not be described in detail for now, but will be explained in detail later.

[0170] For example, the L types of elements include at least the first type and the second type of elements, where each Zc*Zc matrix in the first submatrix of the first type of elements is an all-zero matrix, and each Zc*Zc matrix in the first submatrix of the second type of elements is an identity matrix. Further, if L = 2, the two types of elements include both the first and second types of elements.

[0171] For example, if the first region is a partial region of the base matrix, the promotion method for the second region of the base matrix can be: promote the 0 elements in the second region to an all-zero matrix of Zc*Zc, and promote the 1 elements to a cyclic shift matrix of Zc*Zc.

[0172] It is understood that by improving the elements in the base matrix using the improvement method described above, the corresponding LDPC matrix can be obtained. In this application, the LDPC matrix can also be called the LDPC encoding matrix. For example, the LDPC matrix can be an LDPC parity-check matrix or an LDPC generator matrix. The LDPC parity-check matrix or the LDPC generator matrix is ​​a matrix obtained by improving the elements in all regions of the base matrix using the corresponding improvement method, and there is a one-to-one correspondence between the LDPC generator matrix and the LDPC parity-check matrix.

[0173] The following example illustrates the possible promotion methods for the first region. For ease of description, this example uses the first region as the basis matrix for all regions.

[0174] Improvement Method 1: Two-level improvement method.

[0175] In this lifting method, each element in the base matrix is ​​first lifted into an a*b submatrix to obtain the first lifting matrix. The elements in this a*b submatrix are either 0 or 1, and the a*b matrices corresponding to the L types of elements are all different. Then, each 1 element in the first lifting matrix is ​​lifted into a Zc*Zc cyclic shift matrix, and each 0 element is lifted into a Zc*Zc matrix of all 0s, thus obtaining the LDPC parity check matrix.

[0176] It can be understood that an a*b matrix contains a*b elements, each of which is either 0 or 1. Therefore, an a*b matrix can correspond to at most 2... a*b There are L distinct a*b matrices. Since the a*b matrices corresponding to the L elements are all different, the L elements are at most 2^L. a*b A type of element.

[0177] It can also be understood that the L elements described above include the 0 element and L-1 non-zero elements, where L-1 non-zero elements are 1 to 2. a *b The matrix contains L-1 integers. In one possible implementation, this application may not limit the range of values ​​for the L elements. For example, the L elements can be any L different values, as long as the number of element types in the base matrix does not exceed 2^L. a*b That's it. For example, if a = 1 and b = 2, then L can be equal to 3, with the three elements being -1, -2, and 0 respectively, and the a*b matrix after the promotion of the three elements is different for each of them.

[0178] In one possible implementation, the L types of promoted a*b matrices are all different. The value of each element can be converted into a binary sequence of length a*b. Then, the a*b matrix corresponding to the element is the matrix obtained by filling the a*b positions of the a*b matrix with the binary sequence of the element in sequence.

[0179] Optionally, the binary sequence of length a*b can be filled into the a*b positions of the a*b matrix in either row-first or column-first order. For example, a=2, b=3, and the binary sequence of length 6 corresponding to element #1 is 101100. The matrix obtained by filling in row-first order is shown in Table 3, and the matrix obtained by filling in column-first order is shown in Table 4.

[0180] Table 3

[0181] 1 0 1 1 0 0

[0182] Table 4

[0183] 1 1 0 0 1 0

[0184] The following example illustrates this. The basis matrix is ​​shown in Table 5, where a = 1 and b = 2. The basis matrix contains four types of elements: {0, 1, 2, 3}. The 1x2 submatrix of {0, 1, 2, 3} in the basis matrix after lifting is shown in Table 6.

[0185] Table 5

[0186] 1 2 0 1 1 0 3 0

[0187] Table 6

[0188]

[0189] First, each element in Table 5 is promoted to a 1*2 submatrix, and the first promoted matrix is ​​shown in Table 7. Then, each 0 element in Table 7 is promoted to a Zc*Zc matrix of all zeros, and each non-zero element is promoted to a Zc*Zc identity matrix. Then, based on the translation value corresponding to the non-zero element, the Zc*Zc identity matrix is ​​cyclically shifted to obtain the cyclic shift matrix corresponding to the non-zero element, thus obtaining... Figure 8 The LDPC parity-check matrix is ​​shown below. The method for obtaining the shift value corresponding to each non-zero element in the basis matrix will not be described in detail here, but will be explained in detail later.

[0190] Table 7

[0191] 1 1 1 0 0 0 1 1 1 1 0 0 0 1 0 0

[0192] Table 8

[0193]

[0194] Method 2: Direct improvement.

[0195] This boosting method can be understood as directly boosting each element of the base matrix to a (a*Zc)*(b*Zc) matrix (i.e., the boosted (a*Zc)*(b*Zc) matrix), thus obtaining the LDPC parity check matrix.

[0196] For example, in this method, a and b can be predefined or indicated, and each element can be promoted based on a and b to obtain the promoted (a*Zc)*(b*Zc) matrix. Alternatively, the pattern of the first submatrix corresponding to L elements can be directly defined, and each element can be promoted based on the first submatrix corresponding to each element to obtain the promoted (a*Zc)*(b*Zc) matrix.

[0197] It is understandable that the improvement results of both method one and method two are the same, that is, the LDPC parity-check matrices obtained after improvement are the same. The difference lies in that method one is an indirect improvement method, while method two is a direct improvement method.

[0198] The above describes in detail the possible lifting methods for the first region of the basis matrix. The following describes how to obtain the translation value corresponding to each non-zero element in the first region of the basis matrix.

[0199] In one possible implementation, the first element corresponds to a*b translation values. The first element is a non-zero element in the first region. The a*b translation values ​​correspond one-to-one with the (a*b) (Zc*Zc) matrices of the first submatrix of the first element. Among these, the translation value corresponding to the identity matrix of Zc*Zc in the (a*b) (Zc*Zc) matrices is a natural number, and the translation value corresponding to the all-zero matrix of Zc*Zc in the (a*b) (Zc*Zc) matrices is the first character, which is not equal to a natural number.

[0200] Based on the above-mentioned lifting method one, the a*b translation values ​​of the first element correspond one-to-one with the (a*b) (Zc*Zc) matrices of the first submatrix of the first element. It can also be understood that the a*b translation values ​​of the first element correspond one-to-one with the a*b elements in the a*b matrix of the first element (the first lifting matrix of the first element). If the translation value corresponding to the 0 element in the a*b matrix of the first element is the first character, and the translation value corresponding to the 1 element is a natural number.

[0201] For example, the first character can be -1. For example, a=1, b=3. Table 9 shows the translation values ​​of non-zero elements in the first region. Each non-zero element in the base matrix corresponds to 8 sets of translation values, and each set of translation values ​​includes 3 translation values.

[0202] Table 9

[0203]

[0204]

[0205] For example, the a*b shift values ​​of the first element can be matched one-to-one with the a*b elements in the first lifting matrix of the first element in a row-first-column order, or they can be matched one-to-one with the a*b elements in the first lifting matrix of the first element in a row-first-column order.

[0206] It can also be understood that in this implementation, the first lifting matrix (or first submatrix) corresponding to the first element can be determined based on the a*b translation values ​​of the first element. Since the first lifting matrices (or first submatrixes) of the L types of elements are different, this implementation does not need to store the value of each element in the first region. The type of each element can be implicitly indicated based on the a*b translation values ​​corresponding to each element.

[0207] In another possible implementation, the first element corresponds to M translation values. The first element is a non-zero element in the first region. The M translation values ​​correspond one-to-one with the M Zc*Zc identity matrices in the first submatrix of the first element. Each of the M translation values ​​is a natural number, and M is greater than or equal to 1 and less than or equal to a*b.

[0208] Based on the above lifting method one, the above M translation values ​​correspond one-to-one with the M Zc*Zc identity matrices in the first submatrix of the first element. It can also be understood that the M translation values ​​correspond one-to-one with the non-zero elements in the a*b elements of the first lifting matrix, that is, the number of non-zero elements in the first lifting matrix of the first element is M.

[0209] For example, the M shift values ​​of the first element can be matched one-to-one with the M non-zero elements in the first lifting matrix of the first element in a row-first-column order, or they can be matched one-to-one with the M non-zero elements in the first lifting matrix of the first element in a row-first-column order.

[0210] For example, Table 10 shows the translation values ​​of non-zero elements in the first region. Each non-zero element in the first region corresponds to 8 sets of translation values. Each set of translation values ​​for each element contains the same number of translation values, but the number of translation values ​​corresponding to different non-zero elements may be different.

[0211] Table 10

[0212]

[0213]

[0214] In another possible implementation, the first element corresponds to t translation values. The first element is a non-zero element in the first region. The translation value corresponding to the (Zc*Zc) identity matrix in the (a*b) (Zc*Zc) matrices of the first submatrix of the first element is determined based on the t translation values ​​corresponding to the first element and the element type of the first element. t is an integer greater than or equal to 0 and less than Q, where Q is the number of Zc*Zc identity matrices contained in the (a*b) (Zc*Zc) matrices of the first submatrix of the first element. For example, t = 0, 1, or 2.

[0215] Based on the above-mentioned lifting method one, the translation value corresponding to the identity matrix of (Zc*Zc) in the (a*b) (Zc*Zc) matrices of the first submatrix of the first element is determined based on the t translation values ​​corresponding to the first element and the element type of the first element. It can also be understood that the translation value corresponding to the non-zero element in the a*b elements of the first lifting matrix of the first element is determined based on the t translation values ​​corresponding to the first element and the element type of the first element, where t is an integer greater than or equal to 0 and less than Q, and Q can also be understood as the number of non-zero elements in the first lifting matrix of the first element.

[0216] For example, if t is greater than 0 and less than Q, give several possible ways to obtain the translation value corresponding to the first element.

[0217] Method 1: The translation value corresponding to the first element is determined based on the first rule and the second rule. The first rule is used to indicate the correspondence between the t translation values ​​of the first element and the non-zero elements in the first lifting matrix of the first element, which are determined based on the number of translation values ​​t. The second rule is used to generate the translation values ​​corresponding to the remaining non-zero elements in the first lifting matrix of the first element based on the t translation values.

[0218] like Figure 7 As shown, taking t=1, the first element is 1, and the first lifting matrix of the first element is a 1*3 matrix of all 1s as an example. The first element corresponds to one translation value SV1. Based on the number of translation values ​​of the first element, the first rule is used to determine SV1 as the translation value corresponding to the first non-zero element in the first lifting matrix of the first element. Then, based on SV1, the second rule is used to generate the translation values ​​SV2 and SV3 corresponding to the remaining two non-zero elements in the first lifting matrix of the first element.

[0219] Method 2: The translation value corresponding to the first element is determined by the third rule and the second rule. The third rule is used to indicate the correspondence between the t translation values ​​of the first element and the non-zero elements in the first lifting matrix of the first element, which are determined by the number of translation values ​​t and the element type of the first element. The second rule is used to generate the translation values ​​corresponding to the remaining non-zero elements in the first lifting matrix of the first element based on the t translation values.

[0220] like Figure 8 As shown, taking t=1, the first element being 1, and the first lifting matrix of the first element being a 1*3 matrix of all 1s as an example, the first element corresponds to one translation value SV1. Based on the number of translation values ​​and the element type of the first element, the third rule is used to determine SV1 as the translation value corresponding to the first non-zero element in the first lifting matrix of the first element. Then, based on SV1, the second rule is used to generate the translation values ​​SV2 and SV3 corresponding to the remaining two non-zero elements in the first lifting matrix of the first element.

[0221] Method 3: Determine the translation value corresponding to the first element based on the fourth rule, where the fourth rule is used to indicate the translation values ​​corresponding to all non-zero elements in the first lifting matrix of the first element generated based on t translation values.

[0222] like Figure 9 As shown, taking t=1, the first element is 1, and the first lifting matrix of the first element is a 1*3 matrix of all 1s as an example, the first element corresponds to one translation value SV. Based on the translation value SV, the fourth rule is used to determine the translation values ​​SV1, SV2, and SV3 corresponding to all non-zero elements in the first lifting matrix of the first element.

[0223] For example, in one possible implementation, if t = 0, a shift value SV for the first element is determined based on two sequences. All elements of the first sequence correspond one-to-one with all rows of the basis matrix, and all elements of the second sequence correspond one-to-one with all columns of the basis matrix. Further, an SV for the first element located at row i and column j of the basis matrix is ​​determined based on the element R(i) in the first sequence R corresponding to row i of the basis matrix, the element C(j) in the second sequence C corresponding to column j of the basis matrix, and Zc, for example, sV = mod(R(i) * C(j), Zc). Then, the shift value corresponding to the first element can be determined based on any of the methods described in methods one through three.

[0224] The method for obtaining the translation value of the first element has been described above. The following examples illustrate the possible range of regions corresponding to the first region. In one possible implementation, the first region is a partial region of the basis matrix. The basis matrix then includes the first region and the second region, and the union of the first and second regions represents all regions of the basis matrix. That is, each element in the basis matrix either resides in the first region or belongs to the second region. The first region uses the promotion method proposed in this application, and the second region uses the promotion method described above. Examples of the first and second regions are given below.

[0225] Before introducing the specific implementation method, we first describe the row and column characteristics of the basis matrix. As we know, the basis matrix consists of 5 parts. The LDPC matrix has 5 parts: A, B, C, D, and E. The total number of rows in the basis matrix is ​​X, and the total number of columns is Y. The regions formed by the partial rows and partial columns of the basis matrix have the following characteristics: Part A of the LDPC matrix is ​​the region composed of rows 1 to x1 and columns 1 to y1 of the LDPC matrix basis matrix; Part B of the LDPC matrix is ​​the region composed of rows 1 to x1 and columns y1+1 to y2 of the LDPC matrix basis matrix; ... The matrix corresponding to part B is a square matrix. Part C of the LDPC matrix is ​​the region consisting of rows 1 to x1 and columns y2+1 to Y of the LDPC matrix base matrix. The matrix corresponding to part C of the LDPC matrix is ​​a matrix of all zeros. Part D of the LDPC matrix is ​​the region consisting of rows x1+1 to X and columns 1 to y2 of the LDPC matrix base matrix. Part E of the LDPC matrix is ​​the region consisting of rows x1+1 to X and columns y2+1 to Y of the LDPC matrix base matrix. The matrix corresponding to part E of the LDPC matrix is ​​an identity matrix.

[0226] For example, rows 1 to x1 of the base matrix can be called core rows, columns 1 to y1+1 of the base matrix can be called information columns, columns y1+1 to y2 of the base matrix can be called core check columns, columns 1 to y2 of the base matrix can be called core columns, and columns y2+1 to Y can be called extended check columns. The following describes specific implementation methods for possible region division based on the above row and column characteristics.

[0227] Example 1: The first region is the region consisting of rows 1 to X and columns 1 to y2 of the basis matrix (i.e., the A+B+D part of the basis matrix), and the second region is all the remaining regions of the basis matrix except for the first region (i.e., the C+E part of the basis matrix).

[0228] The advantage of this example is that part E supports hybrid automatic repeat request (HARQ) and has a lower triangular structure. The diagonal elements are always non-zero. Using the lifting method proposed in this application, the first lifting matrix corresponding to the diagonal elements is a matrix that is neither all zeros nor all ones, which will cause some additional complexity. Therefore, part E can be lifted based on the lifting method corresponding to the second region.

[0229] Example 2: The first region is the region consisting of rows 1 to x1 and columns 1 to y1 of the base matrix and the region consisting of rows x1+1 to X and columns 1 to y2 of the base matrix (i.e., part A+D). The second region is all the remaining regions in the base matrix except for the first region (i.e., part B+C+E of the base matrix).

[0230] The advantage of this example is that part B can have a more flexible coding structure, simple hardware coding, and optimized trap set in this region, while regions A+D can fully utilize the enhancement method proposed in this application.

[0231] Example 3: The first region is the region consisting of all rows of the base matrix and all columns of the base matrix except for at least one column from the y1+1 to y2 columns (i.e., the core check columns) and the y2+1 to Y columns (i.e., the extended check columns). The second region is all regions remaining in the base matrix except for the first region.

[0232] The advantage of this example is that it achieves easy coding with as few mixed structures as possible, resulting in high hardware utilization.

[0233] Optionally, at least one column from column y1+1 to y2 is all columns from column y1+1 to y2.

[0234] Optionally, at least one of the columns from y1+1 to y2 includes the first column, wherein the column weight of the first column in the region formed by rows 1 to x1 and columns y1+1 to y2 of the base matrix (i.e., part B of the base matrix) is an odd number greater than 1. It should be emphasized that the column weight of the first column in part B is the number of non-zero elements among all elements in the first column in part B.

[0235] The above describes the regions where different promotion methods are used in the base matrix. The design rules for element x in the first region are described below.

[0236] In this context, element x is neither a first-type element nor a second-type element. In the first-type element, each Zc*Zc matrix in the first submatrix is ​​an all-zero matrix, and in the second-type element, each Zc*Zc matrix in the first submatrix is ​​an identity matrix. It can be understood that, based on promotion method one, the first promotion matrix corresponding to the first-type element is an a*b all-zero matrix, and the first promotion matrix corresponding to the second-type element is an a*b all-one matrix. For example, as shown in Table 6, the first-type element is 0, the second-type element is 1, and element x is 2 or 3.

[0237] For example, the design rules for element x in the first region are described here, taking the region consisting of parts A, B, and D of the base matrix as an example.

[0238] (1) When the core matrix (i.e. the A+B part of the base matrix) contains punched columns, the design rules for the elements x are as follows.

[0239] Optionally, the first region corresponds to at least one fixed punch column, and each element in the at least one fixed punch column contains at least one element x. More specifically, at least one row in the region consisting of rows 1 to x1 of the base matrix (i.e., the core row) and at least one fixed punch column contains element x.

[0240] The advantage of this design rule is that the structure of element x is compatible with punctured structures (LDPC cannot decode if each row contains 0 or more than 1 punctured nodes). Therefore, at least one element x is required when operating at the code rate corresponding to the core array. At the same time, element x gives LDPC design greater freedom; however, the structure of element x will lead to a waste of hardware resources. There is a balance between performance and hardware utilization.

[0241] (2) Design rules for element x in the core array when there is no punched column.

[0242] Optionally, each row in part A may contain at most one element x. The advantage of this design rule is that it offers high hardware utilization, supports arbitrary row redistribution, and provides good decoding performance.

[0243] Optionally, part A may not contain element x. The advantage of this design rule is that it maximizes hardware utilization and simplifies the decoding architecture design.

[0244] Optionally, part B (which is an m*m matrix) may contain at most m x's, and each row of part B may contain at most 2 x's. The advantage of this design rule is that it achieves easy coding with as few mixed structures as possible, resulting in high hardware utilization.

[0245] (3) Design rules for element x in the incremental redundancy region (i.e., the D part of the basis matrix).

[0246] In one implementation, within part D, the number of elements x in part D of a row decreases as the row number increases (i.e., as the bitrate decreases). The advantage of this design rule is that the degree distribution design space is larger as the bitrate decreases, thus resulting in higher hardware utilization.

[0247] For example, in region D, the number of elements x in each row is less than the threshold corresponding to each row. The threshold for each row is determined based on the first information corresponding to each row. The first information includes at least one of the following: the current bitrate of each row, the row weight of each row in the base matrix, the row weight of each row when the base matrix does not include punctured columns, and the connection structure of each row's elements x with the punctured columns of the base matrix. For example, the base matrix corresponds to two punctured columns, 1 and 2. The connection structure of each row has four possibilities: connected to both punctured columns 1 and 2, connected to one of punctured columns 1 and 2, or not connected to either punctured columns 1 or 2.

[0248] For example, there is a row number i′ in region D, where rows in region D with row numbers greater than i′ do not contain element x.

[0249] In another implementation, all rows in region D correspond to S row sets. Each of the S row sets includes at least one row, with the row numbers being consecutive. All rows in each row set contain the same number of elements x. Furthermore, the larger the row number of the first row in one of the S row sets, the fewer elements x are contained in the rows within that set. S is an integer greater than 1. Simply put, all rows in region D are divided into S segments, where the number of elements x corresponding to all rows in each segment is a fixed value, and the number of elements x in each segment decreases with each segment. The advantage of this design rule is that as the bitrate decreases, the degree distribution design space becomes larger, resulting in higher hardware utilization.

[0250] For example, in part D, there are row numbers i1, i2, and i3, where i1 < i2 < i3. All rows with row numbers less than i1 correspond to segment 1; all rows with row numbers greater than or equal to i1 and less than i2 correspond to segment 2; all rows with row numbers greater than or equal to i2 and less than i3 correspond to segment 3; and all rows with row numbers greater than or equal to i3 correspond to segment 4. Each segment contains the same number of elements x, and the number of elements x in each segment decreases with each segment. For example, segment 1 contains 3 elements x, segment 2 contains 2 elements x, segment 3 contains 1 element x, and segment 4 contains 0 elements x.

[0251] Optionally, the number of elements x in the extended region is less than that in the core array. The advantage of this design rule is that as the bitrate decreases, there is a larger design space for the degree distribution, resulting in higher hardware utilization compared to the high bitrate portion of part A.

[0252] S630: The transmitting device encodes the information bit sequence according to the LDPC matrix and outputs the codeword sequence.

[0253] For ease of description, this step is briefly explained using the LDPC parity check matrix H as an example. The information bit sequence c is encoded based on the LDPC parity check matrix H to obtain a codeword sequence, where the codeword sequence includes (N+2*Zc-K) parity bits w, where N is the length of the codeword sequence, K = Kb*Zc, and Kb is the number of columns corresponding to the information column in the base map. Specifically, the parity bits w are determined based on the information bit sequence c and the parity check matrix H, where the parity bits are w = [w0, w1, w2, ..., w...]. N+2*Zc-K-1 ] T c = [c0, c1, c2, ..., c K-1 ] T The encoding process is solving equations The process of obtaining w.

[0254] S640, the transmitting device determines the symbol sequence based on the codeword sequence.

[0255] It is understandable that a symbol sequence can be a rate-matched sequence or a modulated sequence. For example, the transmitting device performs rate matching on the codeword sequence, then modulates the rate-matched sequence to obtain a symbol sequence, and then maps the modulated symbol sequence onto physical resources for transmission.

[0256] S650, the transmitting device sends a symbol sequence to the receiving device. Correspondingly, the receiving device receives the symbol sequence from the transmitting device.

[0257] It is understandable that the symbol sequence #1 sent by the transmitting device and the symbol sequence #2 received by the receiving device may be different because channel noise signals may be introduced during the transmission of the symbol sequence.

[0258] In S660, the receiving device decodes the symbol sequence according to the LDPC matrix to obtain the information bit sequence.

[0259] The LDCP matrix used for decoding by the receiving device is the same as the LDPC matrix used for encoding by the transmitting device. The specific method by which the receiving device determines the LDPC matrix can be found in the description on the transmitting device side, and will not be detailed here.

[0260] It is understood that the steps in the above figures are merely illustrative and are not intended to be strictly limited. Furthermore, the sequence numbers of the processes described above do not imply a specific order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0261] It is also understood that some optional features in the various embodiments of this application may not depend on other features in some scenarios, or may be combined with other features in some scenarios, without limitation.

[0262] It is also understood that, in the above-described method embodiments, the methods and operations implemented by the device (transmitting device or receiving device) can also be implemented by components of the device (such as chips or circuits), without limitation.

[0263] The above text combined Figures 1 to 9 The present application provides a detailed description of the method embodiments, which will be discussed below in conjunction with... Figure 10 and Figure 11 This describes an embodiment of the apparatus described in this application. It is understood that, in order to achieve the functions described in the above embodiments, Figure 10 and Figure 11The apparatus includes hardware structures and / or software modules corresponding to perform various functions. Those skilled in the art will readily recognize that, based on the units and method steps described in conjunction with the embodiments disclosed in this application, this application can be implemented in hardware or a combination of hardware and computer software. It is understood that the technical features described in the above method embodiments are also applicable to the following apparatus embodiments.

[0264] Figure 10 and Figure 11 The diagram illustrates the possible structures of apparatuses provided for embodiments of this application. These apparatuses can be used to implement the functions of the transmitting or receiving devices in the above method embodiments, and thus also achieve the beneficial effects of the above method embodiments.

[0265] Figure 10 This is a schematic block diagram of the communication device 1000 provided in an embodiment of this application. Figure 10 As shown, the device 1000 may include a communication unit 1010 and a processing unit 1020. The communication unit 1010 can communicate with the outside world, and the processing unit 1020 is used for data processing. The communication unit 1010 may also be referred to as a communication interface or a transceiver unit.

[0266] In one possible design, the device 1000 can implement the steps or processes corresponding to those performed by the transmitting device in the above method embodiments, wherein the processing unit 1020 is used to perform processing-related operations of the transmitting device in the above method embodiments, and the communication unit 1010 is used to perform transmission-related operations of the transmitting device in the above method embodiments.

[0267] In another possible design, the device 1000 can implement the steps or processes corresponding to those performed by the receiving device in the above method embodiments, wherein the communication unit 1010 is used to perform the receiving-related operations of the receiving device in the above method embodiments, and the processing unit 1020 is used to perform the processing-related operations of the receiving device in the above method embodiments.

[0268] It is understood that the device 1000 here is embodied in the form of a functional unit. The term "unit" here can refer to an application-specific integrated circuit (ASIC), electronic circuitry, a processor (e.g., a shared processor, a proprietary processor, or a group processor, etc.) and memory for executing one or more software or firmware programs, integrated logic circuitry, and / or other suitable components supporting the described functions. In an alternative example, those skilled in the art will understand that the device 1000 may specifically be the transmitting end device in the above embodiments, used to execute the various processes and / or steps corresponding to the transmitting end device in the above method embodiments; or, the device 1000 may specifically be the receiving end device in the above embodiments, used to execute the various processes and / or steps corresponding to the receiving end device in the above method embodiments. To avoid repetition, further details are omitted here.

[0269] The apparatus 1000 of each of the above-described schemes has the function of implementing the corresponding steps performed by the transmitting device in the above-described method, or the apparatus 1000 of each of the above-described schemes has the function of implementing the corresponding steps performed by the receiving device in the above-described method. The function can be implemented by hardware or by hardware executing corresponding software. The hardware or software includes one or more modules corresponding to the above functions; for example, the communication unit can be replaced by a transceiver (e.g., the transmitting unit in the communication unit can be replaced by a transmitter, and the receiving unit in the communication unit can be replaced by a receiver), and other units, such as processing units, can be replaced by a processor, respectively executing the transmission and reception operations and related processing operations in each method embodiment.

[0270] Furthermore, the aforementioned communication unit can also be a transceiver circuit (e.g., it may include a receiving circuit and a transmitting circuit), and the processing unit can be a processing circuit. In embodiments of this application, Figure 10 The device mentioned can be the receiving or transmitting device in the foregoing embodiments, or it can be a chip or a chip system, such as a system on a chip (SoC). The communication unit can be an input / output circuit or a communication interface; the processing unit is a processor, microprocessor, or integrated circuit integrated on the chip. No limitations are imposed here.

[0271] Figure 11 This is a schematic block diagram of a communication device 1100 provided in an embodiment of this application. The device 1100 includes a processor 1110 and a transceiver 1120. The processor 1110 and the transceiver 1120 communicate with each other through an internal connection path. The processor 1110 is used to execute instructions to control the transceiver 1120 to transmit and / or receive signals.

[0272] Optionally, the device 1100 may further include a memory 1130, which communicates with the processor 1110 and the transceiver 1120 via an internal connection path. The memory 1130 stores instructions, and the processor 1110 can execute the instructions stored in the memory 1130. In one possible implementation, the device 1100 is used to implement the various processes and steps corresponding to the transmitting device in the above method embodiments. In another possible implementation, the device 1100 is used to implement the various processes and steps corresponding to the receiving device in the above method embodiments.

[0273] Optionally, the memory 1130 may be integrated into the processor 1110.

[0274] In one possible scenario, device 1100 includes at least one processor with integrated memory, and other memory besides the memory integrated on the processor.

[0275] It is understood that the device 1100 can specifically be the transmitting or receiving device in the above embodiments, or it can be a chip or a chip system. Correspondingly, the transceiver 1120 can be the transceiver circuit of the chip, which is not limited here. Specifically, the device 1100 can be used to execute the various steps and / or processes corresponding to the transmitting or receiving device in the above method embodiments.

[0276] Optionally, the memory 1130 may include read-only memory and random access memory, and provide instructions and data to the processor. The memory may include non-volatile random access memory. For example, the memory may also store device type information. The processor 1110 may be used to execute instructions stored in the memory, and when the processor 1110 executes instructions stored in the memory, the processor 1110 is used to perform the various steps and / or processes of the method embodiments corresponding to the transmitting or receiving devices described above.

[0277] In implementation, each step of the above method can be completed by integrated logic circuits in the processor's hardware or by instructions in software. The steps of the method disclosed in the embodiments of this application can be directly implemented by a hardware processor, or by a combination of hardware and software modules in the processor. The software modules can reside in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. This storage medium is located in memory, and the processor reads information from the memory and, in conjunction with its hardware, completes the steps of the above method. To avoid repetition, detailed descriptions are omitted here.

[0278] It should be noted that the processor in the embodiments of this application can be an integrated circuit chip with signal processing capabilities. During implementation, each step of the above method embodiments can be completed by the integrated logic circuitry in the processor's hardware or by instructions in software form. The processor can be a general-purpose processor, digital signal processing (DSP), ASIC, field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. The processor in the embodiments of this application can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this application. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this application can be directly embodied as being executed by a hardware decoding processor, or executed by a combination of hardware and software modules in the decoding processor. The software modules can be located in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. This storage medium is located in memory; the processor reads information from the memory and, in conjunction with its hardware, completes the steps of the above methods.

[0279] It is understood that the memory in the embodiments of this application can be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. The non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory can be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous linked dynamic random access memory (SLDRAM), and direct rambus RAM (DR RAM). It should be noted that the memory used in the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0280] Optionally, the memory (e.g., 1130) in this embodiment may be integrated into the processor (e.g., 1110).

[0281] In addition, this application also provides a computer-readable storage medium storing computer instructions, which, when executed on a computer, cause the operations and / or processes performed by the sending or receiving device in the various method embodiments of this application to be executed.

[0282] This application also provides a computer program product, which includes computer program code or instructions. When the computer program code or instructions are run on a computer, the operations and / or processes performed by the sending end device or the receiving end device in the various method embodiments of this application are executed.

[0283] Furthermore, this application also provides a chip including a processor. A memory for storing a computer program is provided independently of the chip, and the processor is used to execute the computer program stored in the memory, such that operations and / or processes performed by a transmitting or receiving device in any method embodiment are performed.

[0284] Furthermore, the chip may also include a communication interface. The communication interface may be an input / output interface or an interface circuit, etc. Furthermore, the chip may also include a memory.

[0285] In addition, this application also provides a communication system, including the transmitting end device and the receiving end device in the embodiments of this application.

[0286] It should also be noted that the memory described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0287] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here. In the several embodiments provided in this application, it should be understood that the disclosed systems, devices, and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative; for example, the division of units is merely a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the displayed or discussed mutual coupling or direct coupling or communication connection may be through some interfaces; the indirect coupling or communication connection of devices or units may be electrical, mechanical, or other forms. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs. Furthermore, the functional units in the various embodiments of this application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0288] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, ROM, RAM, magnetic disks, or optical disks.

[0289] It is understood that the term "embodiment" used throughout the specification means that a specific feature, structure, or characteristic related to an embodiment is included in at least one embodiment of this application. Therefore, various embodiments throughout the specification do not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments.

[0290] It can also be understood that in this application, "when," "if," and "if" all refer to the network element making corresponding processing under certain objective circumstances, and are not time-limited, nor do they require the network element to make a judgment when it is implemented, nor do they mean that there are other limitations.

[0291] It can also be understood that in the various embodiments of this application, "B corresponding to A" means that B is associated with A, and B can be determined based on A. However, it can also be understood that determining B based on A does not mean that B is determined solely based on A; B can also be determined based on A and / or other information.

Claims

1. A communication method based on low-density parity-check (LDPC) codes, characterized in that, The method includes: Obtain the information bit sequence; Determine the LDPC matrix, which is based on the LDPC basis matrix and the lifting value Z. c The values ​​a and b are determined, where, The first region of the basis matrix includes L types of elements, which include 0 elements and L-1 non-zero elements, where the L-1 non-zero elements are 1 to 2. a*b L-1 distinct integers in -1, where L is greater than or equal to 2 and less than or equal to 2. a*b The integers, where a and b are both positive integers and not both 1, and the first region is part or all of the base matrix. The L types of elements each have L distinct first submatrices. The first submatrix for each of the L types of elements comprises (a*b) (Zc*Zc) matrices, where each Zc*Zc matrix is ​​either an all-zero matrix or an identity matrix. Zc, a, and b are used to promote each element in the first region to a (a*Zc)*(b*Zc) matrix, wherein the (a*Zc)*(b*Zc) matrix is ​​determined based on the first submatrix corresponding to each element, and the (a*Zc)*(b*Zc) matrix is ​​obtained by cyclically shifting the identity matrix in the first submatrix, or the (a*Zc)*(b*Zc) matrix is ​​an all-zero matrix; The information bit sequence is encoded according to the LDPC matrix to obtain a codeword sequence; Output the codeword sequence.

2. A communication method based on low-density parity-check (LDPC) codes, characterized in that, Obtain the symbol sequence; Determine the LDPC matrix, which is based on the LDPC basis matrix and the lifting value Z. c The values ​​a and b are determined, where, The first region of the basis matrix includes L types of elements, which include 0 elements and L-1 non-zero elements, where the L-1 non-zero elements are 1 to 2. a*b L-1 distinct integers in -1, where L is greater than or equal to 2 and less than or equal to 2. a*b The integers, where a and b are both positive integers and not both 1, and the first region is part or all of the base matrix. The L types of elements each have L distinct first submatrices. The first submatrix for each of the L types of elements comprises (a*b) (Zc*Zc) matrices, where each Zc*Zc matrix is ​​either an all-zero matrix or an identity matrix. Zc, a, and b are used to promote each element in the first region to a (a*Zc)*(b*Zc) matrix, wherein the (a*Zc)*(b*Zc) matrix is ​​determined based on the first submatrix corresponding to each element, and the (a*Zc)*(b*Zc) matrix is ​​obtained by cyclically shifting the identity matrix in the first submatrix, or the (a*Zc)*(b*Zc) matrix is ​​an all-zero matrix; The symbol sequence is decoded based on the LDPC matrix to obtain the information bit sequence.

3. The method according to claim 1 or 2, characterized in that, The determination of the LDPC matrix includes: Each element in the first region is replaced with an a*b matrix, where any element in the a*b matrix is ​​either 0 or 1, and the a*b matrices corresponding to the L types of elements are all different. The LDPC matrix is ​​obtained by replacing the 0 elements in the a*b matrix corresponding to each element with an all-zero matrix of Zc*Zc, and by replacing the 1 elements in the a*b matrix with a cyclic shift matrix of Zc*Zc.

4. The method according to claim 1 or 2, characterized in that, The determination of the LDPC matrix includes: Replace each element in the first region with the (a*Zc)*(b*Zc) matrix corresponding to each element to obtain the LDPC matrix.

5. The method according to any one of claims 1 to 4, characterized in that, If the first region is a portion of the base matrix, then the base matrix further includes a second region, which is the remaining region of the base matrix excluding the first region. The elements in the second region are either 0 or 1. The determination of the LDPC matrix includes: The zero elements in the second region are promoted to an all-zero matrix Zc*Zc, and the one elements in the second region are promoted to a cyclic shift matrix Zc*Zc.

6. The method according to any one of claims 1 to 5, characterized in that, The first element corresponds to a*b translation values, where the first element is a non-zero element in the first region. The a*b translation values ​​correspond one-to-one with the (a*b) (Zc*Zc) matrices of the first submatrix of the first element. The translation value corresponding to the identity matrix of the Zc*Zc matrix in the (a*b) (Zc*Zc) matrices is a natural number, and the translation value corresponding to the all-zero matrix of the Zc*Zc matrix in the (a*b) (Zc*Zc) matrices is the first character, which is not equal to a natural number.

7. The method according to claim 6, characterized in that, The a*b translation values ​​corresponding to the first element correspond one-to-one with the (a*b) (Zc*Zc) matrices of the first submatrix of the first element in a row-first-column-second order. or, The a*b translation values ​​corresponding to the first element correspond one-to-one with the (a*b) (Zc*Zc) matrices of the first submatrix of the first element in the order of column first and then row.

8. The method according to any one of claims 1 to 5, characterized in that, The first element corresponds to M translation values. The first element is a non-zero element in the first region. The M translation values ​​correspond one-to-one with the M Zc*Zc identity matrices in the first submatrix of the first element. Each of the M translation values ​​is a natural number, and M is greater than or equal to 1 and less than or equal to a*b.

9. The method according to claim 8, characterized in that, The M translation values ​​corresponding to the first element correspond one-to-one with the M Zc*Zc identity matrices in the first submatrix of the first element, in a row-first, column-second order. or, The M translation values ​​corresponding to the first element correspond one-to-one with the M Zc*Zc identity matrices in the first submatrix of the first element, in the order of column first and then row.

10. The method according to any one of claims 1 to 5, characterized in that, The first element corresponds to t translation values. The first element is a non-zero element in the first region. The translation value corresponding to the (Zc*Zc) identity matrix in the (a*b) (Zc*Zc) matrices of the first sub-matrix of the first element is determined based on the t translation values ​​corresponding to the first element and the element type of the first element. The t is an integer greater than or equal to 0 and less than Q. The Q is the number of Zc*Zc identity matrices contained in the (a*b) (Zc*Zc) matrices of the first sub-matrix of the first element.

11. The method according to any one of claims 1 to 10, characterized in that, The basis matrix comprises X rows and Y columns. The first region is the region consisting of rows 1 to x and columns 1 to y2 of the base matrix. or, The first region is the region consisting of rows 1 to x1 and columns 1 to y1 of the base matrix, and the region consisting of rows x1+1 to x and columns 1 to y2 of the base matrix. or, The first region is the region consisting of all rows of the base matrix and all columns of the base matrix except for at least one column from column y1+1 to y2 and the remaining columns from column y2+1 to Y. Where 1 < x1 < X, 1 < y1 < y2 < Y, and x1, X, y1, y2, and Y are all integers.

12. The method according to claim 11, characterized in that, At least one of the columns y1+1 to y2 includes a first column, wherein the column weight of the first column in the region formed by the first to x1 rows and the y1+1 to y2 columns of the base matrix is ​​an odd number greater than 1.

13. The method according to any one of claims 1 to 12, characterized in that, The basis matrix consists of five parts: A, B, C, D, and E. The basis matrix comprises X rows and Y columns. Part A is the region consisting of rows 1 to x1 and columns 1 to y1 of the base matrix. Part B is the region consisting of rows 1 to x1 and columns y1+1 to y2 of the base matrix, and the matrix corresponding to Part B is a square matrix. The C portion is the region consisting of rows 1 to x1 and columns y2+1 to Y of the base matrix, and the matrix corresponding to the C portion is a matrix consisting entirely of zeros. The D portion is the region consisting of rows x1+1 to x and columns 1 to y2 of the base matrix. The E portion is the region consisting of rows x1+1 to X and columns y2+1 to Y of the base matrix, and the matrix corresponding to the E portion is the identity matrix.

14. The method according to claim 13, characterized in that, The first region is the region consisting of rows 1 to X and columns 1 to y2 of the base matrix. The first region includes a second element, which is an element of other types besides the first and second types of elements among the L types of elements. In the first submatrix of the first type of element, each Zc*Zc matrix is ​​an all-zero matrix, and each Zc*Zc matrix of the first submatrix of the second type of element is an identity matrix.

15. The method according to claim 14, characterized in that, The first region corresponds to at least one punch column, and each punch column contains at least one of the second elements.

16. The method according to claim 15, characterized in that, At least one row in the region consisting of the first to x1 rows of the base matrix and the at least one fixed punch column includes the second element.

17. The method according to claim 14, characterized in that, There are no punched columns in the first area. Each row in section A contains at most one of the second elements. or, The second element is not included in part A.

18. The method according to any one of claims 14 to 17, characterized in that, In section D, the larger the row number, the fewer the number of the second element contained in the corresponding row.

19. The method according to claim 18, characterized in that, The number of the second elements contained in each row of the D part is less than the threshold corresponding to each row. The threshold corresponding to each row is determined based on the first information corresponding to each row. The first information includes at least one of the following: the bitrate corresponding to each row, the row weight corresponding to each row in the base matrix, the row weight corresponding to each row when the base matrix does not include the punched column, and the connection structure between the second element contained in each row and the punched column of the base matrix.

20. The method according to any one of claims 14 to 17, characterized in that, In the D part, all rows correspond to S row sets, wherein each of the S row sets includes at least one row, the at least one row is a row with consecutive row numbers, all rows in each row set contain the same number of the second element, and the larger the row number of the first row in the first row set of the S row sets, the fewer the number of the second element contained in the rows in the first row set, the first row is the row with the smallest row number in the first row set, and S is an integer greater than 1.

21. The method according to any one of claims 1 to 20, characterized in that, The L = 2, and the L elements include a first type of element and a second type of element, wherein each Zc*Zc matrix in the first submatrix of the first type of element is an all-zero matrix, and each Zc*Zc matrix in the first submatrix of the second type of element is an identity matrix.

22. A communication device, characterized in that, The device includes at least one processor and an interface circuit, the interface circuit being configured to receive signals from other communication devices besides the communication device and transmit them to the processor, or to send signals from the processor to other communication devices besides the communication device, the processor causing the method as described in any one of claims 1 to 23 to be implemented via logic circuits or executing code instructions.

23. The communication device according to claim 22, characterized in that, The communication device is a chip or chip system.

24. A computer-readable storage medium, characterized in that, The storage medium stores a computer program or instructions that, when executed, cause the method as described in any one of claims 1 to 21 to be implemented.

25. A computer program product, characterized in that, Includes a computer program that, when run, causes the method as described in any one of claims 1 to 21 to be implemented.

26. A communication system, characterized in that, include: A transmitting device for performing the method as described in any one of claims 1, 3 to 21; A receiving device for performing the method as described in any one of claims 2 to 21.

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