Method for improving bending resistance of flexible circuit board

Abstract

The invention belongs to the technical field of electronic packaging and printed circuit boards, and particularly relates to a method for improving the bending resistance of a flexible circuit board, which comprises the following steps: after plasma pretreatment is carried out on the surface of a polyimide substrate, a three-dimensional nano-column array structure is constructed by depositing gold nanoparticles as a mask and combining reactive ion etching; then removing the mask to obtain a clean polyimide nano structure; and depositing a titanium / copper seed crystal layer through magnetron sputtering, and realizing conformal filling and coating of the copper conductive layer on the nano structure by adopting pulse reverse electroplating to form an adhesive-free mechanical interlocking interface. An adhesive-free three-dimensional mechanical interlocking structure is used for replacing an adhesive layer which is weak in physical performance and prone to fatigue failure, and the structural weak link that a traditional flexible circuit board is layered and cracked first under dynamic bending stress is thoroughly removed.

Description

Technical Field

[0001] This invention belongs to the field of electronic packaging and printed circuit board technology, specifically a method for improving the bending resistance of flexible circuit boards. Background Technology

[0002] With the rapid evolution of electronic technology and the increasing trend of consumer electronics towards thinner, lighter, more portable, and more integrated functions, flexible printed circuits (FPCs), as key components for interconnecting signals within electronic devices, are becoming increasingly important and widely used. Compared to traditional rigid printed circuit boards, FPCs, with their superior flexibility, lightweight physical properties, and efficient three-dimensional wiring capabilities, play an irreplaceable role in fields with stringent requirements for spatial layout and dynamic performance, such as foldable smartphones, wearable devices, precision medical instruments, automotive electronics, and aerospace.

[0003] In current technological practices, typical flexible printed circuit boards (FPCBs) typically employ a mature multilayer composite structure. This structure uses a polymer film such as polyimide (PI) or polyester (PET) as the insulating substrate, providing basic mechanical support and electrical insulation properties. On top of this substrate, one or more conductive metal layers, usually rolled copper foil or electrolytic copper foil, are deposited through lamination or coating to form a pre-defined circuit pattern. A specialized adhesive is generally used to firmly bond the insulating substrate and the conductive metal layers. This three- or multi-layer structure of substrate-adhesive-conductive layer effectively solved the problem of stable circuit connection under static or low-frequency bending conditions at a specific historical stage of development, constituting the mainstream technological paradigm in the current flexible printed circuit board manufacturing field and providing a solid foundation for the miniaturization and form factor innovation of electronic products.

[0004] However, with the continuous development of related technologies and the increasingly stringent requirements for performance indicators in application scenarios, especially in situations requiring dynamic bending with high frequency and small curvature radius (such as the hinge area of ​​foldable screen phones or the motion joints of industrial robots), some inherent characteristics of the aforementioned traditional composite structures at the principle level have gradually revealed their inherent limitations when facing extreme mechanical stress challenges. The reason for this is that the structure is essentially a heterogeneous composite composed of various materials with vastly different physical properties. Specifically, the conductive metal layer (such as copper) has a high elastic modulus and hardness, exhibiting significant rigidity; while the polymer insulating substrate (such as PI) has a low elastic modulus, exhibiting good flexibility; the adhesive layer in between has its own unique mechanical properties. When the flexible circuit board undergoes bending deformation, a stress-neutral layer is formed within its cross-section. The material on the outside of the neutral layer is subjected to tensile stress, while the material on the inside is subjected to compressive stress. Due to significant differences in the elastic modulus, Poisson's ratio, and other mechanical parameters between the copper layer, adhesive layer, and PI substrate layer, the deformation between the layers is not coordinated during bending, resulting in huge interlaminar shear stress and peel stress at their interface. This stress concentration phenomenon caused by the mismatch of material physical properties is an inherent physical property of this composite structure. In single or low-frequency bending, this stress can be absorbed and alleviated by the elastic deformation of the adhesive layer. However, under long-term, repeated dynamic bending loads, the concentrated stress will continuously act on the weakest interface between the adhesive layer and the conductive layer, causing fatigue of the adhesive, initiation and propagation of microcracks, and ultimately delamination and blistering between the conductive layer and the substrate, or directly causing the copper foil circuit with high stress concentration to crack or even break due to metal fatigue, resulting in permanent failure of the entire circuit. This failure mode is not simply due to insufficient material strength, but stems from the inherent contradiction of its multilayer heterogeneous structure under dynamic stress. That is, the adhesive layer used to achieve structural bonding becomes the source of failure under dynamic stress cycling.

[0005] Therefore, the present invention provides a method for improving the bending resistance of flexible circuit boards. Summary of the Invention

[0006] In order to overcome the shortcomings of the prior art, at least one technical problem raised in the background art is solved.

[0007] The technical solution adopted by this invention to solve its technical problem is: a method for improving the bending resistance of flexible circuit boards, comprising the following steps: Step 1: Provide and pre-treat the insulating substrate, which is a polyimide film. The polyimide film has a thickness of 25 micrometers, a dielectric constant of 3.4 at a frequency of 1 GHz, a glass transition temperature higher than 300 degrees Celsius, and a tensile strength greater than 200 MPa. First, one surface of the polyimide film is pretreated to remove organic contaminants, particles, and adsorbed moisture from its surface, and the surface is activated to improve the uniformity and adhesion of subsequent process steps. The pretreatment process specifically involves placing the polyimide film in a vacuum plasma cleaning device, introducing 99.999% pure argon gas as the working gas, and maintaining the pressure inside the vacuum chamber at 20 Pascals. The radio frequency power supply is activated, applying 13.56 MHz of radio frequency power with a power density set to 0.5 W / cm², and the surface of the polyimide film is subjected to continuous plasma bombardment cleaning for 180 seconds.

[0008] Step Two: In-situ generation of a three-dimensional nanoarray structure on the surface of the insulating substrate. The aim is to transform the originally two-dimensional, flat surface of the insulating substrate into a three-dimensional nanostructure with a high aspect ratio and high specific surface area. Specifically, this step includes the following sub-steps: Sub-step 2.1: Preparation of the sacrificial mask layer. A discontinuous sacrificial mask layer composed of nanoparticles is deposited on the pretreated polyimide film surface using physical vapor deposition. Specifically, an electron beam evaporation deposition system is used, with 99.99% pure gold as the evaporation source, and a vacuum level better than 5 × 10⁻⁻⁻⁶. 4 In a Pascal environment, a gold layer with a nominal thickness of 5 nanometers was deposited on the surface of the polyimide film at a deposition rate of 0.1 Å / s. Due to the poor wettability of gold on the polyimide surface and the Woland-Weber growth pattern, the deposited gold automatically forms a discontinuous, randomly distributed nanoparticle island structure, which will serve as a hard mask in the subsequent etching process.

[0009] Sub-step 2.2: Anisotropic Reactive Ion Etching. A polyimide film with a gold nanoparticle mask is transferred to an inductively coupled plasma reactive ion etching (ICP-REI) apparatus. The etching gas is a mixture of oxygen and carbon tetrafluoride, with an oxygen flow rate of 40 standard cubic centimeters per minute and a carbon tetrafluoride flow rate of 10 standard cubic centimeters per minute. The gas pressure in the reaction chamber is stabilized at 1.5 Pascals. The ICP RF source power is set to 800 watts to generate a high-density reactive plasma; simultaneously, a bias RF source with a power of 100 watts is applied to the lower electrode of the substrate to achieve directional acceleration of ions, thereby performing anisotropic etching. Under these process conditions, the gold nanoparticles exhibit extremely high etch selectivity to the plasma, protecting the underlying polyimide material, while the uncovered areas are etched vertically downwards by reactive ions. The etching process is continued for 480 seconds. After this process, a densely arranged array of nanopillars, composed of polyimide material itself and perpendicular to the substrate surface, was generated in situ on the surface of the polyimide film. The formed nanopillar array has an average height of 1.2 micrometers, an average diameter of 150 nanometers, and an array density of 5 × 10⁻⁶ per square centimeter. 8 indivual.

[0010] Sub-step 2.3: Removal of the sacrificial mask layer. The etched polyimide film is immersed in a chemical etching solution specifically designed for gold removal. This etching solution consists of an aqueous solution of iodine and potassium iodide, with an iodine concentration of 40 g / L and a potassium iodide concentration of 100 g / L. Immersion at room temperature for 300 seconds completely dissolves and removes the gold nanoparticles covering the top of the nanopillars through a chemical reaction. The film is then repeatedly rinsed with deionized water and dried with high-purity nitrogen.

[0011] Thus, an insulating substrate with a clean three-dimensional nanopillar array structure whose surface is entirely composed of polyimide was obtained.

[0012] Step 3: Conformal Deposition and Bulk Filling of the Conductive Layer. This step aims to precisely deposit the conductive metal into the three-dimensional nanoarray structure, achieving complete filling of the gaps between the nanostructures and coating of the nanopillars, forming a microscopic mechanical interlock. This step specifically includes the following sub-steps: Sub-step 3.1: Preparation of the metal seed layer. To make the surface of the insulating polyimide nanostructure conductive to facilitate subsequent electrochemical deposition, an ultrathin, conformal metal seed layer needs to be deposited first. Using magnetron sputtering deposition technology, a 20 nm thick titanium layer is first sputtered in a vacuum environment as an adhesion reinforcement layer. This titanium layer can form a strong chemical bond with the functional groups on the polyimide surface. Subsequently, a 50-nanometer-thick copper layer is sputtered on top of the titanium layer as a conductive seed layer. The magnetron sputtering process has excellent step coverage capability, ensuring that the titanium and copper layers uniformly and continuously coat the top surface and sidewalls of each polyimide nanopillar, penetrating deep into the root of the array.

[0013] Sub-step 3.2: Pulsed reverse current electroplating of the main conductive layer. A polyimide substrate with a metal seed layer is used as the cathode and placed in a specially prepared electroplating solution to thicken the main conductive layer. The electroplating solution is a copper sulfate electroplating solution, with the following main components and concentrations: copper sulfate pentahydrate 220 g / L, concentrated sulfuric acid 60 g / L, and chloride ions 50 mg / L. To achieve void-free filling of the high aspect ratio nanostructure, the electroplating solution also contains two key organic additives: polyethylene glycol (molecular weight 3000, concentration 300 mg / L) as an inhibitor; and bis(3-sulfopropyl) disulfide (concentration 5 mg / L) as an accelerator. The electroplating process uses a pulsed reverse current waveform. One working cycle consists of one forward pulse and one reverse pulse. The current density of the forward pulse is 3 amperes per square decimeter (A / dm²), and the duration is 10 milliseconds. A reverse pulse with a current density of 15 amperes per square decimeter and a duration of 1 millisecond was then applied. This waveform utilizes the synergistic effect of SPS preferentially adsorbing onto protruding parts of the structure under an electric field, accelerating deposition, and PEG preferentially adsorbing onto flat regions, inhibiting deposition, as well as the leveling effect of the reverse pulse locally dissolving the protruding tips. This promotes the superfilling behavior of copper ions growing upwards from the bottom of the nanostructure. Electroplating continued until the deposited copper layer thickness exceeded the top of the nanopillars by 12 micrometers, forming a flat and dense copper conductive layer with a total thickness of approximately 13.2 micrometers. At this point, the copper metal had completely filled all the voids between the polyimide nanopillars and formed a tight mechanical interlocking structure with the nanopillars.

[0014] Step 4: Circuit Patterning and Post-processing. This step involves processing the continuous conductive layers into a pre-defined circuit pattern.

[0015] Sub-step 4.1: Photoresist Coating and Pattern Exposure. A 5-micrometer-thick layer of positive photoresist is uniformly coated onto the surface of the copper conductive layer by spin coating. This photoresist is a phenolic resin system based on diazonaphthoquinone (DNQ) and is sensitive to ultraviolet light at a wavelength of 365 nanometers (nm). Subsequently, the photoresist is exposed to ultraviolet light using a contact lithography machine with a quartz chrome mask containing a preset circuit pattern at an exposure energy of 120 millijoules per square centimeter (mJ / cm²).

[0016] Sub-step 4.2: Development and Etching. The exposed substrate is immersed in a 2.38% tetramethylammonium hydroxide aqueous solution for development to remove the photoresist in the exposed areas, thereby exposing the underlying copper layer. Subsequently, a ferric chloride aqueous solution is used as the etching solution to chemically etch the exposed copper layer until all copper metal outside the circuit pattern is completely removed.

[0017] Sub-step 4.3: Resin Removal and Capping. Residual photoresist is removed using a dedicated remover, exposing the final copper conductive lines. Finally, a polyimide capping film is thermo-pressed onto the circuit surface. This capping film is pre-windowed to expose the pads requiring electrical connections. The capping conditions are: temperature 180°C, pressure 2 MPa, duration 3600 seconds.

[0018] The beneficial effects of this invention are as follows: By replacing the adhesive layer, which is physically weak and prone to fatigue failure, with a three-dimensional mechanical interlocking structure without adhesives, the structural weak link that is the first to delaminate and crack under dynamic bending stress in traditional flexible circuit boards is completely removed.

[0019] This invention achieves efficient stress dissipation and redistribution. The gradient modulus transition region formed by this invention disperses the interlaminar shear stress and peeling stress generated during bending from a two-dimensional plane into a three-dimensional composite region for absorption and transmission. The stress is no longer concentrated at a sharp interface, but is uniformly distributed in the near-surface volume of the substrate through hundreds of millions of microscopic metal anchoring structures, greatly improving the interface's threshold for fatigue damage.

[0020] Under the same dynamic bending test conditions, its failure cycle count can be increased by more than an order of magnitude compared with traditional adhesive-based flexible circuit boards, which can meet the extremely demanding dynamic application requirements.

[0021] This ensures excellent electrical performance and high-frequency characteristics. The direct bonding method without adhesives avoids problems such as uneven dielectric constant, increased high-frequency loss, and deterioration of electrical performance after moisture absorption in humid and hot environments that may be caused by adhesive layers, providing a more ideal physical basis for the stable transmission of high-frequency and high-speed signals. Attached Figure Description

[0022] The invention will now be further described with reference to the accompanying drawings.

[0023] Figure 1 This is a flowchart illustrating a method for improving the bending resistance of flexible circuit boards provided by the present invention. Figure 2 This is a schematic diagram of the three-dimensional nanoarray structure formed on the surface of the insulating substrate in the method of the present invention; Figure 3This is a schematic diagram of the conformal deposition of a metal seed layer on the surface of a three-dimensional nanoarray structure in the method of this invention; Figure 4 This is a schematic diagram of the three-dimensional nanoarray structure filled and covered by the main conductive layer in the method of the present invention; Figure 5 This is a schematic diagram of the gradient modulus transition region in the flexible circuit board finally prepared by this invention; In the figure: 10, insulating substrate; 11, nanopillar; 20, metal seed layer; 30, conductive layer; 40, gradient modulus transition region. Detailed Implementation

[0024] To make the technical means, creative features, objectives and effects of this invention easier to understand, the invention will be further described below in conjunction with specific embodiments.

[0025] Reference Figures 1 to 5 This invention discloses a systematic process method aimed at fundamentally improving the dynamic bending reliability of flexible printed circuit boards (FPCBs). The core of this method lies in abandoning the adhesive layer commonly used in traditional FPCB manufacturing processes. Instead, it constructs a microscopic three-dimensional topological structure in situ on the surface of an insulating substrate and utilizes advanced metal deposition technology to achieve physical, integrated interlocking between the conductive layer and this three-dimensional structure. This forms an interface transition zone with gradient mechanical properties, replacing the substrate-adhesive-copper foil interface in traditional technologies, which is mechanically weak and prone to fatigue failure.

[0026] In some embodiments, the method for improving the bending resistance of flexible circuit boards provided by the present invention includes the following detailed process flow and parameter settings: The first step of this method is to provide and pre-treat the insulating substrate 10. In this embodiment, the selected insulating substrate 10 is a high-performance polyimide (PI) film. The physical and electrical properties of this film are precisely selected to meet the requirements of subsequent micro / nano fabrication and high-performance applications of the final product; Specifically, the polyimide film has a thickness of 25 micrometers (µm), which ensures sufficient mechanical support strength while also providing excellent overall flexibility for the circuit board. Its dielectric constant (Dk) at 1 gigahertz (GHz) is 3.4, and its dielectric loss tangent (Df) is less than 0.005. These parameters ensure low loss and high signal integrity in high-frequency signal transmission applications. In addition, its glass transition temperature (Tg) is higher than 300 degrees Celsius, ensuring the stability of material dimensions in subsequent high-temperature processes such as sputtering and hot pressing; its tensile strength is greater than 200 MPa and its elongation at break is more than 50%, providing excellent mechanical reliability for the final product.

[0027] It should be noted that before proceeding with the construction of the micro / nano structures, a rigorous pretreatment of one surface of the polyimide film is required. The purpose of this pretreatment is to thoroughly remove organic contaminants, dust particles, and physically adsorbed water molecules that may have adhered to the surface during storage and transportation. Simultaneously, energy bombardment activates the polymer surface at both physical and chemical levels, breaking some surface chemical bonds and forming dangling bonds, thereby significantly improving surface wettability and affinity for subsequent deposited materials. In this embodiment, the pretreatment process is carried out in a vacuum plasma cleaning device; As mentioned earlier, the polyimide film, either in rolls or sheets, is first loaded into the vacuum chamber, and the chamber is then evacuated to a basic vacuum level better than 1×10⁻⁶. -3 Pascal (Pa); Subsequently, high-purity argon (Ar) gas with a purity of 99.999% was introduced as the working gas, and the gas flow rate was precisely controlled at 100 standard cubic centimeters per minute (sccm) using a mass flow controller. Simultaneously, the pumping speed of the vacuum pump was adjusted to maintain a stable dynamic working pressure of 20 Pascals (Pa) within the vacuum chamber. At this pressure, the radio frequency power supply was activated, applying radio frequency power at a frequency of 13.56 MHz to the electrodes within the chamber, with the power density set to 0.5 W / cm². 2 Under the influence of a high-frequency electric field, argon gas is ionized to form a high-density plasma; In this process, high-energy argon ions, accelerated by an electric field, physically bombard the surface of the polyimide film, effectively removing microscopic contaminants. Simultaneously, ultraviolet light and active particles in the plasma induce the recombination and activation of surface chemical bonds. The entire plasma bombardment cleaning process lasts 180 seconds. After treatment, the RF power supply and working gas are shut off, and the chamber is restored to a high vacuum state, preparing for the next step of in-situ deposition.

[0028] Next, the second step of the method of the present invention is to generate a three-dimensional nanoarray structure in situ on the surface of the pretreated insulating substrate 10. This step is fundamental to constructing an adhesive-free mechanical interlocking interface, and its goal is to transform the relatively flat two-dimensional polyimide surface at the microscale into a three-dimensional nanotopological structure composed of the material itself, with an extremely high aspect ratio and a huge specific surface area. (Refer to...) Figure 2 Specifically, this structure is a dense array of numerous polyimide nanopillars 11. This step is accomplished through a series of precisely controlled sub-steps.

[0029] In some embodiments, sub-step 2.1 involves the preparation of a sacrificial mask layer. The purpose of this step is to form a discontinuous hard mask composed of nanoscale particles on the surface of the polyimide, which will be used to selectively protect the underlying polyimide material during subsequent etching processes. In this embodiment, the sacrificial mask layer is prepared using electron beam evaporation deposition (EPD) technology. The plasma-pretreated polyimide film is directly transferred or held in the same multi-chamber system's EPD module under vacuum. Gold (Au) with a purity of up to 99.99% is selected as the evaporation source material and placed in a water-cooled copper crucible. The vacuum level is ensured to be better than 5 × 10⁻⁻⁻⁻⁶. -4 In the ultra-high vacuum environment of Pascal (Pa), a high-energy electron beam is used to precisely bombard a gold target, causing it to melt and evaporate. By controlling the power and scanning mode of the electron beam and using a quartz crystal oscillation monitoring system to monitor the deposition rate in real time, the gold deposition rate is stably controlled at an extremely low 0.1 Å / s. As mentioned earlier, under these conditions, a polyimide film was deposited on the surface until the nominal thickness reached 5 nanometers (nm). Since the interaction energy between gold atoms and the polyimide substrate surface is much smaller than the binding energy between gold atoms, and gold has extremely poor wettability on the polyimide surface, its growth mode follows a typical Volmer-Weber island growth mechanism. Continuing from the above, even with a nominal thickness of 5 nanometers, the deposited gold layer is not a continuous thin film, but rather spontaneously aggregates into a large number of isolated, randomly distributed island-like structures of gold nanoparticles with sizes on the order of tens of nanometers. These in-situ formed gold nanoparticles with excellent etching resistance constitute the high-quality sacrificial mask required for subsequent anisotropic etching.

[0030] In some embodiments, sub-step 2.2 involves anisotropic reactive ion etching. A polyimide film with a gold nanoparticle mask is transferred to an inductively coupled plasma reactive ion etching (ICP-RIE) apparatus. This apparatus has the ability to independently control plasma density and ion bombardment energy, which is crucial for achieving high aspect ratio and high verticality micro / nanostructure etching. The reactive gas used in the etching process is a mixture of oxygen (O2) and carbon tetrafluoride (CF4) in a precisely proportioned ratio. Specific parameters are set as follows: the oxygen flow rate is set to 40 standard cubic centimeters per minute (sccm), and the carbon tetrafluoride flow rate is set to 10 standard cubic centimeters per minute (sccm). Understandably, under this gas composition, oxygen is the primary etching species. Its active particles (such as oxygen free radicals) can effectively break the carbon-carbon and carbon-nitrogen chemical bonds in polyimide, generating volatile products such as CO and CO2. The small amount of added carbon tetrafluoride decomposes in the plasma to generate fluorine-containing free radicals. These free radicals can form a thin passivation layer on the sidewalls of the etched nanopillars, inhibiting lateral etching and thus greatly improving the anisotropy of the etching. The gas pressure in the reaction chamber is stabilized at a low level of 1.5 Pa using an automatic pressure controller to increase the mean free path of the ions and ensure their directional movement. Subsequently, the ICP radio frequency source was activated and its power was set to 800 watts (W). This high power generated a high-density reaction plasma at the top of the reaction chamber through induction coils. Simultaneously, an independent bias RF source with a power set to 100 watts (W) is applied to the lower electrode supporting the polyimide substrate. This bias establishes a DC self-bias between the substrate and the plasma, which is used to extract positive ions from the sheath in the plasma and accelerate them vertically to bombard the substrate surface. Understandably, under these process conditions, the polyimide areas not covered by the gold nanoparticle mask are rapidly etched away by continuous vertical bombardment from high-energy reactive ions, while the areas below, protected by the gold nanoparticles, are retained, gradually forming nanopillar structures perpendicular to the substrate surface. The entire etching process is precisely controlled within 480 seconds. Following the above, after the process was completed, the structure was characterized by scanning electron microscopy (SEM). The results showed that a densely packed array of nanopillars 11, composed of polyimide material itself, was successfully formed in situ on the surface of the polyimide film. Statistical analysis of this array showed that the average height of the formed nanopillars 11 was approximately 1.2 micrometers (µm), the average diameter was approximately 150 nanometers (nm), and the aspect ratio was approximately 8:1. The array density was extremely high, reaching 5 × 10⁻⁶ per square centimeter. 8 The nanopillars provide a large mechanically interlocked interface area for subsequent metal filling.

[0031] In some embodiments, sub-step 2.3 involves sacrificing the removal of the mask layer. After the construction of the polyimide nanopillar array is completed, the gold nanoparticle mask covering the top of each nanopillar 11 must be completely removed to expose the pure polyimide three-dimensional structure. In this embodiment, the gold mask is removed using wet chemical etching. The polyimide film etched by ICP-RIE is completely immersed in a specially formulated gold etching solution; As shown above, this etching solution is an iodine / iodide-based system with the following composition: This solution was prepared by dissolving 40 grams of analytical grade iodine (I₂) and 100 grams of analytical grade potassium iodide (KI) in 1 liter of deionized water. In this solution, iodine reacts with iodide ions (I₂, I₂, I₃ ...�, I₂, I� - (Provided by KI) will form soluble triiodide ions (I 3- The latter is a mild yet highly efficient oxidizing agent that can oxidize metallic gold into gold ions (Au). + The gold ions then complex with a large number of iodide ions in the solution to form a very stable tetraiodoaluminate ([AuI4)). - This process dissolves the gold in the aqueous solution. Immersing the film at room temperature (approximately 25 degrees Celsius) for 300 seconds is sufficient to ensure complete reaction and dissolution of the gold particles at the tips of all nanopillars. After removal, the film is removed from the etching solution and immediately rinsed repeatedly and thoroughly with copious amounts of deionized water to remove all residual etching solution ions and prevent contamination of subsequent processes. Finally, the film surface is gently dried using high-purity nitrogen. Thus, an insulating substrate 10 with a clean, regular, high-density three-dimensional nanopillar array structure, entirely composed of polyimide material, is prepared.

[0032] In some embodiments, the third step of the method is conformal deposition and bulk filling of the conductive layer. The goal of this step is to precisely deposit a highly conductive metal, in this embodiment copper, into the prepared three-dimensional nanoarray structure. This requires not only that the metal fill all the tiny gaps between the nanopillars 11 without defects, but also that the metal tightly coats the sidewalls and top surface of each nanopillar 11, thereby forming billions of mechanical anchoring points at the microscale, constructing a robust interlocking structure. (Refer to...) Figure 3 and Figure 4 This step specifically includes the following two key sub-steps.

[0033] In some embodiments, sub-step 3.1 involves the preparation of the metal seed layer 20. Since the polyimide nanostructure itself is electrically insulating, it cannot be directly electrochemically deposited (e.g., electroplated). Therefore, an ultrathin and conductive metal seed layer 20 must first be prepared on its surface to provide a conductive substrate for the subsequent electroplating of the main conductive layer. (Refer to...) Figure 3 The seed layer 20 was deposited using magnetron sputtering technology, which has good step coverage and adaptability to complex morphologies. In a multi-target magnetron sputtering system, a 20-nanometer (nm) thick titanium (Ti) layer is first sputtered as an adhesion enhancement layer. Titanium is an active metal, and its atoms can form strong Ti-OC chemical bonds with functional groups such as carbonyl groups on the surface of polyimide during the deposition process, which greatly enhances the intrinsic bonding force between the metal layer and the polymer substrate. After the titanium layer deposition is completed, without breaking the vacuum, the target site is switched, and a 50-nanometer-thick copper (Cu) layer is sputtered on top of the titanium layer as a conductive seed layer. The sputtering process parameters are optimized to ensure that the deposited titanium / copper bilayer film can uniformly and continuously coat the top surface and sidewalls of each polyimide nanopillar 11, and can penetrate into the root of the nanopillar array to form a seamless, continuous conductive network.

[0034] In some embodiments, sub-step 3.2 involves pulsed reverse current electroplating of the main conductive layer 30. A polyimide substrate with a metal seed layer 20 is used as the cathode, clamped in a specially designed electroplating fixture, and placed in a specially prepared electroplating solution to thicken the main conductive layer 30. To achieve bottom-up, void-free superfilling of high aspect ratio nanostructures, the chemical formulation of the electroplating solution and the current waveform were precisely designed. The electroplating solution was an acidic copper sulfate solution with the following basic components and concentrations: copper sulfate pentahydrate (CuSO4·5H2O) 220 g / L, providing copper ions as the main salt; concentrated sulfuric acid (H2SO4) 60 g / L, used to improve the solution's conductivity and stabilize the plating solution; chloride ions (Cl... - 50 mg / L (added in the form of hydrochloric acid) as a key synergist; More importantly, the electroplating solution also contains two functional organic additives: one is an inhibitor, which is polyethylene glycol (PEG) with a molecular weight of 3000 and a concentration of 300 mg / L. Another option is an accelerator, which is bis(3-sulfopropyl) disulfide (SPS) at a concentration of 5 mg / L. During the electroplating process, PEG molecules tend to adsorb at structural openings and flat surfaces, forming a thin film that hinders the deposition of copper ions; SPS molecules are preferentially transported and adsorbed to the bottom of the structural depression under the action of an electric field, and catalyze the reduction reaction of copper ions there, significantly increasing the local deposition rate.

[0035] To maximize the effectiveness of this competitive adsorption mechanism, the electroplating process does not use traditional direct current, but instead employs an advanced pulsed reverse current waveform. A complete working cycle consists of one forward pulse and one reverse pulse. In this embodiment, the peak current density of the positive pulse is set to 3 amperes per square decimeter (A / dm²). 2The duration is 10 milliseconds (ms), during which copper ions preferentially grow from the bottom of the nanostructure upwards under the acceleration of SPS; Immediately following, a brief but intense reverse pulse is applied, with a current density as high as 15 amperes per square decimeter (A / dm²) and a duration of only 1 millisecond (ms). This reverse pulse (anodic pulse) preferentially dissolves the tiny protrusions and tips formed at the openings or tops of the structure during the deposition process, acting as a leveling agent and facilitating the redistribution of inhibitors and accelerators, thereby further enhancing the bottom-up filling pattern; By continuously applying such pulsed reverse current, copper metal grows layer by layer upwards from the root of the nanopillar array, eventually completely and densely filling all the gaps between the nanopillars 11 and ultimately covering the entire nanoarray structure. Electroplating continues until the deposited copper layer thickness exceeds the top of the nanopillars by 12 micrometers (µm), forming a flat and dense copper conductive layer 30 with a total thickness of approximately 13.2 micrometers. At this point, the copper metal has formed a robust mechanically interlocked structure with the polyimide nanopillar array, which is interlocked at the microscopic level and integrated macroscopically.

[0036] Finally, the method proceeds to the fourth step, namely circuit patterning and post-processing. This step uses a standard printed circuit board subtractive process to fabricate the continuous conductive layer 30 formed in the previous step into a preset circuit pattern.

[0037] In some embodiments, sub-step 4.1 involves photoresist coating and pattern exposure. A 5-micrometer-thick layer of positive photoresist is uniformly coated onto the smooth surface of the copper conductive layer 30 by spin coating. This photoresist is a phenolic resin (Novolac) system based on diazonaphthoquinone (DNQ) photosensitizer, which exhibits high sensitivity to ultraviolet light (i-line) at a wavelength of 365 nanometers (nm). After spin coating, a pre-baking process is performed to remove the solvent. Subsequently, using a contact lithography machine, a pre-fabricated quartz chrome mask with a preset circuit pattern is tightly bonded to the surface of a substrate coated with photoresist for ultraviolet exposure. The exposure dose is precisely controlled at 120 millijoules per square centimeter (mJ / cm²) to ensure sufficient photochemical reaction of the photoresist in the patterned area.

[0038] In some embodiments, sub-step 4.2 involves development and etching. The exposed substrate is immersed in a 2.38% (by weight) aqueous solution of tetramethylammonium hydroxide (TMAH) for development. Under the action of the developer, the photoresist in the ultraviolet-exposed areas becomes soluble due to changes in its chemical structure, and is thus completely dissolved and removed, exposing the underlying copper layer. The photoresist in the unexposed areas remains unchanged, continuing to act as a resist layer to protect the underlying copper. After development, an aqueous solution of ferric chloride (FeCl3) is used as a chemical etching solution. The exposed copper layer is chemically etched by spraying or immersion until all copper metal outside the circuit pattern is completely removed.

[0039] In some embodiments, sub-step 4.3 involves photoresist removal and overlay lamination. After etching, a dedicated organic photoresist remover (such as a solution of N-methylpyrrolidone) is used to completely remove the remaining photoresist layer on the circuit pattern, exposing the final copper conductive lines with precise geometry. To protect the circuitry and provide insulation, a polyimide coverlay is finally applied to the circuit surface via thermoforming. This coverlay also has a semi-cured adhesive and has been pre-windowed using stamping or laser cutting to expose the pads for soldering or electrical connections. The coverlay bonding process is set at 180 degrees Celsius and 2 MPa, held at these conditions for 3600 seconds to ensure complete adhesive curing and a strong bond with the underlying circuitry and substrate.

[0040] Through all the above steps, a flexible circuit board with high-performance bending resistance is finally prepared. (Refer to...) Figure 5 The most core structural feature of this flexible circuit board is that there is no independent, macroscopic adhesive layer between its conductive layer 30 and the insulating substrate 10. Instead, there is a gradient modulus transition region 40 where structure and function are highly integrated at the microscale; From a microscopic perspective, this transition region 40 is a composite structure consisting of a high-density polyimide nanopillars 11 array extending vertically upward from the insulating substrate 10 body, and a copper metal matrix that completely fills the gaps between these nanopillar arrays and densely coats them. Within this transition region 40, which is approximately 1.2 micrometers thick, the material composition smoothly and continuously transitions from 100% polyimide at the bottom to 100% copper at the top. This gradient change in composition directly leads to a gradient change in the mechanical properties of this region. Specifically, the effective elastic modulus of this region changes continuously and gradually from approximately 3 gigapascals (GPa) of the bottom polyimide to approximately 110 gigapascals (GPa) of the top pure copper. This gradient mechanical property effectively eliminates stress singularities at the interface caused by abrupt changes in the elastic modulus of materials in traditional hard-soft-hard structures. When the flexible circuit board is subjected to bending deformation, the interlayer shear stress and peel stress are no longer concentrated on a fragile two-dimensional plane, but are effectively dispersed throughout the volume of the entire three-dimensional interlocking structure, jointly supported and dissipated by hundreds of millions of copper-polyimide micro-anchoring units. This stress dispersion mechanism greatly enhances the bonding strength and fatigue resistance of the interface, enabling the circuit board to withstand extremely harsh dynamic bending tests and maintain its structural and electrical integrity over a long period of time.

[0041] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The embodiments and descriptions in the specification are merely illustrative of the principles of the invention. Various changes and modifications can be made to the invention without departing from its spirit and scope, and all such changes and modifications fall within the scope of the present invention as claimed. The scope of protection of the present invention is defined by the appended claims and their equivalents.

Claims

1. A method for improving the bending resistance of flexible circuit boards, characterized in that, This method abandons the composite structure using independent adhesive layers and includes the following steps: Provide and pre-treat the insulating substrate (10); On one surface of the insulating substrate (10), a three-dimensional nanoarray structure composed of the insulating substrate (10) body material is generated in situ by etching the insulating substrate (10) body material. The three-dimensional nanoarray structure includes a plurality of densely arranged nanopillars (11) extending vertically upward from the surface of the insulating substrate (10). A conductive layer (30) is deposited on the three-dimensional nanoarray structure. The metallic material of the conductive layer (30) fills all the gaps between the nanopillars (11) and conformally covers the multiple nanopillars (11). Thus, a three-dimensional mechanically interlocked structure with interlocking at the microscale is formed between the insulating substrate (10) and the conductive layer (30) without an independent adhesive layer. This structure is composed of the nanopillars (11) and the metallic material that fills and covers them. The three-dimensional mechanically interlocked structure constitutes a gradient modulus transition region (40) with gradient mechanical properties. The conductive layer (30) is processed into a circuit pattern to form a preset conductive line.

2. The method for improving the bending resistance of flexible circuit boards according to claim 1, characterized in that, The step of generating a three-dimensional nanoarray structure in situ on the surface of the insulating substrate (10) specifically includes: A sacrificial mask layer composed of discontinuous nanoparticles is prepared on the surface of the pretreated insulating substrate (10). The nanoparticles are randomly distributed on the surface of the insulating substrate (10) and serve as a hard mask in the subsequent etching process. Anisotropic reactive ion etching process is used, with the sacrificial mask layer as a mask, to vertically etch the area of ​​the insulating substrate (10) not covered by the nanoparticles until the array of nanopillars (11) with a predetermined height is formed. The sacrificial mask layer covering the top of the nanopillars (11) is completely removed by chemical wet etching to expose the three-dimensional nanoarray structure made of pure insulating substrate (10) bulk material.

3. The method for improving the bending resistance of flexible circuit boards according to claim 2, characterized in that, The step of preparing the sacrificial mask layer includes: depositing a layer of metal material on the surface of the insulating substrate (10) by physical vapor deposition; the metal material is gold, which is deposited by electron beam evaporation.

4. The method for improving the bending resistance of flexible circuit boards according to claim 2, characterized in that, The anisotropic reactive ion etching step is performed in an inductively coupled plasma reactive ion etching apparatus; the etching process uses a mixed gas composed of oxygen and carbon tetrafluoride as the reaction gas, wherein oxygen is the main etching species used to break the polymer chemical bonds of the insulating substrate (10), while the fluorine-containing free radicals generated by the decomposition of carbon tetrafluoride are used to form a passivation layer on the sidewall of the nanopillar (11) to suppress lateral etching, thereby improving the anisotropy of the etching; In the etching process, a high-density reactive plasma is generated by an inductively coupled plasma radio frequency source, and at the same time, the ions in the plasma are accelerated in a directional manner by a bias radio frequency source applied to the lower electrode of the insulating substrate (10) to achieve vertical bombardment etching of the insulating substrate (10).

5. The method for improving the bending resistance of flexible circuit boards according to claim 4, characterized in that, The specific parameters of the anisotropic reactive ion etching process are set as follows: the oxygen flow rate is 40 standard cubic centimeters / minute, the carbon tetrafluoride flow rate is 10 standard cubic centimeters / minute; the gas pressure in the reaction chamber is maintained at 1.5 Pascals; the power of the inductively coupled plasma radio frequency source is 800 watts, the power of the bias radio frequency source is 100 watts; the etching duration is 480 seconds; the average height of the nanopillars (11) formed by this process is 1.2 micrometers, and the average diameter is 150 nanometers.

6. The method for improving the bending resistance of flexible circuit boards according to claim 1, characterized in that, The step of depositing the conductive layer (30) specifically includes: First, on all exposed surfaces of the three-dimensional nanoarray structure, an ultrathin and conductive metal seed layer (20) is conformally deposited using physical vapor deposition. The metal seed layer (20) provides a continuous conductive substrate for subsequent electrochemical deposition. The insulating substrate (10) with the metal seed layer (20) is placed in an electroplating solution as a cathode. The main conductive layer is thickened and filled on the metal seed layer (20) by electrochemical deposition until the main conductive layer completely fills all the gaps between the nanopillars (11) and continues to grow upward to exceed the top of the nanopillars (11) to reach a predetermined total thickness, thereby forming the conductive layer (30).

7. The method for improving the bending resistance of flexible circuit boards according to claim 6, characterized in that, The specific steps of depositing the metal seed layer (20) are as follows: using magnetron sputtering deposition technology, a titanium layer is first sputtered on the surface of the three-dimensional nanoarray structure as an adhesion enhancement layer, and the titanium layer is chemically bonded to the functional groups on the surface of the insulating substrate (10) to enhance the bonding force. Subsequently, without disrupting the vacuum environment, a copper layer is sputtered onto the titanium layer as a conductive seed layer.

8. The method for improving the bending resistance of flexible circuit boards according to claim 6, characterized in that, The step of forming the main conductive layer by electrochemical deposition specifically involves: employing a pulsed reverse current electroplating process; the electroplating solution is an acidic copper sulfate electroplating solution, the formulation of which, in addition to copper sulfate main salt, sulfuric acid and chloride ions, also specifically contains at least one organic additive as an inhibitor and at least one organic additive as an accelerator; utilizing the synergistic effect of the inhibitor preferentially adsorbing at structural openings and flat surfaces to inhibit deposition, and the accelerator preferentially adsorbing at the bottom of structural depressions to catalyze deposition, combined with the local dissolution and leveling effect of the reverse pulse on the protruding tips in the pulsed reverse current waveform, together achieving bottom-up, void-free superfilling growth of the three-dimensional nanoarray structure.

9. The method for improving the bending resistance of a flexible circuit board according to claim 8, characterized in that, The specific components and concentrations of the electroplating solution are as follows: The concentration of copper sulfate pentahydrate is 220 g / L, the concentration of concentrated sulfuric acid is 60 g / L, and the concentration of chloride ions is 50 mg / L; the inhibitor is polyethylene glycol with a molecular weight of 3000 and a concentration of 300 mg / L. The accelerator is bis(3-sulfopropyl) disulfide at a concentration of 5 mg / L; One working cycle of the pulsed reverse current waveform includes a forward pulse and a reverse pulse, wherein the current density of the forward pulse is 3 amperes per square decimeter and the current density of the reverse pulse is 15 amperes per square decimeter.

10. The method for improving the bending resistance of a flexible circuit board according to claim 1, characterized in that, The insulating substrate (10) is a polyimide film; and before the step of generating the three-dimensional nanoarray structure in situ, a pretreatment step is included on the surface of the insulating substrate (10), the pretreatment step being: The polyimide film was placed in a vacuum plasma cleaning device, and under an argon atmosphere with a pressure of 20 Pascals, radio frequency power with a power density of 0.5 W / cm² and a frequency of 13.56 MHz was applied to bombard the surface of the polyimide film with plasma for 180 seconds.

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