LDMOS device and manufacturing method thereof

Abstract

The invention provides an LDMOS (Laterally Diffused Metal Oxide Semiconductor) device and a manufacturing method thereof. The LDMOS device comprises an epitaxial layer; the drift region and the body region are located in the epitaxial layer; the gate structure is located on the epitaxial layer and stretches across the drift region and the body region; the drain injection region is positioned in the drift region; the source injection region and the plurality of body region injection regions are positioned in the body region; wherein the source injection region comprises a plurality of first source injection regions and a plurality of second source injection regions; the plurality of first source injection regions and the plurality of body region injection regions are alternately distributed in the channel width direction of the LDMOS device; and the plurality of second source injection regions are respectively positioned in the side edge regions, facing the gate structure, of the plurality of body region injection regions so as to form the source injection regions which are communicated along the width direction of the channel. According to the scheme, the N-type injection region is additionally arranged on the polycrystalline silicon channel side of the device to achieve channel compensation, and balance among the cellular pitch, the leakage current and the electric safety working region of the device is better achieved under the condition that the specific on-resistance of the device can be reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, in particular to an LDMOS device and a manufacturing method thereof. BACKGROUND

[0002] As a kind of power field effect transistor device, Lateral Double-Diffused MOSFET (LDMOS) device has been widely used due to its good thermal stability, high gain and low thermal resistance.

[0003] Ronsp (specific on-resistance) refers to the product of the on-resistance of the chip and the chip area, and is an important parameter index for measuring the performance of switch LDMOS device. Since lower Ronsp can significantly reduce the power consumption of chip and system, obtaining smaller Ronsp has become an important research direction for optimizing LDMOS device. SUMMARY

[0004] In order to solve the above technical problems, the present application provides an LDMOS device and a manufacturing method thereof, which aims to reduce the specific on-resistance of the device, and optimize the drain current of the device while reducing the cell pitch of the device, so as to better realize the balance between the cell pitch, drain current and electrical safety operation area (esoa) of the device.

[0005] According to a first aspect of the present application, an LDMOS device is provided, comprising:

[0006] an epitaxial layer located on a substrate;

[0007] a drift region and a body region located in the epitaxial layer;

[0008] a gate structure located on the epitaxial layer and crossing the drift region and the body region;

[0009] a drain implant region located in the drift region;

[0010] a source implant region and a plurality of body implant regions located in the body region;

[0011] wherein the source implant region comprises a plurality of first source implant regions and a plurality of second source implant regions;

[0012] the plurality of first source implant regions and the plurality of body implant regions are alternately distributed in the channel width direction of the LDMOS device;

[0013] The plurality of second source implant regions are located at side edge regions of the plurality of body implant regions towards the gate structure to form source implant regions connected along a channel width direction.

[0014] Optionally, the plurality of first source implant regions and the plurality of second source implant regions contain implant ions of the same type.

[0015] Optionally, the gate structure comprises a first gate structure and a second gate structure arranged oppositely;

[0016] A first side edge region of the body region is located under the first gate structure, and a second side edge region of the body region is located under the second gate structure.

[0017] The plurality of body implant regions are located in the body region region between the first gate structure and the second gate structure.

[0018] Optionally, the plurality of second source implant regions comprises a plurality of first implant regions and a plurality of second implant regions.

[0019] Along a direction perpendicular to the channel width direction, each body implant region is formed with one first implant region arranged adjacent to the body implant region towards the first gate structure, and each body implant region is formed with one second implant region arranged adjacent to the body implant region towards the second gate structure.

[0020] Further, along a direction perpendicular to the channel width direction, each first source implant region is formed with one first implant region arranged adjacent to the first source implant region towards the first gate structure, and each first source implant region is formed with one second implant region arranged adjacent to the first source implant region towards the second gate structure.

[0021] Optionally, the second source implant regions comprise a plurality of first implant regions and a plurality of second implant regions.

[0022] Along a direction perpendicular to the channel width direction, each body implant region of an odd column is formed with one first implant region arranged adjacent to the body implant region towards the first gate structure, and each body implant region of an even column is formed with one second implant region arranged adjacent to the body implant region towards the second gate structure.

[0023] Optionally, part of the second source implant regions are located under the gate structure.

[0024] Optionally, a projection of at least part of the plurality of body implant regions on an upper surface of the epitaxial layer has a rectangular shape.

[0025] Alternatively, a shape of a projection of an upper surface of the epitaxial layer onto the at least part of the plurality of body region implantation regions is a rhombus.

[0026] Optionally, the substrate, the epitaxial layer, the drift region, the drain implantation region and the source implantation region have a first doping type,

[0027] The body region and the plurality of body region implantation regions have a second doping type.

[0028] Optionally, the first doping type is one of P-type doping and N-type doping, and the second doping type is the other of P-type doping and N-type doping.

[0029] According to a second aspect of the present application, there is provided a method for manufacturing a LDMOS device, comprising:

[0030] forming a gate structure on a substrate;

[0031] forming a drift region at a drain end region of the LDMOS device and a drain end implantation region within the drift region;

[0032] forming a body region at a source end region of the LDMOS device, a plurality of body region implantation regions within the body region and a plurality of first source implantation regions, the plurality of first source implantation regions and the plurality of body region implantation regions being alternately distributed in a channel width direction of the LDMOS device;

[0033] forming a plurality of second source implantation regions at side edge regions of the plurality of body region implantation regions towards the drift region to form source implantation regions being connected in the channel width direction.

[0034] Optionally, the gate structure comprises a first gate structure and a second gate structure.

[0035] The method for forming the plurality of second source implantation regions comprises:

[0036] providing a first implantation window extending in the channel width direction at an interface region of the first gate structure and the body region, a portion of the first gate structure being exposed within the first implantation window, and a portion of each body region implantation region and a portion of each first source implantation region being also exposed within the first implantation window;

[0037] providing a second implantation window extending in the channel width direction at an interface region of the second gate structure and the body region, a portion of the second gate structure being exposed within the second implantation window, and a portion of each body region implantation region and a portion of each first source implantation region being also exposed within the second implantation window;

[0038] performing ion implantation within the first implantation window to form a plurality of first implantation regions.

[0039] performing ion implantation in the second implantation windows to form a plurality of second implantation regions;

[0040] wherein, along a direction perpendicular to the channel width direction, each of the body region implantation regions is formed with one first implantation region adjacent to the body region implantation region on a side of the first gate structure, each of the body region implantation regions is formed with one second implantation region adjacent to the body region implantation region on a side of the second gate structure, and each of the first source implantation regions is formed with one first implantation region adjacent to the first source implantation region on a side of the first gate structure, each of the first source implantation regions is formed with one second implantation region adjacent to the first source implantation region on a side of the second gate structure.

[0041] Optionally, the gate structure comprises a first gate structure and a second gate structure.

[0042] The method for forming the plurality of second source implantation regions comprises:

[0043] one first implantation window is arranged at a junction region of the first gate structure and each of the odd column body region implantation regions, each of the first implantation windows exposes at least a portion of the first gate structure, and each of the first implantation windows further exposes at least a portion of the corresponding odd column body region implantation region;

[0044] one second implantation window is arranged at a junction region of the second gate structure and each of the even column body region implantation regions, each of the second implantation windows exposes at least a portion of the second gate structure, and each of the second implantation windows further exposes at least a portion of the corresponding even column body region implantation region;

[0045] performing ion implantation in the first implantation windows to form a plurality of first implantation regions;

[0046] performing ion implantation in the second implantation windows to form a plurality of second implantation regions;

[0047] wherein, along a direction perpendicular to the channel width direction, each of the odd column body region implantation regions is formed with one first implantation region adjacent to the body region implantation region on a side of the first gate structure, each of the even column body region implantation regions is formed with one second implantation region adjacent to the body region implantation region on a side of the second gate structure.

[0048] Optionally, the gate structure comprises a first gate structure and a second gate structure.

[0049] The method for forming the plurality of second source implantation regions comprises:

[0050] a first implantation window is arranged at a junction region between the first gate structure and each body region implantation region, each first implantation window exposes at least a portion of the first gate structure, and each first implantation window also exposes at least a portion of a corresponding body region implantation region;

[0051] a second implantation window is arranged at a junction region between the second gate structure and each body region implantation region, each second implantation window exposes at least a portion of the second gate structure, and each second implantation window also exposes at least a portion of a corresponding body region implantation region;

[0052] ion implantation is performed in the plurality of first implantation windows to form a plurality of first implantation regions;

[0053] ion implantation is performed in the plurality of second implantation windows to form a plurality of second implantation regions;

[0054] wherein, along a direction perpendicular to the channel width direction, each body region implantation region is formed with a first implantation region adjacent to the body region implantation region on a side of the body region implantation region facing the first gate structure, and each body region implantation region is formed with a second implantation region adjacent to the body region implantation region on a side of the body region implantation region facing the second gate structure.

[0055] The application has at least the following beneficial effects:

[0056] The LDMOS device and the manufacturing method thereof provided by the application optimizes the source region layout of the device, and the plurality of first source implantation regions and the plurality of body region implantation regions are alternately distributed in the body region in the channel width direction of the LDMOS device, so that the cell pitch of the device is no longer limited by the width and interval of the source implantation region and the body region implantation region, the cell pitch of the device is greatly reduced, the specific on-resistance of the device is reduced, and by reasonably designing the distance between the two adjacent body region implantation regions, the body region width of the device can also be reduced, so that the safe working area of the device is greatly improved. On this basis, the application further provides a plurality of second source implantation regions on the side of the plurality of body region implantation regions facing the gate structure, so that the source implantation region connected along the channel width direction of the LDMOS device can be formed in the body region of the device, which effectively compensates for the layout of the plurality of body region implantation regions for the device channel, so that the cell pitch of the device is reduced while the drain current of the device is optimized, and the balance between the cell pitch, the drain current and the electrical safety working area of the device is better achieved.

[0057] It should be noted that the foregoing general description and the following detailed description are only exemplary and explanatory, and cannot limit the application. BRIEF DESCRIPTION OF DRAWINGS

[0058] Figure 1A cross-sectional structure schematic diagram of an LDMOS device is shown;

[0059] Figure 2 A cross-sectional structure schematic diagram of a source region in an LDMOS device is shown;

[0060] Figure 3 An embodiment schematic diagram of a layout of an implant region in an LDMOS device in the related art is shown;

[0061] Figure 4 Another embodiment schematic diagram of a layout of an implant region in an LDMOS device in the related art is shown;

[0062] Figure 5 An embodiment schematic diagram of a layout of an implant region in an LDMOS device in the related art is shown; Figure 3 A cross-sectional view of a corresponding LDMOS device at C1 is shown;

[0063] Figure 6 An embodiment schematic diagram of a layout of an implant region in an LDMOS device according to an embodiment of the present application is shown;

[0064] Figure 7 An embodiment schematic diagram of a layout of an implant region in an LDMOS device according to an embodiment of the present application is shown;

[0065] Figure 8 An embodiment schematic diagram of a layout of an implant region in an LDMOS device according to an embodiment of the present application is shown;

[0066] Figure 9 An embodiment schematic diagram of a layout of an implant region in an LDMOS device according to an embodiment of the present application is shown;

[0067] Figure 10 An embodiment schematic diagram of a layout of an implant region in an LDMOS device according to an embodiment of the present application is shown; Figure 6 A cross-sectional view of a corresponding LDMOS device at A1 is shown;

[0068] Figure 11 An embodiment schematic diagram of a layout of an implant region in an LDMOS device according to an embodiment of the present application is shown; Figure 6 A cross-sectional view of a corresponding LDMOS device at B is shown;

[0069] Figure 12 An embodiment schematic diagram of a layout of an implant region in an LDMOS device according to an embodiment of the present application is shown; Figure 7 A cross-sectional view of a corresponding LDMOS device at C2 is shown;

[0070] Figure 13 An embodiment schematic diagram of a layout of an implant region in an LDMOS device according to an embodiment of the present application is shown; Figure 8 A cross-sectional view of a corresponding LDMOS device at A2 is shown;

[0071] Figure 14 An embodiment schematic diagram of a layout of an implant region in an LDMOS device according to an embodiment of the present application is shown;

[0072] Figure 15 An embodiment of a method for manufacturing an LDMOS device is shown. DETAILED DESCRIPTION

[0073] For the purpose of clarity, the present application will be described with reference to the accompanying drawings in which preferred embodiments of the application are shown. The application may, however, be embodied in different forms, not just the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and fully convey the scope of the application to the skilled in the art.

[0074] Reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the application. Thus, the appearances of the phrases "in one embodiment" or "in some embodiments" in various places throughout this specification are not necessarily all referring to the same embodiment, but can refer to different embodiments, although the phrases can be used to describe particular implementations of example embodiments of the application. The terms "including," "comprising," "having," and variations thereof are meant to encompass the items listed thereafter and equivalents thereof as well as additional items.

[0075] In the description of the application, the word "exemplary" or "for example" is used to mean "an example of" or "an example, only. Any implementation described herein as "exemplary" or "for example" is not necessarily to be construed as preferred or advantageous over other implementations. The term "plurality" refers to two or more. In addition, the term "first", "second", etc. are used herein only to identify one of a number of similar items or conditions, and do not require or imply a specific order or sequence. The term "on" or "onto" refers to direct contact between two items or conditions, unless otherwise noted.

[0076] In describing the structure of devices, when a layer, a region is referred to as being "on" or "over" another layer, another region, it can be directly on or over the other layer, another region, or intervening layers or regions can also be present. In addition, if the device is turned over, the layer, the region will be "under" or "beneath" the other layer, another region.

[0077] If for the purpose of description, the expression "A directly on B" or "A directly on and adjacent to B" is used herein. In the present application, "A directly in B" means A is in B and A is directly adjacent to B, not A is in the doped region formed by B.

[0078] Unless otherwise specifically noted, the various layers or regions of the semiconductor device can be formed of materials known to those skilled in the art. Semiconductor materials include, for example, III-V semiconductors such as GaAs, InP, GaN, SiC, and Group IV semiconductors such as Si, Ge. The gate conductor, electrode layers can be formed of various materials that are electrically conductive, such as a metal layer, a doped polysilicon layer, or a stack gate conductor including a metal layer and a doped polysilicon layer, or other electrically conductive materials such as TaC, TiN, TaSiN, HfSiN, TiSiN, TiCN, TaAlC, TiAlN, TaN, PtSix, Ni3Si, Pt, Ru, W, and combinations of the various conductive materials.

[0079] In addition, like reference numerals in the figures indicate like or similar structure, and so description thereof will not be repeated, i.e., the various portions of the specification are described using a combination of parallel and progressive description, with each portion highlighting differences from other portions, and the same or similar portions are cross-referenced among the various portions.

[0080] The specific embodiments of the present application will be further described in conjunction with the drawings and examples.

[0081] Figure 1 A cross-sectional structure schematic of an LDMOS device is shown, referring to Figure 1 The LDMOS device generally includes a substrate 101, a buried layer 102 and an epitaxial layer 103 formed in the substrate 101, a well region 104, a drift region 105 and a body region 106 formed in the epitaxial layer 103, an implant region 113 formed in the well region 104, a drain implant region 110 formed in the drift region 105, a source implant region 111 and a body implant region 112 formed in the body region 106, a gate oxide layer 108 formed above the substrate 101 and a gate conductor layer 109 formed on the gate oxide layer 108. In some embodiments, an isolation region 107 is also formed in the epitaxial layer 103.

[0082] The drift region 105 and the drain implant region 110 inside it correspond to the drain region of the LDMOS device, the body region 106 and the source implant region 111 and the body implant region 112 inside it correspond to the source region of the LDMOS device, and by forming a metal contact on the source implant region 111, the drain implant region 110 and the gate conductor layer 109, the source electrode S, the drain electrode D and the gate electrode G of the LDMOS device can be respectively led out.

[0083] There are two conventional ways to reduce the specific on-resistance (Ronsp) of an LDMOS device: one is to fix the cell pitch of the device and increase the Idlin (drain current when the device works in the linear region) per unit width of the device; the other is to fix the Idlin of the device and reduce the cell pitch of the device. The cell pitch of the device can generally be simplified as follows: source contact region & body contact region, channel region, drift region, and drain contact region. Thanks to self-alignment process, the channel region has now been compressed to the minimum, which can be controlled within 0.1 um for BCD process; for the drift region, the cell pitch of the device cannot be compressed indefinitely due to the requirement of BV (breakdown voltage); for the drain contact region, this part is mainly limited by the size of the CT hole and the design rule of the AA CT package, which accounts for a very small proportion and has little optimization significance; and for the source contact region & body contact region, this part is usually limited by the process manufacturing capability, i.e., the width of the body contact region (also referred to as body implant region in this paper) and the space of the source contact region (also referred to as source implant region in this paper), which is difficult to compress.

[0084] Reference Figure 2 , Wsp represents the width dimension of the body implant region 112 in the LDMOS device. For the way of optimizing the overall size of the device by optimizing the size of the source contact region & body contact region, thereby reducing the cell pitch of the device, to reduce the Ronsp of the LDMOS device, one way in the related art is to define the device size by using the width and space design rule of the source implant region 111 and the body implant region 112. Taking 0.18 um line width as an example, the typical value of the width (or the space of the source implant region 111) of the body implant region 112 Wsp is 0.44 um, and the boundary distance between the body region 106 and the source implant region 111 considering process fluctuation is usually a certain fixed small size, eg: 0.3 um. That is to say, in the LDMOS device manufactured by using the existing process steps, there is usually a cell pitch of about 1.04 um between the source end region and the drain end region (for example, between the drain implant region and the body implant region 112). For low-voltage switch-type LDMOS devices below 30V, the top cell pitch is usually less than 3 microns, and for devices below 10V, the top cell pitch can even be as small as a few tenths of a micron. At this time, the size proportion of the source implant region 111 / body implant region 112 of the device is particularly prominent.

[0085] It should be noted that, Figure 1 and Figure 2The source implant region 111 and the body implant region 112 shown in the middle are only an abstract representation for facilitating the understanding of the width dimension of the source implant region 111 and the body implant region 112 in the body region 106. In actual LDMOS devices, only one of the source implant region 111 and the body implant region 112 in the body region 106 can be actually cut in the LDMOS cross section shown, which can be understood in detail with reference to subsequent embodiments and drawings. Figure 1 The source implant region 111 and the body implant region 112 shown in the middle are only an abstract representation for facilitating the understanding of the width dimension of the source implant region 111 and the body implant region 112 in the body region 106. In actual LDMOS devices, only one of the source implant region 111 and the body implant region 112 in the body region 106 can be actually cut in the LDMOS cross section shown, which can be understood in detail with reference to subsequent embodiments and drawings.

[0086] Figure 3 An embodiment of the layout of the implant regions of the LDMOS device in the related art is shown, Figure 4 Another embodiment of the layout of the implant regions of the LDMOS device in the related art is shown, Figure 5 An embodiment of the layout of the implant regions of the LDMOS device in the related art is shown, Figure 3 A cross-sectional view of the corresponding LDMOS device at C1.

[0087] In some related art, the layout of the source implant region and the body implant region of the LDMOS device is as shown in Figure 3 or Figure 4 , wherein 111c and 112c respectively represent the implantation window of the source implant region 111 and the body implant region 112 in the LDMOS device, which defines the horizontal cross-sectional shape of the source implant region 111 and the body implant region 112 and their distribution in the LDMOS device. Specifically, in combination with Figure 1 , Figure 3 and Figure 4 , from the perspective of the top view of the LDMOS device, the source implant region 111 and the body implant region 112 are located in the body region between the two gate structures (such as between the left and right gate conductor layers 109), and the source implant region 111 and the body implant region 112 are alternately distributed in the channel width direction of the LDMOS device. Among them, Figure 3 An example is shown in which the implantation window 112c of the body implant region 112 is in a rectangular shape, and the horizontal cross section of the body implant region 112 formed by the implantation window 112c is also in a rectangular shape, Figure 4 An example is shown in which the implantation window 112c of part of the body implant region 112 is in a rectangular shape, and the implantation window 112c of part of the body implant region 112 is in a rhombus shape. The horizontal cross section of the body implant region 112 formed by the implantation window 112c is partially in a rectangular shape and partially in a rhombus shape.

[0088] or Figure 3 or Figure 4In the manner of the first aspect, on one hand, the cell pitch of the device is no longer limited by the width and space of the source implant region 111 and the body implant region 112, which greatly reduces the cell pitch of the device, thereby reducing the specific on-resistance of the device; on the other hand, by reasonably designing the distance between the two adjacent body implant regions 112, the body width (body res) of the device can also be reduced, thereby greatly improving the esoa (Electrical safety Operation area, safety operating area or electrical safety operating area) of the device. However, in the manner of the first aspect or the second aspect, the effective channel width is sacrificed, as shown in Figure 3 Figure 4 Figure 5 As shown in the figure, on the channel side of the gate structure of the device, the effective channel width is only approximately equal to the sum of the widths of the plurality of source implant regions 111, i.e., W11+W12+W13, which is less than the body width of the device, resulting in a decrease in idlin.

[0089] Based on this, the present application provides a new optimization scheme, which optimizes the layout of the source implant region and the body implant region in the LDMOS device, so as to reduce the cell pitch of the device while also optimizing the drain current (idlin) of the device, thereby better achieving the balance between the cell pitch, the drain current and the electrical safety operating area of the device.

[0090] Figure 6 A first embodiment of the layout of the implant region of the LDMOS device provided by the present application is shown, Figure 7 A second embodiment of the layout of the implant region of the LDMOS device provided by the present application is shown, Figure 8 A third embodiment of the layout of the implant region of the LDMOS device provided by the present application is shown, Figure 9 A fourth embodiment of the layout of the implant region of the LDMOS device provided by the present application is shown, Figure 10 A corresponding cross-sectional view of the LDMOS device at A1 is shown, Figure 6 A corresponding cross-sectional view of the LDMOS device at B is shown, Figure 11 A corresponding cross-sectional view of the LDMOS device at C2 is shown, Figure 6 A corresponding cross-sectional view of the LDMOS device at A2 is shown, Figure 12 A corresponding cross-sectional view of the LDMOS device at C3 is shown, Figure 7 A corresponding cross-sectional view of the LDMOS device at A2 is shown, Figure 13 A corresponding cross-sectional view of the LDMOS device at C3 is shown, Figure 8 A corresponding cross-sectional view of the LDMOS device at A2 is shown, Figure 14 A corresponding cross-sectional view of the LDMOS device at C3 is shown, Figure 9 A corresponding cross-sectional view of the LDMOS device at A2 is shown, Figure 14 ​​A fifth embodiment of the layout of the implantation region of the LDMOS device is shown.

[0091] In combination Figure 1 , Figure 6 , Figure 7 , Figure 8 , Figure 9 and Figure 14 , in an embodiment of the present application, the LDMOS device comprises: a substrate 101; a buried layer 102 and an epitaxial layer 103 on the substrate 101; a well region 104, a drift region 105 and a body region 106 in the epitaxial layer 103; an implantation region 113 in the well region 104; a drain implantation region 110 in the drift region 105; a source implantation region and a plurality of body implantation regions 112 in the body region 106; and a gate structure on the epitaxial layer 103 and across the drift region 105 and the body region 106.

[0092] The drift region 105 and the drain implantation region 110 inside the drift region 105 correspond to the drain region of the LDMOS device, the body region 106 and the source implantation region and the body implantation regions 112 inside the body region 106 correspond to the source region of the LDMOS device, and by forming a metal contact on the source implantation region, the drain implantation region 110 and the gate conductor layer 109, the source electrode S, the drain electrode D and the gate electrode G of the LDMOS device can be respectively led out.

[0093] In some embodiments, an isolation region 107 is further formed in the epitaxial layer 103.

[0094] In an embodiment of the present application, the gate structure in the LDMOS device comprises: a first gate structure and a second gate structure arranged oppositely, wherein the first gate structure is across the first end of the drift region 105 and the body region 106, and the second gate structure is across the second end of the drift region 105 and the body region 102, in other words, the first side edge region of the body region 106 is below the first gate structure, and the second side edge region of the body region 106 is below the second gate structure. The plurality of body implantation regions 112 are in the body region between the first gate structure and the second gate structure.

[0095] It can be understood that, when ion implantation or doping is performed, due to the diffusion effect, in some embodiments, when the corresponding implantation is performed in the body region to form the plurality of body implantation regions 112, each body implantation region 112 can also have a portion below the first gate structure and the second gate structure.

[0096] Further, the first gate structure and the second gate structure each comprise: a gate oxide layer 108 and a gate conductor layer 109 on the gate oxide layer 108. The gate oxide layer 108 is, for example, a silicon oxide layer, and the gate conductor layer 109 is, for example, a polysilicon layer.

[0097] In some other embodiments, other dielectric layers are further provided between the gate oxide layer 108 and the gate conductor layer 109, or below the gate oxide layer 108 or above the gate conductor layer 109.

[0098] In the present embodiment, the substrate 101, the epitaxial layer 103, the drift region 105, the drain implant region 110 and the source implant region are of a first doping type, and the buried layer 102, the body region 106 and the plurality of body implant regions 112 are of a second doping type. Optionally, the first doping type is one of P-type doping and N-type doping, and the second doping type is the other of P-type doping and N-type doping, wherein the doping ions of P-type doping include but are not limited to boron ions, and the doping ions of N-type doping include but are not limited to phosphorus, arsenic, antimony, etc.

[0099] In the present embodiment, the source implant region includes a plurality of first source implant regions 111 and a plurality of second source implant regions. The plurality of first source implant regions 111 and the plurality of body implant regions 112 are alternately distributed in the channel width direction of the LDMOS device, i.e., one first source implant region 111 is provided between every two adjacent body implant regions 112. In this way, the cell pitch of the device is no longer limited by the width and spacing of the plurality of first source implant regions and body implant regions, greatly reducing the cell pitch of the device and reducing the specific on-resistance of the device. By reasonably designing the distance between the two adjacent body implant regions 112, the width of the body region of the device can also be reduced, thereby greatly improving the safe operating area of the device.

[0100] Reference is made to Figure 1 , Figures 6-14 , wherein 111c and 112c represent the implantation windows of the first source implant region 111 and the body implant region 112 in the LDMOS device, respectively, which define the horizontal cross-sectional shape and distribution of the source implant region 111 and the body implant region 112 in the LDMOS device. Specifically, in some embodiments, reference is made to Figure 6 , Figure 8 and Figure 14 The implantation windows 112c of the plurality of body implant regions 112 are in a rectangular shape, and the horizontal cross-sections of the body implant regions 112 formed via the implantation windows 112c are also in a rectangular shape. In other embodiments, reference is made to Figure 7 and Figure 9 The implantation windows 112c of some of the plurality of body implant regions 112 are in a rectangular shape, and the implantation windows 112c of some of the plurality of body implant regions 112 are in a rhombus shape. The horizontal cross-sections of the body implant regions 112 formed via the implantation windows 112c are also partly in a rectangular shape and partly in a rhombus shape.

[0101] Of course, in some other embodiments, the projections of the plurality of body implant regions 112 on the upper surface of the epitaxial layer 103 can also be other common single shape layouts or combinations of multiple shapes, including but not limited to circular, semi-circular, parallelogram, trapezoidal, other irregular shapes, etc.

[0102] Further, the plurality of second source implant regions are respectively located at the side regions of the plurality of body implant regions 112 towards the gate structure. In this embodiment, the plurality of first source implant regions 611 and the plurality of second source implant regions 612 contain the same type of implant ions. Compared with the conventional scheme, this application is equivalent to adding a plurality of second source implant regions in the body region 106 near the junction region of the body region 106 and the gate structure by using additional implant layout design (for example, the implant windows 611c and 612c shown in Figures 6-9 and Figure 14 , so that the part of the plurality of body implant regions 112 close to the gate structure can exhibit the characteristics of the source implant region, so that in the body region 106 of the device, the source implant regions with the same type of ion implantation can be formed along the channel width direction of the LDMOS device, effectively compensating for the layout mode of the plurality of body implant regions for the sacrifice of the device channel, so that while reducing the cell pitch of the device, the drain current of the device can also be optimized, and the balance between the cell pitch, the drain current and the electrical safety working area of the device is better achieved.

[0103] Further, the plurality of second source implant regions include a plurality of first implant regions 611 and a plurality of second implant regions 612. Referring to Figures 6-14 , wherein 611c and 612c respectively represent the implant windows of the first implant region 611 and the body implant region 612 in the LDMOS device, which define the distribution of the plurality of first implant regions 611 and the plurality of second implant regions 612 in the LDMOS device among the plurality of second source implant regions formed.

[0104] It should be noted that in the overlapping region of each first implant region 611, each second implant region 612 and the body implant region 112, there are both first type of implant ions and second type of implant ions, so that this part of the overlapping region can have the characteristics of the source implant region.

[0105] In some embodiments, referring to Figure 14 and Figure 10In the direction perpendicular to the channel width, two sides of each body region implantation region 112 are respectively formed with a first implantation region 611 and a second implantation region 612 adjacent to the body region implantation region, i.e., the plurality of first implantation regions 611 are respectively located at the side edge regions of the plurality of body region implantation regions 112 towards the first gate structure, and the plurality of second implantation regions 612 are respectively located at the side edge regions of the plurality of body region implantation regions 112 towards the second gate structure. That is to say, in these embodiments, only the side edges of the body region implantation regions 112 towards the gate structure are formed with the second source implantation region. Further, since the first implantation region 611, the second implantation region 612 and the first source implantation region 111 contain the same type of implantation ions, in the junction region of the body region 106 and the gate structure, a source implantation region with the same ion implantation type along the channel width direction of the LDMOS device can be formed in the body region 106 of the device. It can be understood that at this time, in the junction region of the body region 106 and the gate structure, the effective channel width of the LDMOS device is equal to the total width of the plurality of first implantation regions 611 (or the plurality of second implantation regions 612) and the plurality of first source implantation regions 111, and the total width is greater than W11+W12+W13, thereby effectively compensating for the layout mode of the plurality of body region implantation regions for the sacrifice of the device channel.

[0106] In other embodiments, with reference to Figure 6 、 Figure 7 、 Figure 10 and Figure 11 , in the direction perpendicular to the channel width, one side of each body region implantation region 112 towards the first gate structure is formed with a first implantation region 611 adjacent to the body region implantation region, one side of each body region implantation region 112 towards the second gate structure is formed with a second implantation region 612 adjacent to the body region implantation region, one side of each first source implantation region 111 towards the first gate structure is formed with a first implantation region 611 adjacent to the first source implantation region, and one side of each first source implantation region 111 towards the second gate structure is formed with a second implantation region 612 adjacent to the first source implantation region, i.e., the plurality of first implantation regions 611 are respectively located at the side edge regions of the plurality of body region implantation regions 112 and the plurality of first source implantation regions 111 towards the first gate structure, and the plurality of second implantation regions 612 are respectively located at the side edge regions of the plurality of body region implantation regions 112 and the plurality of first source implantation regions 111 towards the second gate structure. That is to say, in these embodiments, the side edges of the body region implantation regions 112 and the first source implantation regions 111 towards the gate structure are simultaneously formed with the second source implantation region. With reference to Figure 12In the embodiments, in the vicinity of the junction region of the body region 106 and the gate structure, source implantation regions 612 and 611 (611 not shown) of the same ion implantation type which are connected along the channel width direction of the LDMOS device can be formed in the body region 106 of the device, and at this time, in the vicinity of the junction region of the body region 106 and the gate structure, the effective channel width of the LDMOS device is equal to the width W2 of the connected source implantation region 612, and it can be understood that W2 is greater than W11+W12+W13, thereby effectively compensating for the layout mode of the plurality of body implantation regions for the sacrifice of the device channel.

[0107] In still other embodiments, with reference to Figure 8 and Figure 9 In the embodiments, in the vicinity of the junction region of the body region 106 and the gate structure, source implantation regions 612 and 611 (611 not shown) of the same ion implantation type which are connected along the channel width direction of the LDMOS device can be formed in the body region 106 of the device, and at this time, in the vicinity of the junction region of the body region 106 and the gate structure, the effective channel width of the LDMOS device is equal to the width W2 of the connected source implantation region 612, and it can be understood that W2 is greater than W11+W12+W13, thereby effectively compensating for the layout mode of the plurality of body implantation regions for the sacrifice of the device channel.

[0108] It can be understood that Figure 6 , Figure 7 and Figure 14 In the embodiments shown in FIGS. 11 and 12, the maximum length (along the channel length direction of the LDMOS device) of the second source implantation region which can be formed in the LDMOS device is easily restricted by the gap Ssn between the first implantation region 611 and the second implantation region 612, and especially when the gap between the first gate structure and the second gate structure is small, due to the restriction of the gap Ssn, a second source implantation region which is wide enough along the channel length direction of the LDMOS device cannot be formed, thereby resulting in limited compensation or no compensation at all. On this basis, by adopting the layout mode shown in FIGS. 13 and 14, the maximum length (along the channel length direction of the LDMOS device) of the second source implantation region which can be formed in the LDMOS device is no longer restricted by the gap Ssn between the first implantation region 611 and the second implantation region 612, and the maximum length of the second source implantation region which can be formed in the LDMOS device is increased, thereby effectively compensating for the layout mode of the plurality of body implantation regions for the sacrifice of the device channel. Figure 8 and Figure 9The multiple second source injection regions arranged alternately on the left and right of the multiple body region injection regions 112 can make the length of the formed multiple second source injection regions in the channel length direction of the LDMOS device not be restricted by the gap Ssn, so that a better compensation effect can be achieved.

[0109] It is verified that, compared with the solutions in Figure 3 and Figure 4 , the technical solutions provided by the embodiments of the present application can achieve at least 50% stable compensation effect on the device channel, and can better balance the cell pitch, drain current and electrical safety working area of the device.

[0110] Further, the embodiments of the present application also provide a manufacturing method of an LDMOS device, Figure 15 An embodiment of the manufacturing method of the LDMOS device provided by the embodiments of the present application is shown, and the manufacturing method is used to manufacture the LDMOS device disclosed in the foregoing embodiments of the present application, and the specific implementation of the two can be referred to each other. Specifically, as Figure 15 shown, the manufacturing method of the LDMOS device includes performing the following steps:

[0111] In step 151, a gate structure is formed on a substrate.

[0112] In this step, the gate structure includes a first gate structure and a second gate structure. And the first gate structure and the second gate structure both include a gate oxide layer and a gate conductor layer located on the gate oxide layer.

[0113] In step 152, a drift region and a drain end injection region located in the drift region are formed in a drain end region of the LDMOS device.

[0114] In step 153, a body region, multiple body region injection regions and multiple first source injection regions located in the body region are formed in a source end region of the LDMOS device, and the multiple first source injection regions and the multiple body region injection regions are alternately distributed in the channel width direction of the LDMOS device.

[0115] In step 154, multiple second source injection regions are formed on the side of the multiple body region injection regions towards the drift region.

[0116] The various layer structures of the LDMOS device can be formed by using various existing processes.

[0117] In this embodiment, on the basis of performing step 153, the injection window 611c and 612c corresponding to the injection region 611 and 612 shown in any one of Figures 6 to 9 , and Figure 14 may be used to perform the injection and formation of the multiple second source injection regions.

[0118] Specifically, in some embodiments, with reference to Figure 6 and Figure 7 , step 154 further comprises: providing, at the interface region between the first gate structure and the body region, a first implantation window extending along the channel width direction, the first implantation window exposing a portion of the first gate structure, and the first implantation window also exposing a portion of each body region implantation region and a portion of each first source implantation region; providing, at the interface region between the second gate structure and the body region, a second implantation window extending along the channel width direction, the second implantation window exposing a portion of the second gate structure, and the second implantation window also exposing a portion of each body region implantation region and a portion of each first source implantation region; performing ion implantation in the first implantation window to form a plurality of first implantation regions; performing ion implantation in the second implantation window to form a plurality of second implantation regions; wherein, along a direction perpendicular to the channel width direction, each body region implantation region is formed with one first implantation region adjacent to the body region implantation region on a side of the body region implantation region facing the first gate structure, each body region implantation region is formed with one second implantation region adjacent to the body region implantation region on a side of the body region implantation region facing the second gate structure, and each first source implantation region is formed with one first implantation region adjacent to the first source implantation region on a side of the first source implantation region facing the first gate structure, each first source implantation region is formed with one second implantation region adjacent to the first source implantation region on a side of the first source implantation region facing the second gate structure.

[0119] In other embodiments, with reference to Figure 8 and Figure 9 , step 154 further comprises: providing, at the interface region between the first gate structure and each odd column of body region implantation regions, one first implantation window, each first implantation window exposing at least a portion of the first gate structure, and each first implantation window also exposing at least a portion of a corresponding odd column of body region implantation regions; providing, at the interface region between the second gate structure and each even column of body region implantation regions, one second implantation window, each second implantation window exposing at least a portion of the second gate structure, and each second implantation window also exposing at least a portion of a corresponding even column of body region implantation regions; performing ion implantation in the plurality of first implantation windows to form a plurality of first implantation regions; performing ion implantation in the second implantation windows to form a plurality of second implantation regions; wherein, along a direction perpendicular to the channel width direction, each odd column of body region implantation regions is formed with one first implantation region adjacent to the body region implantation region on a side of the body region implantation region facing the first gate structure, and each even column of body region implantation regions is formed with one second implantation region adjacent to the body region implantation region on a side of the body region implantation region facing the second gate structure.

[0120] In yet other embodiments, with reference to Figure 14The step 154 further comprises: setting a first implantation window at the junction area of the first gate structure and each body region implantation region, each first implantation window exposing at least part of the first gate structure and part of the corresponding body region implantation region; setting a second implantation window at the junction area of the second gate structure and each body region implantation region, each second implantation window exposing at least part of the second gate structure and part of the corresponding body region implantation region; performing ion implantation in the first implantation windows to form a plurality of first implantation regions; and performing ion implantation in the second implantation windows to form a plurality of second implantation regions; wherein, along a direction perpendicular to the channel width direction, each body region implantation region forms a first implantation region adjacent to the body region implantation region on a side of the body region implantation region facing the first gate structure, and forms a second implantation region adjacent to the body region implantation region on a side of the body region implantation region facing the second gate structure.

[0121] Finally, it should be noted that the above-mentioned embodiments are merely exemplary for clearly illustrating the present application, and are not intended to limit the embodiments. Based on the above description, other different forms of changes or variations can be made by those skilled in the art. Here, it is not necessary and impossible to enumerate all the embodiments. The changes or variations derived therefrom are still within the protection scope of the present application.

Claims

1. An LDMOS device, comprising: Epitaxial layer, located on the substrate; The drift region and the volume region are located in the epitaxial layer; A gate structure is located on the epitaxial layer and spans the drift region and the body region; The drain injection region is located within the drift region; The source injection region and multiple body injection regions are located within the body region; The source injection region includes: a plurality of first source injection regions and a plurality of second source injection regions; The plurality of first source injection regions and the plurality of body injection regions are alternately distributed in the channel width direction of the LDMOS device; The plurality of second source injection regions are located on the side regions of the plurality of body injection regions facing the gate structure, so as to form source injection regions that are connected along the channel width direction.

2. The LDMOS device according to claim 1, wherein, The plurality of first source injection regions and the plurality of second source injection regions contain the same type of injected ions.

3. The LDMOS device according to claim 1, wherein, The gate structure includes: a first gate structure and a second gate structure disposed opposite to each other; The first side region of the body region is located below the first gate structure, and the second side region of the body region is located below the second gate structure; The plurality of body injection regions are located within the body region between the first gate structure and the second gate structure.

4. The LDMOS device according to claim 3, wherein, The plurality of second source injection regions include: a plurality of first injection regions and a plurality of second injection regions; Along the direction perpendicular to the channel width, each body injection region has a first injection region formed on the side facing the first gate structure, which is adjacent to the body injection region, and each body injection region has a second injection region formed on the side facing the second gate structure, which is adjacent to the body injection region.

5. The LDMOS device according to claim 4, wherein, Along the direction perpendicular to the channel width, each first source injection region has a first injection region disposed adjacent to the first gate structure on the side facing the first source injection region, and each first source injection region has a second injection region disposed adjacent to the first source injection region on the side facing the second gate structure.

6. The LDMOS device according to claim 3, wherein, The second source injection region includes: a plurality of first injection regions and a plurality of second injection regions; Along the direction perpendicular to the channel width, each odd-numbered column of body injection regions has a first injection region formed on the side facing the first gate structure, which is adjacent to the body injection region. Each even-numbered column of body injection regions has a second injection region formed on the side facing the second gate structure, which is adjacent to the body injection region.

7. The LDMOS device according to any one of claims 1-6, wherein, A portion of the second source injection region is located below the gate structure.

8. The LDMOS device according to any one of claims 1-6, wherein, At least a portion of the multiple body injection regions have a rectangular shape in the projection onto the upper surface of the epitaxial layer; Alternatively, at least a portion of the multiple body injection regions have a rhomboid shape in the projection onto the upper surface of the epitaxial layer.

9. The LDMOS device according to claim 1, wherein, The substrate, the epitaxial layer, the drift region, the drain injection region, and the source injection region have a first doping type. The body region and the plurality of body region implantation regions have a second doping type.

10. The LDMOS device according to claim 9, wherein, The first doping type is one of P-type doping and N-type doping, and the second doping type is the other of P-type doping and N-type doping.

11. A method for manufacturing an LDMOS device, comprising: A gate structure is formed on the substrate; A drift region and a drain injection region located within the drift region are formed in the drain region of the LDMOS device; A body region is formed in the source region of the LDMOS device, and a plurality of body injection regions and a plurality of first source injection regions are located in the body region. The plurality of first source injection regions and the plurality of body injection regions are alternately distributed in the channel width direction of the LDMOS device. Multiple second source injection regions are formed in the side regions of the multiple body injection regions facing the drift region to form source injection regions that are connected along the channel width direction.

12. The manufacturing method according to claim 11, wherein, The gate structure includes a first gate structure and a second gate structure; Methods for forming multiple second source injection regions include: A first injection window extending along the channel width direction is provided at the boundary region between the first gate structure and the body region. The first injection window exposes a portion of the first gate structure, and also exposes a portion of each body region injection region and a portion of each first source injection region. A second injection window extending along the channel width direction is provided at the boundary region between the second gate structure and the body region. The second injection window exposes a portion of the second gate structure, and also exposes a portion of each body region injection region and a portion of each first source injection region. Ion implantation is performed within the first implantation window to form multiple first implantation regions; Ion implantation is performed within the second implantation window to form multiple second implantation regions; Specifically, along a direction perpendicular to the channel width, each body injection region has a first injection region adjacent to the body injection region on the side facing the first gate structure, and each body injection region has a second injection region adjacent to the body injection region on the side facing the second gate structure. Furthermore, each first source injection region has a first injection region adjacent to the first source injection region on the side facing the first gate structure, and each first source injection region has a second injection region adjacent to the first source injection region on the side facing the second gate structure.

13. The manufacturing method according to claim 11, wherein, The gate structure includes a first gate structure and a second gate structure; Methods for forming multiple second source injection regions include: A first injection window is provided at the boundary between the first gate structure and the body injection region of each odd-numbered column. Each first injection window exposes at least a portion of the first gate structure and at least a portion of the corresponding odd-numbered column body injection region. A second injection window is provided at the boundary between the second gate structure and the body injection region of each even-numbered column. Each second injection window exposes at least a portion of the second gate structure and at least a portion of the corresponding even-numbered column's body injection region. Ion implantation is performed within the plurality of first implantation windows to form a plurality of first implantation regions; Ion implantation is performed within the plurality of second implantation windows to form a plurality of second implantation regions; In this configuration, along the direction perpendicular to the channel width, each odd-numbered column of body injection regions has a first injection region formed on the side facing the first gate structure, which is adjacent to the body injection region. Each even-numbered column of body injection regions has a second injection region formed on the side facing the second gate structure, which is adjacent to the body injection region.

14. The manufacturing method according to claim 11, wherein, The gate structure includes a first gate structure and a second gate structure; Methods for forming multiple second source injection regions include: A first injection window is provided at the boundary region between the first gate structure and each body injection region. Each first injection window exposes at least a portion of the first gate structure and at least a portion of the corresponding body injection region. A second injection window is provided at the boundary region between the second gate structure and each body injection region. Each second injection window exposes at least a portion of the second gate structure and at least a portion of the corresponding body injection region. Ion implantation is performed within the plurality of first implantation windows to form a plurality of first implantation regions; Ion implantation is performed within the plurality of second implantation windows to form a plurality of second implantation regions; In this configuration, along the direction perpendicular to the channel width, each body injection region has a first injection region formed on the side facing the first gate structure, which is adjacent to the body injection region, and each body injection region has a second injection region formed on the side facing the second gate structure, which is adjacent to the body injection region.

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