Chip fault detection method and device, equipment and storage medium

Abstract

The invention relates to the field of chip fault detection, in particular to a chip fault detection method and device, equipment and a storage medium. The method comprises the following steps of collecting a whole-process test data set of a target chip, performing intelligent data cleaning processing, and generating a standardized test data sample; performing tiny flaw depth identification and detail expansion on the standardized test data sample to generate a flaw-expanded sample; performing normalized defect detection division based on the defect expansion sample to generate an abnormal fault precursor; performing multi-step fault prediction on the abnormal fault precursor to obtain multi-step fault evolution prediction data; and performing dynamic risk trend assessment based on the multi-step fault evolution prediction data, and performing fault diagnosis decision. According to the invention, the chip fault is accurately and efficiently detected, and the chip diagnosis efficiency is improved.

Description

Technical Field

[0001] This invention relates to the field of chip fault detection, and in particular to a chip fault detection method, apparatus, device, and storage medium. Background Technology

[0002] Throughout a chip's lifecycle, various factors such as micro-defects during manufacturing, material aging, thermal stress accumulation, and electromigration effects can gradually cause physical layer damage or performance degradation, ultimately leading to functional abnormalities or failures. Furthermore, as system complexity increases, chips may also be affected by external electromagnetic interference, power consumption fluctuations, and software faults during operation, triggering random, intermittent, or sudden latent faults. These faults are often difficult to detect promptly using traditional testing methods. Simultaneously, facing the stringent requirements of high availability and robustness for chip systems in critical fields, achieving continuous monitoring of chip health status, early identification of abnormal behavior, and accurate prediction of fault trends has become a core challenge for the safe operation of chips.

[0003] Existing chip fault detection methods primarily rely on Design for Test (DFT) structures during the design phase, built-in self-test (BIST) mechanisms, and simple monitoring tools during operation, such as power consumption monitoring, voltage sampling, and temperature sensing. While these methods can perceive the chip's operating status to some extent, they generally suffer from limited detection accuracy, low fault coverage, and an inability to dynamically predict faults. Furthermore, most existing methods depend on preset rules and manual analysis, making them ill-suited to the complex, dynamic, and non-linearly evolving fault characteristics of modern chip systems, and even more difficult to achieve intelligent fault identification and diagnosis in multi-scenario, multi-task environments. Summary of the Invention

[0004] To address the aforementioned technical problems, this invention proposes a chip fault detection method, apparatus, device, and storage medium to solve at least one of the aforementioned technical problems.

[0005] To achieve the above objectives, the present invention provides a chip fault detection method, comprising the following steps: Step S1: Collect the full-process test dataset of the target chip, perform intelligent data cleaning and processing, and generate standardized test data samples; Step S2: Perform in-depth identification and detail magnification of minor defects on the standardized test data samples to generate defect magnification samples; Step S3: Based on the expanded defect sample, perform normalized defect detection classification and generate abnormal fault precursors; Step S4: Perform multi-step fault prediction on the abnormal fault precursors to obtain multi-step fault evolution prediction data; Step S5: Perform dynamic risk trend assessment based on multi-step fault evolution prediction data, and make fault diagnosis decisions.

[0006] This specification provides a chip fault detection apparatus for performing the chip fault detection method described above, comprising: The data cleaning module is used to collect the full-process test dataset of the target chip, perform intelligent data cleaning processing, and generate standardized test data samples. The detail enhancement module is used to perform in-depth identification and detail enhancement of minor defects in standardized test data samples, generating defect-enhanced samples. The defect classification module is used to classify normal defects based on expanded defect samples and generate abnormal fault precursors; A multi-step fault prediction module is used to perform multi-step fault prediction on the abnormal fault precursors to obtain multi-step fault evolution prediction data. The fault diagnosis module is used to perform dynamic risk trend assessment based on multi-step fault evolution prediction data and to make fault diagnosis decisions.

[0007] The present invention also provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps of the chip fault detection method described in any of the preceding claims.

[0008] The present invention also provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the steps of the chip fault detection method described in any of the preceding claims.

[0009] The beneficial effects of this invention are as follows: Full-process test data includes information on the entire process from manufacturing, packaging, aging, power-on, operation to failure, providing diagnostics with breadth in terms of time and process dimensions; intelligent data cleaning (such as anomaly removal, missing data filling, and outlier smoothing) effectively removes noise interference and improves the quality of training data; standardized processing (such as normalization, format unification, and feature unification) makes subsequent AI model training more efficient, avoiding accuracy degradation due to inconsistent data formats; it provides clean and reliable input, offering high-quality learning samples for subsequent fault identification and prediction models. Deep learning models (such as high-resolution residual convolutional networks) can identify extremely small and difficult-to-detect anomalies; defect amplification operations (such as fault feature enhancement and anomaly diffusion simulation) help form more representative "potential fault precursor" samples in the training set; by amplifying and visualizing micro-defects, the problem of traditional methods ignoring "weak anomalies" can be effectively avoided; data augmentation techniques can be used to generate synthetic anomaly samples to improve the model's generalization ability. Compared to static threshold determination mechanisms, this method dynamically defines the boundary between normal and abnormal states based on a learning model. Abnormal precursors may not constitute direct failures, but they reflect the sub-health state of devices and can be used for early warning. "Boundary faults" that are difficult for conventional algorithms to identify are judged as abnormal by AI, giving the system a new ability to identify non-standard faults. The earlier abnormal precursors are identified, the earlier repair or scheduling can be intervened, improving chip lifecycle management capabilities. Starting from the current state, predictive maintenance is achieved by using temporal neural networks (such as LSTM and Transformer) to extrapolate multiple time steps into the future. This allows for a clear understanding of how abnormal signals gradually evolve into serious faults, providing insights into system-level fault propagation. Based on predictive data, safety strategies such as power reduction and task migration can be configured in advance, reducing system-level risks caused by sudden failures and enhancing the ability to respond to "black swan" events. Based on the evolution trend, the system can assess the scope of impact, urgency, and possible consequences of a fault; the AI ​​model can output a risk probability score or trend chart for fault level classification and emergency response priority allocation; such as switching operating modes (low power, partial hibernation) in real time based on risk assessment results and guiding redundant resources to take over; the risk trend assessment model can be deployed in SoC or edge chips to achieve millisecond-level decision-making. Attached Figure Description

[0010] Figure 1 This is a schematic diagram of the steps of one method of the present invention; Figure 2 This is a detailed flowchart illustrating the implementation steps of step S1. Figure 3 This is a flowchart illustrating the detailed implementation steps of step S2. Detailed Implementation

[0011] It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the scope of the invention.

[0012] This application provides a method, apparatus, device, and storage medium. The execution entities of the method, apparatus, device, and storage medium include, but are not limited to, mechanical equipment, data processing platforms, cloud server nodes, network upload devices, etc., which can be considered general computing nodes of this application. The data processing platform includes, but is not limited to, at least one of an audio / image management system, an information management system, and a cloud data management system.

[0013] Please see Figures 1 to 3 The present invention provides a method comprising the following steps: Step S1: Collect the full-process test dataset of the target chip, perform intelligent data cleaning and processing, and generate standardized test data samples; Step S2: Perform in-depth identification and detail magnification of minor defects on the standardized test data samples to generate defect magnification samples; Step S3: Based on the expanded defect sample, perform normalized defect detection classification and generate abnormal fault precursors; Step S4: Perform multi-step fault prediction on the abnormal fault precursors to obtain multi-step fault evolution prediction data; Step S5: Perform dynamic risk trend assessment based on multi-step fault evolution prediction data, and make fault diagnosis decisions.

[0014] In the embodiments of the present invention, see Figure 1 The diagram below illustrates the steps of a method according to the present invention. In this example, the steps of the method include: Step S1: Collect the full-process test dataset of the target chip, perform intelligent data cleaning and processing, and generate standardized test data samples; In this embodiment, at the initial stage of the fault diagnosis process, a complete test dataset needs to be collected from all stages of the target chip's manufacturing process, including wafer-level electrical testing, functional module logic testing, aging stress testing, and comprehensive verification after packaging. The collected data often exhibits multi-dimensionality and heterogeneity. For example, electrical parameters cover leakage current, voltage offset, and clock jitter; functional testing involves instruction accuracy and memory consistency; aging testing includes performance degradation under different temperature and stress conditions; and the packaging stage generates data such as solder joint reliability and pin contact resistance. Since the raw data inevitably contains incomplete records, mid-process exits, excessive numerical deviations, or test anomalies, intelligent data cleaning is necessary to remove invalid samples. Cleaning methods can combine threshold-based rule-based removal (e.g., current anomaly deviation exceeding ±5σ), clustering-based outlier detection (e.g., DBSCAN identifying outliers), and time-series-based outlier correction (e.g., sliding window averaging to remove abrupt changes). During this process, time-series alignment and normalization processing are also required for data from multiple batches and under multiple process conditions, for example, normalizing voltage fluctuation curves under different temperature conditions to a unified reference temperature. The final standardized test data samples can fully reflect the true characteristics of the chip and have a unified scale and timing benchmark, providing reliable input for subsequent intelligent analysis.

[0015] Step S2: Perform in-depth identification and detail magnification of minor defects on the standardized test data samples to generate defect magnification samples; In this embodiment, after obtaining standardized test data samples, the next step is to perform in-depth identification of potential minor defects. These defects often manifest as slight fluctuations in electrical parameters or local logic delay offsets, which are difficult to detect directly using conventional detection methods. Specifically, a multi-scale convolutional decomposition model is introduced to extract features from the data at different scales. Low-scale convolutional layers are used to identify macroscopic trends, such as overall voltage fluctuations; medium- and high-scale convolutional layers focus on minute details, such as the instantaneous delay deviation of a functional module at a specific moment. To avoid weak features being submerged in deep networks, a residual connection mechanism is used to preserve the original signal characteristics, and feature fusion is used to enhance the representation of minor defects. After identifying minor defects, detail amplification processing is also required, i.e., using deconvolution and convolution amplification methods to amplify the originally low-amplitude features into clearly distinguishable patterns. For example, a delay deviation of 0.02 ns can be amplified to an equivalent representation of 0.2 ns, or current fluctuations that only appear in a few bit lines can be expanded into visible feature maps. After this processing, the resulting "defect amplification sample" not only retains the core information of the minor defects, but also amplifies the detailed features, enabling subsequent classification and diagnosis to be carried out in a more significant feature space, thereby improving the anomaly detection rate and robustness.

[0016] Step S3: Based on the expanded defect sample, perform normalized defect detection classification and generate abnormal fault precursors; In this embodiment, based on the expanded defect sample, it is necessary to classify defect types into normalized and abnormal types to clarify which are normal process deviations and which may evolve into serious failures. Normalized defects usually originate from process tolerances or minor material differences, such as ±3% variation within the allowable range of metal interconnect width; while abnormal defects manifest as electrical anomalies or persistent deviations exceeding a threshold, which may lead to failure. The implementation method combines supervised learning and unsupervised clustering: First, a supervised classification model (such as Support Vector Machine (SVM) or lightweight neural network) is trained using historical large-scale good product samples to define the distribution range of normal defects; second, a clustering algorithm (such as K-means or Gaussian Mixture Model (GMM)) is combined to identify abnormal groups outside the distribution. When a feature value deviates from the statistical distribution by more than ±5σ, or when the distance between a certain type of sample and the normal distribution exceeds a set threshold, it is marked as an abnormal defect. At this time, the system records it as a "precursor to failure". This warning sign is not only reflected in numerical values, but may also be reflected in the timing of events. For example, if a logic module experiences a delay deviation exceeding a set threshold five times in a row within 30 minutes, it will be marked as a potential fault.

[0017] Step S4: Perform multi-step fault prediction on the abnormal fault precursors to obtain multi-step fault evolution prediction data; In this embodiment, after extracting the precursors of anomalous faults, it is necessary to predict their future evolution so that measures can be taken in advance. The key to multi-step fault prediction lies in combining time series modeling and state transition analysis to infer the evolution trend of the anomaly at different future time points. First, the precursor signal is abstracted into a state sequence, such as "mild anomaly," "moderate anomaly," and "severe anomaly," and a state transition matrix is ​​constructed. Based on historical data, Hidden Markov Models (HMMs), Long Short-Term Memory Networks (LSTMs), or Gated Recurrent Units (GRUs) can be used for prediction. These methods can capture both short-term fluctuations and long-term trends. For example, if the current anomaly is currently in a mild state, the probability of it entering a moderate state after 5 hours is predicted to be 0.4, and the probability of it entering a severe state after 10 hours is predicted to be 0.7, indicating that the risk accumulates rapidly over time. To enhance the stability of the prediction, Monte Carlo simulations can be used for repeated sampling to obtain multiple possible evolution paths and calculate their probability distributions.

[0018] Step S5: Perform dynamic risk trend assessment based on multi-step fault evolution prediction data, and make fault diagnosis decisions.

[0019] In this embodiment, after obtaining multi-step prediction data, the final step is to perform dynamic risk trend assessment and conduct diagnostic decisions based on the fault type. The core of risk assessment is mapping the predicted anomaly level value to a risk level curve, dynamically displaying the change in risk over time. For example, risk index ranges can be set: 0~0.3 for low risk, 0.3~0.6 for medium risk, and 0.6~1.0 for high risk. If the prediction result shows that the risk index will rise from 0.4 to 0.8 within the next 10 hours, the system will determine it as a high-risk trend. Based on this, the fault diagnosis decision module will combine the risk level, precursor type, and attribution information to generate corresponding processing suggestions. For example, when the fault is attributed to electromigration, the system may recommend frequency reduction and current redistribution before the risk index reaches 0.6; when attributed to thermally related failures, it recommends adjusting heat dissipation conditions or reducing power consumption within 12 hours. To optimize the timeliness and reliability of decisions, a multi-objective optimization method can be used to balance the fault control effect with the impact on normal operation. The final diagnostic decision output includes not only the "fault category" and "risk level," but also clearly specifies the "optimal handling time" and "type of prevention and control measures." Through this closed-loop process, the chip's fault detection and prevention form a complete end-to-end execution chain.

[0020] In this embodiment, see Figure 2 The diagram below illustrates the detailed implementation steps of step S1. In this embodiment, the detailed implementation steps of step S1 include: Collect the full-process test dataset of the target chip, including the original tests of electrical testing, functional testing, aging testing and packaging testing; The entire process test dataset is subjected to abnormal test data identification, and abnormal test data is extracted; the abnormal test data includes test incompleteness, mid-process withdrawal, test abnormality, and numerical deviation exceeding the threshold. Intelligent data cleaning and processing is performed on abnormal test data to generate a cleaned and optimized dataset; Identify different test batches and process conditions in the cleaning optimization dataset; Based on the different test batches and process conditions, multi-source timestamp identification is performed, and time sequence calibration is carried out to generate standardized test data samples.

[0021] In this embodiment, the data preparation stage for chip fault detection and diagnosis first requires the construction of a comprehensive full-process test dataset. This dataset must include electrical testing after wafer fabrication, logic function verification, performance records under aging stress, and a complete set of test information for the final packaging stage. The electrical testing section covers parameters such as quiescent current, voltage threshold, and I / O drive capability; the functional testing section includes the functional coverage of logic circuits, timing logic correctness, and register access accuracy; aging testing focuses on performance degradation under high temperature, high humidity, and bias voltage stress conditions, such as detecting changes in current and timing delay after continuous power-on at 125°C for 48 hours; the packaging stage checks the integrity of solder joint interconnects and stability under packaging stress. During data acquisition, environmental conditions (temperature, voltage, humidity), machine number, and batch information must be recorded simultaneously, along with a high-precision timestamp. For example, in the electrical testing stage, VDD=1.2V, and the current detection range is from nA to mA; in the high-temperature aging stage, current drift is recorded every 12 hours. After data collection, large-scale data inevitably contains various anomalies, requiring identification through a combination of rule-based detection and intelligent methods. Anomalies are mainly categorized into four types: ① Incomplete test process, manifested as insufficient test vectors or premature termination; ② Mid-test exit, usually due to machine interruption or operational errors, which can be identified by comparing test step records; ③ Test anomalies, typically characterized by all zeros or empty values ​​in the output, which can be determined through statistical distribution bias and variance tests; ④ Values ​​deviating from thresholds, for example, if the IDDQ current of a chip should be in the range of 0.5 μA to 10 μA, but it is 50 μA or higher, this is a significant anomaly. For threshold-type anomalies, a set range plus a statistical standard of "mean ± 5σ" can be used for screening. For high-dimensional feature anomalies, unsupervised identification can be performed using Isolation Forest or One-Class SVM. This step not only captures numerical deviations but also ensures that the integrity of the process and logical consistency are verified. For example, if a test record lacks a key voltage measurement, even if other parameters are normal, it will be identified as incomplete data.

[0022] After identifying anomalous data, further cleaning is required to eliminate invalid information and repair some usable samples, thereby improving the overall effectiveness and reliability of the dataset. The core tasks of data cleaning include: missing value imputation, noise correction, duplicate data removal, and logical inconsistency correction. When handling missing values, if the missing percentage of a parameter is less than 30%, it can be imputed using the mean or median under similar conditions in the same batch; if the missing percentage is too high, the record is directly removed. For noise correction, moving averages, outlier interpolation, or autoencoder-based reconstruction methods can be used to smooth the values. For duplicate values, duplicate entries are merged by comparing the chip ID with the timestamp to ensure uniqueness. Logically inconsistent data (such as negative power supply voltage or disordered time sequence) is directly removed to avoid misleading subsequent analysis. To further improve the level of intelligence, KNN nearest neighbor imputation algorithms or probability distribution-based interpolation methods can be combined to repair some anomalous samples. For example, if a current parameter is abnormally high in a small range, reasonable values ​​can be restored through nearest neighbor distribution interpolation. After cleaning, the dataset maintains consistency and integrity, reduces noise levels, and its numerical distribution better reflects actual process characteristics, providing a standardized and highly reliable sample set for model input. The cleaned data must then be further differentiated according to different production batches and process conditions. Chip performance parameters are significantly affected by process drift, equipment differences, and batch variations; therefore, explicit labeling management is necessary in data analysis. Specifically, this is achieved using metadata fields such as lot ID, wafer number, mask version, equipment number, test temperature, and voltage. If the metadata is complete, grouping can be done through direct matching; if some metadata is missing, unsupervised clustering algorithms (such as K-means or DBSCAN) can be used for automatic segmentation based on key parameters (delay distribution, leakage current level, functional coverage, etc.). After grouping, data under different process conditions can be clearly distinguished, such as the difference in electrical characteristics between chips from the same batch operating at 25℃ / 1.2V and 125℃ / 1.0V. Analysis shows that the mean current parameters may drift by more than 8% between different batches. If this process-related difference is not distinguished, it will seriously affect the generalization ability of subsequent modeling.

[0023] Because data sources involve multiple process stages and testing equipment, the accuracy and alignment of timestamps are crucial steps in achieving data fusion. Different devices may use different time formats (such as millisecond or microsecond precision), and there may be system clock drift or delayed recording phenomena, causing data sequences from the same chip to be unable to be directly aligned. To solve this problem, all timestamps need to be uniformly identified and standardized in format, using a unified reference clock source as a benchmark, such as a laboratory-grade NTP timing signal or a high-precision crystal oscillator inside the testing equipment. Subsequently, Dynamic Time Warping (DTW) algorithms or interpolation-based time alignment methods are used to ensure that sequences from different sources can be strictly matched in the time dimension. For example, under aging test conditions, the chip collects current data every 12 hours, but there may be a few minutes of offset between testing equipment. Timing calibration can ensure the consistency of data points on the global time axis. Finally, all data samples are standardized into a three-dimensional structure of "sample-feature-time," ensuring not only numerical consistency but also strict alignment in the time dimension. This provides a unified input for AI-based fault diagnosis models, avoiding the introduction of spurious features due to time drift or batch differences, thereby significantly improving diagnostic accuracy and stability.

[0024] In this embodiment, see Figure 3 The diagram below illustrates the detailed implementation steps of step S2. In this embodiment, the detailed implementation steps of step S2 include: The standardized test data samples are subjected to multi-scale convolution decomposition and micro-defect depth recognition to generate micro-defect features; Residual connections are performed on the micro-defect features to analyze the location and type of micro-defects; Deconvolutional detail optimization is performed based on the location and type of minor defects to generate defect detail optimization data; The flaw detail optimization data is subjected to detail information convolutional expansion processing to generate flaw expansion samples.

[0025] In this embodiment, a multi-scale convolutional decomposition method is used to identify potential minute defects in chip data. The core idea of ​​multi-scale convolutional decomposition is to use convolutional kernels of different sizes to extract features from the data, thereby capturing multi-level information from macroscopic trends to microscopic anomalies. For example, when processing time-series data of current and voltage, 1×3, 1×5, and 1×7 convolutional kernels can be set to extract features of short-term spikes, local fluctuations, and overall shifts, respectively. In chip characterization data, minute defects often manifest as slight current fluctuations (such as a 2%~5% deviation), small jitters in timing delays (less than 10 ps), or nonlinear drifts in voltage thresholds, which are difficult to detect at a single scale. Through a multi-scale convolutional network, abnormal patterns can be extracted at different resolutions, ensuring that fine-grained features are not masked by global trends. To improve recognition accuracy, an attention mechanism can be used to weight the feature layers, highlighting areas sensitive to defects. In practical applications, a deep residual convolutional network is often used to compare the differences between normal and abnormal samples, ultimately generating a deep feature map labeled with minute defect features. This is achieved through residual connection networks. The advantage of residual connections is that they can preserve shallow features during deep network training, preventing features from being over-smoothed or lost during layer-by-layer propagation. Specifically, the weak anomalous signals extracted by the primary convolutional layers are added point-by-point with the complex features extracted by the deeper convolutional layers, forming multi-level fused features. This preserves the detailed information of minor anomalies while introducing global context to aid in judgment. For example, if a parameter in chip data shows slight fluctuations in the 100 μs to 120 μs range, residual connections can accurately locate the time window corresponding to the anomaly and determine whether it is a transient current anomaly or a leakage current shift. Simultaneously, combining the feature vector with a classification layer for labeling can further distinguish defect types, such as "functional logic error," "electrical noise anomaly," or "packaging stress influence." A commonly used strategy in this process is classification training based on the cross-entropy loss function, combined with Softmax output to achieve a type probability distribution.

[0026] Deconvolution is used to restore and optimize details in defective regions. Deconvolution (also known as transposed convolution) is a technique commonly used for feature map upscaling and detail reconstruction. It can restore low-resolution feature maps to a higher-resolution space, thereby revealing the detailed features of minute defects. In practice, for the location marked as an anomaly, the corresponding feature map region is selected and upsampled using a deconvolution layer. For example, when a 2% abnormal fluctuation is detected in a current signal, after deconvolution processing, this fluctuation can be displayed at a finer time scale (e.g., expanded from 10 μs resolution to 1 μs resolution), thus revealing the detailed morphology of the anomaly. In encapsulation stress anomalies, deconvolution can help recover weak fluctuations lost due to signal compression, making them easier to identify in subsequent analysis. This step is usually combined with batch normalization and nonlinear activation functions (such as ReLU) to improve the stability and expressiveness of the reconstruction. Through detail information convolution upscaling, these subtle anomalies are transformed into more significant "defect upscaling samples" that can be learned by the model. This process is similar to "data amplification" or "anomaly enhancement," aiming to transform minute imperfections that are originally extremely difficult to detect into training samples with obvious features, thereby improving the model's sensitivity to minor anomalies. Specifically, it involves using specific convolutional kernels to amplify the optimized data; for example, using 3×3 convolutions stacked with multiple convolutional blocks to enhance the amplitude and boundaries of local anomaly features. For time-series signals, temporal spreading convolutions can be used to expand the original 10 μs anomaly window to a 100 μs coverage area, making the anomaly more prominent in the global context. For image-based or two-dimensional mapping data, pyramidal convolutional structures can be used to amplify tiny current fluctuation regions in two-dimensional space, making them appear as more obvious "abnormal spots." This amplification process not only improves the visibility of anomalies in the feature space but also enables subsequent classification and diagnostic models to identify minute imperfections with higher recall.

[0027] In this embodiment, step S3 includes the following steps: Deep data mining is performed on the expanded sample of defects, and defect details are analyzed to generate defect patterns; Based on the defect pattern, normal defects are classified and extracted as regular defects and abnormal defects. The degree of abnormality of non-normal defects is quantified to obtain the degree of abnormality value; Based on a preset deviation threshold, the abnormality of defects is evaluated by data comparison, and abnormal fault precursors are generated.

[0028] In this embodiment, deep data mining is used to deeply analyze the multidimensional information contained in the data, aiming to extract defect patterns that can characterize chip failure features. Deep data mining typically combines convolutional neural networks (CNNs), long short-term memory networks (LSTMs), or self-attention mechanisms to extract features from defect samples at multiple levels. CNNs are responsible for capturing local spatial features, such as local current fluctuation ranges or instantaneous voltage shifts; LSTMs or Transformer models can analyze long-term temporal dependencies and identify the evolution trend of defects throughout the test sequence. For example, if the chip's current fluctuation is not significant at 25°C but exhibits gradually increasing current leakage at 125°C, the model can identify this temperature-related anomaly pattern through time series mining. Simultaneously, feature visualization methods can be used to map high-dimensional data into two-dimensional or three-dimensional feature maps, showing the abnormal distribution of defects in the frequency domain, time domain, or voltage-current plane. Different defect patterns are classified according to their frequency of occurrence and process-acceptable range, distinguishing between regular defects and abnormal defects. Routine defects are typically minor deviations unavoidable in the manufacturing process, such as normal fluctuations in current (±2%) or voltage threshold drift within ±0.05 V. While these deviations are considered defects, they are within acceptable limits and do not substantially affect chip functionality. Anomalous defects, on the other hand, manifest as deviations in magnitude or shape far exceeding the normal range. For example, leakage current exceeding three times the normal average, or random jumps during logic function testing. This classification process can be achieved through a combination of statistical modeling and clustering algorithms: first, a probability distribution model of the defect pattern is established, calculating its mean, variance, and confidence interval; then, clustering methods (such as Gaussian Mixture Model or K-means) are used to group the pattern samples, classifying those with distribution centers close to the normal range as routine defects and those with significant deviations as anomalous defects. For example, if a batch of chips exhibits latency concentrated in the 5 ps to 8 ps range during timing testing, then data points falling outside this range by 15 ps are considered anomalous defects. This classification method allows for the accurate identification of potential failure hazards while ensuring manufacturing tolerances.

[0029] The feature vectors of anomalous defects are compared with the mean of the normal distribution, and methods such as Mahalanobis distance, Euclidean distance, or KL divergence are used to measure the degree of deviation. For example, if the normal current mean is 2 μA and the standard deviation is 0.2 μA, while a sample current reaches 3.5 μA, its deviation value corresponds to a Z-score of 7.5, significantly exceeding the conventional threshold. In time-series data, the similarity between abnormal waveforms and standard waveforms can also be measured using DTW (Dynamic Time Warping). If the deviation rate exceeds 10%, it can be defined as a high-level anomaly. To enhance the model's universality, the anomaly severity value can be standardized to the range of 0 to 1, where close to 0 indicates a mild anomaly and close to 1 indicates a severe anomaly. In this way, each anomalous defect is assigned a quantitative index, enabling subsequent analysis not only to determine whether an anomaly exists but also to specifically measure its severity, forming a more refined fault early warning system. Data comparison and evaluation are performed in conjunction with preset deviation thresholds to identify potential fault precursors. Threshold settings are typically based on long-term statistical analysis and process tolerances. For example, a Z-score > 3 or an anomaly level > 0.7 might be considered a precursor to a fault. A multi-threshold grading mechanism can be introduced to classify anomalies into mild, moderate, and severe levels. For instance, 0.4–0.6 might be considered a mild warning, 0.6–0.8 a moderate warning, and anything above 0.8 would be directly marked as a high-risk precursor to a fault. The evaluation process requires comprehensive consideration of multiple parameters, such as current, delay, voltage, and logic error rate, and the final risk index is calculated through multi-dimensional fusion scoring. For example, if a chip has a current anomaly level of 0.65 and a delay anomaly level of 0.75, the weighted average yields a comprehensive index of 0.70, which is higher than the threshold and is therefore classified as a moderate precursor to a fault. Finally, the system establishes a mapping relationship between anomalous defects and their corresponding fault risks, outputting a report containing the chip ID, fault location, anomaly level, and precursor level.

[0030] In this embodiment, step S4 includes the following steps: Dynamic time-series tracking analysis is performed on the aforementioned abnormal fault precursors to generate time-series change trends; Calculate the state transition probability of the time-series change trend; Based on the aforementioned temporal change trend, the fault evolution trajectory is analyzed to obtain the fault evolution trajectory; Based on the fault evolution trajectory, the propagation path is identified, and a fault propagation path is generated; Multi-step fault prediction is performed based on the state transition probability and fault propagation path to obtain multi-step fault evolution prediction data.

[0031] In this embodiment, dynamic time-series tracking analysis is performed on the evolution of the fault over time to form a complete time-series trend. The goal of this process is to capture the intensity, duration, and periodicity of precursor signals, thereby revealing the potential development pattern of the fault. Specifically, the parameters corresponding to the precursors (such as the degree of current anomaly, voltage drift amplitude, delay offset, etc.) are organized into time-series data and continuously monitored and recorded. For example, when the leakage current of the chip increases from 2 μA to 5 μA, and then to 12 μA within 10 hours, its trend curve shows a typical gradual deterioration characteristic. To ensure the accuracy of the trend analysis, a sliding window method can be used to smooth the data, and a fast Fourier transform (FFT) or wavelet transform can be used to detect the periodic components, thereby distinguishing between regular fluctuations and sudden anomalies. At the same time, deep time-series prediction methods such as autoregressive moving average model (ARIMA) or gated cyclic unit (GRU) can be combined to make short-term predictions of the trend in the future, further enhancing the foresight of the trend analysis. The continuous trend curve is discretized into multiple states, such as "normal," "slight deviation," "moderate anomaly," and "severe anomaly," and the state transition probabilities are calculated using statistical methods or Markov chain models. In practice, multiple threshold ranges can be set for the time-series data. For example, a current anomaly value <0.3 is defined as normal, 0.3~0.6 as slight deviation, 0.6~0.8 as moderate anomaly, and >0.8 as severe anomaly. Subsequently, the transition frequency between each state is statistically analyzed using a large-scale historical data sample, thus obtaining the transition probability matrix. For example, the probability of transitioning from "slight deviation" to "moderate anomaly" might be 0.35, while the probability of directly jumping to "severe anomaly" is only 0.05. This state transition modeling can clearly describe the evolution of fault precursors and provide a mathematical basis for subsequent trajectory analysis. To improve accuracy, a Hidden Markov Model (HMM) can be introduced to include unobservable potential factors (such as internal stress or material degradation) in the modeling scope, making the state transition probabilities more consistent with the real physical process.

[0032] By combining temporal trends, a fault evolution trajectory is constructed. The fault evolution trajectory refers to the dynamic process by which anomalies gradually develop from an initial state to potential failure. Its analytical goal is to reveal the fault's occurrence path and evolution rate. This is achieved by combining the temporal changes of precursor signals with a state transition matrix to generate a state sequence that changes over time. For example, a chip might maintain a "slight deviation" for 0-50 hours, then enter a "moderate anomaly" state for 50-70 hours, and accelerate to a "severe anomaly" state after 70 hours. This trajectory clearly depicts the fault evolution process. Bayesian inference or particle filtering methods can be used in trajectory analysis to dynamically update the evolution path to adapt to random fluctuations under different conditions. Furthermore, visualization techniques can be used to present the trajectory as a curve in a multi-dimensional space. For example, using "anomaly degree-time-temperature" as a three-dimensional coordinate axis, the evolution trajectory can be plotted as the process environment changes. This analysis allows for the identification of differences in the evolution rate among different chips; some may deteriorate rapidly within tens of hours, while others remain in a moderate state for a long time, providing important basis for classification and prediction. After obtaining the fault evolution trajectory, it is necessary to further identify its propagation path within the chip or along the test parameter dimensions. The propagation path describes the process by which a fault spreads from one parameter or region to other related parameters or functional modules. For example, leakage current anomalies may first appear in I / O cells and then gradually spread to the core logic region; similarly, delay anomalies may be triggered by the clock tree, ultimately affecting registers and data paths. Propagation path identification methods primarily rely on graph models and causal relationship analysis. First, the chip's key test parameters or functional modules are considered as nodes in a graph, and the logical or electrical relationships between them are considered as edges. Then, Granger causality tests or methods based on mutual information are used to identify the causal transmission relationships between parameters, thereby determining the direction of fault propagation. In numerical implementation, the path can be inferred by calculating the correlation coefficients and timing relationships of the anomaly values ​​of each node. For example, if a voltage fluctuation occurs in a power supply cell 30 minutes later, and the core logic current subsequently rises, the propagation path from the power supply cell to the logic cell can be determined. Multi-step fault prediction is then performed to anticipate potential future failure evolutions of the chip. The core of multi-step prediction is to combine the state transition probability matrix with the directed graph of the propagation path to simulate the development of faults over multiple time steps in the future. Specifically, using the current state as initial conditions, random sampling or matrix multiplication based on the transition probabilities is used to estimate the state distribution for several future steps. For example, if the chip is currently in a "moderately abnormal" state, and the propagation path indicates that the abnormality has spread to logic cells, the prediction result might show a probability of 0.6 of entering a "severe abnormal" state in the next 10 hours and a probability of 0.3 of system-level failure in the next 20 hours. To improve the robustness of the prediction, Monte Carlo simulation can be used for multiple sampling to obtain a more stable prediction distribution.Simultaneously, by incorporating deep reinforcement learning methods, the predicted path is dynamically updated, allowing the prediction results to be continuously corrected based on real-time data input. Ultimately, the output multi-step fault evolution prediction data not only includes the probability and time of fault occurrence but also labels the modules and paths that may be affected, thus providing a quantitative basis for reliability assessment and preventative maintenance.

[0033] In this embodiment, step S5 includes the following steps: The abnormal defects are located and traced, and the chip structure is three-dimensionally located, and the three-dimensional location coordinates of the defects are marked. Based on multi-step fault evolution prediction data, multi-time-point fault impact analysis is performed to generate the fault impact range at multiple time points; Based on the fault impact range and the three-dimensional positioning coordinates of the defect, the evolution of the fault structure is predicted, and a dynamic risk trend assessment is performed to generate a real-time fault risk level. Deep fault diagnosis is performed based on the multi-step fault evolution prediction data to carry out fault detection and fault prevention operations.

[0034] In this embodiment, based on the source of the test data, the abnormal signal is mapped to a specific circuit unit or functional module, such as an I / O unit, power management module, clock tree, or logic core. Next, using the chip design layout information and process layer data, the position of this module in the three-dimensional structure is determined. The three-dimensional structure of a chip typically consists of multiple metal layers, dielectric layers, and active regions, with the geometric dimensions of each layer reaching nanometer-level precision. For example, at a 7 nm process node, the metal layer spacing is typically 30-40 nm, while the diameter of a via is only about 20 nm. During the localization process, a mapping table of "test parameters—functional modules—physical locations" can be established to associate the current anomaly with its corresponding power trace layer or local transistor region. Subsequently, the localization results are labeled in three-dimensional coordinates, such as (x=120 μm, y=85 μm, z=Layer M4), clearly indicating the physical coordinates and layer of the defect. This three-dimensional localization not only visually displays the location of the anomaly but also provides a structural basis for subsequent propagation path analysis and risk assessment. By combining the predicted anomaly severity with propagation path information, modules that may be affected at several future time points are labeled. For example, in the t+10 hour prediction, the anomaly might be limited to the power network; in the t+20 hour prediction, logic units are also affected; and in the t+30 hour prediction, the memory control unit begins to exhibit anomalies. This time-by-time expanding impact range can be calculated using Monte Carlo sampling and probability superposition, i.e., by repeating simulations multiple times along different prediction paths and statistically analyzing the probability of each module being affected, a reliable point-in-time impact distribution can be obtained. In numerical analysis, a threshold probability can be set; for example, when the probability of a module being affected exceeds 0.6, it is included in the fault impact range. The final result is presented as a multi-time-point impact map, showing the process of the fault gradually expanding from local to global over time.

[0035] After clarifying the three-dimensional location and multi-time-point impact range of the defect, these two aspects can be combined to predict the evolution of the fault in the chip structure and assess its risk level in real time. The core of fault structure evolution prediction is to simulate the expansion path of the defect in three-dimensional space and time. For example, if a severe current anomaly is detected in the power layer M4, and the prediction shows that the anomaly will expand to the core logic of the M6 ​​layer within 20 hours, an evolution path from the power unit to the logic core can be derived. Based on this, combined with material properties (such as metal electromigration threshold, dielectric breakdown electric field strength) and process parameters (such as current density limit, thermal conductivity), the fault propagation speed and range can be predicted more accurately. Dynamic risk trend assessment is achieved by mapping the anomaly intensity value and the structural evolution path to a risk level system. For example, if the anomaly intensity value > 0.8 and the impact range covers more than 30% of the critical modules, it is judged as "high risk"; if the anomaly value is between 0.5 and 0.7 and is limited to peripheral units, it is judged as "medium risk". Based on the aforementioned prediction and risk assessment, in-depth fault diagnosis is carried out, thereby supporting specific detection and prevention operations. The goal of deep diagnostics is to pinpoint the root cause of a fault and provide actionable prevention and control recommendations. This is achieved by inputting multi-step prediction data and 3D localization information into a deep learning diagnostic network. This network combines convolutional neural networks (CNNs) and graph neural networks (GNNs) to simultaneously process information about spatial structure and propagation paths. For example, CNNs are used to identify abnormal patterns in local modules, while GNNs are used to capture the electrical and logical coupling relationships between modules. Through this fusion modeling, it can be determined whether a fault is caused by electromigration, gate oxide breakdown, or packaging stress. After diagnosis, the system can propose prevention and control measures based on different types of faults: for risks caused by electromigration, the evolution can be mitigated by reducing current density or optimizing power consumption distribution; for thermally related faults, it is recommended to improve heat dissipation conditions or reduce operating frequency; for packaging-related defects, targeted screening needs to be added during quality inspection. Ultimately, deep fault diagnosis not only outputs the fault category and root cause but also provides prevention and control recommendations and detection schemes, forming an end-to-end closed-loop system of detection-diagnosis-prevention, thereby maximizing chip reliability and lifespan.

[0036] In this embodiment, the specific steps for performing in-depth fault diagnosis based on the multi-step fault evolution prediction data to execute fault detection and fault prevention operations are as follows: Deep fault diagnosis is performed based on the multi-step fault evolution prediction data to extract fault types and fault causes. Multi-objective optimization analysis is performed based on real-time fault risk level, fault type and fault attribution, and fault handling decisions are made to generate fault handling methods and optimal handling time points. Fault detection and prevention operations are performed based on fault handling methods and optimal handling time points.

[0037] In this embodiment, multi-step prediction data is fused with the chip's functional module information. For example, if the prediction data shows that the power module will enter a severely abnormal state within the next 10 hours, accompanied by a continuous increase in current density, it may be attributed to electromigration of the metal interconnects; if the prediction results indicate that the logic delay gradually deteriorates and is strongly correlated with high-temperature regions, it may be attributed to gate oxide breakdown or local overheating. To ensure the accuracy of the diagnosis, a deep learning-based classifier can be introduced, such as a hybrid model combining convolutional neural networks (CNN) and long short-term memory networks (LSTM). CNN is used to extract spatial features (local anomaly distribution patterns), and LSTM is used to capture temporal features (the evolution of anomalies over time). Simultaneously, a knowledge graph approach is used to encode existing chip failure modes (such as thermal failure, electrical stress failure, and packaging stress failure) into rules to assist the deep model in attribution inference. In this way, "fault types" (such as electromigration, gate oxide breakdown, and packaging cracks) and "fault attributions" (such as current overload, insufficient thermal management, and mechanical stress accumulation) can be extracted. Multi-objective optimization analysis is conducted in conjunction with real-time risk levels to generate the optimal fault handling strategy and time point. The core of multi-objective optimization is to comprehensively consider different factors: on the one hand, risk level, such as high-risk cases must be prioritized; on the other hand, fault type and attribution, with different faults corresponding to different handling methods; and simultaneously, the impact of handling timing on chip performance and production efficiency must be considered. Specifically, a multi-objective optimization model is constructed using risk level (low, medium, high), fault type (electromigration, breakdown, package cracks, etc.), and attribution factors (current, voltage, heat, stress) as input variables. Optimization objectives include: ① minimizing the probability of fault propagation; ② maximizing the effectiveness of fault handling; and ③ minimizing interference with normal chip operation. For example, when the electromigration risk of a chip reaches 0.8, and it is predicted that it will propagate to the core logic region after 12 hours, the optimal decision given by the optimization model might be "to implement frequency reduction and current redistribution within 8 hours," which reduces risk and avoids production losses caused by immediate shutdown. Mathematically, Pareto optimality methods or adaptive policy search methods based on reinforcement learning can be used to achieve multi-objective optimization. During the output phase, the system not only provides "fault handling methods" (such as frequency reduction, partial shutdown, thermal distribution optimization, and functional redundancy switching), but also provides "optimal processing time points" to offer quantitative guidance for subsequent execution stages. Depending on the handling method, corresponding operational strategies are adopted. For example, if the system suggests "frequency reduction operation," the operating frequency is automatically adjusted at the optimal time point, reducing it from 2.5 GHz to 2.0 GHz to mitigate electromigration risks. If "current redistribution" is suggested, a backup power channel is enabled or high-risk circuits are shut down at the package level to reduce current density.For thermal management-related risks, the power of local heat dissipation devices can be increased at recommended times, or the activity intensity in power-intensive areas can be reduced through Dynamic Power Management (DPM). Simultaneously, to ensure the effectiveness of prevention and control measures, continued monitoring and feedback are necessary after implementation: key parameters such as voltage, current, temperature, and latency are monitored online to confirm whether the prevention and control measures have achieved the expected results. If the risk level fails to decrease effectively, the system will automatically adjust its strategy, such as switching to a backup module earlier or extending the processing time. Through this closed-loop mechanism of detection-execution-feedback, the chip can achieve intelligent self-protection during operation, not only extending its lifespan but also significantly improving overall reliability.

[0038] In this embodiment, a chip fault detection device is provided for performing the chip fault detection method described above, including: The data cleaning module is used to collect the full-process test dataset of the target chip, perform intelligent data cleaning processing, and generate standardized test data samples. The detail enhancement module is used to perform in-depth identification and detail enhancement of minor defects in standardized test data samples, generating defect-enhanced samples. The defect classification module is used to classify normal defects based on expanded defect samples and generate abnormal fault precursors; A multi-step fault prediction module is used to perform multi-step fault prediction on the abnormal fault precursors to obtain multi-step fault evolution prediction data. The fault diagnosis module is used to perform dynamic risk trend assessment based on multi-step fault evolution prediction data and to make fault diagnosis decisions.

[0039] The present invention also provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps of the chip fault detection method described in any of the preceding claims.

[0040] The present invention also provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the steps of the chip fault detection method described in any of the preceding claims.

[0041] Therefore, the embodiments should be considered as exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of the equivalents of the application are intended to be included within the invention.

[0042] The above description is merely a specific embodiment of the present invention, enabling those skilled in the art to understand or implement it. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein are implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the present invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features of the invention herein.

Claims

1. A chip fault detection method, characterized in that, Includes the following steps: Step S1: Collect the full-process test dataset of the target chip, perform intelligent data cleaning and processing, and generate standardized test data samples; Step S2: Perform in-depth identification and detail magnification of minor defects on the standardized test data samples to generate defect magnification samples; Step S3: Based on the expanded defect sample, perform normalized defect detection classification and generate abnormal fault precursors; Step S4: Perform multi-step fault prediction on the abnormal fault precursors to obtain multi-step fault evolution prediction data; Step S5: Perform dynamic risk trend assessment based on multi-step fault evolution prediction data, and make fault diagnosis decisions.

2. The chip fault detection method according to claim 1, characterized in that, The specific steps of step S1 are as follows: Collect the full-process test dataset of the target chip, including the original tests of electrical testing, functional testing, aging testing and packaging testing; The abnormal test data is identified and extracted from the full-process test dataset; The abnormal test data includes tests that are not completed, exited midway, test errors, and numerical deviations that exceed the threshold. Intelligent data cleaning and processing is performed on abnormal test data to generate a cleaned and optimized dataset; Identify different test batches and process conditions in the cleaning optimization dataset; Based on the different test batches and process conditions, multi-source timestamp identification is performed, and time sequence calibration is carried out to generate standardized test data samples.

3. The chip fault detection method according to claim 1, characterized in that, The specific steps of step S2 are as follows: The standardized test data samples are subjected to multi-scale convolution decomposition and micro-defect depth recognition to generate micro-defect features; Residual connections are performed on the micro-defect features to analyze the location and type of micro-defects; Deconvolutional detail optimization is performed based on the location and type of minor defects to generate defect detail optimization data; The flaw detail optimization data is subjected to detail information convolutional expansion processing to generate flaw expansion samples.

4. The chip fault detection method according to claim 1, characterized in that, Step S3 is as follows: Deep data mining is performed on the expanded sample of defects, and defect details are analyzed to generate defect patterns; Based on the defect pattern, normal defects are classified and extracted as regular defects and abnormal defects. The degree of abnormality of non-normal defects is quantified to obtain the degree of abnormality value; Based on a preset deviation threshold, the abnormality of defects is evaluated by data comparison, and abnormal fault precursors are generated.

5. The chip fault detection method according to claim 1, characterized in that, The specific steps of step S4 are as follows: Dynamic time-series tracking analysis is performed on the aforementioned abnormal fault precursors to generate time-series change trends; Calculate the state transition probability of the time-series change trend; Based on the aforementioned temporal change trend, the fault evolution trajectory is analyzed to obtain the fault evolution trajectory; Based on the fault evolution trajectory, the propagation path is identified, and a fault propagation path is generated; Multi-step fault prediction is performed based on the state transition probability and fault propagation path to obtain multi-step fault evolution prediction data.

6. The chip fault detection method according to claim 1, characterized in that, The specific steps of step S5 are as follows: The abnormal defects are located and traced, and the chip structure is three-dimensionally located, and the three-dimensional location coordinates of the defects are marked. Based on multi-step fault evolution prediction data, multi-time-point fault impact analysis is performed to generate the fault impact range at multiple time points; Based on the fault impact range and the three-dimensional positioning coordinates of the defect, the evolution of the fault structure is predicted, and a dynamic risk trend assessment is performed to generate a real-time fault risk level. Deep fault diagnosis is performed based on the multi-step fault evolution prediction data to carry out fault detection and fault prevention operations.

7. The chip fault detection method according to claim 6, characterized in that, The specific steps for performing in-depth fault diagnosis based on the multi-step fault evolution prediction data to execute fault detection and fault prevention operations are as follows: Deep fault diagnosis is performed based on the multi-step fault evolution prediction data to extract fault types and fault causes. Multi-objective optimization analysis is performed based on real-time fault risk level, fault type and fault attribution, and fault handling decisions are made to generate fault handling methods and optimal handling time points. Fault detection and prevention operations are performed based on fault handling methods and optimal handling time points.

8. A chip fault detection device, characterized in that, For performing the chip fault detection method as described in claim 1, including: The data cleaning module is used to collect the full-process test dataset of the target chip, perform intelligent data cleaning processing, and generate standardized test data samples. The detail enhancement module is used to perform in-depth identification and detail enhancement of minor defects in standardized test data samples, generating defect-enhanced samples. The defect classification module is used to classify normal defects based on expanded defect samples and generate abnormal fault precursors; A multi-step fault prediction module is used to perform multi-step fault prediction on the abnormal fault precursors to obtain multi-step fault evolution prediction data. The fault diagnosis module is used to perform dynamic risk trend assessment based on multi-step fault evolution prediction data and to make fault diagnosis decisions.

9. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the chip fault detection method according to any one of claims 1 to 7.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the steps of the chip fault detection method according to any one of claims 1 to 7.

Images