Single-pin trimming circuit

Abstract

The invention discloses a single-pin trimming circuit, which relates to the technical field of analog circuit design and comprises a comparator module, a first input end of the comparator module is connected to a single pin, a second input end of the comparator module is connected to a reference voltage, and the comparator module is used for comparing an input voltage of the single pin with the reference voltage and outputting a comparison signal; the input end of the time sequence decoding module is connected to the output end of the comparator module, and the time sequence decoding module is configured as follows: a, the logic state of a trimming position is judged according to the duration time of the pulse in the comparison signal; and b, addressing different trimming positions according to the number of pulses in the comparison signal, and further generating a multi-position trimming control signal through a series of pulse signals input by the single pin. Accurate control of a multi-bit fuse trimming circuit in a chip is realized by using single-pin resources.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of analog circuit design, in particular to a single-pin trimming circuit, which is mainly applied to the trimming of a chip and can be used in both CP (chip manufacturing middle stage test) and FT (final test) stages. BACKGROUND

[0002] In a chip, trimming technology can effectively reduce the influence of process fluctuation on chip parameters, thereby improving parameter accuracy and chip yield.

[0003] For traditional fuse trimming circuit technology, a trimming point corresponding to each trimming bit needs to be introduced, that is, a pad connected to each trimming bit. When the number of trimming bits is too high, it will cause great loss of chip area.

[0004] In particular, for FT stage trimming, the FT stage is through pin multiplexing technology to multiplex the trimming pad and the chip function pad. However, for a chip with only a few pins, such as an LDO chip, there are typically only three pins, input VIN, output VOUT, and feedback FB. The package form also has only three pins. Moreover, the input VIN pin needs to play the role of power supply during testing, and the output VOUT pin needs to play the role of measurement during testing. Therefore, only one pin can provide trimming control.

[0005] Therefore, for a chip with a large number of fuse trimming bits and a small number of pads / pins, a single-pin trimming control circuit needs to be designed to maximize the saving of pad / pin number. SUMMARY

[0006] The technical problem to be solved by the present application is to solve the contradiction between a large number of fuse trimming bits and a small number of pads / pins in a traditional trimming control circuit.

[0007] To solve the above technical problems, the present application provides a single-pin trimming circuit, comprising: a comparator module, a first input end of which is connected to a single pin, and a second input end of which is connected to a reference voltage, the comparator module being configured to compare the input voltage of the single pin with the reference voltage and output a comparison signal; a timing decoding module, an input end of which is connected to an output end of the comparator module, the timing decoding module being configured to: a, determining the logic state of a trimming bit according to the duration of a pulse in the comparison signal; b, addressing different trimming bits according to the number of pulses in the comparison signal, and then generating a multi-bit trimming control signal through a series of pulse signals input by the single pin.

[0008] Further, the timing decoding module comprises: a first delay unit, an input end of which is connected to an output end of the comparator module, and the first delay unit is configured to delay the comparison signal to generate a clock signal; a second delay unit, an input end of which is connected to an output end of the first delay unit, and a delay amount of the second delay unit is greater than that of the first delay unit, and the second delay unit is configured to delay the clock signal to generate a data signal; a counter unit, a clock input end of which is connected to an output end of the first delay unit, and the counter unit is configured to count the clock signal and output a count value; a decoder unit, a first input end of which is connected to an output end of the counter unit and a second input end of which is connected to an output end of the second delay unit, and the decoder unit is configured to address a target trimming bit according to the count value and determine a logic state of the trimming bit according to a level state of the data signal.

[0009] Further, the decoder unit is configured to: when a pulse width of the clock signal is less than the delay amount of the second delay unit, the data signal is a first logic level, and the decoder unit determines that the logic state of the target trimming bit is a first state; when the pulse width of the clock signal is greater than or equal to the delay amount of the second delay unit, the data signal is a second logic level, and the decoder unit determines that the logic state of the target trimming bit is a second state.

[0010] Further, the first delay unit and the second delay unit are both RC delay circuits.

[0011] Further, the counter unit is composed of a plurality of D flip-flops connected in series.

[0012] Optionally, the circuit is applied to a middle-stage test phase or a final test phase of chip manufacturing, and is multiplexed with a functional pin of the chip through the single pin.

[0013] Further, the single pin is multiplexed with one functional pin of the chip in the test phase.

[0014] Compared with the prior art, the embodiment of the present application has the following beneficial effects: The present application uses the single pin to analyze the width and quantity information of the input pulse by using the timing decoding module, realizes the precise control of the multi-bit fuse trimming circuit in the chip by using the single pin resource, and fundamentally solves the technical problems that the traditional trimming method cannot be applied in the chip with few pins due to the limitation of the number of pins, or the chip area and cost are increased due to the large number of trimming bits. BRIEF DESCRIPTION OF DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative effort based on these drawings.

[0016] Figure 1 is a single-pin trimming circuit architecture disclosed by the present application; Figure 2 is a circuit schematic diagram of a comparator module disclosed by the present application; Figure 3 is a circuit schematic diagram of a delay module disclosed by the present application; Figure 4 is a circuit schematic diagram of an N-bit (N=3) counter unit disclosed by the present application; Figure 5 is a circuit schematic diagram of an N-bit (N=3) decoder unit disclosed by the present application; Figure 6 is a circuit key signal waveform diagram disclosed by the present application.

[0017] In the drawings: 10, comparator module; 20, timing decoding module; 21, first delay unit; 22, second delay unit; 23, counter unit; 24, decoder unit. DETAILED DESCRIPTION

[0018] In order to make the person skilled in the art better understand the present application, the technical solutions in the embodiments of the present application will be described clearly and completely in the following with reference to the drawings of the embodiments of the present application. Obviously, the described embodiments are only some embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present application.

[0019] The present application aims to provide a single-pin trimming circuit, which can generate multi-bit trimming control signals through only one test pin, thereby greatly saving chip pin resources and reducing chip area and cost.

[0020] The single-pin trimming circuit provided by the application mainly comprises a comparator module 10 and a timing decoding module 20, wherein the first input end of the comparator module 10 is connected to a single pin, and the second input end is connected to a reference voltage; the comparator module 10 is used for comparing the input voltage of the single pin with the reference voltage and outputting a comparison signal; the input end of the timing decoding module 20 is connected to the output end of the comparator module 10, and the timing decoding module 20 is configured to: a. determining the logic state of one trimming bit according to the duration of the pulse in the comparison signal.

[0021] b. addressing different trimming bits according to the number of pulses in the comparison signal, and then generating a multi-bit trimming control signal through a series of pulse signals input by the single pin.

[0022] It should be noted that the scheme needs to provide a reference voltage Vref in the system externally, and also needs to provide an enable signal EN.

[0023] The comparator module 10 and the timing decoding module 20 are described in detail below.

[0024] Firstly, the comparator module 10 is described.

[0025] Please refer to Figure 2 , in addition to the power supply and the ground, the comparator module 10 also has an input positive end, an input negative end and an output end; the input positive end of the comparator module 10 is connected to the single pin TestPin, and the input negative end is connected to the reference voltage Vref; the output end of the comparator module 10 is connected to the input end of the first delay unit 21. The function of the comparator module 10 is to output a high level when TestPin>Vref, and output a low level when TestPin

[0026] Then, the timing decoding module 20 is described.

[0027] Please refer to Figure 1 , the timing decoding module 20 comprises a first delay unit 21, a second delay unit 22, a counter unit 23 and a decoder unit 24.

[0028] Specifically: As shown in the circuit principle diagram of the first delay unit 21 shown in Figure 3 , the input end of the first delay unit 21 is connected to the output end of the comparator module 10, and the first delay unit 21 is used for delaying the comparison signal to generate a clock signal.

[0029] The circuit realizes the function of delaying the rising edge of the input signal by td1 time by using the process of charging and discharging the capacitor by the current.

[0030] The circuit schematic of the second delay unit 22 is the same as that of the first delay unit 21. The input terminal of the second delay unit 22 is connected to the output terminal of the first delay unit 21. Because the capacitor of the second delay unit 22 is larger, the delay amount of the second delay unit 22 is greater than that of the first delay unit 21, making the overall circuit parameters more robust. The second delay unit 22 is used to delay the clock signal to generate a data signal.

[0031] In this scheme, both the first delay unit 21 and the second delay unit 22 are RC delay circuits.

[0032] like Figure 4 The circuit schematic shown is for an N-bit (N=3) counter unit 23. N can be expanded according to the number of fuses required by the chip, while the circuit architecture remains unchanged. The clock input terminal of the counter unit 23 is connected to the output terminal of the first delay unit 21. The counter unit 23 is used to count the clock signal and output the count value.

[0033] The counter unit 23 is composed of multiple D flip-flops connected in series. The EN pin is responsible for clearing the counter unit 23. After clearing, the counter unit 23 outputs a binary number Q2Q1Q0 to count the number of pulses of TEST_CMP_OUT.

[0034] like Figure 5 The circuit diagram shown is of an N-bit (N=3) decoder unit 24. The first input terminal of the decoder unit 24 is connected to the output terminal of the counter unit 23, and the second input terminal is connected to the output terminal of the second delay unit 22. The decoder unit 24 is used to address the target trim bit according to the count value and determine the logic state of the trim bit according to the level state of the data signal.

[0035] In this scheme, the decoder unit 24 is configured as follows: When the pulse width of the clock signal is less than the delay amount of the second delay unit 22, the data signal is at the first logic level, and the decoder unit 24 determines that the logic state of the target trimming bit is the first state.

[0036] When the pulse width of the clock signal is greater than or equal to the delay amount of the second delay unit 22, the data signal is at the second logic level, and the decoder unit determines that the logic state of the target trimming bit is the second state.

[0037] It can be understood that the function of the decoder unit 24 is to decode the position of the pulse according to the result of the counter unit 23, and then read the width information of the corresponding pulse according to the state of EN, and output TRIM_CTL<2^n-1:0> to control the adjustment of the corresponding bit.

[0038] The single-pin adjustment circuit provided by this invention is applied to the mid-stage or final testing stage of chip manufacturing, and can be multiplexed with the functional pins of the chip through a single pin.

[0039] like Figure 6 The timing diagram of the key signal waveform shown demonstrates the processing results of three tuning pulses: 1. First pulse (narrow pulse): Counter address is 001, TEST_DATA = 0, result is TRIM_CTL <0> =0, meaning no tuning.

[0040] 2. The second pulse (wide pulse): the counter address is 010, TEST_DATA=1, and the result is TRIM_CTL. <1> =1, meaning adjustment.

[0041] 3. The third pulse (medium-width pulse): The counter address is 011, TEST_DATA=0 (because the pulse width is still less than td2), and the result is TRIM_CTL. <2> =0, meaning no tuning.

[0042] Combination Figure 6 The key signal waveform timing diagram shown illustrates the technical principle of this solution: The single pin of the adjustment control circuit is TestPin. After comparing it with the reference, it can convert the control pattern level into the adjustment control signal TEST_CMP_OUT powered by the chip's internal level.

[0043] After the first-stage delay td1, TEST_CMP_OUT generates the clock cycle TEST_CLK. The purpose of the delay td1 is to filter out glitches in the signal and prevent power supply jitter or glitches from causing errors in the tuning control logic.

[0044] After a second-stage delay td2, TEST_CLK generates trimming control data TEST_DATA. The purpose of delay td2 is to determine whether the trimming control data represents a trimming / non-trimming signal. When the TEST_CLK pulse width is shorter than the td2 time, TEST_DATA is a digital signal "0" during the trimming pulse period, and the subsequent control logic can interpret this as no trimming of that bit. Conversely, when the TEST_CLK pulse width is longer than the td2 time, TEST_DATA is a digital signal "1" during the trimming pulse period, and the subsequent control logic can interpret this as trimming of that bit.

[0045] Meanwhile, TEST_CLK is given to an N-bit counter, the number of which is determined by the control bits that need to be adjusted. A given N can generate up to 2^N bits of adjustment control. The output of the N-bit counter is then given to an N-bit decoder. The N-bit decoder can sample the TEST_DATA signal according to the TEST_CLK clock cycle, and thus output the TRIM_CTL<2^N-1:0> adjustment control signal.

[0046] This invention successfully decodes serial input information into parallel, precise multi-bit tuning control signals by utilizing the timing characteristics (number and width) of pulses using only one pin.

[0047] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A single pin trim circuit, comprising: The circuit comprises: a comparator module, a first input end of which is connected to a single pin, and a second input end of which is connected to a reference voltage, the comparator module being configured to compare an input voltage of the single pin with the reference voltage and output a comparison signal; a timing decoding module, an input end of which is connected to an output end of the comparator module, the timing decoding module being configured to: a. determine a logic state of a trimming bit according to a duration of a pulse in the comparison signal; and b. address different trimming bits according to a number of pulses in the comparison signal, so as to generate a multi-bit trimming control signal through a series of pulse signals input by the single pin.

2. The single pin trim circuit of claim 1, wherein, The timing decoding module comprises: a first delay unit, an input end of which is connected to an output end of the comparator module, the first delay unit being configured to delay the comparison signal to generate a clock signal; a second delay unit, an input end of which is connected to an output end of the first delay unit, the second delay unit having a delay amount greater than that of the first delay unit, and being configured to delay the clock signal to generate a data signal; a counter unit, a clock input end of which is connected to an output end of the first delay unit, the counter unit being configured to count the clock signal and output a count value; and a decoder unit, a first input end of which is connected to an output end of the counter unit, and a second input end of which is connected to an output end of the second delay unit, the decoder unit being configured to address a target trimming bit according to the count value, and determine a logic state of the target trimming bit according to a level state of the data signal.

3. The single pin trimmer circuit of claim 2, wherein, The decoder unit is configured to: when a pulse width of the clock signal is less than the delay amount of the second delay unit, the data signal is a first logic level, and the decoder unit determines that the logic state of the target trimming bit is a first state; when the pulse width of the clock signal is greater than or equal to the delay amount of the second delay unit, the data signal is a second logic level, and the decoder unit determines that the logic state of the target trimming bit is a second state.

4. The single pin trim circuit of claim 2, wherein, The first delay unit and the second delay unit are RC delay circuits.

5. The single pin trimmer circuit of claim 2, wherein, The counter unit is composed of a plurality of D flip-flops connected in series.

6. The single pin trim circuit of claim 1, wherein, The circuit is applied to a middle-stage test phase or a final test phase of chip manufacturing, and a function pin of the chip is multiplexed with the single pin in the test phase.

7. The single pin trimmer circuit of claim 6, wherein, The single pin is multiplexed with a function pin of the chip in the test phase.

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