Temperature control testing device for high-temperature chip

Abstract

The invention provides a temperature control testing device for a high-temperature chip. The temperature control testing device comprises an inner-layer temperature control structure and an outer-layer temperature control structure, the outer-layer temperature control structure comprises an air isolation cover and a bottom substrate, and the air isolation cover is fixed on the upper surface of the bottom substrate to define a high-temperature inner cavity; the inner-layer temperature control structure is provided with a chip carrying table which is arranged in the high-temperature inner cavity, the upper surface of the chip carrying table carries a chip, and a vacuum adsorption device with a plurality of adsorption holes is integrated. The inner layer temperature control structure and the outer layer temperature control structure are connected through a plurality of low-heat-conductivity connecting columns. An inner-outer double-layer temperature control structure design is adopted, and heat conduction is weakened through the low-heat-conductivity connecting columns. The outer layer forms a closed high-temperature inner cavity through an air isolation cover, and is integrated with a high-boron glass observation window and a slidable partition plate; the temperature of the inner layer is controlled through a chip carrier, and a vacuum adsorption device is integrated to fix a chip. The outer layer isolates outside airflow, the inner layer reduces the temperature difference between the chip and the cavity, closed-loop temperature control is achieved through the inner heating element, the outer heating element and the temperature sensor, the problem that temperature fluctuation of single-layer temperature control is large is solved, and stable temperature control is achieved.

Description

Technical Field

[0001] This application relates to the field of optical chip testing equipment technology, and in particular to a high-temperature chip temperature control testing device. Background Technology

[0002] In the field of chip performance testing, especially in high-temperature environment testing of precision chips such as optical chips, temperature control stability and test adaptability directly affect the accuracy and reliability of test results. Existing high-temperature chip temperature control testing devices generally suffer from the following technical pain points: First, the temperature control structure design is unreasonable, mostly single-layer temperature control, which is easily affected by external airflow disturbances, resulting in large temperature fluctuations within the chamber and failing to guarantee a stable testing environment; Second, a large temperature difference easily arises between the controlled chip and the chamber environment, affecting the accurate simulation of the chip's actual working state and thus reducing test accuracy; Third, the adaptability for coupling testing of optical chips is poor, making it difficult to achieve flexible coupling testing of different regions of the optical chip structure, and the chamber's airtightness is easily affected during the testing process; Fourth, significant heat conduction occurs at the connection points between the inner and outer layers of the device, further aggravating temperature fluctuations and failing to meet the temperature control accuracy requirements within the range of room temperature to 300℃.

[0003] Therefore, developing a highly stable high-temperature chip temperature control test device that can isolate external airflow disturbances, reduce the temperature difference between the chip and the cavity, adapt to optical chip coupling test, and reduce the heat conduction between the inner and outer layers has become an urgent problem to be solved in the field of chip testing technology. Summary of the Invention

[0004] The purpose of this application is to solve the problems of existing high-temperature chip temperature control testing devices being easily affected by external environmental airflow disturbances, easily generating large temperature differences, and failing to meet temperature control requirements.

[0005] This application provides a high-temperature chip temperature control testing device, including: an inner layer temperature control structure and an outer layer temperature control structure; The outer temperature control structure includes an air isolation cover and a bottom substrate. The air isolation cover is fixed to the upper surface of the bottom substrate and encloses it to form a high-temperature inner cavity. The inner temperature control structure includes: a chip stage, which is disposed in the high-temperature inner cavity, and the upper surface of the chip stage is used to support the chip; The chip stage integrates a vacuum adsorption device, which includes multiple adsorption holes formed on the upper surface of the chip stage. The inner temperature control structure and the outer temperature control structure are connected by multiple low thermal conductivity connecting pillars. One end of each low thermal conductivity connecting pillar is fixed to the lower surface of the inner temperature control structure, and the other end is fixed to the upper surface of the bottom substrate of the outer temperature control structure.

[0006] In one feasible implementation, the outer temperature control structure further includes a borosilicate glass observation window; The high borosilicate glass observation window is located at the top opening of the air isolation cover and is connected to the air isolation cover through a sealing structure.

[0007] In one feasible implementation, the outer temperature control structure further includes a sliding partition; The slidable partition is slidably engaged with the side wall of the air isolation cover via a guide rail, which extends along the horizontal direction of the air isolation cover; The sliding partition has coupling openings.

[0008] In one feasible implementation, the vacuum adsorption device further includes an air channel formed inside the chip stage, the air channel being connected to the adsorption hole; The end of the air passage extends to the side wall of the chip stage and is provided with a vacuum generator interface.

[0009] In one feasible implementation, the inner temperature control structure has an internal heating element and an internal temperature sensor built in. The inner heating element is a columnar electric heating tube embedded inside the chip carrier. The inner heating element is used to heat the chip. The inner temperature sensor is a PT sensor, which is embedded on the side of the chip stage near the upper surface. The inner temperature sensor is used to detect the chip temperature in real time.

[0010] In one feasible implementation, the outer temperature control structure has an integrated outer heating element and an outer temperature sensor. The outer heating element is a ceramic heating plate, which is fixed on the upper surface of the bottom substrate of the outer temperature control structure. The outer heating element is used to heat the air isolation cover and the high-temperature inner chamber. The outer temperature sensor is disposed on the inner wall of the air isolation cover, and the outer temperature sensor is used to detect the temperature of the air isolation cover in real time.

[0011] One feasible implementation also includes: a bottom adapter; The bottom adapter is disposed below the bottom substrate and is connected via the low thermal conductivity connecting post; The bottom adapter is made of heat-insulating material and is used to connect external devices.

[0012] In one feasible implementation, the guide rail is a rectangular groove, which is formed on the left and right side walls of the air isolation cover; The slidable partition is engaged with the slide groove by a slider, and the slider is fixed to the bottom of the slidable partition.

[0013] In one feasible implementation, the low thermal conductivity connecting posts are zirconia ceramic pillars, and the low thermal conductivity connecting posts are evenly distributed at the four corners of the lower surface of the chip stage.

[0014] In one feasible implementation, an openable access door is provided on one side of the air isolation cover. The access door is connected to the air isolation cover via a hinge, and a sealing strip is provided at the contact point between the access door and the air isolation cover.

[0015] The beneficial effects of the high-temperature chip temperature control testing device provided in this application are as follows: Through the synergistic effect of the dual-layer temperature control structure, the outer layer isolates external airflow disturbances, while the inner layer directly contacts the chip to control the temperature and reduce temperature difference. Combined with the zirconium oxide ceramic pillar to reduce heat conduction, it effectively improves the temperature control stability in the range of room temperature to 300℃, which can meet the temperature control requirements of different precision. The sliding partition and opening design allow for flexible adjustment of the coupling position, adapting to different specifications of optical coupling components and broadening the applicability of the device. The vacuum adsorption device ensures that the chip is firmly fixed, the sealing structure enhances the airtightness of the chamber, and the temperature control system achieves precise temperature control. All components work together to ensure the accuracy and reliability of the test results. The high borosilicate glass observation window facilitates real-time observation, the openable and closable access door makes chip retrieval convenient, and the sliding partition allows for flexible adjustment, improving the ease of operation of the device. Attached Figure Description

[0016] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with the implementation of this application and, together with the description, serve to explain the principles of the embodiments of this application. It is obvious that the drawings described below are merely some embodiments of the implementation of this application, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0017] Figure 1 This is a schematic diagram of the overall structure of a high-temperature chip temperature control testing device shown in an exemplary embodiment of this application; Figure 2 This is a schematic diagram illustrating the structure of the inner temperature control structure in an exemplary embodiment of this application; Figure 3 This is a schematic diagram of the structure of an air isolation cover shown in an exemplary embodiment of this application.

[0018] Attached image annotations: 1-High borosilicate glass observation window; 2-Sliding partition; 3-Air isolation cover; 4-Bottom substrate; 5-Low thermal conductivity connecting post; 6-Bottom adapter; 7-Vacuum generator interface; 8-Adsorption hole; 9-Chip stage; 10-Inner layer temperature sensor; 11-Heating element; 12-Outer layer heating element; 13-Coupling opening. Detailed Implementation

[0019] Example implementations will now be described more fully with reference to the accompanying drawings. However, example implementations can be implemented in many forms and should not be construed as limited to the examples set forth herein.

[0020] Conversely, these implementations are provided to make the embodiments of this application more comprehensive and complete, and to fully convey the concept of exemplary embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more implementations. In the following description, numerous specific details are provided to give a thorough understanding of the implementation of the embodiments of this application.

[0021] This embodiment provides a high-temperature chip temperature control testing device, including an inner layer temperature control structure and an outer layer temperature control structure working together, as shown in the following figure. Figures 1-3 As shown, the outer temperature control structure includes an air isolation cover 3 and a bottom substrate 4. The air isolation cover 3 is installed on the upper surface edge of the bottom substrate 4 by mechanical fixing (such as bolt connection), thereby enclosing a relatively sealed high-temperature inner cavity.

[0022] The inner temperature control structure includes a chip stage 9, which is located within a high-temperature inner cavity, and its upper surface is used to directly support the chip to be tested. The chip stage 9 is connected to a vacuum adsorption device, which includes multiple adsorption holes 8 formed on the upper surface of the chip stage 9 for fixing the chip by negative pressure.

[0023] The inner temperature control structure and the outer temperature control structure are connected by multiple low thermal conductivity connecting posts 5. One end of the low thermal conductivity connecting post 5 is fixed to the lower surface of the chip stage 9 (e.g., by high temperature adhesive bonding), and the other end is fixed to the corresponding position on the upper surface of the bottom substrate 4.

[0024] In this configuration, the air isolation cover 3 is used to physically isolate the external airflow, the bottom substrate 4 serves as a supporting base to ensure structural stability, the chip stage 9 achieves precise temperature control of the chip through direct contact, the vacuum adsorption device provides a non-contact fixing method to avoid mechanical damage to the chip, and the low thermal conductivity connecting post 5 undertakes the mechanical connection function while minimizing the heat conduction path.

[0025] Optionally, the air isolation cover 3 can be configured as a cuboid box structure, and the bottom substrate 4 is a rectangular plate to match the standard chip size; the low thermal conductivity connecting pillars 5 can be evenly distributed at the four corners of the lower surface of the chip stage 9 to optimize the force distribution.

[0026] When the device is started, the chip under test is first placed on the upper surface of the chip stage 9. The vacuum adsorption device is activated by an external vacuum pump, creating negative pressure at the adsorption holes 8 to firmly adsorb and fix the chip. Subsequently, the outer temperature control structure forms a sealed chamber through the air isolation cover 3, effectively blocking the interference of external airflow on the internal temperature; the inner temperature control structure controls the temperature by heating or cooling through direct contact with the chip. The low thermal conductivity connecting post 5, while connecting the inner and outer structures, significantly reduces heat conduction loss from the high-temperature inner chamber to the external environment due to its low thermal conductivity.

[0027] This embodiment reduces heat loss and temperature fluctuations through physical isolation and material optimization. The dual-layer temperature control design reduces interference from external airflow to the testing environment, improving temperature stability and solving the problems of temperature instability caused by external airflow disturbances, excessive temperature differences between the chip and the cavity, and thermal conduction interference in existing technologies. Secondly, direct contact temperature control reduces the temperature difference between the chip and the cavity environment, making the chip's operating state closer to real-world scenarios. Finally, the low thermal conductivity connecting post 5 weakens the heat conduction path, further improving energy efficiency and temperature control accuracy. Through the synergy of the dual-layer structure—the outer layer focusing on environmental isolation and the inner layer directly controlling the chip temperature—a more stable temperature field is achieved within the range of room temperature to 300°C.

[0028] In some embodiments, the outer temperature control structure further includes a borosilicate glass observation window 1, which is disposed at the top opening of the air isolation hood 3. The opening is typically designed to be rectangular or circular to match the overall structure of the air isolation hood 3. The borosilicate glass observation window 1 is connected to the edge of the opening of the air isolation hood 3 through a sealing structure (e.g., a rubber gasket). The sealing structure surrounds the circumferential surface of the borosilicate glass observation window 1 and is pressed against the contact interface of the air isolation hood 3, thereby enhancing the airtightness of the high-temperature inner cavity while ensuring optical transmittance.

[0029] The high borosilicate glass observation window 1 provides the operator with a real-time observation channel to facilitate monitoring the status of the chip inside the cavity, while the sealing structure is used to prevent heat leakage or intrusion of external contaminants under high temperature conditions.

[0030] Optionally, the high borosilicate glass observation window 1 can be made of high borosilicate glass, whose high temperature resistance ensures that it maintains transparency and structural stability at 300°C; the sealing structure can be set as a compression gasket, which is fixed by bolts or clips to accommodate the thermal expansion effect.

[0031] When the device is started and enters the high-temperature testing phase, the operator can directly visually inspect the surface condition of the chip or the optical coupling process through the borosilicate glass observation window 1, enhancing the transparency and controllability of the testing process. Furthermore, it eliminates the need to open the air isolation hood 3, thus avoiding sudden temperature changes caused by frequent opening and closing. The sealing structure maintains pressure during thermal cycling, effectively blocking the exchange of airflow between the inside and outside, reducing heat loss, and helping to maintain temperature uniformity within the high-temperature chamber.

[0032] In some embodiments, the outer temperature control structure further includes a sliding partition 2. In one embodiment, the sliding partition 2 is slidably engaged with the side wall of the air isolation cover 3 via a guide rail. The guide rail extends horizontally along the air isolation cover 3 and is typically located on the left and right side walls of the air isolation cover 3, forming a rectangular groove structure. The sliding partition 2 is provided with a coupling opening 13 (e.g., a circular hole with a diameter of 16 mm) for inserting an optical coupling probe during optical chip testing.

[0033] The sliding partition 2 serves to flexibly adjust the test position to adapt to the coupling requirements of different areas of the chip, while the guide rail provides guidance to ensure smooth movement and accurate positioning of the partition. Optionally, the guide rail can be designed as a linear groove with a depth and width matching the slider size of the sliding partition 2; the position of the coupling opening 13 can be optimized based on the chip layout to achieve multi-area coverage.

[0034] During device use, testers can align the coupling opening 13 with specific test points on the chip by horizontally sliding the sliding partition 2. Then, external optical coupling components can be inserted through the coupling opening 13 for measurement without disassembling the air isolation cover 3. The guide rail ensures a linear sliding trajectory, avoiding alignment errors caused by offset.

[0035] In some embodiments, in addition to the adsorption holes 8, the vacuum adsorption device also includes air channels formed inside the chip stage 9. These air channels communicate with the adsorption holes 8, forming a network or branched path to ensure uniform negative pressure distribution. The ends of the air channels extend to the sidewall of the chip stage 9 and are provided with a vacuum generator interface 7. The vacuum generator interface 7 generally adopts... The threaded interface and vacuum generator interface 7 can be a metal tube for connecting an external vacuum pump. The function of the air passage is to conduct negative pressure airflow to achieve synergistic adsorption of the adsorption holes 8, while the vacuum generator interface 7 serves as a connection point for external equipment, simplifying system integration.

[0036] In this embodiment, an external vacuum pump delivers negative pressure to the gas channel through the vacuum generator interface 7, causing the adsorption holes 8 to generate adsorption force, thus fixing the chip to the upper surface of the chip stage 9. The gas channel layout ensures consistent pressure in each hole, avoiding localized stress concentration and reducing the risk of chip warping. This solves the problem of insecure chip fixation or poor thermal contact, improving temperature control uniformity while reducing mechanical clamping.

[0037] In some embodiments, the inner layer temperature control structure further includes an inner layer heating element 11 and an inner layer temperature sensor 10.

[0038] In one embodiment, the inner heating element 11 is configured as a columnar heating tube and embedded inside the chip stage 9, typically distributed in the core area of ​​the stage to optimize heat conduction; the inner temperature sensor 10 is configured as a PT1000 sensor and embedded on the side of the chip stage 9 near the upper surface, with its position corresponding to the chip contact surface to ensure representative detection.

[0039] The inner heating element 11 is used to rapidly heat up the chip through direct thermal contact, while the inner temperature sensor 10 is used to monitor the chip temperature in real time and provide feedback signals.

[0040] The solution allows for the addition of an external temperature control system, electrically connected to the inner heating element 11 and the inner temperature sensor 10. This system adjusts the output power of the heating element based on the temperature detection signal, achieving precise temperature control. When the temperature control system is activated, the inner heating element 11 receives the control signal and begins to heat up. The heat is conducted to the chip via the chip carrier 9, achieving temperature rise. Simultaneously, the inner temperature sensor 10 collects temperature data in real time and feeds it back to the external temperature control system. The temperature control system dynamically adjusts the heating power using a PID algorithm to maintain the set temperature.

[0041] This embodiment achieves rapid and uniform heating through the inner heating element 11, reducing the temperature difference between the chip and the environment. Secondly, the inner temperature sensor 10 provides high-precision temperature feedback, enhancing temperature control stability. The overall integrated design reduces external interference, thereby improving test repeatability and reliability, and further strengthening the accuracy of inner layer temperature control.

[0042] In some embodiments, the outer temperature control structure further includes an outer heating element 12 and an outer temperature sensor.

[0043] In one embodiment, the outer heating element 12 is configured as a ceramic heating plate, fixed to the upper surface of the bottom substrate 4 of the outer temperature control structure, and typically attached to the central area of ​​the substrate to radiate heat; the outer temperature sensor is disposed on the inner wall of the air isolation shroud 3, with its position selected at a key point of airflow circulation to represent the chamber temperature. The function of the outer heating element 12 is to assist in heating the air isolation shroud 3 and the high-temperature inner chamber, reducing the ambient temperature difference, while the outer temperature sensor is used to detect the shroud temperature in real time and provide feedback for outer temperature control.

[0044] Optionally, the outer heating element 12 can be arranged in an array to cover the effective area of ​​the bottom substrate 4; the type of the outer temperature sensor can be the same as that of the inner temperature sensor to ensure system compatibility.

[0045] When the device is running, the outer heating element 12 works in conjunction with the heating element 11 to preheat the air isolation cover 3 and the air in the inner cavity to reduce thermal shock; the outer temperature sensor continuously collects data and compares it with the inner temperature signal through the temperature control system to dynamically adjust the outer heating power to compensate for environmental heat loss.

[0046] This process resolves the temperature control disturbances caused by outer layer temperature lag or unstable airflow, achieving balanced thermal management through dual-layer temperature monitoring. By introducing an outer layer heating compensation mechanism, overall temperature consistency is improved while maintaining chamber sealing.

[0047] In one embodiment, the device further includes a bottom adapter 6. The bottom adapter 6 is disposed below the bottom substrate 4 and is typically connected to the lower surface of the bottom substrate 4 by mechanical fastening (such as bolting or bonding), and indirectly coupled to the upper structure via low thermal conductivity connecting posts 5 (such as zirconia ceramic posts). The bottom adapter 6 is made of a thermally insulating material, such as a ceramic composite or a polymer thermal insulation layer, to reduce heat conduction and provide an interface for external devices.

[0048] The bottom adapter 6 serves to enhance the overall thermal insulation performance of the device, while also acting as a mechanical base to connect external equipment (such as support frames or auxiliary systems), and the low thermal conductivity connecting column 5 maintains thermal insulation between the inner and outer layers.

[0049] Optionally, the bottom adapter 6 can be designed as a plate structure with dimensions matching the bottom substrate 4 to optimize stress distribution; its thermal insulation material blocks heat transfer downwards through low thermal conductivity, and the external device interface can be standardized as a threaded hole or slot for easy integration.

[0050] In one embodiment, the guide rail is configured as a rectangular groove, which is opened on the left and right side walls of the air isolation cover 3 and usually extends along the vertical or horizontal direction of the side wall to form a straight guide channel; the slidable partition 2 is engaged with the groove by a slider, and the slider is fixed to the bottom of the slidable partition 2, for example by bolts or adhesive, to ensure the fit between the partition and the groove during the sliding process.

[0051] The rectangular groove serves to provide a precise movement path, restricting the sliding partition 2 to move only in a set direction, while the slider acts as a sliding carrier to reduce frictional resistance.

[0052] Optionally, the depth and width of the rectangular groove can be designed based on the partition size to match the shape of the slider; the slider material can be a low coefficient of friction material, such as polytetrafluoroethylene, to improve the smoothness of sliding.

[0053] In one embodiment, the low thermal conductivity connecting post 5 is specifically a zirconia ceramic post, and its material is selected from zirconia ceramic to take advantage of its low thermal conductivity characteristics; the low thermal conductivity connecting posts 5 are evenly distributed at the four corners of the lower surface of the chip stage 9, and are usually fixed by high temperature adhesive or mechanical fastening, for example, the two ends of the post are respectively connected to the lower surface of the chip stage 9 and the upper surface of the bottom substrate 4.

[0054] The low thermal conductivity connecting column 5 serves to mechanically support the inner temperature control structure. At the same time, the low thermal conductivity of ceramics reduces the conduction of heat from the high-temperature inner cavity to the external environment, while uniform distribution optimizes the force balance and avoids stress concentration.

[0055] In some embodiments, the air isolation hood 3 is provided with an openable and closable access door.

[0056] In one embodiment, an openable access door is provided on one side of the air isolation cover 3, for example, connected to the air isolation cover 3 by a hinge, allowing the door to rotate around an axis to open and close; a sealing strip, usually made of rubber or silicone, is provided at the contact point between the access door and the air isolation cover 3, and is installed around the edge of the door frame.

[0057] By setting up an openable and closable door, it is convenient to pick up and put down chip samples, reducing test interruption time, while the sealing strip is used to maintain the airtightness of the high-temperature inner chamber when the door is closed, preventing heat leakage.

[0058] As can be seen from the above embodiments, when using the high-temperature chip temperature control testing device provided in this application, the chip is first placed through the openable and closable door and fixed by vacuum adsorption; then the sliding partition is adjusted to align with the test point and the chamber is closed; then the temperature control system is started, parameters are set, the double-layer heating elements work together to raise the temperature, and the internal and external temperature sensors provide real-time feedback for dynamic adjustment; during the test, the device is monitored through a high borosilicate glass observation window, and the optical coupling component is connected through the opening in the partition; after completion, the device is reset.

[0059] This application employs a collaborative design of an inner and outer dual-layer temperature control structure, comprising an outer and an inner temperature control structure connected by low thermal conductivity connecting pillars to reduce heat conduction. The outer structure forms a relatively sealed high-temperature internal chamber through an air isolation hood and integrates a high-borosilicate glass observation window for observation and a sliding partition for optical chip coupling testing. The inner structure directly contacts the chip for temperature control via a chip stage and integrates a vacuum adsorption device to fix the chip. This solution isolates the chip from external airflow disturbances through the outer structure, reduces the temperature difference between the chip and the chamber through the inner structure, and achieves closed-loop temperature control through internal and external heating elements and internal and external temperature sensors. It solves the technical pain points of single-layer temperature control, such as large temperature fluctuations, poor adaptability, and thermal conduction interference, achieving high-precision and stable temperature control from room temperature to 300℃.

[0060] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the disclosure in the specification and the embodiments. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein.

Claims

1. A high temperature chip thermal control test apparatus, characterized by, The application relates to a temperature-controllable structure for a wafer prober. The temperature-controllable structure comprises an inner temperature-controllable structure and an outer temperature-controllable structure. The outer temperature-controllable structure comprises an air isolation cover (3) and a bottom base plate (4), the air isolation cover (3) is fixed to the upper surface of the bottom base plate (4) and forms a high-temperature inner chamber. The inner temperature-controllable structure comprises a chip carrier (9), the chip carrier (9) is arranged in the high-temperature inner chamber and the upper surface of the chip carrier (9) is used for carrying a chip. The chip carrier (9) is integrated with a vacuum adsorption device, the vacuum adsorption device comprises a plurality of adsorption holes (8) formed in the upper surface of the chip carrier (9). The inner temperature-controllable structure (9) and the outer temperature-controllable structure are connected through a plurality of low-thermal-conductivity connecting columns (5), one end of the low-thermal-conductivity connecting column (5) is fixed to the lower surface of the inner temperature-controllable structure (9) and the other end is fixed to the upper surface of the bottom base plate (4) of the outer temperature-controllable structure.

2. The high temperature chip thermal control test apparatus of claim 1, wherein, The outer temperature-controllable structure further comprises a high-boron glass observation window (1). The high-boron glass observation window (1) is arranged at the top opening of the air isolation cover (3) and is connected with the air isolation cover (3) through a sealing structure.

3. The high temperature chip thermal control test apparatus of claim 1, wherein The outer temperature-controllable structure further comprises a slidable partition plate (2). The slidable partition plate (2) is slidably connected with the side wall of the air isolation cover (3) through a guide rail, the guide rail extends along the horizontal direction of the air isolation cover (3). A coupling hole (13) is formed in the slidable partition plate (2).

4. The high temperature chip thermal control test apparatus of claim 1, wherein The vacuum adsorption device (8) further comprises an air channel formed in the inner portion of the chip carrier (9), the air channel is communicated with the adsorption hole (8). The end of the air channel extends to the side wall of the chip carrier (9) and is provided with a vacuum generator interface (7).

5. The high temperature chip thermal control test apparatus of claim 1, wherein The inner temperature-controllable structure is internally provided with an inner heating element (11) and an inner temperature sensor (10). The inner heating element (11) is a columnar electric heating tube embedded in the inner portion of the chip carrier (9), the inner heating element (11) is used for heating the chip. The inner temperature sensor (10) is a PT1000 sensor embedded in the side close to the upper surface of the chip carrier (9), the inner temperature sensor (10) is used for detecting the temperature of the chip in real time.

6. The high temperature chip thermal control test apparatus of claim 1, wherein The outer temperature-controllable structure is internally provided with an outer heating element (12) and an outer temperature sensor. The outer heating element (12) is a ceramic heating sheet fixed to the upper surface of the bottom base plate (4) of the outer temperature-controllable structure, the outer heating element (12) is used for heating the air isolation cover (3) and the high-temperature inner chamber. The outer temperature sensor is arranged on the inner side wall of the air isolation cover (3), the outer temperature sensor is used for detecting the temperature of the air isolation cover (3) in real time.

7. The high temperature chip thermal control test apparatus of claim 1, wherein The application further comprises a bottom adapter (6). The bottom adapter (6) is arranged below the bottom base plate (4) and is connected through the low-thermal-conductivity connecting column (5). The bottom adapter (6) is made of heat insulation material and is used for connecting external equipment. The guide rail is a rectangular sliding groove formed in the left and right side walls of the air isolation cover (3).

8. The high temperature chip thermal control test apparatus of claim 3, wherein, ​ The slidable partition plate (2) is matched with the sliding groove through a sliding block fixed to the bottom of the slidable partition plate (2).

9. The high-temperature chip thermal control test apparatus of claim 1, wherein, The low-thermal-conductivity connecting column (5) is a zirconium oxide ceramic column, and is evenly distributed at the four corner positions of the lower surface of the chip loading platform (9).

10. The high-temperature chip thermal control test apparatus of claim 1, wherein, One side of the air isolation cover (3) is provided with an openable and closable taking and placing door, the taking and placing door is connected with the air isolation cover (3) through a hinge, and a sealing strip is arranged at the contact position of the taking and placing door and the air isolation cover (3).

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