Method and device for upgrading firmware of digital signal processor and electronic equipment

Abstract

The invention discloses a method and a device for upgrading firmware of a digital signal processor and electronic equipment. The method comprises the following steps: acquiring a slave state of a slave digital signal processor by a host system-on-chip; selecting an upgrading mode by the host system-on-chip according to the slave state; and carrying out firmware upgrading on the slave digital signal processor by the host system-on-chip through bridging from a serial peripheral interface to an advanced peripheral bus SPI2APB according to the upgrading mode. According to the method, the host SoC and the slave DSP complete firmware upgrading on the basis of SPI2APB bridging, no extra switch chip needs to be configured in the process, and no time division multiplexing needs to be performed on a DSP Flash memory, so that non-inductive and empty chip upgrading is realized, the upgrading cost is reduced, and the upgrading efficiency is improved.

Description

Technical Field

[0001] This invention relates to the field of smart cockpit firmware upgrade technology, and in particular to methods, apparatus, and electronic devices for upgrading digital signal processor firmware. Background Technology

[0002] Upgrading the Digital Signal Processor (DSP) in existing smart cockpits involves adding a switch chip (a core component of an Ethernet switch, responsible for efficient data forwarding between multiple ports) to time-multiplex the DSP's Flash memory. During startup, the DSP Flash memory connects to the DSP, and the bootloader reads the firmware from the DSP Flash memory into Static Random-Access Memory (SRAM) for booting. During upgrades, the DSP Flash memory connects to the System-on-Chip (SoC) host, which controls the DSP Flash memory to perform erase and write operations, updating the firmware. This design allows for seamless and blank DSP upgrades. However, this upgrade scheme requires an external switch chip to implement time-multiplexing of the DSP Flash memory, increasing upgrade costs and reducing upgrade efficiency. Summary of the Invention

[0003] This invention provides a method, apparatus, and electronic device for upgrading the firmware of a digital signal processor, which can reduce upgrade costs and improve upgrade efficiency while achieving seamless and blank chip upgrades.

[0004] In one aspect of the present invention, a method for upgrading the firmware of a digital signal processor is provided. The method includes: obtaining a slave status of a slave digital signal processor from a host system-on-a-chip (SoC); selecting an upgrade method based on the slave status from the host SoC; and performing a firmware upgrade on the slave digital signal processor by the host SoC via a Serial Peripheral Interface (SPI) to an Advanced Peripheral Bus (SPI2APB) bridge according to the upgrade method.

[0005] In another aspect of the invention, an apparatus for upgrading the firmware of a digital signal processor is provided. The apparatus includes: a host system-on-a-chip (SoC) and a slave digital signal processor; the host SoC is configured to acquire a slave status of the slave digital signal processor, select an upgrade method based on the slave status, and send system firmware to the slave digital signal processor via a Serial Peripheral Interface to Advanced Peripheral Bus (SPI2APB) bridge according to the upgrade method; the slave digital signal processor is configured to receive the system firmware sent by the host SoC via the SPI2APB bridge for firmware upgrade.

[0006] In another aspect of the invention, an electronic device is provided. The electronic device includes a memory configured to store an executable program; and a processor configured to execute the program to perform the aforementioned method for upgrading the firmware of a digital signal processor.

[0007] According to the technical solution of the present invention, the host system-on-a-chip (SoC) obtains the slave status of the slave digital signal processor (DSP), selects the upgrade method based on the slave status, and performs firmware upgrade on the slave DSP through the serial peripheral interface to the Advanced Peripheral Bus (SPI2APB) bridge according to the upgrade method. In this way, the host SoC and the slave DSP complete the firmware upgrade based on the SPI2APB bridge. This process does not require the configuration of an additional switch chip, nor does it require time-division multiplexing of the DSP Flash memory, thereby achieving seamless and empty chip upgrade while reducing upgrade costs and improving upgrade efficiency. Attached Figure Description

[0008] Figure 1 This is a flowchart of a method for upgrading the firmware of a digital signal processor according to an embodiment of the present invention; Figure 2 This is a schematic diagram of the upgrade process of a method for upgrading the firmware of a digital signal processor according to an embodiment of the present invention; Figure 3 This is a schematic diagram illustrating the interaction between a host SoC and a slave DSP in a method for upgrading the firmware of a digital signal processor according to an embodiment of the present invention. Figure 4 This is a schematic diagram of an apparatus for upgrading the firmware of a digital signal processor according to an embodiment of the present invention; Figure 5 This is a schematic diagram of the structure of an electronic device according to an embodiment of the present invention. Detailed Implementation

[0009] To explain in detail the technical content, objectives, and effects of the present invention, the following description is provided in conjunction with the embodiments and accompanying drawings.

[0010] In existing technologies, firmware upgrades for DSPs are performed by adding a switch chip to the hardware. The DSP Flash memory is time-multiplexed using the switch_sel pin (a control pin used to control the switching circuit or select different signal paths). During the power-on process, the DSP Flash memory is connected to the DSP through the switch chip. During the upgrade process, the DSP Flash memory is connected to the SoC through the switch chip to complete the firmware upgrade. However, the external switch chip increases the upgrade cost, and time-multiplexing the DSP Flash memory also reduces the upgrade efficiency.

[0011] To address at least the aforementioned technical problems, this disclosure provides a method for upgrading the firmware of a digital signal processor (DSP). According to this disclosure, the host system-on-a-chip (SoC) obtains the slave status of the slave DSP, selects an upgrade method based on the slave status, and performs a firmware upgrade on the slave DSP via a Serial Peripheral Interface (SPI) to Advanced Peripheral Bus (SPI2APB) bridge. In this manner, the host SoC and the slave DSP complete the firmware upgrade via SPI2APB bridging. This process eliminates the need for an additional switch chip and time-division multiplexing of the DSP Flash memory, thereby achieving seamless and blank-chip upgrades while reducing upgrade costs and improving upgrade efficiency.

[0012] In the following, the technical solutions according to this disclosure will be described with reference to specific embodiments and in conjunction with the accompanying drawings.

[0013] Figure 1 This is a flowchart illustrating a method 100 for upgrading the firmware of a digital signal processor according to an embodiment of the present disclosure. (Refer to...) Figure 1 The method 100 includes the following steps 102 to 106.

[0014] In step 102, the slave status of the slave digital signal processor is obtained by the host system-on-a-chip.

[0015] In some embodiments, the host system-on-a-chip (SoC) is electrically coupled to the slave digital signal processor (DSP) via a Serial Peripheral Interface (SPI). Furthermore, the SoC sends a status read command to the slave DSP, and the slave DSP sends a status register value to the SoC according to the status read command.

[0016] In this way, the slave DSP sends the status register value to the host SoC, enabling the host SoC to obtain the current system status of the slave DSP and thus determine which upgrade method can be used to successfully complete the firmware upgrade.

[0017] In some embodiments, the method 100 may further include: the host system-on-a-chip sending a communication data packet to the slave digital signal processor via a serial peripheral interface (SPI); the slave digital signal processor receiving the communication data packet via the SPI2APB bridge and returning a response data packet to the host system-on-a-chip; and the host system-on-a-chip receiving the response data packet via the SPI2APB bridge to establish communication between the host system-on-a-chip and the slave digital signal processor.

[0018] In this way, the host SoC and the slave DSP communicate via SPI to achieve high-speed data transmission and ensure efficient firmware upgrades.

[0019] In step 104, the host system-on-a-chip selects the upgrade method based on the slave device status.

[0020] In some embodiments, if the slave device is in a normal state, the host system-on-a-chip (SoC) selects a seamless upgrade method. Conversely, if the slave device is in an abnormal state, the host SoC selects a blank chip upgrade method.

[0021] In this way, when the slave device is in normal condition, a seamless upgrade can be directly selected, and when the slave device is in abnormal condition, a blank chip upgrade can be selected, which improves the flexibility of firmware upgrades and also enables security detection of system status.

[0022] In step 106, the host system-on-a-chip performs firmware upgrade on the slave digital signal processor by bridging the serial peripheral interface to the Advanced Peripheral Bus (SPI2APB) according to the upgrade method.

[0023] In some embodiments, if the upgrade method is the seamless upgrade method, the host system-on-a-chip (SoC) transmits the system firmware to the slave digital signal processor (DSP) via the SPI2APB bridge. Furthermore, after receiving the system firmware via the SPI2APB bridge, the slave DSP writes the system firmware into the flash memory of the slave DSP through an application program to complete the firmware upgrade.

[0024] In this way, when the slave device is in normal condition, each core does not need to enter a special mode during the upgrade process. The upgrade is achieved efficiently and seamlessly between the host SoC and the slave DSP via SPI2APB bridging, without affecting audio functions, etc.

[0025] In some embodiments, the host system-on-a-chip (SoC) packages the system firmware, and the host SoC transmits the packaged system firmware to the slave digital signal processor via the SPI2APB bridge.

[0026] In this way, by transmitting the system firmware in packets, network bandwidth can be utilized more efficiently, the overall transmission speed can be improved, and each packet is relatively independent and small. Even if some packets fail to transmit, the impact on the overall firmware transmission is small, reducing the risk of transmission interruption due to network problems and ensuring the stability of data transmission.

[0027] In some embodiments, if the upgrade method is the blank chip upgrade method, the host system-on-a-chip (SoC) sends a request to enter a special programming mode to the slave digital signal processor (DSP) via the SPI2APB bridge. After receiving the request via the SPI2APB bridge, the slave DSP enters the special programming mode. The host SoC sends the bootloader to the slave DSP via the SPI2APB bridge. After receiving the bootloader via the SPI2APB bridge, the slave DSP programs the bootloader into its flash memory. The host SoC sends the system firmware to the slave DSP via the SPI2APB bridge. Furthermore, after receiving the system firmware via the SPI2APB bridge, the slave DSP programs the system firmware into its flash memory to complete the firmware upgrade.

[0028] In this way, based on SPI2APB bridging, the DSP can still be upgraded normally without time-multiplexing the DSP Flash memory and adding an external switch chip when the system is abnormal, thus reducing the upgrade cost while ensuring the reliability of firmware upgrades.

[0029] In some embodiments, after step 106, the method 100 may further include: after the firmware upgrade is completed, the slave digital signal processor returns the write status to the host system-on-a-chip via the SPI2APB bridge.

[0030] In this way, the host SoC can directly and conveniently understand the firmware upgrade completion status by having the slave DSP return the write status.

[0031] Figure 2 This is a flowchart illustrating a method for upgrading the firmware of a digital signal processor according to an embodiment of the present invention. (Refer to...) Figure 2 The method includes steps 201 to 213.

[0032] In step 201, the slave status of the slave DSP is obtained by the host SoC.

[0033] In some embodiments, the host SoC and the slave DSP are electrically coupled via SPI. Furthermore, the host SoC sends a status read command to the slave DSP, and the slave DSP sends the status register value back to the host SoC based on the status read command.

[0034] In some embodiments, prior to step 201, the method may further include: the host SoC sending a communication data packet to the slave DSP via SPI; the slave DSP receiving the communication data packet via SPI2APB bridging and returning a response data packet to the host SoC; and the host SoC receiving the response data packet via SPI2APB bridging to establish communication between the host SoC and the slave DSP.

[0035] In step 202, if the slave device is in a normal state, the host SoC will select the seamless upgrade method.

[0036] For example, if the status register value sent by the slave DSP is 1, it means that the slave is in a normal state, and the upgrade method is selected as the seamless upgrade method.

[0037] In step 203, if the slave device is in an abnormal state, the host SoC will select the blank chip upgrade method as the upgrade method.

[0038] For example, if the status register value sent by the slave DSP is 0, it indicates that the slave is in an abnormal state, and the upgrade method will be selected as blank chip upgrade method.

[0039] In step 204, if the upgrade method is a seamless upgrade method, the host SoC will transmit the system firmware to the slave DSP via the SPI2APB bridge.

[0040] In some embodiments, the host SoC divides the system firmware into packets, and the host SoC transmits the divided system firmware to the slave DSP via SPI2APB bridging.

[0041] In step 205, after the slave DSP receives the system firmware via the SPI2APB bridge, the application program writes the system firmware into the DSP Flash memory to complete the firmware upgrade.

[0042] In step 206, the slave DSP returns the write status to the host SoC via the SPI2APB bridge.

[0043] In step 207, if the upgrade method is blank chip upgrade, the host SoC sends a request to enter a special programming mode (such as maskroom mode) to the slave DSP via SPI2APB bridge.

[0044] In step 208, after the slave DSP receives the request via SPI2APB bridge, it enters a special programming mode.

[0045] In step 209, the host SoC sends the bootloader to the slave DSP via the SPI2APB bridge.

[0046] In step 210, after the slave DSP receives the boot program via SPI2APB bridge, the boot program is burned into the DSPFlash memory.

[0047] In step 211, the host SoC sends the system firmware to the slave DSP via the SPI2APB bridge.

[0048] In some embodiments, the host SoC divides the system firmware into packets, and the host SoC transmits the divided system firmware to the slave DSP via SPI2APB bridging.

[0049] In step 212, after the slave DSP receives the system firmware via SPI2APB bridge, it burns the system firmware into the DSPFlash memory to complete the firmware upgrade.

[0050] In step 213, the slave DSP returns the write status to the host SoC via the SPI2APB bridge.

[0051] Figure 3 This is a schematic diagram illustrating the interaction between the host SoC and the slave DSP in a method for upgrading the firmware of a digital signal processor according to an embodiment of the present invention. (Refer to...) Figure 3 When a firmware upgrade of the slave DSP is required, the master SoC first obtains the slave status of the slave DSP. The slave DSP returns its slave status, and the master SoC determines whether the system status is abnormal or normal based on the slave status. If the system status is determined to be abnormal, the blank chip upgrade method is selected. The master SoC requests the slave DSP to enter a special upgrade mode, such as maskroom mode. Then, the master SoC writes the bootloader to the slave DSP and then writes the firmware to the slave DSP in a loop. After the slave DSP completes the writing, it returns the write status to the master SoC, thus completing the firmware upgrade in the abnormal slave status. If the system status is determined to be normal, the seamless upgrade mode is selected. The master SoC requests the slave DSP to prepare for the upgrade, and the master SoC writes the firmware to the slave DSP in a loop. After the slave DSP completes the writing, it returns the write status to the master SoC, thus completing the firmware upgrade in the normal slave status.

[0052] According to another aspect of the invention, Figure 4 This is a block diagram illustrating an apparatus 300 for upgrading the firmware of a digital signal processor according to an embodiment of the present invention. (Refer to...) Figure 4 The device 300 for upgrading the firmware of a digital signal processor includes a host system-on-a-chip 302 and a slave digital signal processor 304.

[0053] The host system-on-a-chip 302 is configured to acquire the slave status of the slave digital signal processor 304, select an upgrade method based on the slave status, and send the system firmware to the slave digital signal processor 304 via a Serial Peripheral Interface to Advanced Peripheral Bus (SPI2APB) bridge based on the upgrade method.

[0054] The slave digital signal processor 304 is configured to receive the system firmware sent by the host system-on-a-chip 302 via the SPI2APB bridge for firmware upgrade.

[0055] It should be understood that the host system-on-a-chip 302 and the slave digital signal processor 304 can be configured to further perform the corresponding steps or actions in the method for upgrading the digital signal processor firmware described in the above embodiments, which will not be repeated here.

[0056] According to another aspect of the invention, Figure 5 This is a schematic diagram illustrating a device 400 for upgrading the firmware of a digital signal processor according to an embodiment of the present invention. (Refer to...) Figure 5 The electronic device 400 includes a memory 402, a processor 404, and an executable program stored in the memory and executable on the processor. When the processor executes the executable program, it implements the steps of the method for upgrading the firmware of a digital signal processor as described above.

[0057] In summary, according to the embodiments of this disclosure, the host system-on-a-chip (SoC) obtains the slave status of the slave digital signal processor (DSP). Based on the slave status, the SoC selects an upgrade method and performs a firmware upgrade on the slave DSP via a Serial Peripheral Interface (SPI) to an Advanced Peripheral Bus (SPI2APB) bridge. This allows the host SoC and slave DSP to complete the firmware upgrade via SPI2APB bridging. This process eliminates the need for an additional switch chip and time-multiplexing of the DSP Flash memory, thereby achieving seamless and blank chip upgrades while reducing upgrade costs and improving upgrade efficiency. Furthermore, when the slave status is normal, a seamless upgrade is directly selected; when the slave status is abnormal, a blank chip upgrade is selected, improving the flexibility of firmware upgrades and providing security detection of the system status. When the slave status is normal, each core does not need to enter a special mode during the upgrade process. Efficient seamless upgrades are achieved between the host SoC and slave DSP via SPI2APB bridging without affecting audio functions, etc. Based on SPI2APB bridging, the DSP can still be upgraded normally without time-multiplexing the DSPFlash memory and adding an external switch chip when the system is abnormal, thus ensuring the reliability of firmware upgrades while reducing upgrade costs.

[0058] The above description is merely an embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent modifications made based on the content of the present invention's specification and drawings, or direct or indirect applications in related technical fields, are similarly included within the patent protection scope of the present invention.

Claims

1. A method for upgrading digital signal processor firmware, the method comprising: Comprising: acquiring, by a host system-on-chip, a slave status of a slave digital signal processor; selecting, by the host system-on-chip, an upgrade mode according to the slave status; and performing, by the host system-on-chip, firmware upgrade on the slave digital signal processor through a serial peripheral interface to advanced peripheral bus (SPI2APB) bridge according to the upgrade mode. Selecting, by the host system-on-chip, an upgrade mode according to the slave status comprises:

2. The method of claim 1, wherein, if the slave status is a normal status, selecting, by the host system-on-chip, the upgrade mode as a no-sense upgrade mode; and if the slave status is an abnormal status, selecting, by the host system-on-chip, the upgrade mode as a blank upgrade mode. Performing, by the host system-on-chip, firmware upgrade on the slave digital signal processor through a serial peripheral interface to advanced peripheral bus (SPI2APB) bridge according to the upgrade mode comprises:

3. The method of claim 2, wherein, if the upgrade mode is the no-sense upgrade mode, transmitting, by the host system-on-chip, system firmware to the slave digital signal processor through the SPI2APB bridge; and after receiving the system firmware through the SPI2APB bridge, writing, by the slave digital signal processor, the system firmware into a flash memory of the slave digital signal processor through an application program to complete the firmware upgrade. Transmitting, by the host system-on-chip, system firmware to the slave digital signal processor through the SPI2APB bridge comprises:

4. The method of claim 3, wherein, packetizing, by the host system-on-chip, the system firmware; and transmitting, by the host system-on-chip, the packetized system firmware to the slave digital signal processor through the SPI2APB bridge. Performing, by the host system-on-chip, firmware upgrade on the slave digital signal processor through a serial peripheral interface to advanced peripheral bus (SPI2APB) bridge according to the upgrade mode comprises:

5. The method of claim 2, wherein, if the upgrade mode is the blank upgrade mode, sending, by the host system-on-chip, a request for entering a special burning mode to the slave digital signal processor through the SPI2APB bridge; after receiving the request through the SPI2APB bridge, entering, by the slave digital signal processor, the special burning mode; sending, by the host system-on-chip, a boot program to the slave digital signal processor through the SPI2APB bridge; after receiving the boot program through the SPI2APB bridge, burning, by the slave digital signal processor, the boot program into a flash memory of the slave digital signal processor; sending, by the host system-on-chip, system firmware to the slave digital signal processor through the SPI2APB bridge; and after receiving the system firmware through the SPI2APB bridge, burning, by the slave digital signal processor, the system firmware into the flash memory to complete the firmware upgrade. Further comprising:

6. The method according to claim 3 or 5, characterized in that, after completing the firmware upgrade, returning, by the slave digital signal processor, a write status to the host system-on-chip through the SPI2APB bridge. ​ 7. The method of claim 1, wherein, Obtaining, by a host system-on-chip, a slave state of a slave digital signal processor includes: Sending, by the host system-on-chip, a state read instruction to the slave digital signal processor, the host system-on-chip electrically coupled to the slave digital signal processor through a serial peripheral interface; and Sending, by the slave digital signal processor, a state register value to the host system-on-chip according to the state read instruction.

8. The method of claim 1, wherein, Further comprising: Sending, by the host system-on-chip, a communication data packet to the slave digital signal processor via the serial peripheral interface; Receiving, by the slave digital signal processor, the communication data packet through the SPI2APB bridge and returning a response data packet to the host system-on-chip; and Receiving, by the host system-on-chip, the response data packet through the SPI2APB bridge to establish communication between the host system-on-chip and the slave digital signal processor. Comprising:

9. An apparatus for upgrading digital signal processor firmware, the apparatus comprising: a host system-on-chip and a slave digital signal processor; the host system-on-chip configured to obtain a slave state of the slave digital signal processor, select an upgrade mode according to the slave state, and send a system firmware to the slave digital signal processor through a serial peripheral interface to an advanced peripheral bus SPI2APB bridge according to the upgrade mode; the slave digital signal processor configured to receive the system firmware sent by the host system-on-chip through the SPI2APB bridge for firmware upgrade. Comprising:

10. An electronic device, comprising: a memory configured to store an executable program; and a processor configured to execute the program to perform the method according to any one of claims 1 to 8. ​ ​

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