adc data processing circuit of a touch controller

Abstract

The present disclosure relates to ADC data processing circuitry for touch controllers. According to one embodiment, a signal processing circuit includes a coefficient accumulator and a dual multiplexer path for processing invalid ADC samples in a touch controller. When an ADC sample exceeds a saturation threshold, the circuit selects a zero value through one multiplexer while accumulating a coefficient through the other multiplexer path. Upon receiving a first valid sample, the circuit multiplies it with the accumulated coefficient and then resumes normal coefficient processing. This architecture enables continuous processing across multiple touch sensor channels without the need for buffering while maintaining mathematical equivalence through multiplication distribution rates.

Description

Technical Field

[0001] This disclosure generally relates to signal processing architecture, and in specific embodiments to a multiply-accumulate circuit for processing invalid touch sensor data in a multichannel touchscreen controller. Background Technology

[0002] Touchscreen systems employ a matrix arrangement of sensing elements to detect user interactions using capacitive sensing technology. These systems generate analog signals when a conductive object (such as a finger or stylus) alters the capacitive field of the sensing elements. These signals are then processed by an analog-to-digital converter (ADC) to generate digital data suitable for processing by the touchscreen controller.

[0003] Modern touchscreen controllers process data from multiple sensing channels simultaneously. Each channel provides a continuous stream of ADC samples representing capacitance measurements at different locations on the touch sensor matrix. ADC samples typically have defined resolution limitations, such as 8-bit values ​​from 0 to 256, where values ​​close to the maximum value can indicate signal saturation.

[0004] Touchscreen systems operate in environments where various interference sources can affect signal integrity. For example, wireless charging systems generate electromagnetic fields, which can cause signal distortion in touch sensor readings. When such interference occurs, affected ADC samples may reach saturation levels, generating invalid data points in the digital signal stream. In multi-channel touch detection systems, the processing architecture maintains a consistent sampling and processing rate across all channels to ensure accurate touch position detection. Summary of the Invention

[0005] The embodiments disclosed herein generally achieve technical advantages, and these embodiments describe a multiply-accumulate circuit for processing invalid touch sensor data in a multichannel touchscreen controller.

[0006] The first aspect relates to a method for continuously processing signals in a touch controller, the method comprising: receiving analog-to-digital converter (ADC) samples from a plurality of parallel channels; for each channel, comparing each ADC sample with a saturation threshold to determine validity; in response to detecting an initial ADC sample exceeding the saturation threshold for each channel: selecting a zero value for multiplication to maintain continuous processing without buffering, and accumulating coefficient values ​​in a coefficient accumulator; in response to detecting a first valid ADC sample below the saturation threshold for each channel: selecting a first valid ADC sample for multiplication, and selecting an accumulated coefficient value from the coefficient accumulator to resume processing from the initial invalid sample; and performing multiplication using the first valid ADC sample and the accumulated coefficient value to maintain equivalence through a distribution rate.

[0007] The second aspect relates to a touch sensing system comprising: a touch sensor configured to sense input to a touchscreen; and a touch controller coupled to receive sensed input from the touch sensor, the touch controller including a first processing circuit and a second processing circuit, each processing circuit including: a coefficient input node configured to receive coefficient values; a coefficient accumulator; a first multiplexer having: a first input coupled to the coefficient input node, a second input coupled to the output of the coefficient accumulator, and a selection input coupled to receive an ADC validity signal; an ADC input node coupled to receive the sensed input; a second multiplexer having: a first input coupled to the ADC input node, a second input coupled to a zero-value source, and a selection input coupled to receive an ADC validity signal; and a multiplication circuit having: a first input coupled to the output of the first multiplexer and a second input coupled to the output of the second multiplexer, wherein the first processing circuit provides coefficient values ​​for determining the amplitude of the sensed input, and the second processing circuit provides coefficient values ​​for determining the phase of the sensed input.

[0008] The third aspect relates to a circuit for processing ADC samples, the circuit comprising: a coefficient input node configured to receive coefficient values; a coefficient accumulator; a first multiplexer having: a first input coupled to the coefficient input node, a second input coupled to the output of the coefficient accumulator, and a selection input coupled to receive an ADC validity signal; an ADC input node providing ADC samples; a second multiplexer having: a first input coupled to the ADC input node, a second input coupled to a zero-value source, and a selection input coupled to receive an ADC validity signal; and a multiplication circuit having: a first input coupled to the output of the first multiplexer, and a second input coupled to the output of the second multiplexer, wherein the selection input controls the first and second multiplexers to: select a zero value and a coefficient value when the ADC validity signal indicates an invalid sample, and select a first valid ADC sample and an accumulated coefficient value when the ADC validity signal indicates a first valid sample.

[0009] The embodiments can be implemented using hardware, software, or any combination thereof. Attached Figure Description

[0010] To gain a more complete understanding of this disclosure and its advantages, reference is now made to the following description in conjunction with the accompanying drawings, wherein:

[0011] Figure 1 This is a block diagram of the device in the embodiment;

[0012] Figure 2 This is a block diagram of the circuit in the embodiment;

[0013] Figure 3This is a block diagram of the selected generation circuit in the embodiment;

[0014] Figure 4 This is a block diagram of the selected generation circuit in the embodiment;

[0015] Figure 5 This is a flowchart of an embodiment method for processing distorted samples;

[0016] Figure 6 This is a timing diagram showing the normal multiplication-accumulation operation when the ADC sample is valid for a single channel; and

[0017] Figure 7 The timing diagram of the multiplication-accumulation operation when the initial ADC sample is invalid is shown. Detailed Implementation

[0018] This disclosure provides numerous applicable inventive concepts that can be embodied in a variety of specific contexts. Specific embodiments are merely illustrative of particular configurations and do not limit the scope of the claimed embodiments. Unless otherwise stated, features from different embodiments can be combined to form other embodiments. Various embodiments are illustrated in the accompanying drawings, wherein the same components and elements are identified by the same reference numerals, and repeated descriptions are omitted for brevity.

[0019] The variations or modifications described in one embodiment may also be applied to other embodiments. Furthermore, various changes, substitutions, and alterations may be made herein without departing from the spirit and scope of this disclosure as defined by the appended claims.

[0020] While the inventive aspects are described primarily in the context of touchscreen controllers that process capacitive sensor signals, it should be appreciated that these inventive aspects can also be applied to other signal processing applications that require parallel data stream processing. In particular, aspects of this disclosure can be similarly applied to digital signal processing systems where the input data stream may contain invalid or saturated samples that require continuous processing without buffering delays.

[0021] According to various embodiments, the signal processing architecture processes invalid analog-to-digital converter (ADC) samples via a multiply-accumulate circuit (MAC) that includes dual multiplexer paths. A first multiplexer selects between direct coefficient values ​​and accumulated coefficient values, while a second multiplexer selects between the ADC input sample and zero. This architecture determines sample validity by comparing the ADC value to a saturation threshold, such as 254 for an 8-bit converter.

[0022] In one or more embodiments, the architecture processes data from multiple channels simultaneously (e.g., 44 channels). Each channel provides consecutive ADC samples representing capacitance measurements at different locations on the touch sensor matrix. When wireless charging or other interference sources cause signal saturation, affected channels may produce invalid ADC samples, while other channels provide valid data.

[0023] In various embodiments, when ADC samples are valid, the circuit processes the data by selecting them via a multiplexer path and guiding coefficient values ​​for multiplication via another path. During periods of invalid data, the circuit maintains continuous operation by selecting zero values ​​for multiplication while accumulating coefficients in parallel. This approach allows processing to continue without requiring large data buffers or introducing delays.

[0024] This architecture offers a particular advantage when handling initially invalid data samples. Instead of stalling until valid data becomes available, the circuit accumulates coefficients during the invalid period. When the first valid sample arrives, the circuit multiplies that sample by the accumulated coefficients. After the first valid sample multiplication, the circuit transitions to normal operation using individual system values ​​for subsequent samples.

[0025] In one or more embodiments, this architecture can implement in-phase and quadrature (IQ) signal processing using sine and cosine coefficients. Depending on hardware requirements, the coefficient values ​​can be normalized to an 8-bit or 9-bit representation. The implementation uses two parallel multiply-accumulate circuits: one circuit processes the in-phase components with sine coefficients, and the other circuit processes the quadrature components with cosine coefficients.

[0026] The multiply-accumulate architecture allows for continuous processing across all channels without pausing or buffering when invalid samples are encountered. For channels experiencing signal saturation, the circuit maintains operation through zero substitution while preserving coefficient information through accumulation. When valid data returns, the circuit seamlessly merges the accumulated coefficients to maintain signal processing accuracy.

[0027] By handling invalid data through coefficient accumulation and zero substitution, this architecture eliminates the need for buffering samples or pausing processing. This approach is particularly valuable in multi-channel applications where some channels may experience temporary signal saturation while others continue to provide valid data. The circuit maintains a consistent processing rate while efficiently managing the transition between invalid and valid data conditions. These and other details will be further disclosed below.

[0028] Figure 1A block diagram of an embodiment device 100 is shown. Device 100 includes a touch controller 102, a touch screen 104, a processor 110, a memory 112, an interface 114, and a power system 116, which may (or may not) be arranged as shown. Device 100 may include additional components not shown, such as long-term memory (e.g., non-volatile memory), additional input and output interfaces, sensors, speakers, etc.

[0029] In this embodiment, device 100 is a smartphone, smartwatch, wearable device, tablet, laptop, gaming device, personal computer, or any other stylus-enabled device, including grid-type sensors such as touchscreen devices.

[0030] In this embodiment, the touch controller 102 is disposed on a system-on-a-chip (SoC). The touch controller 102 can be any component or set of components adapted to perform computational or other signal processing-related tasks. In this embodiment, during normal operation, the touch controller 102 controls the operation of the touchscreen 104. For example, in some embodiments, the touch controller 102 receives raw input data from the touchscreen 104 to determine the location and type of touch.

[0031] Processor 110 is configured to operate device 100. In embodiments, processor 110 is implemented as a general-purpose, custom controller, host processor, or application processor, coupled to memory 112 and configured to execute instructions from memory 112 or another memory of device 100.

[0032] In some embodiments, processor 110 may be coupled to a second memory of device 100, which stores instructions to be executed by processor 110. In some embodiments, touch controller 102 is implemented as part of processor 110. In some embodiments, processor 110 is a main processing unit, and touch controller 102 is an auxiliary processing unit. In some embodiments, touch controller 102 and processor 110 may be implemented as a single processing unit.

[0033] Memory 112 may be any component or collection of components suitable for storing programming or instructions executed by touch controller 102, processor 110, or both. In one embodiment, memory 112 includes a non-transitory computer-readable medium. In some embodiments, memory 112 is part of processor 110. In some embodiments, memory 112 is external to processor 110, such as within touch controller 102. Other implementations are also possible. In some embodiments, memory 112 may also store other data types.

[0034] Interface 114 can be any component or set of components that allows device 100 to communicate with other devices / components or a user. For example, interface 114 may be adapted to receive wireless power from an external source using transceiver circuitry and an antenna. Furthermore, interface 114 may include circuitry that allows device 100 to transmit signals, either inside or outside the device 100, the user, or the stylus.

[0035] In one embodiment, the touchscreen 104 allows a user to interact and communicate with the device 100 using a touch or stylus. In another embodiment, the touchscreen 104 includes a display layer 106 and a touch sensing layer 108.

[0036] Display layer 106 is configured to display an image. In an embodiment, a panel driver (not shown) may be coupled to display layer 106 and processor 110. The panel driver may be used to drive display layer 106. Display layer 106 may incorporate one or more display technologies, such as a light-emitting diode (LED) display, an organic LED (OLED) display, a liquid crystal display (LCD), or an active-matrix organic LED (AMOLED) display.

[0037] Touch sensing layer 108 may include an array of sensors arranged in a grid (e.g., touch grid, touch cells, or sensing elements). For example, touch sensing layer 108 may include a plurality of sensors 122 arranged in rows and columns. Sensors 122 and touch sensing layer 108 may be implemented in any manner known in the art. In an embodiment, touchscreen 104 is capacitive. In an embodiment, sensors 122 in touch sensing layer 108 may detect voltage modulation from a stylus coupled to sensor electrodes.

[0038] The touch sensing layer 108 can record user input via touch on the surface of the display layer 106. It can also be configured to detect input from other sources, such as a stylus (active or passive) device. In embodiments, the touchscreen 104 may include sensors such as a gyroscope or accelerometer. One or more of these sensors may be integrated.

[0039] In one embodiment, the touchscreen 104 may be configured to receive image data to be displayed on the display layer 106. In various embodiments, the touch controller 102 and the touch sensing layer 108 may be configured to operate based on mutual capacitance sensing technology, self-capacitance sensing methods, or a combination thereof.

[0040] Typically, touchscreen devices (such as device 100) utilize two sensing methods to detect touch: mutual capacitance and self-capacitance. Mutual capacitance sensing, or mutual sensing data, refers to a touchscreen technology in which touch detection is based on measuring the capacitance between two sensors, typically arranged in a grid of rows and columns. In this system, one sensor (transmitter) emits a signal, and the other sensor detects the corresponding change in capacitance (receiver). When a finger or stylus approaches or touches display layer 106, it interferes with the electric field between sensors on touch sensing layer 108, thereby changing the mutual capacitance at that point, which is then detected by the system. For stylus detection, touch controller 102 can use sensor electrodes to detect voltage modulation from, for example, the dual transmitters of a stylus, which enables precise position calculation.

[0041] The main advantage of mutual capacitance sensing is its ability to accurately detect and track multiple touch points, enabling advanced multi-touch functionality. Due to its high resolution and accuracy in detecting touch input used in modern touchscreens, it is suitable for applications requiring complex gestures and interactions.

[0042] Conversely, self-capacitance sensing, or self-sensing data, involves detecting touch based on changes in capacitance of individual sensors within the touch sensing layer 108. This method measures the capacitance between each sensor and ground. When a finger or stylus approaches or touches the display layer 106, it acts as a conductive object, changing the self-capacitance of the sensors in the touch sensing layer 108, which the system recognizes as a touch.

[0043] Self-capacitance faces challenges in distinguishing multiple simultaneous touches. Meanwhile, mutual capacitance is better suited for multi-touch detection because each row and column intersection can be measured independently. However, self-capacitance is more suitable for applications requiring only simple touch interactions and where cost-effectiveness is a priority. Furthermore, self-capacitance is generally more sensitive to conductive objects and can detect proximity from a greater distance, but it may be more susceptible to noise and interference. While mutual capacitance is less sensitive than self-capacitance, it is generally more accurate and less affected by noise and interference.

[0044] Power system 116 provides power for the operation and portability of device 100. Power system 116 may be a power management integrated circuit (PMIC). Power system 116 may include a controller, battery, charging circuitry, interface, and other components to allow inductive charging by transferring power from a charging pad or base station to device 100. Power system 116 may be any component or set of components for managing and controlling power distribution, conversion, and regulation within device 100. In various embodiments, power system 116 is configured to regulate the power supply voltages of various components of device 100 and control battery charging, discharging, and operational monitoring.

[0045] In one embodiment, the touch controller 102 receives analog signals representing touch or stylus interactions on the sensor grid from the touch sensing layer 108. The touch controller 102 converts these signals into digital data via analog-to-digital conversion for subsequent processing. Due to the matrix arrangement of the sensors 122 in the touch sensing layer 108, the touch controller 102 can process multiple signal channels in parallel to maintain the responsiveness of the touch system.

[0046] In this embodiment, external interference sources may cause signal distortion in some channels of the touch sensing layer 108. When distortion occurs, it may be necessary to identify the affected digital samples and replace them with valid data to maintain continuous signal processing. The touch controller 102 can process valid and invalid samples on different channels simultaneously because interference patterns may affect different parts of the touch sensing layer 108 differently.

[0047] In embodiments where subsequent samples in a channel are valid, the touch controller 102 can replace distorted samples with subsequent valid data. However, when the initial samples of a channel are distorted, there is no previously valid data to replace them. Conventional handling of such scenarios may require the touch controller 102 to pause processing or implement extensive data buffering. In multi-channel implementations, different channels may experience different modes of signal distortion, and significant hardware resources may be required to buffer the valid data while waiting for all channels to provide valid samples.

[0048] According to various embodiments, ADC samples from the touch sensor exhibit different characteristics under normal and distorted conditions. Under normal operation, the ADC samples form periodic patterns with varying amplitudes within the ADC's operating range, representing valid touch or stylus interactions detected by the touch sensing layer.

[0049] When interference occurs, such as from wireless charging operation, ADC samples may become distorted. This distortion can manifest as signal saturation, where affected samples reach their maximum ADC value, deviating significantly from the expected periodic pattern. This saturation represents invalid data that cannot be used for accurate touch detection.

[0050] Conventional methods for handling such distorted signals require buffering valid data from unaffected channels while waiting for valid samples to arrive from the distorted channels. This buffering requirement increases as channels experience consecutive distorted samples, thus increasing hardware complexity. Furthermore, processing delays occur when operation is paused until all channels provide valid data.

[0051] In this embodiment, the proposed signal processing method employs multiplexer-based signal processing to handle distorted samples without buffering. When the initial sample is distorted, the processing path replaces invalid ADC data with zero values ​​while accumulating coefficient values. After detecting the first valid ADC sample, the accumulated coefficients are applied to that first valid ADC sample. Processing then transitions to normal operation for subsequent valid samples, maintaining continuous operation without requiring additional buffer storage.

[0052] Figure 2 A block diagram of embodiment circuit 200 is shown. Circuit 200 includes a first multiplexer 202, a second multiplexer 204, a coefficient accumulator 206, a multiplier 208, an accumulator 210, and an output register 212, which may (or may not) be arranged as shown. Circuit 200 receives coefficient values, ADC data, and zero-value inputs.

[0053] In this embodiment, circuit 200 efficiently processes invalid ADC samples without requiring data buffering or processing delays. During invalid data periods, the circuit maintains continuous operation through two parallel processes: accumulating coefficient values ​​in coefficient accumulator 206 while simultaneously performing zero-value multiplication in multiplier 208.

[0054] When valid data is available, the circuit recovers the signal processing by applying the accumulated coefficients to the first valid sample, effectively capturing the mathematical operations that occurred during the invalid period. After processing the first valid sample with the accumulated coefficients, the circuit seamlessly transitions back to normal operation to select system values ​​for subsequent valid samples. This architecture eliminates the need for a large data buffer while maintaining the accuracy of signal processing through the multiplication distribution rate.

[0055] In various embodiments, circuit 200 operates in different modes depending on the validity of the initial ADC samples. When processing begins with valid data below a saturation threshold, the circuit operates directly. First multiplexer 202 selects the direct coefficient path, while second multiplexer 204 selects the ADC data input. Under these conditions, multiplier 208 processes each coefficient-ADC sample pair directly, and accumulator 210 maintains the running sum of the products.

[0056] When the initial ADC sample becomes invalid due to saturation, circuit 200 enters a different operating mode. The second multiplexer 204 selects a zero-value input, while the coefficient accumulator 206 begins summing consecutive coefficient values. During this period, due to the zero-value selection, the multiplier 208 produces a zero output, and the coefficient information is stored through accumulation.

[0057] Upon detecting a first valid ADC sample below a threshold, circuit 200 performs a recovery operation. A second multiplexer 204 switches to select valid ADC data, while a first multiplexer 202 selects the path of accumulated coefficients from coefficient accumulator 206. This allows multiplier 208 to combine all accumulated coefficients with the first valid ADC sample in a single operation to effectively recover the signal processing that occurred during the invalid period.

[0058] After processing the first valid sample with accumulated coefficients, circuit 200 returns to normal operation. The first multiplexer 202 returns to selecting the direct coefficient path, while the second multiplexer 204 continues selecting the ADC data input. This achieves standard multiply-accumulate processing for all subsequent valid samples, maintaining efficient operation until another invalid sample is detected.

[0059] As shown in the figure, the output of the first multiplexer 202 is coupled to the first input of the multiplier 208, while the output of the second multiplexer 204 is coupled to the second input of the multiplier 208. The output of the multiplier 208 is coupled to the accumulator 210, which in turn is coupled to the output register 212.

[0060] In embodiments that handle multiple parallel channels, each channel can implement an instance of circuit 200. Channels can operate independently, allowing some channels to process valid data normally, while others process invalid data through coefficient accumulation and zero substitution. Independent operation ensures that all channels maintain a consistent processing rate without requiring synchronization or buffering between channels.

[0061] Circuit 200 sequentially processes ADC samples from ADC 214 while simultaneously managing coefficient accumulation in parallel. When an invalid sample is detected, coefficient accumulator 206 maintains the running sum of the coefficients, while a zero-value path prevents invalid samples from affecting the output. After the first valid sample is detected, the accumulated coefficients are applied in a single multiplication operation to effectively recover the processing that occurred during the invalid period.

[0062] In this embodiment, the first multiplexer 202 and the second multiplexer 204 are controlled by a first selection signal (SEL_1) and a second selection signal (SEL_2). The first selection signal controls coefficient path selection, switching the first multiplexer 202 to select an accumulated coefficient value from the coefficient accumulator 206 only when a first valid ADC sample is detected after an invalid data period. The first selection signal switches the first multiplexer 202 for subsequent valid samples to select a direct coefficient input path. The second selection signal is generated based on ADC data validity detection, switching the second multiplexer 204 to select zero input when ADC samples from ADC 214 reach a saturation level.

[0063] When ADC data is invalid, coefficient accumulator 206 sums the continuous coefficient values ​​(COEFF). Coefficient accumulator 206 includes a feedback path capable of continuously adding coefficient values ​​during invalid data periods. The feedback path enables continuous operation while maintaining the running sum required for coefficient accumulation.

[0064] In one or more embodiments, the coefficient values ​​(COEFF) can represent various filter responses. For example, in an IQ signal processing implementation, circuit 200 can be replicated, with one instance using sine coefficients to process the in-phase component and another instance using cosine coefficients to process the quadrature component. The coefficient values ​​can be normalized based on hardware requirements, such as in an 8-bit or 9-bit representation.

[0065] The second multiplexer 204 selects between ADC data and a zero-value input based on the validity of the input data. When the ADC data is determined to be invalid, such as when a saturation level is reached, the second multiplexer 204 selects the zero-value input. When valid ADC data is detected, the second multiplexer 204 selects the ADC data path.

[0066] Multiplier 208 receives outputs from first multiplexer 202 and second multiplexer 204 and performs multiplication. During invalid ADC data periods, multiplication with zero values ​​results in zero output, while coefficient accumulator 206 continues to sum the coefficient values. When the first valid ADC data arrives, multiplier 208 combines this data with the accumulated coefficients from coefficient accumulator 206.

[0067] Accumulator 210 sums the products from multiplier 208 over time and stores the result in output register 212. For subsequent valid ADC samples after the first valid sample, circuit 200 operates as follows: direct coefficient values ​​are selected via first multiplexer 202, and ADC data is selected via second multiplexer 204.

[0068] Similar to coefficient accumulator 206, accumulator 210 includes a feedback path for summing the products from multiplier 208 over time. The feedback path enables continuous operation while maintaining the running sum required for output generation.

[0069] In one or more embodiments, circuit 200 maintains continuous operation by accumulating coefficients during invalid periods and applying them when valid data is available, without requiring an additional data buffer. This approach allows for parallel processing across multiple channels while managing scenarios where different channels may experience different modes of valid and invalid data.

[0070] In this embodiment, ADC data validity is determined by comparing ADC samples to a saturation threshold. For example, in an 8-bit ADC implementation, the maximum value is 256, and samples close to this maximum value (such as values ​​of 254 or 255) can indicate signal saturation. Such saturated samples are considered invalid data that requires special processing by circuitry 200.

[0071] Invalid ADC data may occur due to various interference sources. In an embodiment where device 100 receives wireless charging, the electromagnetic field generated during charging may cause signal saturation in some channels of the touch sensing layer 108. Saturation may affect different channels at different times, generating different modes of valid and invalid data on the parallel processing channels.

[0072] In this embodiment, initial ADC samples from the channel may be invalid due to interference during system startup. Conventional methods suspend processing or implement data buffering until valid samples are available. Circuit 200 solves these problems by maintaining operation through zero substitution and preserving coefficient information through accumulation, thereby enabling continuous processing without additional buffer storage.

[0073] In this embodiment, circuit 200 operates within a defined clock domain, and coefficient accumulator 206, accumulator 210, and output register 212 update their values ​​based on clock cycles. Feedback paths in both accumulators can implement value updates on each clock cycle while preserving previously accumulated values.

[0074] In one embodiment, circuit 200 includes a reset function to initialize coefficient accumulator 206, accumulator 210, and output register 212 to a known state. Initialization can be performed at system startup or during transitions between different processing modes.

[0075] In various embodiments, circuit 200 can be implemented in pairs to process in-phase (I) and quadrature (Q) signal components for frequency detection. A first instance of circuit 200 can process ADC samples using sine wave coefficients to generate the in-phase component, while a parallel instance can process the same ADC samples using cosine wave coefficients to generate the quadrature component. For example, when detecting a 200 kHz signal, the coefficient values ​​represent the sampling points of a 200 kHz sine and cosine wave.

[0076] Parallel processing of the I and Q components enables the detection of signal amplitude and phase information. When the input signal contains frequency components that match the coefficient frequency (e.g., 200 kHz), the accumulated product reaches its maximum value in both the I and Q paths. The relative amplitudes of the I and Q accumulator outputs indicate the phase relationship between the input signal and the reference coefficients.

[0077] In embodiments where the initial ADC sample is invalid, both the I and Q processing paths independently accumulate their respective coefficients. When the first valid ADC sample arrives, each path multiplies that sample by its accumulated coefficients (sine coefficients for the I path and cosine coefficients for the Q path). This maintains proper phase relationships despite the presence of invalid samples at the beginning of the sequence.

[0078] After processing the first valid sample, both the I and Q paths revert to normal operation, directly multiplying subsequent valid ADC samples by the individual sine and cosine coefficients, respectively. The parallel architecture maintains continuous processing on both paths while preserving the phase relationship required for accurate frequency detection, even when processing invalid samples through zero substitution and coefficient accumulation.

[0079] In various embodiments, coefficient values ​​are normalized within an 8-bit or 9-bit representation to optimize hardware implementation while maintaining sufficient signal resolution. These bit width choices are consistent with common digital design practices, where powers of 2 (such as 256 for 8-bit values) enable efficient hardware implementation. For example, using 8-bit coefficient values ​​can represent -256 to +255, providing sufficient dynamic range for sine and cosine coefficients while maintaining reasonable hardware complexity.

[0080] The coefficient normalization process takes into account hardware constraints and signal processing requirements. When implementing the sine and cosine coefficients, the maximum amplitude value is scaled to fit the chosen bit width while preserving the relative relationships between the coefficient values. This scaling ensures that the multiplication results remain within a manageable range while maintaining sufficient numerical precision for accurate frequency detection.

[0081] In embodiments where coefficients are accumulated during invalid sample periods, the accumulator width can be configured to accommodate the maximum possible sum without overflowing. For example, if three consecutive coefficients need to be accumulated, the accumulator width is the maximum possible sum of the three 8-bit or 9-bit values. This ensures that coefficient information is accurately preserved during the accumulation period while maintaining efficient hardware utilization.

[0082] Normalized coefficient values ​​can be stored in memory and retrieved systematically during processing. The normalization scheme enables efficient multiplication while providing sufficient resolution to distinguish signal features in a touch detection system. This approach strikes a balance between processing accuracy and hardware resource utilization, which is particularly advantageous when implementing multiple parallel channels, each requiring its own coefficient processing path.

[0083] In various embodiments, circuit 200 operates under the control of a state machine that manages the coefficient retrieval and processing sequence. The state machine can implement a counter-based method for retrieving coefficient values ​​from memory in a systematic order. For example, when processing ADC samples for frequency detection, the counter sequence fetches the appropriate sine or cosine value for each processing cycle via the coefficient address.

[0084] The state machine coordinates the timing relationships between coefficient retrieval, ADC sample processing, and accumulator updates. The counter advances on each clock cycle to fetch the next coefficient value for processing with the corresponding ADC sample. When an invalid sample is detected, the state machine maintains the coefficient retrieval sequence while directing the value to coefficient accumulator 206 instead of directly to multiplier 208.

[0085] In this embodiment, the state machine implements the complete sequence of coefficient retrieval and processing operations before resetting to process the next set of samples. The counter-based approach ensures deterministic timing of coefficient retrieval while maintaining synchronization with ADC sample processing across all channels.

[0086] The clock domain relationships in management circuitry 200 ensure proper setup and hold times between coefficient retrieval, multiplexer switching, and multiply-accumulate operations. A state machine generates control signals to coordinate these operations, with coefficient retrieval occurring sufficiently early in the clock cycle to meet the setup time requirements of the multiplexer and multiplier stages. This timing coordination can be particularly advantageous when transitioning between invalid and valid sample processing, where coefficient accumulation seamlessly switches to direct multiplication.

[0087] Figure 3 A block diagram of the selection generation circuit 300 of an embodiment is shown. The selection generation circuit 300 includes a flip-flop 302 and combinational logic 304, which may (or may not) be arranged as shown. The selection generation circuit 300 receives an ADC validity signal (ADC_VALID) and generates a first selection signal (SEL_1) for controlling the first multiplexer 202 of the control circuit 200.

[0088] In this embodiment, trigger 302 stores the validity status of previous ADC samples. It receives an ADC validity signal and outputs a previously valid signal (PREV_VALID) to indicate whether a previous ADC sample was valid. Trigger 302 updates its stored value every clock cycle to maintain the history of ADC sample validity.

[0089] In this embodiment, combinational logic 304 includes an inverter 306 and an AND gate 308. The inverter 306 receives a previously valid signal from the flip-flop 302 and generates an inverted previously valid signal. The AND gate 308 receives the inverted previously valid signal and the current ADC validity signal to generate a first selection signal (SEL_1) in response to the current ADC sample being valid while the previous sample is invalid.

[0090] In one embodiment, in response to the detection of a first valid ADC sample after an invalid sampling period, the selection generation circuit 300 generates a single-cycle pulse on a first selection signal. The pulse signal notifies the circuit 200 to select the path via the accumulated coefficients through the first multiplexer 202. After this first valid sample, the previously valid signal remains high, causing the output of the inverter 306 to go low, which forces the first selection signal to remain low through the AND gate 308 to select the direct coefficient path for subsequent valid samples.

[0091] The selection generation circuit 300 can operate synchronously with the system clock signal. The flip-flop 302 can sample the ADC validity signal on each rising edge of the clock to create a one-cycle delay between the input ADC validity signal and the previous validity signal. The combinational logic 304 can generate a first selection signal after a propagation delay through the inverter 306 and the AND gate 308, which can be configured to satisfy the setup time requirement of the first multiplexer 202 in circuit 200. When an ADC sample transitions from invalid to valid, the first selection signal asserts within the same clock cycle as the valid ADC sample, allowing the first multiplexer 202 to select the accumulated coefficients as the first valid sample arrives.

[0092] For example, when the ADC sample is initially invalid, the ADC validity signal remains low, causing the previously valid signal, flip-flop 302, to remain low. During this period, the output of inverter 306 remains high, but the first select signal remains low due to the low ADC validity signal to AND gate 308. When the first valid ADC sample arrives, the ADC validity signal transitions high, while the previously valid signal remains low for one or more clock cycles. This creates a single-cycle window where the input to AND gate 308 is high to generate a one-cycle pulse on the first select signal. In the next clock cycle, flip-flop 302 updates to store the valid state, causing the output of inverter 306 to go low and forcing the first select signal low via AND gate 308.

[0093] Figure 4A block diagram of an embodiment selection generation circuit 400 is shown. The selection generation circuit 400 includes a comparator 402 and an inverter 404, which may (or may not) be arranged as shown. The selection generation circuit 400 receives ADC data and generates a second selection signal (SEL_2) for controlling a second multiplexer 204 of the control circuit 200.

[0094] In various embodiments, comparator 402 receives ADC data samples (ADC_DATA) and a predefined threshold (TH) from ADC 214. The threshold can be programmable and set near the maximum ADC value, such as 254 for an 8-bit ADC implementation. Comparator 402 compares each ADC sample with the threshold and outputs an ADC validity signal (ADC_VALID) indicating whether the ADC sample is below the threshold.

[0095] Inverter 404 receives the ADC validity signal from comparator 402 and generates a second selection signal (SEL_2). When the ADC sample is valid (i.e., below the threshold), the ADC validity signal is high, and inverter 404 outputs a low value for the second selection signal, causing the second multiplexer 204 to select the ADC data path. Conversely, when the ADC sample is invalid (i.e., at or above the threshold), the ADC validity signal is low, and inverter 404 outputs a high value for the second selection signal, causing the second multiplexer 204 to select a zero-value input.

[0096] The selection generation circuit 400 can be configured to continuously monitor incoming ADC samples and update the second selection signal based on the comparison results. This enables immediate detection of signal saturation and rapid switching between ADC data and the zero-value path in circuit 200. The ADC validity signal from comparator 402 can also be provided to the selection generation circuit 300 to generate the first selection signal (SEL_1).

[0097] In this embodiment, the selection generation circuit 400 operates in combination to continuously monitor ADC data without clock synchronization. Comparator 402 can generate an ADC validity signal after receiving new ADC data or a propagation delay of a threshold. Inverter 404 can generate a second selection signal after an additional small propagation delay. These combined delays can be configured to meet the setup time requirements of the second multiplexer 204 in circuit 200 to ensure that the second selection signal stabilizes before the ADC data arrives at the multiplexer input.

[0098] For example, when an ADC sample transitions from valid to invalid by exceeding a threshold, the output of comparator 402 goes low after its propagation delay. Then, inverter 404 drives it high after the propagation delay of the second selection signal to select a zero-value input path before the invalid ADC sample propagates through circuit 200. Similarly, when an ADC sample returns to a valid level below the threshold, the output of comparator 402 goes high to cause the second selection signal to go low, and promptly selects an ADC data path to process the valid sample.

[0099] In an embodiment where the selection generation circuit 400 provides an ADC validity signal to the selection generation circuit 300, the propagation delay of the comparator 402 ensures that the validity signal arrives at the trigger 302 in a timely manner to meet its setup requirements. This timing relationship allows for proper synchronization between the generation of the first selection signal and the second selection signal, thereby allowing the circuit 200 to coordinate coefficient accumulation by replacing invalid ADC samples with zeros.

[0100] Figure 5 A flowchart of an embodiment method 500 for processing distorted samples from, for example, an ADC in a touch controller is shown. Note that all steps outlined in the flowchart of method 500 are not necessarily required and may be optional. Furthermore, similar considerations can be made regarding changes to the arrangement of steps, removal of one or more steps and path connections, and addition of steps and path links.

[0101] In step 502, an ADC sample is received from one of the multiple parallel channels of the touch sensing layer 108. The ADC sample represents a digital measurement of capacitive coupling at a specific location on the touch sensor grid. In embodiments with wireless charging interference, these ADC samples may experience a saturation effect.

[0102] In step 504, comparator 402 performs a threshold comparison operation on the received ADC samples. The threshold can be programmable and can be set near the maximum ADC range, such as 254 for an 8-bit ADC. This comparison can detect potentially saturated or distorted samples that may affect touch detection accuracy.

[0103] Step 506 represents the decision point based on the comparison result of step 504. When the value of the ADC sample is below the threshold, the ADC sample is considered valid, indicating that the signal level is normal. Conversely, when the sample value is equal to or exceeds the threshold, the sample is considered invalid, indicating that there may be signal saturation or interference.

[0104] In step 508, when an invalid sample is detected, the second selection signal provided to the selection input of the second multiplexer 204 is driven high by the inverter 404. This configures the second multiplexer 204 to select the zero-value input path, effectively eliminating the impact of invalid samples on subsequent calculations.

[0105] In step 510, coefficient accumulator 206 begins or continues its accumulation operation. Each new coefficient value is added to the previously accumulated sum via the feedback path of coefficient accumulator 206. This accumulation serves several purposes: it preserves coefficient information that would otherwise be lost during invalid sample periods, maintains the mathematical relationship between coefficients and data samples through the multiplication distribution law, and resumes signal processing after valid data is returned.

[0106] For example, in an IQ signal processing implementation, the accumulated coefficients can represent the sum of multiple sine or cosine wave coefficients, preserving phase relationship information even if the sample is invalid. The coefficient accumulator 206 continues this summation process for each clock cycle in which an invalid sample is detected, to effectively compress multiple coefficient operations into a single accumulated value.

[0107] In step 512, in response to a valid sample, the second selection signal is driven low to configure the second multiplexer 204 to pass ADC data for processing.

[0108] In step 514, the previously valid signal from trigger 302 is checked to determine if this is the first valid sample after the invalid data period.

[0109] In response to the first valid sample identified in step 514, in step 516, the first selection signal is set to a high level for one clock cycle. This momentarily configures the first multiplexer 202 to select the accumulated coefficient value, allowing the circuitry to resume processing that occurred during the invalid period.

[0110] In step 518, for all other valid samples, the first selection signal remains low, and the direct coefficient path is selected for normal operation.

[0111] In step 520, a multiplication-accumulation operation is performed in multiplier 208 using the selected coefficients and ADC values. For invalid samples, multiplication by zero produces a zero result, while the accumulated coefficients are preserved. For the first valid sample, the multiplication combines the accumulated coefficients with the valid ADC data. For subsequent valid samples, normal coefficient multiplication is performed.

[0112] In step 522, the result of the multiplication-accumulation operation is captured in output register 212. This step maintains a continuous data stream while managing the transition between valid and invalid sample periods. The stored result can then be used for subsequent touch detection processing.

[0113] Method 500 is executed sequentially for each channel, while steps 502 to 522 are performed independently and in parallel on multiple channels. This parallel processing architecture can efficiently handle different interference patterns at different touch sensor locations without requiring channel synchronization or data buffering.

[0114] Figure 6 Timing diagram 600 is shown, illustrating the normal multiply-accumulate operation when an ADC sample is valid for a single channel. The diagram shows five time intervals 601, 603, 605, 607, and 609, labeled T0 to T4, representing consecutive sampling intervals during normal operation.

[0115] During time period T0601, multiplier 602 combines the first coefficient (COEFF1) with its corresponding ADC sample ADC1. This product is provided to adder 604, which adds it to the current value (ACC1) in accumulator 606.

[0116] During time period T1603, the second coefficient (COEFF2) is multiplied by the second ADC sample (ADC2), and adder 604 combines the product with the previously accumulated value to generate a second accumulated value (ACC2) in accumulator 608.

[0117] The operation continues in time period T2605, where the third coefficient (COEFF3) and the third ADC sample (ADC3) are multiplied together, and their product is added to the accumulated value to produce the third accumulated value (ACC3) in accumulator 610.

[0118] In time period T3607, multiplier 602 processes the fourth coefficient (COEFF4) and the fourth ADC sample (ADC4), and adder 604 combines the product into the fourth accumulated value (ACC4) stored in accumulator 612.

[0119] In time period T4608, multiplier 602 processes the fifth coefficient (COEFF5) and the fifth ADC sample (ADC5), and adder 604 combines the product into the fifth accumulated value (ACC5) in accumulator 614.

[0120] Accumulators (606-614) can be used to implement digital filters and detect specific signal characteristics. For example, in IQ signal processing implementations, the accumulation of ADC samples with multiplied coefficients can detect signal frequency and phase information.

[0121] Each product of the coefficients and the ADC sample represents a term in a larger filtering operation. By accumulating these products over time, the circuit achieves filtering functions such as associating the input signal with a specific frequency component. In the case of sine and cosine coefficients, this accumulation produces in-phase (I) and quadrature (Q) signal components to indicate the presence and intensity of specific frequencies in the touch sensor signal.

[0122] Without accumulation, the circuit would only see individual product and fail to capture the relationships between consecutive samples. The accumulation operation effectively implements the summation part of the digital filtering equation, where multiple coefficient-weighted samples are combined to extract the desired signal characteristics. This enables the touch controller to distinguish valid touch or stylus signals from noise or interference.

[0123] For example, when processing a 200kHz signal, the product of the ADC sample and the accumulated 200kHz sine and cosine coefficients will reach a maximum value when this frequency component is present in the input signal. Therefore, the accumulation is used as a frequency detection mechanism, and the accumulated value indicates the correlation strength between the input signal and the coefficient sequence.

[0124] This timing diagram represents ideal operation in the absence of external interference or signal saturation, allowing each ADC sample to be processed directly using its corresponding coefficients. The continuous flow of valid data enables direct multiplication and accumulation operations without the need for special processing or coefficient accumulation.

[0125] Figure 7 Timing diagram 700 is shown, illustrating the multiplication-accumulation operation when the initial ADC sample is invalid. The diagram shows five time periods 701, 703, 705, 707, and 709, labeled T0 through T4, demonstrating how circuit 200 handles invalid data through coefficient accumulation and zero substitution.

[0126] During the first three periods (T0-T2), due to invalid ADC samples, multiplier 702 combines the coefficient values ​​(COEFF1-COEFF3) with zero values. Although these multiplications result in zero output, adder 704 and accumulators 706-710 maintain the running sum of the coefficient values ​​through their feedback paths.

[0127] At time interval T3707, the first valid ADC sample (ADC4) arrives. At this point, multiplier 702 combines the first valid ADC sample (ADC4) with the sum of the first three coefficients (COEFF_ACC4 = COEFF1 + COEFF2 + COEFF3). This multiplication effectively recovers the processing that occurred during the invalid time interval. This product is then accumulated in the fourth accumulated value (ACC4) 712.

[0128] At time T4709, the circuit returns to normal operation, and multiplier 702 directly processes the fifth coefficient (COEFF5) using the fifth ADC sample (ADC5) and accumulates the result in the fifth accumulated value (ACC5) 714. This demonstrates how the architecture can maintain continuous operation during invalid time periods while preserving signal processing accuracy through coefficient accumulation.

[0129] This timeline illustrates the advantages of the coefficient accumulation method—it enables continuous processing without requiring a data buffer to store invalid samples. Mathematical equivalence is preserved through the distributive law, where the sum of coefficients multiplied by a single valid sample produces the same result as adding the products of individual coefficient samples (i.e., ...). ADC 4× COEFF 1)+( ADC 4× COEFF 2)+( ADC 4× COEFF 3)+( ADC 4× COEFF 4)= ADC 4×( COEFF 1+ COEFF 2+ COEFF 3+ COEFF 4).

[0130] The first aspect relates to a method for continuously processing signals in a touch controller, the method comprising: receiving analog-to-digital converter (ADC) samples from a plurality of parallel channels; for each channel, comparing each ADC sample with a saturation threshold to determine validity; in response to detecting an initial ADC sample exceeding the saturation threshold for each channel: selecting a zero value for multiplication to maintain continuous processing without buffering, and accumulating coefficient values ​​in a coefficient accumulator; in response to detecting a first valid ADC sample below the saturation threshold for each channel: selecting a first valid ADC sample for multiplication, and selecting an accumulated coefficient value from the coefficient accumulator to resume processing from the initial invalid sample; and performing multiplication using the first valid ADC sample and the accumulated coefficient value to maintain equivalence through a distribution rate.

[0131] In a first implementation of the method, according to the first aspect itself, receiving ADC samples includes receiving samples from multiple parallel channels, each channel providing a continuous ADC sample representing capacitance measurements from different locations on the touch sensor matrix.

[0132] In a second implementation of the method, depending on the first aspect itself or any prior implementation of the first aspect, the method further includes maintaining continuous operation without buffering, which includes performing zero-value multiplication during invalid sample periods while accumulating coefficients in parallel; and applying the accumulated coefficients when valid data is available.

[0133] In a third implementation of the method, depending on the first aspect itself or any prior implementation of the first aspect, the method further includes, after performing multiplication using the first valid ADC sample and the accumulated coefficient value: selecting subsequent ADC samples for multiplication; and selecting individual system values ​​instead of the accumulated coefficient value.

[0134] In a fourth implementation of the method, depending on the first aspect itself or any prior implementation of the first aspect, the method further includes processing in-phase components using sine wave coefficients in a first processing path; and processing quadrature components using cosine wave coefficients in a second processing path.

[0135] In a fifth implementation of the method, depending on the first aspect itself or any prior implementation of the first aspect, the method further includes operating within a defined clock domain; updating coefficient values ​​and accumulator values ​​based on clock cycles; and maintaining the timing relationship between coefficient processing and ADC sample processing.

[0136] In a sixth implementation of the method, comparing each ADC sample, according to the first aspect itself or any previous implementation of the first aspect, includes: comparing the ADC sample with a programmable threshold near the maximum ADC value; and generating an ADC validity signal based on the comparison.

[0137] The second aspect relates to a touch sensing system comprising: a touch sensor configured to sense input to a touchscreen; and a touch controller coupled to receive sensed input from the touch sensor, the touch controller including a first processing circuit and a second processing circuit, each processing circuit including: a coefficient input node configured to receive coefficient values; a coefficient accumulator; a first multiplexer having: a first input coupled to the coefficient input node, a second input coupled to the output of the coefficient accumulator, and a selection input coupled to receive an ADC validity signal; an ADC input node coupled to receive the sensed input; a second multiplexer having: a first input coupled to the ADC input node, a second input coupled to a zero-value source, and a selection input coupled to receive an ADC validity signal; and a multiplication circuit having: a first input coupled to the output of the first multiplexer and a second input coupled to the output of the second multiplexer, wherein the first processing circuit provides coefficient values ​​for determining the amplitude of the sensed input, and the second processing circuit provides coefficient values ​​for determining the phase of the sensed input.

[0138] In the first implementation of the touch sensing system, according to the second aspect itself, the touch controller processes multiple parallel channels simultaneously.

[0139] In a second implementation of the touch sensing system, depending on the second aspect itself or any previous implementation of the second aspect, the coefficient accumulator includes a feedback path capable of continuously adding coefficient values ​​during periods of invalid data.

[0140] In a third implementation of the touch sensing system, depending on the second aspect itself or any previous implementation of the second aspect, after processing the first valid ADC sample, the selection input changes from selecting the accumulated coefficient value to selecting the system value.

[0141] In a fourth implementation of the touch sensing system, depending on the second aspect itself or any previous implementation of the second aspect, the touch sensing system further includes a comparator circuit configured to compare ADC samples with a programmable threshold; and an inverter configured to generate an ADC validity signal based on the comparison.

[0142] In a fifth implementation of the touch sensing system, according to the second aspect itself or any previous implementation of the second aspect, the first processing circuit uses sine wave coefficients to process the in-phase component, and the second processing circuit uses cosine wave coefficients to process the quadrature component, wherein the first and second processing circuits accumulate their respective coefficients during invalid data periods, wherein the first and second processing circuits multiply their respective accumulated coefficients with the first valid ADC sample, and wherein the first and second processing circuits transform into using individual coefficients for subsequent valid samples.

[0143] In a second implementation of the touch sensing system, depending on the second aspect itself or any prior implementation of the second aspect, the touch sensing system further includes a state machine configured to control the coefficient retrieval and processing sequences on the first and second processing circuits.

[0144] The third aspect relates to a circuit for processing ADC samples, the circuit comprising: a coefficient input node configured to receive coefficient values; a coefficient accumulator; a first multiplexer having: a first input coupled to the coefficient input node, a second input coupled to the output of the coefficient accumulator, and a selection input coupled to receive an ADC validity signal; an ADC input node providing ADC samples; a second multiplexer having: a first input coupled to the ADC input node, a second input coupled to a zero-value source, and a selection input coupled to receive an ADC validity signal; and a multiplication circuit having: a first input coupled to the output of the first multiplexer, and a second input coupled to the output of the second multiplexer, wherein the selection input controls the first and second multiplexers to: select a zero value and a coefficient value when the ADC validity signal indicates an invalid sample, and select a first valid ADC sample and an accumulated coefficient value when the ADC validity signal indicates a first valid sample.

[0145] In a first implementation of the circuit, according to the third aspect itself, the coefficient accumulator includes a feedback path capable of continuously adding coefficient values ​​during invalid sample periods.

[0146] In a second implementation of the circuit, depending on the third aspect itself or any previous implementation of the third aspect, the multiplication circuit includes a multiplier coupled to an accumulator; the accumulator includes a feedback path for summing the product from the multiplier over time; and the accumulator is configured to hold the sum of multiple coefficient values ​​during invalid sample periods.

[0147] In a third implementation of the circuit, multiple instances of the circuit operate in parallel to process multiple channels simultaneously, depending on the third aspect itself or any previous implementation of the third aspect.

[0148] In the fourth implementation of the circuit, according to the third aspect itself or any previous implementation of the third aspect, the first instance of the circuit uses sine wave coefficients to handle the in-phase components; and the second instance of the circuit uses cosine wave coefficients to handle the quadrature components.

[0149] In a fifth implementation of the circuit, depending on the third aspect itself or any previous implementation of the third aspect, the circuit also includes a state machine configured to: implement a counter-based method for retrieving coefficient values ​​from memory, and coordinate the timing relationship between coefficient retrieval, ADC sample processing, and accumulator updates.

[0150] Although the description has been described in detail, it should be understood that various changes, substitutions, and variations can be made without departing from the spirit and scope of this disclosure as defined by the appended claims. In the various figures, the same elements are indicated by the same reference numerals. Furthermore, the scope of this disclosure is not intended to be limited to the specific embodiments described herein, as it will be readily understood from this disclosure by those skilled in the art that existing or later-developed processes, machines, manufactures, material compositions, components, methods, or steps can perform substantially the same functions or achieve substantially the same results as the corresponding embodiments described herein. Therefore, the appended claims are intended to include such processes, machines, manufactures, material compositions, components, methods, or steps within their scope.

[0151] Therefore, the specification and drawings should be regarded as a simple description of the disclosure as defined in the appended claims, and should cover any and all modifications, variations, combinations or equivalents falling within the scope of this disclosure.

Claims

1. A method for continuously processing signals in a touch controller, the method comprising: Receive analog-to-digital converter (ADC) samples from multiple parallel channels; For each channel, each ADC sample is compared with a saturation threshold to determine effectiveness; In response to the detection of an initial ADC sample exceeding the saturation threshold for each channel: Choosing zero values ​​for multiplication maintains continuous processing without buffering, and Accumulate the coefficient values ​​in the coefficient accumulator; In response to the detection of the first valid ADC sample below the saturation threshold for each channel: Select the first valid ADC sample for multiplication, and Select accumulated coefficient values ​​from the coefficient accumulator to recover from the initial invalid samples; as well as Multiplication is performed using the first valid ADC sample and the accumulated coefficient value to maintain equivalence through the allocation rate.

2. The method of claim 1, wherein receiving ADC samples comprises receiving samples from a plurality of parallel channels, each channel providing consecutive ADC samples representing capacitance measurements from different locations on the touch sensor matrix.

3. The method of claim 1, further comprising maintaining continuous operation without buffering, wherein maintaining continuous operation without buffering includes: Zero-value multiplication is performed during invalid sample periods, while coefficients are accumulated in parallel. as well as When valid data is available, the accumulated coefficient is applied.

4. The method of claim 1, further comprising performing a multiplication using the first valid ADC sample and the accumulated coefficient value: Select subsequent ADC samples for multiplication; and Choose a system value instead of an accumulated coefficient value.

5. The method according to claim 1, further comprising: Sine wave coefficients are used to process in-phase components in the first processing path; as well as The orthogonal components are processed using cosine coefficients in the second processing path.

6. The method according to claim 5, further comprising: Operate within the defined clock domain; The coefficient values ​​and accumulator values ​​are updated based on the clock cycle; as well as Maintain the timing relationship between coefficient processing and ADC sample processing.

7. The method of claim 1, wherein comparing each ADC sample comprises: The ADC sample is compared with a programmable threshold near the maximum ADC value; as well as Based on the comparison, an ADC validity signal is generated.

8. A touch sensing system, comprising: A touch sensor is configured to sense input to the touchscreen; as well as A touch controller, coupled to receive sensing input from the touch sensor, includes a first processing circuit and a second processing circuit, each processing circuit including: The coefficient input node is configured to receive coefficient values; Coefficient accumulator; The first multiplexer has the following features: The first input is coupled to the coefficient input node. The second input is coupled to the output of the coefficient accumulator, and Select the input, which is coupled to receive the ADC validity signal; The ADC input node is coupled to receive the sensed input. The second multiplexer has the following features: The first input is coupled to the ADC input node. The second input, coupled to the zero-value source, and Select an input, coupled to receive the ADC validity signal; and A multiplication circuit has the following characteristics: The first input, coupled to the output of the first multiplexer, and The second input is coupled to the output of the second multiplexer. The first processing circuit provides coefficient values ​​for determining the amplitude of the sensing input, and the second processing circuit provides coefficient values ​​for determining the phase of the sensing input.

9. The touch sensing system of claim 8, wherein the touch controller processes multiple parallel channels simultaneously.

10. The touch sensing system of claim 8, wherein the coefficient accumulator includes a feedback path capable of continuously adding coefficient values ​​during invalid data periods.

11. The touch sensing system of claim 8, wherein after processing the first valid ADC sample, the selection input changes from selecting the accumulated coefficient value to selecting an individual system value.

12. The touch sensing system according to claim 8, further comprising: The comparator circuit is configured to compare ADC samples with a programmable threshold. as well as An inverter is configured to generate the ADC validity signal based on the comparison.

13. The touch sensing system according to claim 8, The first processing circuit uses sine wave coefficients to process the in-phase components, and the second processing circuit uses cosine wave coefficients to process the quadrature components. The first processing circuit and the second processing circuit accumulate their respective coefficients during the invalid data period. The first processing circuit and the second processing circuit multiply their respective accumulated coefficients by the first effective ADC sample, and The first and second processing circuits are transformed into using individual coefficients for subsequent valid samples.

14. The touch sensing system of claim 8 further includes a state machine configured to control the coefficient retrieval and processing sequences on the first processing circuit and the second processing circuit.

15. A circuit for processing ADC samples, the circuit comprising: The coefficient input node is configured to receive coefficient values; Coefficient accumulator; The first multiplexer has the following features: The first input is coupled to the coefficient input node. The second input is coupled to the output of the coefficient accumulator, and Select the input, which is coupled to receive the ADC validity signal; ADC input node, providing ADC samples; The second multiplexer has the following features: The first input is coupled to the ADC input node. The second input, coupled to the zero-value source, and Select an input, which is coupled to receive the ADC validity signal; as well as A multiplication circuit has the following characteristics: The first input, coupled to the output of the first multiplexer, and The second input is coupled to the output of the second multiplexer. The selection input controls the first multiplexer and the second multiplexer to: When the ADC validity signal indicates an invalid sample, select the zero value and coefficient value, and When the ADC validity signal indicates a first valid sample, the first valid ADC sample and the accumulated coefficient value are selected.

16. The circuit of claim 15, wherein the coefficient accumulator includes a feedback path capable of continuously adding coefficient values ​​during invalid sample periods.

17. The circuit according to claim 15, wherein: The multiplication circuit includes a multiplier coupled to the accumulator; The accumulator includes a feedback path for summing the products from the multiplier over time; and The accumulator is configured to hold the sum of multiple coefficient values ​​during invalid sample periods.

18. The circuit of claim 15, wherein multiple instances of the circuit operate in parallel to process multiple channels simultaneously.

19. The circuit according to claim 15, wherein: The first instance of the circuit uses sinusoidal coefficients to handle the in-phase components; and The second example of the circuit uses cosine wave coefficients to handle quadrature components.

20. The circuit of claim 15, further comprising a state machine configured to: Implement a counter-based method for retrieving coefficient values ​​from memory, and Timing relationship between coordination coefficient retrieval, ADC sample processing, and accumulator update.

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