DVS camera integrated use method based on FPGA

Abstract

The invention relates to the technical field of crossing of embedded systems and machine vision, in particular to an FPGA-based DVS camera integrated use method, which comprises the following steps: constructing an embedded Linux system at a PS end of an FPGA, and configuring a USB driving environment by starting libusb1 and libusb-complex libraries and compiling a system mirror image; performing cross compiling on an equipment interface library and a visual processing library of the DVS camera aiming at the ARM architecture; developing an application program based on an ARM architecture, pulling event data through the equipment interface library and deploying the event data to the FPGA; and monitoring logs through a serial port tool and verifying data integrity and real-time performance through a visual tool. The problems that a traditional DVS camera only supports an x86 architecture platform and is poor in compatibility with an FPGA embedded system are solved, a set of complete FPGA-DVS integration scheme is constructed through driving adaptation, architecture compatible library compiling and application layer interface development, the deployment threshold of the DVS in an embedded scene is lowered, and the real-time performance and the integration degree of the system are improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of embedded systems and machine vision, and particularly relates to a DVS camera integration use method based on FPGA. BACKGROUND

[0002] As a new type of visual sensor, the DVS camera is different from the traditional frame camera, and only outputs event data (containing coordinate, polarity, timestamp, etc.) when the brightness of the pixel changes, has high time resolution, low data redundancy, low power consumption and other advantages, and is widely used in high-speed motion detection, real-time tracking and other scenes.

[0003] At present, the mainstream use mode of the DVS camera is based on the x86 architecture of the Windows or Linux system, and the data acquisition and processing are realized through the official SDK and OpenCV and other dependent libraries. However, in the embedded scene, the FPGA becomes the core carrier of the edge computing and embedded vision system because of the strong programmability, high real-time performance and high degree of customization. However, due to the difference in instruction set between the ARM architecture of the PS end of the FPGA and the x86 architecture, the official driver, interface library and dependent library of the DVS camera cannot be directly compatible, which greatly limits the application of the DVS on the FPGA platform.

[0004] In the prior art, there is a lack of systematic solution for the integration of the DVS and the FPGA, and the following problems exist: first, the driver is not compatible, the USB driver of the DVS camera cannot be directly loaded in the FPGA embedded Linux system; second, the library architecture is not matched, the official interface library and the vision processing library are for the x86 architecture, and cannot run on the PS end of the ARM architecture; third, the application program is difficult to adapt, the DVS data acquisition program developed based on the x86 architecture cannot be directly deployed on the FPGA.

[0005] Therefore, there is an urgent need for a method that can solve the above compatibility problems and realize the stable operation of the DVS camera on the FPGA. SUMMARY

[0006] The present application aims to overcome the shortcomings of the prior art, and provides a DVS camera integration use method based on FPGA, which solves the technical problem that the traditional DVS camera only supports the x86 architecture platform and has poor compatibility with the FPGA embedded system; through driver adaptation, cross-compilation and application development, the stable operation of the DVS on the FPGA is realized.

[0007] The above-mentioned purpose is achieved by the following technical solutions: A DVS camera integration use method based on FPGA, comprising the following steps: Step (1): Constructing an embedded Linux system on the PS (Processing System) end of the FPGA, and configuring the USB driver environment required by the DVS camera; Step (2): Cross-compiling the device interface library of the DVS camera for the ARM architecture of the FPGA, so that it adapts to the embedded Linux system; Step (3): Cross-compiling the vision processing library relied on by the DVS camera to ensure the compatibility of the vision processing library with the device interface library; Step (4): Developing an application program based on the ARM architecture, which pulls event data from the DVS camera through the device interface library and runs on the PS end of the FPGA; Step (5): Verifying the running stability of the DVS camera on the FPGA platform, including the integrity and real-time performance of the event data.

[0008] Preferably, the USB driver environment required by the DVS camera in step (1) specifically includes: enabling the libusb1 and libusb-compat libraries through the root file system configuration tool of the FPGA embedded Linux system, and recompiling the system image to load the USB driver, so that the DVS camera can be correctly recognized after being connected to the PS end of the FPGA through the USB interface.

[0009] Preferably, the device interface library of the DVS camera in step (2) specifically includes: obtaining the device interface library source code provided by the official DVS camera, modifying the compilation script of the source code, specifying the compiler as the cross-compiler aarch64-linux-gnu-gcc / g++ matching the ARM architecture of the FPGA, and adjusting the library dependency path to adapt to the embedded environment of the FPGA, and compiling to generate the device interface library file adapted to the ARM architecture.

[0010] Preferably, the vision processing library in step (3) is the OpenCV library, and the version of the OpenCV library is 3.3.0; the process of cross-compiling the vision processing library includes: downloading the OpenCV 3.3.0 source code, entering the tool chain configuration file directory of the source code (such as platform / linux), modifying the tool chain configuration file of the corresponding architecture (such as aarch64-gnu.toolchain.cmake), specifying the cross-compiler path (including C compiler and C++ compiler) matching the ARM architecture of the FPGA in the file, configuring the compilation parameters and library file installation path, and at the same time, closing the hardware acceleration module (such as CUDA) incompatible with the FPGA platform, then executing the compilation and installation instructions, and generating the OpenCV library adapted to the ARM architecture.

[0011] Preferably, the application program in step (4) pulls event data through API functions provided by the DVS camera device interface library, the event data including pixel coordinates, polarity and timestamp information; the application program also implements the initialization of the DVS camera, the configuration of the working mode (such as the event intensity mode) and the disabling operation of the irrelevant functional modules.

[0012] Preferably, the process of verifying the stability of the DVS camera in step (5) specifically includes: Step (51): monitoring the event data log output by the application program through the PC serial port tool to confirm that the event data format is correct and there is no packet loss, so as to verify the data integrity; Step (52): real-time display of the transmission state and the number of events of the event data through a visual tool (such as a Qt interface) to verify the data real-time performance; If the verification results of steps (51) and (52) both meet the requirements, it is determined that the DVS camera is stably running on the FPGA platform.

[0013] Preferably, the process of constructing the embedded Linux system in step (1) is implemented based on the Petalinux engineering environment, specifically including: starting the Petalinux project, executing the configuration instruction to enter the root file system configuration interface, locating to the file system software package path "filesystem packages￫libs" in the interface, selecting and enabling the library files related to the USB interface communication (including libusb1, libusb-compat and all sub-options thereof, the sub-options covering the development library and the runtime library), saving the configuration and executing the system construction instruction, recompiling the system image, and generating the system startup file BOOT.BIN; writing the BOOT.BIN into a removable storage medium (such as an SD card), and inserting the storage medium into the startup interface of the FPGA to complete the construction of the embedded Linux system.

[0014] Preferably, the model of the FPGA is Xilinx XCZU3EG, and the PS end of the FPGA adopts the ARM Cortex-A53 architecture; the model of the DVS camera is CeleX-V, and the DVS camera is connected with the USB port of the FPGA board through the USB 3.0 interface.

[0015] Preferably, the deployment process of the application program in step (4) comprises: compiling the application program source code using a cross-compiler matching the FPGA ARM architecture to generate an executable file; placing the executable file into a FAT partition according to the file system structure of the FPGA, placing the device interface library file generated in step (2) and the visual processing library file generated in step (3) into a Lib folder of an EXT4 partition, and completing the deployment of the application program and the dependent library.

[0016] Preferably, after configuring the USB driver environment in step (1), a USB driver verification step is further included: after the system is powered on and started, a drive state detection instruction is executed to confirm that the libusb related driver modules have been successfully loaded; then a USB device query instruction is executed, and if the device identification information matching the CeleX-V camera is detected in the query result, it is determined that the USB driver and the dependent library have been correctly installed and are available.

[0017] The FPGA-based DVS camera integration use method provided by the application builds a complete FPGA-DVS integration scheme through driver adaptation, library compilation compatible with the architecture, and application layer interface development, reduces the deployment threshold of DVS in the embedded scene, and improves the real-time performance and integration degree of the system. Specific beneficial effects include: 1. Strong compatibility: through driver adaptation (enabling the libusb1 and libusb-compat libraries and compiling the system image) and cross-compilation (adapting the ARM architecture cross-compiler), the compatibility problem of the DVS camera on the FPGA ARM architecture is solved, so that the DVS camera originally only supporting the x86 platform can be directly used on the FPGA without relying on an additional x86 host.

[0018] 2. High integration degree: the DVS camera and the FPGA platform are deeply integrated without an additional x86 host as an intermediate node, which reduces the hardware complexity and power consumption of the system and is suitable for resource-constrained scenes such as edge computing.

[0019] 3. Good real-time performance: through optimization of library dependencies (closing incompatible hardware acceleration modules) and application program interfaces (directly pulling data through APIs), the intermediate links of data transmission are reduced, ensuring real-time acquisition and processing of DVS event data on the FPGA, and meeting the requirements of high real-time scenes such as high-speed motion detection.

[0020] 4. Strong scalability: the method can be extended to other models of DVS cameras and FPGA platforms, and only needs to adjust the driver configuration and compilation parameters for specific devices, which has strong universality. BRIEF DESCRIPTION OF DRAWINGS

[0021] Figure 1An embedded architecture diagram of the FPGA-based DVS camera integrated use method according to the application; Figure 2 A use flowchart of the FPGA-based DVS camera integrated use method according to the application; Figure 3 An embedded system configuration method flowchart in the FPGA-based DVS camera integrated use method according to the application. DETAILED DESCRIPTION

[0022] The application will be further described in detail below according to the drawings and embodiments. The described embodiments are only a part of the embodiments of the application, rather than all the embodiments. Based on the embodiments in the application, all other embodiments obtained by those skilled in the art without creative labor fall within the protection scope of the application.

[0023] The present application provides a FPGA-based DVS camera integrated use method, which specifically comprises the following steps: Step (1) constructing an embedded Linux system at the PS end of the FPGA and configuring a USB driver environment As shown in Figure 1 and 3 , an embedded Linux system is constructed at the PS end of the FPGA, and the system construction is realized based on a Petalinux project environment, and the specific operation is as follows: starting the Petalinux project, executing a configuration instruction to enter a root file system configuration interface, locating to a file system software package path "filesystem packages￫libs" in the interface, selecting and enabling library files related to USB interface communication, including "libusb1", "libusb-compat" and all sub-options thereof (the sub-options cover two types of development library and runtime library). After saving the configuration, executing a system construction instruction to recompile the system image, and generating a system startup file BOOT.BIN containing the library file support.

[0024] The system startup file BOOT.BIN is written into a removable storage medium (such as an SD card), and is inserted into the startup interface of the FPGA. After the system is powered on and started, a driver state detection instruction is executed to confirm that the libusb related driver modules have been successfully loaded; then, the DVS camera is connected to the USB port of the FPGA board through the USB interface (such as the USB 3.0 interface), a USB device query instruction is executed, and if the device identification information matched with the DVS camera is detected in the query result, it indicates that the USB driver and its dependent library have been correctly installed and are in a usable state, and the USB driver environment configuration required by the DVS camera is completed.

[0025] Step (2) Cross-compile the DVS camera device interface library adapted to ARM architecture As shown in Figure 2 , obtain the device interface library source code provided by the DVS camera (such as the CeleX-V camera) officially, which is adapted to the x86 architecture compiler by default. The compilation configuration file (such as Makefile) needs to be adjusted: replace the compilation tool chain parameters of the x86 architecture compiler (gcc / g++) with the cross-compiler aarch64-linux-gnu-gcc / g++ compatible with the ARM architecture of the FPGA, and synchronously adjust the dependent path of the library file (including the storage location of the link library and the reference path of the header file) to adapt to the embedded system environment of the FPGA.

[0026] Execute the compilation instruction to compile the source code and generate the device interface library file (such as libCelex.so); use a file attribute detection tool to verify the architecture attribute of the interface library file. If the detection result shows that it is aarch64 architecture, it means that the interface library file has been adapted to the PS end ARM architecture of the FPGA.

[0027] This step corresponds to Figure 2 the "DVS device interface library cross-compilation" link in Figure 1 , the interface library is the core component of the PS end software layer, and provides interface support for the interaction between the application program and the DVS camera.

[0028] Step (3) Cross-compile the visual processing library adapted to ARM architecture As shown in Figure 2 , select a visual processing library compatible with the DVS device interface library (in this embodiment, OpenCV library version 3.3.0 is selected), download its source code, and enter the tool chain configuration file directory (such as platform / linux) of the source code. Modify the tool chain configuration file (such as aarch64-gnu.toolchain.cmake) corresponding to the architecture: specify the cross-compiler path matching the ARM architecture of the FPGA in the file, including the C compiler and the C++ compiler, configure the compilation parameters, specify the installation path of the library file, and at the same time, close the hardware acceleration module (such as the CUDA module) incompatible with the FPGA hardware platform.

[0029] Create a compilation directory and an installation directory under the source code directory, enter the compilation directory to execute the configuration instruction, generate a compilation script, and then execute a multi-threaded compilation instruction and an installation instruction to install the generated library file, header file and auxiliary file to the preset installation directory; the bin, lib, include folders and the like generated in the installation directory contain the visual processing library adapted to the ARM architecture and related resources.

[0030] This step corresponds to Figure 2 In the "cross-compilation of visual processing libraries" step, the generated visual processing library serves as... Figure 1 The supporting components of the mid-PS software layer provide functional support for the basic processing of event data.

[0031] Step (4) Develop and deploy ARM architecture-based applications like Figure 2 As shown, based on the DVS device interface library generated in step (2) and the vision processing library generated in step (3), an application that can run on the FPGA PS is developed. The application implements the core functions through the API functions provided by the device interface library, specifically including: DVS camera initialization (specifying the interface type), camera working mode configuration (such as event intensity mode), disabling irrelevant function modules, camera parameter settings, and pulling event data from the DVS camera through the data pull interface (the event data includes pixel coordinates, polarity and timestamp information).

[0032] The application source code is compiled using a cross-compiler that matches the FPGA ARM architecture to generate an executable file. The executable file is placed in the FAT partition according to the FPGA file system structure. The device interface library file generated in step (2) and the vision processing library file generated in step (3) are placed in the Lib folder of the EXT4 partition to complete the deployment of the application and dependent libraries.

[0033] This step corresponds to Figure 2 In the "Application Development and Deployment" stage, the developed application serves as... Figure 1 The top-level component of the mid-PS software layer enables the control and data acquisition of the DVS camera.

[0034] Step (5) Verify the operational stability of the DVS camera on the FPGA platform. like Figure 2 As shown, a removable storage medium containing the application and dependent libraries is inserted into the FPGA's storage interface. The FPGA system is powered on and started. The PC serial port tool is used to log in to the operating system environment on the PS side and run the application. After the application starts, it automatically completes the initialization and parameter configuration of the DVS camera and begins to pull event data from the camera.

[0035] The verification process consists of two parts: first, monitoring the event data logs output by the application using a PC serial port tool to confirm the correct data format and absence of packet loss, thus verifying the integrity of the event data; second, displaying the transmission status and number of events in real time using a visualization tool (such as a Qt interface) to verify the data's real-time performance. If the log output is normal, the data format is complete, and the real-time performance meets the requirements, it indicates that the DVS camera is operating stably on the FPGA platform.

[0036] This step corresponds to Figure 2 The “Operation and Verification” section clarifies the specific verification methods and judgment criteria.

[0037] As a specific embodiment of this solution, this embodiment takes a Xilinx XCZU3EG FPGA (with an ARM Cortex-A53 architecture on the PS side) and a CeleX-V DVS camera as examples to explain in detail the implementation process of the present invention.

[0038] In this embodiment, the embedded system configuration is first completed in the Petalinux project environment. For example... Figure 3 As shown in the diagram, this illustrates the entire process from starting the Petalinux project to generating the system boot file BOOT.BIN. The specific configuration steps are as follows: To customize a Linux system using Petalinux, execute the configuration command to enter the root file system configuration interface. Navigate to the file system package path "filesystem packages → libs" and select and enable the libraries related to USB interface communication, including "libusb1", "libusb-compat", and all their sub-options. These sub-options cover both development and runtime libraries. After completing the configuration, save the settings and execute the system build command to recompile the system image, generating the system boot file BOOT.BIN, which contains the libraries supported by the specified libraries.

[0039] The system startup file is written to a removable storage medium (e.g., an SD card) and inserted into the FPGA's boot interface. After the system powers on, the libusb-related driver modules are successfully loaded using a driver status detection command. The execution location of this detection step matches the expected result. Figure 3 The corresponding annotations are also present (such as the driver detection command input node and the "driver loaded successfully" feedback indicator). Subsequently, the CeleX-V camera is connected to the FPGA board's USB port via a USB 3.0 interface, and a USB device query command is executed to identify the system's USB bus devices. If a device identifier matching the CeleX-V camera is detected in the query results, it indicates that the USB driver and its dependent libraries have been correctly installed and are available, thus enabling the FPGA system to support this type of USB camera. This process corresponds to... Figure 2 In the "Embedded Linux System Configuration and Driver Installation" section, the hardware connection relationships are as follows: Figure 1 As shown: The DVS camera establishes a physical connection with the PS side of the FPGA via a USB interface, and the embedded Linux system runs on the PS side and provides driver support.

[0040] The official device interface library source code for the CeleX-5 series DVS cameras is adapted to the x86 architecture compiler by default. The compilation configuration file (such as Makefile) needs to be adjusted: replace the compiler toolchain parameters from the x86 architecture compiler (gcc / g++) to a cross-compiler compatible with the ARM architecture of FPGA (aarch64-linux-gnu-gcc / g++), and adjust the dependency paths of the library files (including the storage location of the linked libraries and the reference path of the header files) to adapt to the embedded system environment of FPGA.

[0041] The source code is compiled using compilation instructions to generate a device interface library file (e.g., libCelex.so). The interface library file's architecture attributes are verified using a file attribute detection tool. If the detection result shows it to be an aarch64 architecture, it indicates that the interface library file is compatible with the ARM architecture on the FPGA's PS side. This process corresponds to... Figure 2 In the "Cross-compilation of DVS Device Interface Library" section, the interface library serves as... Figure 1 The core component of the PS-side software layer provides interface support for the interaction between the application and the DVS camera.

[0042] Select a vision processing library compatible with the DVS device interface library, download its source code, and then enter the toolchain configuration file directory of the source code (e.g., platform / linux). Modify the toolchain configuration file aarch64-gnu.toolchain.cmake for the corresponding architecture: specify the path of the cross-compiler that matches the FPGA's ARM architecture, including the C compiler and C++ compiler, and configure the compilation parameters. Specify the installation path of the library files, and disable hardware acceleration modules (such as the CUDA module) that are incompatible with the FPGA hardware platform.

[0043] Create a compilation directory and an installation directory in the source code directory. Enter the compilation directory and execute the configuration instructions to generate the compilation script. Then execute the multi-threaded compilation instructions and installation instructions to install the generated library files, header files, and auxiliary files to the preset installation directory. The bin, lib, include, and other folders generated in the installation directory contain the visual processing library and related resources adapted for the ARM architecture. This process corresponds to... Figure 2 In the "cross-compilation of visual processing libraries" step, the generated visual processing library serves as... Figure 1 The supporting components of the mid-PS software layer provide functional support for the basic processing of event data.

[0044] The application uses the DVS device interface library and vision processing library generated by the aforementioned cross-compilation method to implement core functions through the APIs provided by the device interface library. These functions include: Initialize the DVS camera and specify the interface type. Configure camera working mode Disable irrelevant functional modules Set camera parameters Retrieve event data from the DVS camera via the data retrieval interface. The source code is compiled using a cross-compiler compatible with the FPGA architecture to generate an executable file. The executable file and all dependent library files (including the DVS device interface library and vision processing library) are then copied to the FPGA's storage medium according to a predefined file system structure. The library files are stored in the Lib folder of the EXT4 partition, and the executable file is stored in the FAT partition. This process corresponds to... Figure 2 In the "Application Development and Deployment" stage, the developed application serves as... Figure 1 The top-level component of the mid-PS software layer enables the control and data acquisition of the DVS camera.

[0045] Insert the storage medium into the FPGA's storage interface, power on the FPGA system, and log in to the operating system environment on the PS side via a serial port tool to run the application. After the application starts, it will automatically complete the initialization and parameter configuration of the DVS camera and begin pulling event data from the camera. Verify the camera initialization status and the continuity of event data output by checking the system log output information; confirm the integrity of the data by checking the format of the event data.

[0046] Simultaneously, the transmission status and number of events are displayed in real time using simple visualization components such as a Qt interface to verify the real-time performance of data transmission. If the log output is normal, the data format is complete, and the real-time performance meets the requirements, it indicates that the DVS camera is operating stably on the FPGA platform. This process corresponds to... Figure 2 The "Operation and Verification" stage.

[0047] The above description is merely illustrative of the embodiments of the present invention and is not intended to limit the present invention. For those skilled in the art, any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for integrating and using a DVS camera based on FPGA, characterized in that, Includes the following steps: Step (1): Build an embedded Linux system on the PS side of the FPGA and configure the USB driver environment required by the DVS camera; Step (2): For the ARM architecture of the FPGA, cross-compile the device interface library of the DVS camera to adapt it to the embedded Linux system; Step (3): Cross-compile the vision processing library that the DVS camera depends on to ensure the compatibility of the vision processing library with the device interface library; Step (4): Develop an application based on the ARM architecture. The application pulls event data from the DVS camera through the device interface library and runs on the PS side of the FPGA. Step (5): Verify the stability of the DVS camera on the FPGA platform, including the integrity and real-time performance of event data.

2. The method for integrating and using a DVS camera based on FPGA according to claim 1, characterized in that, The configuration of the USB driver environment required for the DVS camera in step (1) specifically includes: enabling the libusb1 and libusb-compat libraries through the root file system configuration tool of the FPGA embedded Linux system, and recompiling the system image to load the USB driver, so as to ensure that the DVS camera can be correctly recognized after being connected to the PS end of the FPGA through the USB interface.

3. The method for integrating and using a DVS camera based on FPGA according to claim 1, characterized in that, The cross-compiling of the DVS camera's device interface library in step (2) specifically includes: obtaining the device interface library source code provided by the official DVS camera, modifying the compilation script of the source code, specifying the compiler as the cross-compiler aarch64-linux-gnu-gcc / g++ that matches the ARM architecture of the FPGA, adjusting the library dependency path to adapt to the embedded environment of the FPGA, and compiling to generate a device interface library file adapted to the ARM architecture.

4. The method for integrating and using a DVS camera based on FPGA according to claim 1, characterized in that, The vision processing library mentioned in step (3) is the OpenCV library, and the version of the OpenCV library is 3.3.

0. The process of cross-compiling the vision processing library includes: downloading the OpenCV 3.3.0 source code, entering the toolchain configuration file directory of the source code, modifying the toolchain configuration file of the corresponding architecture, specifying the cross-compiler path that matches the ARM architecture of the FPGA in the file, configuring the compilation parameters and the library file installation path, and disabling the hardware acceleration module that is incompatible with the FPGA platform. Then, the compilation and installation instructions are executed to generate the OpenCV library adapted to the ARM architecture.

5. The method for integrating and using a DVS camera based on an FPGA according to claim 1, characterized in that, In step (4), the application retrieves event data through the API functions provided by the DVS camera device interface library. The event data includes pixel coordinates, polarity, and timestamp information. The application also performs DVS camera initialization, working mode configuration, and disabling of irrelevant functional modules.

6. The method for integrating and using a DVS camera based on FPGA according to claim 1, characterized in that, The process of verifying the operational stability of the DVS camera described in step (5) specifically includes: Step (51): Monitor the event data log output by the application through the PC serial port tool to confirm that the event data format is correct and there is no packet loss, so as to verify the data integrity; Step (52): Use visualization tools to display the transmission status and number of events in real time to verify the real-time performance of the data; If the verification results of steps (51) and (52) both meet the requirements, then the DVS camera is determined to be running stably on the FPGA platform.

7. The method for integrating and using a DVS camera based on FPGA according to claim 1, characterized in that, The process of building the embedded Linux system described in step (1) is based on the Petalinux project environment. Specifically, it includes: starting the Petalinux project, executing the configuration command to enter the root file system configuration interface, locating the file system package path "filesystem packages￫libs" in the interface, selecting and enabling the library files related to USB interface communication, saving the configuration and then executing the system build command to recompile the system image and generate the system startup file BOOT.BIN; writing the BOOT.BIN to the removable storage medium, inserting the storage medium into the FPGA's boot interface, and powering on to complete the embedded Linux system construction.

8. The method for integrating and using a DVS camera based on FPGA according to claim 1, characterized in that, The FPGA is a Xilinx XCZU3EG, and its PS side uses an ARM Cortex-A53 architecture; the DVS camera is a CeleX-V, and it is connected to the USB port of the FPGA board via a USB 3.0 interface.

9. The method for integrating and using a DVS camera based on an FPGA according to claim 1, characterized in that, The deployment process of the application in step (4) includes: compiling the application source code using a cross-compiler that matches the FPGA ARM architecture to generate an executable file; placing the executable file into the FAT partition according to the FPGA file system structure; placing the device interface library file generated in step (2) and the vision processing library file generated in step (3) into the Lib folder of the EXT4 partition to complete the deployment of the application and dependent libraries.

10. The method for integrating and using a DVS camera based on an FPGA according to claim 1, characterized in that, After configuring the USB driver environment in step (1), the USB driver verification step is also included: after the system is powered on and started, the driver status detection command is executed to confirm that the libusb related driver modules have been successfully loaded; then the USB device query command is executed. If the query result detects device identification information that matches the CeleX-V camera, it is determined that the USB driver and dependent libraries have been correctly installed and are available.

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