12T-SRAM storage unit for ultra-low-voltage rapid read-write

Abstract

The invention relates to a 12T-SRAM (Static Random Access Memory) storage unit for ultra-low-voltage rapid read-write, and relates to the technical field of memory integrated circuits, the 12T-SRAM storage unit comprises eight NMOS (N-channel Metal Oxide Semiconductor) transistors (N1, N2, N3, N4, N5, N6, N7 and N8) and four PMOS (P-channel Metal Oxide Semiconductor) transistors (P1, P2, P3 and P4); a writing word line WWL controls the transistors N6 and N5; a read-write control signal WL controls PMOS (P-channel Metal Oxide Semiconductor) tubes P4 and P3; an inversion signal WL'is read and written to control NMOS (N-channel Metal Oxide Semiconductor) tubes N4 and N3; a read word line RWL controls transistors N8 and N7; the writing bit line BL and the writing bit line non-BLB are respectively connected with the N5 and the N6; the read bit line RBL and the read bit line non-RBLB are respectively connected with the N7 and the N8; a bit line is directly driven to read by combining a dynamic cut-off feedback device with an internal phase inverter, and complex latch writing is simplified into direct driving of the phase inverter, so that the flip critical voltage is remarkably reduced; under the ultra-low-voltage working condition, the SRAM still has strong write-in capability and higher write-in speed, and the problem of write-in failure of a traditional SRAM under the near-threshold voltage is effectively solved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of memory integrated circuits, in particular to a 12T-SRAM storage unit for ultra-low voltage fast reading and writing. BACKGROUND

[0002] Memory plays an important role in the design of very large scale integrated circuits. As an important type of storage chip, SRAM (Static Random Access Memory) has a significant position in the market that cannot be replaced, although it is not as good as DRAM and NAND Flash in storage capacity. However, with the continuous evolution of semiconductor processes to the nanometer level, such as 14 nanometers, 7 nanometers, etc.

[0003] The existing patent discloses a 13T storage unit, which introduces WWLA, WWLB and RWL signals to finely control the data writing and reading process, and uses Q and QB signals to ensure the stability of the half-selected unit. When writing data, the transmission of the power voltage is regulated by WWLA and WWLB signals, so that the power supply of a column of inverters enters a floating state, which cuts off the feedback path of the inverter, effectively avoiding the write conflict of the traditional storage unit, and realizing the rapid writing of data. In addition, with the help of Q and QB signals, the unit can turn off a column of transistors when reading data, thereby reducing the leakage and interference of the half-selected unit.

[0004] The existing technical solutions in the above have the following defects: 1. The existing storage unit controls the switch through two write word line signals (WWLA and WWLB), and the write word line signal needs to change according to the write data, which makes the signal control more complex and requires a large number of peripheral circuits to realize, increasing the chip area. SUMMARY

[0005] In view of the deficiencies of the prior art, the purpose of the present application is to add P3, P4, N3 and N4 transistor pairs controlled by read-write control signal WL and its inverse signal WL', form a dynamic feedback cutter, simplify the complex latch writing to direct driving of the inverter, significantly reduce the flip critical voltage, effectively solve the write failure problem of the traditional SRAM at near threshold voltage, and realize the dynamic management of the internal feedback path of the storage unit.

[0006] The following technical solutions are adopted: The present application provides a 12T-SRAM storage unit for ultra-low voltage fast reading and writing, which comprises an internal inverter, a dynamic feedback cutter, an access transistor and a read path; wherein, The internal inverter comprises a first inverter composed of a first PMOS tube and a first NMOS tube and a second inverter composed of a second PMOS tube and a second NMOS tube; The dynamic cut-off feedback device comprises a first transistor pair composed of a third PMOS tube and a third NMOS tube and a second transistor pair composed of a fourth PMOS tube and a fourth NMOS tube. The access transistor comprises a fifth NMOS tube, a sixth NMOS tube, a seventh NMOS tube and an eighth NMOS tube. The read path comprises a first read path composed of the seventh NMOS tube and the first NMOS tube and a second read path composed of the second NMOS tube and the eighth NMOS tube. The internal inverter is connected with the dynamic cut-off feedback device, and the access transistor and the read path are both connected with the internal inverter.

[0007] By adopting the above technical scheme, by constructing a 12T-SRAM storage unit comprising a double inverter (composed of a first PMOS / NMOS and a second PMOS / NMOS), a dynamic cut-off feedback device (two groups of PMOS / NMOS transistor pairs are used to realize feedback loop control), an access transistor (four groups of NMOS tubes are responsible for data access) and a double read path (composed of a seventh NMOS and a first NMOS, a second NMOS and an eighth NMOS), the dynamic cut-off feedback device is used to cut off the feedback loop through a third NMOS during the writing operation to enhance the writing driving capability, and the read interference on the storage node is eliminated through a read buffer structure (a fifth PMOS, a sixth NMOS and a seventh NMOS), so that fast reading and writing and stability are realized in an ultra-low voltage environment, and the problem of writing capability reduction caused by voltage reduction in a single-end structure is solved.

[0008] The application is further provided as follows: the source of the first PMOS tube is connected with the source of the second PMOS tube, and the source of the first NMOS tube is connected with the source of the second NMOS tube; the gate of the first PMOS tube is connected with the gate of the first NMOS tube and the first end of the first transistor pair, and the drain of the first PMOS tube is connected with the drain of the first NMOS tube and the first end of the second transistor pair; the gate of the second PMOS tube is connected with the gate of the second NMOS tube and the other end of the second transistor pair, and the drain of the first PMOS tube is connected with the drain of the second NMOS tube and the other end of the first transistor pair; the gate of the third NMOS tube is connected with the gate of the fourth NMOS tube, and the gates of the third PMOS tube and the fourth PMOS tube are both control ends.

[0009] By adopting the technical scheme, the source of the first PMOS and the second PMOS is connected to a power supply, and the source of the first NMOS and the second NMOS is connected to a ground, a double inverter core structure is constructed, wherein the gate of the first PMOS is connected to the gate of the first NMOS and one end of the first transistor pair (the third PMOS / the third NMOS), the drain is cross-coupled to one end of the second transistor pair (the fourth PMOS / the fourth NMOS), the gate of the second PMOS is connected to the gate of the second NMOS and the other end of the second transistor pair, and the drain is fed back to the other end of the first transistor pair, a symmetric cross-coupled feedback loop is formed, the feedback strength is dynamically adjusted by the inverting end of the gate of the third NMOS / the fourth NMOS and the control end of the PMOS, in an ultra-low voltage environment, the driving capability is improved by enhancing the feedback loop opening depth (the third NMOS is turned off) when writing, and the storage node disturbance is isolated by using the independent read path formed by the seventh NMOS / the eighth NMOS and the first NMOS / the second NMOS when reading, fast reading and writing and high static noise margin are realized, and the problems of writing difficulty and reading interference of the traditional SRAM in a low voltage environment are effectively solved.

[0010] The application is further provided: the 12T-SRAM memory cell further includes a write word line, a read word line, a write bit line, a write bit line non, a read bit line, a read bit line non, a driving node and a storage node; the storage node includes a first storage node and a second storage node; the driving node includes a first driving node and a second driving node; the write word line is connected to the gate of the fifth NMOS and the gate of the sixth NMOS; the read word line is connected to the gate of the seventh NMOS and the gate of the eighth NMOS; the write bit line is connected to the drain of the fifth NMOS; the write bit line non is connected to the drain of the sixth NMOS; the read bit line is connected to the drain of the seventh NMOS; the read bit line non is connected to the drain of the eighth NMOS; the first storage node is connected to the common gate of the first inverter and the first end of the first transistor pair; the second storage node is connected to the common gate of the second inverter and the other end of the second transistor pair; the first driving node is connected to the common drain of the first inverter and the first end of the second transistor pair; and the second driving node is connected to the common drain of the second inverter and the other end of the first transistor pair. The potentials of the first storage node and the second storage node are reversed between 0 and 1, and the potentials of the first storage node and the second storage node are opposite; The state of the read bit line is controlled by the on-off of the first driving node; and the state of the read bit line non is controlled by the on-off of the second driving node.

[0011] By adopting the technical scheme, through the writing word line (controlling the fifth and sixth NMOS gate), the reading word line (controlling the seventh and eighth NMOS gate), the writing / reading bit line (transferring the data signal) and the driving / storage node (cross connection through the inverter and the dynamic cut-off feedback device), the dynamic cut-off feedback device is used to cut off the feedback loop in the writing operation to enhance the writing driving capability, and the independent reading path design (the reading bit line state is controlled by the driving node on-off) is used to eliminate the direct coupling interference of the storage node and the bit line in the reading operation, so that the fast reading and writing and high stability are realized under the super low voltage (such as sub-threshold or low voltage power supply), and the writing failure or reading interference problem caused by the voltage reduction of the traditional single-end or double-end structure is solved.

[0012] The application is further provided: when the read-write control signal of the control end is high, the read-write inverted signal of the inverting end is low, the feedback path of the first storage node and the first driving node is open circuit, and the feedback path of the second storage node and the second driving node is open circuit; when the read-write control signal of the control end is low, the read-write inverted signal of the inverting end is high, the feedback path of the first storage node and the first driving node is closed circuit, and the feedback path of the second storage node and the second driving node is closed circuit.

[0013] By adopting the technical scheme, the feedback path between the first and second storage nodes and the driving node is dynamically controlled through the inverted signal (high / low level) of the control end and the inverting end, the signal isolation and stable transmission in the reading and writing operation are realized, the reading and writing interference is effectively avoided, and the stability and power efficiency of the storage unit under the super low voltage are improved.

[0014] The application is further provided: when the initial state of the first storage node is 1 and the initial state of the second storage node is 0, the writing 0 operation is performed, the writing bit line potential is 0, the writing bit line non-potential is 1, the reading word line potential is 0, the writing word line potential is 1, the fifth NMOS tube and the sixth NMOS tube are turned on, the first storage node is connected to the writing bit line, and the second storage node is connected to the writing bit line non.

[0015] By adopting the technical scheme, in the writing 0 operation, the fifth and sixth NMOS tubes are turned on through the high potential of the writing word line, the first storage node is forced to be pulled to the low potential (0) of the writing bit line, and the second storage node is pulled to the high potential (1) of the writing bit line non, reliable state inversion is realized, the writing speed and anti-interference ability are effectively improved, and the power efficiency is optimized.

[0016] In summary, the beneficial technical effects of the application are: By the dynamic cut-off feedback device, the complex latch writing is simplified to the direct driving of the inverter, the inversion critical voltage is significantly reduced, under the super low voltage working condition, the strong writing capability and the faster writing speed are still possessed, and the writing failure problem of the traditional SRAM under the near threshold voltage is effectively solved; The reading is directly driven by the internal inverter to the bit line, which provides strong output driving current, ensures the reading speed, physically separates the reading and writing paths, completely eliminates the "read disturb" phenomenon, ensures that the reading operation does not affect the integrity of the stored data, and greatly improves the reliability of the reading operation and the data security. In the data retention state, the dynamic cut-off feedback device is re-established to form a reinforced cross-coupled latch, which provides extremely high static noise margin, improves the data retention robustness of the unit under power voltage fluctuation, temperature change and noise interference, and guarantees the long-term stable storage of data in complex environment. BRIEF DESCRIPTION OF DRAWINGS

[0017] Figure 1 is a circuit diagram of a 12T storage unit of one embodiment of the present application; Figure 2 is a circuit diagram of a data retention state of one embodiment of the present application; Figure 3 is a circuit diagram of a data read state of one embodiment of the present application; Figure 4 is a circuit diagram of a data write state of one embodiment of the present application. DETAILED DESCRIPTION

[0018] The present application will be further described in detail below with reference to the accompanying drawings.

[0019] REFERENCE Figure 1 A 12T-SRAM storage unit for ultra-low voltage fast reading and writing disclosed by the present application includes eight NMOS transistors (N1, N2, N3, N4, N5, N6, N7 and N8) and four PMOS transistors (P1, P2, P3 and P4): wherein, The internal inverter includes a first inverter composed of a first PMOS tube P1 and a first NMOS tube N1, and a second inverter composed of a second PMOS tube P2 and a second NMOS tube N2; The dynamic cut-off feedback device includes a first transistor pair composed of a third PMOS tube P3 and a third NMOS tube N3, and a second transistor pair composed of a fourth PMOS tube P4 and a fourth NMOS tube N4; The access transistor includes a fifth NMOS tube N5, a sixth NMOS tube N6, a seventh NMOS tube N7 and an eighth NMOS tube N8; The read path includes a first read path composed of the seventh NMOS tube N7 and the first NMOS tube N1, and a second read path composed of the second NMOS tube N2 and the eighth NMOS tube N8; The internal inverter is connected with the dynamic cut-off feedback device, and the access transistor and the read path are both connected with the internal inverter; The sources of the first PMOS transistor P1 and the second PMOS transistor P2 are both connected to the power supply; the sources of the first NMOS transistor N1 and the second NMOS transistor N2 are both grounded; the gate of the first PMOS transistor P1 is connected to the gate of the first NMOS transistor N1 and the first terminal of the first transistor pair, and the drain of the first PMOS transistor P1 is connected to the drain of the first NMOS transistor N1 and the first terminal of the second transistor pair, respectively; the gate of the second PMOS transistor P2 is connected to the gate of the second NMOS transistor N2 and the other terminal of the second transistor pair, respectively; the drain of the first PMOS transistor P1 is connected to the drain of the second NMOS transistor N2 and the other terminal of the first transistor pair, respectively; the gate of the third NMOS transistor N3 and the gate of the fourth NMOS transistor N4 are connected and are inverting terminals; the gates of the third PMOS transistor P3 and the fourth PMOS transistor P4 are both control terminals.

[0020] The write word line WWL controls transistors N6 and N5; the read / write control signal WL controls PMOS transistors P4 and P3; its read / write inverted signal WL' controls NMOS transistors N4 and N3; the read word line RWL controls transistors N8 and N7; the write bit line BL and the write bit line NOT BLB are connected to N5 and N6 respectively; the read bit line RBL and the read bit line NOT RBLB are connected to N7 and N8 respectively. The 12T-SRAM memory cell also includes a write word line WWL, a read word line RWL, a write bit line BL, a write bit line not BLB, a read bit line RBL, a read bit line not RBLB, a driver node, and a memory node; the memory node includes a first memory node NV0 and a second memory node NV1; the driver node includes a first driver node NV0B and a second driver node NV1B; the write word line WWL is connected to the gate of the fifth NMOS transistor N5 and the gate of the sixth NMOS transistor N6, respectively; the read word line RWL is connected to the gate of the seventh NMOS transistor N7 and the gate of the eighth NMOS transistor N8, respectively; the write bit line BL is connected to the gate of the fifth NMOS transistor N7... The drain of NMOS transistor N5 is connected to the drain of the sixth NMOS transistor N6; the read bit line RBL is connected to the drain of the seventh NMOS transistor N7; the read bit line RBLB is connected to the drain of the eighth NMOS transistor N8; the first memory node NV0 is connected to the common gate of the first inverter and the first terminal of the first transistor pair; the second memory node NV1 is connected to the common gate of the second inverter and the other terminal of the second transistor pair; the first drive node NV0B is connected to the common drain of the first inverter and the first terminal of the second transistor pair; the second drive node NV1B is connected to the common drain of the second inverter and the other terminal of the first transistor pair. The potentials of the first storage node NV0 and the second storage node NV1 flip between 0 and 1, and the potentials of the first storage node NV0 and the second storage node NV1 are opposite. When the read / write control signal WL at the control terminal is high, the read / write inverted signal WL' at the inverting terminal is low, the feedback path between the first storage node NV0 and the first driver node NV0B is open, and the feedback path between the second storage node NV1 and the second driver node NV1B is open; when the read / write control signal WL at the control terminal is low, the read / write inverted signal WL' at the inverting terminal is high, the feedback path between the first storage node NV0 and the first driver node NV0B is closed, and the feedback path between the second storage node NV1 and the second driver node NV1B is closed. The state of the read bit line RBL is controlled by the on / off state of the first driving node NV0B; the state of the read bit line other than RBL is controlled by the on / off state of the second driving node NV1B. The implementation principle of this embodiment is as follows: Ultra-low voltage fast read / write is achieved through a dynamic cutoff feedback mechanism. During a write operation, the write word line WWL is activated, turning on N5 and N6, and forcibly covering the storage nodes NV0 / NV1 with the write bit line BL / BLB potential (0 / 1). Simultaneously, the read / write control signal WL (high level) and the inverting signal WL' (low level) turn off P3 / P4 and turn on N3 / N4, cutting off the positive feedback loop of the cross inverter (the paths NV0→NV1B and NV1→NV0B are disconnected), weakening the ability to maintain the original state, and significantly reducing switching power consumption and latency. During a read operation, the read word line RWL activates N7 / N8, driving nodes NV0B / NV1B to control the current path of the read bit line RBL / RBLB through N1 / N2. Independent read branches avoid read / write interference. Dynamic cutoff through feedback improves write speed and reliability, and independent read / write paths enhance noise tolerance, achieving stable operation across a wide voltage range (including ultra-low voltage).

[0021] Reference Figure 2 Example 1: In data hold mode, both the write word line WWL and the read word line RWL are set to low level, the read / write control signal WL is low level, and the read / write inverting signal WL' is high level; the write bit line BL, write bit line NOT BLB and the read bit line RBL, read bit line NOT RBLB can be in any state.

[0022] When WWL is low, transistors N6 and N5 will be turned off, cutting off the transmission path between the write bit lines BL / BLB and the internal memory nodes NV0 / NV1. Therefore, the state of the write bit lines does not affect the internal memory nodes.

[0023] At this time, WL is low, turning on transistors P4 and P3, while WL' is high, turning on transistors N4 and N3, thus establishing the connection paths from node NV0 to NV1B and from NV1 to NV0B. In this state: When node NV0 is high, N1 is turned on, which pulls node NV0B low. Since NV0B is connected to NV1 through the turned-on N4 and P4, it further pulls NV1 low.

[0024] When node NV1 is low, P2 is turned on, which pulls node NV1B high. Since NV1B is connected to NV0 through the conducting N3 and P3, it charges NV0 and maintains its high level.

[0025] Thus, the circuit forms a cross-coupled negative feedback loop, ensuring that the data is kept stable.

[0026] The implementation principle of this embodiment is as follows: In the data holding state, the write word line WWL and the read word line RWL are set to low level to turn off the access transistors N5 / N6 / N7 / N8. At the same time, the read / write control signal WL is set to low level to turn on the PMOS transistors P3 / P4, and the inverting signal WL' is set to high level to turn on the NMOS transistors N3 / N4. Through NV0 → N1 is turned on → NV0B is pulled low → NV1 is driven to be pulled low through N4 / P4 → P2 is triggered to turn on → NV1B is pulled high → NV0 is maintained at a high level through N3 / P3, forming a cross-coupled negative feedback loop, realizing the self-sustaining potential of the storage node, effectively suppressing leakage current and enhancing data stability, and ensuring anti-interference capability and low power consumption characteristics under ultra-low voltage environment.

[0027] Reference Figure 3 Example 2: In data read mode, the write word line WWL is set to low level, the read word line RWL is set to high level, and the read / write control signal WL is set to high level (the read / write inverting signal WL' is low level); the write bit lines BL and BLB can be in any state.

[0028] When WWL is low, transistors N6 and N5 are turned off, cutting off the write bit line's influence on the internal node. The retention mechanism of the internal memory node is similar to the "data retention" state, maintaining NV0 high and NV1 low through feedback from transistors such as N1 and P2.

[0029] Before the read operation is performed, the read bit lines RBL and RBLB are precharged to a high level. A high level RWL turns on transistors N8 and N7.

[0030] Crucially, when WL is high and WL' is low, N4, P4, N3, and P3 will be simultaneously turned off, thereby cutting off the feedback path between NV0 and NV1B, and between NV1 and NV0B. At this time: The state of the read bit line RBL is determined only by the inverter (driving node NV0B) composed of N1 and P1; the state of the read bit line RBLB is determined only by the inverter (driving node NV1B) composed of N2 and P2.

[0031] This structure allows the read lines to be directly driven by the internal inverter, providing extremely strong driving capability.

[0032] Based on the initial state (NV0=1, NV1=0): RBL is discharged to ground through the conducting N7 transistor and the N1 transistor turned on by NV0B, and is pulled low to a low level; RBLB is maintained high by VDD through the conducting P2 transistor and N8 transistor.

[0033] Data can be read by detecting the voltage difference between RBL and RBLB.

[0034] The implementation principle of this embodiment is as follows: During data reading, WWL is set low to close the write path, RWL is set high to open the read path (N7 / N8 is turned on), and WL high level / WL' low level cuts off the dynamic feedback (N3 / P3, N4 / P4 are turned off), so that the read bit lines RBL / RBLB are driven only by the internal inverters (P1 / N1, P2 / N2): NV0=1 triggers N1 to turn on, and RBL discharges to a low level through N7 / N1; NV1=0 triggers P2 to turn on, and RBLB is kept at a high level through P2 / N8. Data reading is achieved by using the potential difference between the two. At the same time, the independent driving mechanism eliminates the direct coupling between the storage node and the read bit line, enhances anti-interference and improves the reading speed, and ensures reliability and stability under ultra-low voltage.

[0035] Reference Figure 4 Example 3: When the initial state of the first storage node is 1 and the initial state of the second storage node is 0, a write 0 operation is performed. The write bit line potential is 0, the write bit line NOT potential is 1, the read word line potential is 0, the write word line potential is 1, the fifth NMOS transistor and the sixth NMOS transistor are turned on, the first storage node is connected to the write bit line, and the second storage node is connected to the write bit line NOT.

[0036] Assuming the initial state is that node NV0 stores "1" (high level) and node NV1 stores "0" (low level), the writing process is now explained using writing data "0" as an example.

[0037] During data writing, the read word line RWL is set to low level, the write word line WWL is set to high level, and the read / write control signal WL is set to high level (the read / write inverting signal WL' is low level).

[0038] When WWL is high, transistors N6 and N5 will be turned on, connecting node NV0 to the write line BL and node NV1 to the write line BLB.

[0039] To write "0", BL must be set to low level and BLB to high level beforehand.

[0040] Crucially, when WL is high and WL' is low, transistors N4, P4, N3, and P3 are turned off, thus cutting off the feedback paths between NV0 and NV1B, and between NV1 and NV0B. At this point, the memory cell can be considered as two independent, less powerful standard inverters (P2-N2 and P1-N1), significantly reducing the feedback strength required for writing and simplifying the flip-flop process.

[0041] Node NV0 discharges to BL through N5 and is quickly pulled low to a low level. This action pulls node NV0B high.

[0042] Node NV1 is charged from BLB through N6 and is quickly pulled high, which in turn pulls node NV1B low.

[0043] Subsequently, the read / write control signal WL returns to low level (WL' returns to high level), and the feedback path is re-established. At this time, nodes NV1 and NV0B are both high level, and nodes NV0 and NV1B are both low level. The circuit enters a new stable state, completing the write operation of data "0".

[0044] The implementation principle of this embodiment is as follows: During the write operation of "0", N5 / N6 is turned on by setting the write word line WWL high. NV0, which initially stores "1", is connected to the low-level write bit line BL, and NV1, which stores "0", is connected to the high-level write bit line BLB. At the same time, the read / write control signal WL high level / WL' low level turns off the dynamic feedback circuit (N3 / P3, N4 / P4), allowing the internal inverters (P1 / N1, P2 / N2) to respond independently to the write signal with weak drive capability. NV0 is pulled low and NV1 is pulled high, and the drive nodes NV0B and NV1B flip synchronously. After WL returns to low level, the feedback path is rebuilt, the circuit enters a new stable state, and the write is completed. By cutting off the feedback path, the internal stability resistance that needs to be overcome for writing is reduced, significantly improving the write reliability and speed under ultra-low voltage, while avoiding interference and enhancing overall performance.

[0045] The embodiments described in this specific implementation are preferred embodiments of this application and are not intended to limit the scope of protection of this application. Therefore, all equivalent changes made in accordance with the structure, shape and principle of this application should be covered within the scope of protection of this application.

Claims

1. A 12T-SRAM memory cell for ultra-low voltage fast read and write, characterized by: It comprises an internal inverter, a dynamic cut-off feedback, an access transistor and a read path. The internal inverter comprises a first inverter composed of a first PMOS tube and a first NMOS tube and a second inverter composed of a second PMOS tube and a second NMOS tube. The dynamic cut-off feedback comprises a first transistor pair composed of a third PMOS tube and a third NMOS tube and a second transistor pair composed of a fourth PMOS tube and a fourth NMOS tube. The access transistor comprises a fifth NMOS tube, a sixth NMOS tube, a seventh NMOS tube and an eighth NMOS tube. The read path comprises a first read path composed of the seventh NMOS tube and the first NMOS tube and a second read path composed of the second NMOS tube and the eighth NMOS tube. The internal inverter is connected with the dynamic cut-off feedback, and the access transistor and the read path are both connected with the internal inverter.

2. The 12T-SRAM memory cell for ultra-low voltage fast read and write according to claim 1, wherein: The source of the first PMOS tube and the source of the second PMOS tube are both connected with a power supply; the source of the first NMOS tube and the source of the second NMOS tube are both grounded; the gate of the first PMOS tube is connected with the gate of the first NMOS tube and the first end of the first transistor pair respectively, and the drain of the first PMOS tube is connected with the drain of the first NMOS tube and the first end of the second transistor pair respectively; the gate of the second PMOS tube is connected with the gate of the second NMOS tube and the other end of the second transistor pair respectively, and the drain of the second PMOS tube is connected with the drain of the second NMOS tube and the other end of the first transistor pair respectively; the gate of the third NMOS tube and the gate of the fourth NMOS tube are connected and are opposite-phase ends; the gate of the third PMOS tube and the gate of the fourth PMOS tube are both control ends.

3. The 12T-SRAM memory cell for ultra-low voltage fast read and write according to claim 1, wherein: The 12T-SRAM memory cell further comprises a write word line, a read word line, a write bit line, a write bit line non, a read bit line, a read bit line non, a driving node and a storage node; the storage node comprises a first storage node and a second storage node; the driving node comprises a first driving node and a second driving node; the write word line is connected with the gate of the fifth NMOS tube and the gate of the sixth NMOS tube respectively; the read word line is connected with the gate of the seventh NMOS tube and the gate of the eighth NMOS tube respectively; the write bit line is connected with the drain of the fifth NMOS tube; the write bit line non is connected with the drain of the sixth NMOS tube; the read bit line is connected with the drain of the seventh NMOS tube; the read bit line non is connected with the drain of the eighth NMOS tube; the first storage node is connected with the common gate of the first inverter and the first end of the first transistor pair respectively; the second storage node is connected with the common gate of the second inverter and the other end of the second transistor pair respectively; the first driving node is connected with the common drain of the first inverter and the first end of the second transistor pair respectively; the second driving node is connected with the common drain of the second inverter and the other end of the first transistor pair respectively.

4. The 12T-SRAM memory cell for ultra-low voltage fast read and write according to claim 3, wherein: The potentials of the first storage node and the second storage node are reversed between 0 and 1 respectively, and the potentials of the first storage node and the second storage node are opposite.

5. The 12T-SRAM memory cell for ultra-low voltage fast read-write according to claim 2 or 3, characterized in that: When the read-write control signal of the control end is high, the read-write inverse signal of the inverse end is low, the feedback path between the first storage node and the first driving node is open, and the feedback path between the second storage node and the second driving node is open; when the read-write control signal of the control end is low, the read-write inverse signal of the inverse end is high, the feedback path between the first storage node and the first driving node is closed, and the feedback path between the second storage node and the second driving node is closed.

6. The 12T-SRAM memory cell for ultra-low voltage fast read and write according to claim 3, wherein: The state of the read bit line is controlled by the on-off of the first driving node, and the state of the read bit line non is controlled by the on-off of the second driving node.

7. The 12T-SRAM memory cell for ultra-low voltage fast read and write as claimed in claim 3 wherein: When the initial state of the first storage node is 1 and the initial state of the second storage node is 0, the write 0 operation is performed, the potential of the write bit line is 0, the potential of the write bit line non is 1, the potential of the read word line is 0, the potential of the write word line is 1, the fifth NMOS tube and the sixth NMOS tube are turned on, the first storage node is connected to the write bit line, and the second storage node is connected to the write bit line non.

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