Read and write schemes for high-density sram

Abstract

The present invention relates to read and write schemes for high density SRAM. The present disclosure relates to an architecture comprising a dual write bit switching device comprising a plurality of bit switching devices located at different locations of an array of memory cells and configured to enable a write operation at a specific number of cells per bit line of the array of memory cells.

Description

Technical Field

[0001] This disclosure relates to read and write schemes for high-density static random access memory (SRAM), and more specifically, to read and write schemes for high-density SRAM for improving array write and read cycle times. Background Technology

[0002] A memory chip comprises an array of memory cells interconnected by bit lines and word lines. Word lines and bit lines are used to read and write binary values ​​into each memory cell. Each memory cell represents an information bit. Because each memory cell represents an information bit and can be connected to other circuitry, it is desirable that the electrical and operational characteristics of all memory cells be consistent.

[0003] The operational and electrical characteristics of memory cells vary depending on their location within the memory array layout. For example, memory cells along the edge of the memory array may have different electrical and operational characteristics than those located in the inner regions of the memory array. Therefore, the memory array may not have consistent electrical and operational characteristics throughout the entire memory chip.

[0004] In high-density technologies (e.g., 7nm or lower), each metal layer of a static random access memory (SRAM) is highly resistive. Furthermore, in SRAM, bit lines (BLs) are routed to the M0 metal layer (i.e., the lowest metal layer in the SRAM) used for read and write operations. Therefore, the RC time constant of the bit line (BL) (i.e., the time constant of the RC circuit as the product of the RC circuit resistance and RC circuit capacitance) limits the maximum number of cells per bit line (CPBL) in the memory bank of the SRAM. Moreover, after several read and write operations, the RC time constant degrades the read and write cycle time. Summary of the Invention

[0005] In one aspect of this disclosure, there is a structure including a dual write bit switching device, the dual write bit switching device comprising a plurality of bit switching devices at different locations in a memory cell array and configured to perform write operations at a specific number of cells per line of the memory cell array.

[0006] In another aspect of this disclosure, there is a structure including a dual write bit switching device, the dual write bit switching device comprising a first switching device and a second switching device located at different positions in a memory cell array, the dual bit switching device being configured to perform write operations in a static random access memory (SRAM) at a specific number of cells per line of the memory cell array.

[0007] In another aspect of this disclosure, a method includes establishing at least one write operation for a dual write bit switching device, and after establishing at least one write operation for the dual write bit switching device, performing at least one write operation at a specific number of cells per line of a memory cell array. Attached Figure Description

[0008] The present disclosure is described in the following detailed description with reference to the plurality of accompanying drawings, using non-limiting examples of exemplary embodiments thereof.

[0009] Figure 1 A write scheme with a dual write bit switching (DWBS) structure according to aspects of this disclosure is shown.

[0010] Figure 2 A diagram of the DWBS structure according to aspects of this disclosure is shown.

[0011] Figure 3 A flowchart of a write operation using a DWBS structure according to aspects of this disclosure is shown. Detailed Implementation

[0012] This disclosure relates to read and write schemes for high-density static random access memory (SRAM), and more specifically, to read and write schemes for high-density SRAM to improve array write and read cycle times. This disclosure relates to providing a dual write bit switching (DWBS) scheme, which enables write operations at a higher number of cells per bit line (CPBL). Furthermore, the DWBS scheme improves memory density and can also improve yield. For example, yield is improved by providing lower voltage operation than conventional SRAM. The DWBS scheme of this disclosure will also achieve faster array read and write cycle times. Moreover, although this disclosure relates to SRAM, those skilled in the art will understand that the embodiments are not limited to this type of memory and can be applied to other memory types (e.g., DRAM).

[0013] Figure 1 A write scheme with a dual write bit switching (DWBS) structure according to aspects of this disclosure is shown. Figure 1 In this configuration, the dual write bit switching structure 100 includes a parallel inverter 10 connected via an inverted write bit switching signal 40. Furthermore, a first write bit switching signal 20' and a second write bit switching signal 20'' are connected to corresponding inverters within the parallel inverter 10. Figure 1In this process, the inverted write bit switch signal 40 is routed across the word line driver 30. Furthermore, the Digital Line True Write (DLTW) / Digital Line Supplementary Write (DLCW) 50 is routed across the memory cell array 70. The first write bit switch 60 is connected to the second write bit switch 60' via parallel DLTW / DLCW lines 50. Finally, the second write bit switch 60' is connected in series to the write driver 80.

[0014] exist Figure 1 In this configuration, memory cell array 70 is connected to two write bit switching devices 60, 60' via parallel signal lines. Each of the two write bit switching devices 60, 60' is located at a different location within memory cell array 70. In an embodiment, for example, one of the two write bit switching devices 60 is located near the memory cell array 70, while the other 60' is located far from the memory cell array 70. Thus, in one example, one of the two write bit switching devices 60 is located at a bit slice of memory cell array 70, and the other 60' is located at the array edge of memory cell array 70. Specifically, memory cell array 70 is connected to the two write bit switching devices 60, 60' via at least one Digital Line True Write (DLTW) / Digital Line Supplemental Write (DLCW) 50. In an embodiment, the connection may be a controlled collapse chip connection (C4); although other solder or pillar connections are considered herein.

[0015] In the embodiments, Figure 1 In this configuration, the memory cell array 70 is connected to two write bit switching devices 60, 60' via two DLTW / DLCW lines 50. Furthermore, the DLTW / DLCW lines 50 are routed across the memory cell array 70 and are shielded by power supply (e.g., w-40nm / s-80nm). Those skilled in the art will understand that any number of DLTW / DLCW lines can be used to connect the memory cell array 70 to the two write switching devices 60, 60'.

[0016] exist Figure 1In this configuration, write bit switching device 60' is connected in series to write driver 80. In one example, write bit switching device 60' is connected in series to write driver 80 via a transmission gate. Write driver 80 can perform write operations on memory cell array 70. Furthermore, an inverted write bit switching signal 40 is routed across word line driver 30 and buffered at array edges (e.g., w-80nm / s-80nm). Specifically, the inverted write bit switching signal 40 is inverted on both sides by inverter 10 to generate two write bit switching signals 20' and 20''. The two write bit switching signals 20' and 20'' are then applied to each of the two write bit switching devices 60 and 60' to turn each of them on.

[0017] exist Figure 1 In this embodiment, before performing a write operation, the DLTW / DLCW line 50 is established before the write bit switching clock signal arrives. Compared to using only one write bit switch, this disclosure uses an additional RC applied to the DLTW / DLCW line 50. Therefore, compared to a scheme where only one write bit switch is used, the DLTW / DLCW line 50 will have an increased setup time for writing data; however, since the setup time for writing data is typically quite low, the increased setup time cost can be easily absorbed. Furthermore, the additional area for adding a second write bit switching device 60' is small (e.g., approximately 20 PC or 1.12u).

[0018] Still referencing Figure 1 Before the write operation, the data on the DLTW / DLCW line 50 is set during the write data setup time. Then, after the data on the DLTW / DLCW line 50 is set, the write bit switching clock arrives and the write operation is performed by the write driver 80. During the write operation, the inverted write bit switching signal 40 is routed across the word line driver 30 and buffered by the inverter 10. Since the inverted write bit switching signal 40 is inverted by the inverter 10, the write bit switching signal 20' or 20'' can be passed to the two write bit switching devices 60, 60' at the bit slices and array edges of the memory cell array 70 to turn on both write bit switching devices 60, 60'. Finally, after the DLTW / DLWC line 50 is routed across the memory cell array 70, the write operation is completed in the memory cell array 70. Based on a typical write operation, compared to using only one write bit switch, Figure 1 The dual write bit switching structure 100 improves cell write time by 64%.

[0019] Figure 2 A diagram of the DWBS structure according to aspects of this disclosure is shown. Figure 2 In Figure 200 of the DWBS structure 100, the x-axis is shown in nanoseconds, ranging from approximately 2.4 nanoseconds to approximately 3.4 nanoseconds. Furthermore, the y-axis is shown in volts, ranging from approximately 0 volts to approximately 0.6 volts. Figure 200 includes known write waveforms for single-write bit switching and dual-write bit switching.

[0020] Specifically, Figure 200 includes a known near bit line complement (NBLC) 210 for single write bit switching, a near bit line complement (NBLC) 220 for dual write bit switching, a far bit line complement (FBLC) 230 for dual write bit switching, a midpoint bit line complement (MBLC) 240 for dual write bit switching, and a known far bit line complement (FBLC) 250 for single write bit switching. A word line 260, a data line 270 for dual write bit switching, and a data line 280 for known single write bit switching are also shown.

[0021] In the embodiments, the known near bit line complement (NBLC) 210 for single write bit switching and the near bit line complement (NBLC) 220 for dual write bit switching are complement bit line signals close to the write bit switching device. Furthermore, the far bit line complement (FBLC) 230 for dual write bit switching and the known far bit line complement (FBLC) 250 for single write bit switching are complement bit line signals far from the write bit switching device. The midpoint bit line complement (MBLC) 240 for dual write bit switching refers to the complement bit line signal at the midpoint between the NBLC and the FBLC.

[0022] exist Figure 2 In this context, after a write operation is performed, the value of the dual write bit switching data line 270 in the cell of memory array 70 changes its binary value (e.g., from binary value "0" to binary value "1"). Therefore, as... Figure 2 As shown, the dual-write bit-switching data line 270 implemented in the DWBS structure 100 changes the data value in approximately 76 picoseconds after the start of a write operation. In contrast, the single-write bit-switching data line 280 of a conventional structure changes the data value in approximately 210 picoseconds. Therefore, the dual-write bit-switching data line 270 changes the data value approximately 64% faster than the single-write bit-switching data line 280. Figure 2 As shown, the difference between the modified data line 270 for dual write bit switching and the known data line 280 for single write bit switching is illustrated by difference 290.

[0023] Figure 3A flowchart of a write operation using a DWBS structure according to aspects of this disclosure is shown. The process 300 using the DWBS structure 100 for a write operation begins at step 310. At step 320, the DLTW / DLCW line 50 is set up for the write operation. Specifically, the data on the DLTW / DLCW line 50 is set during the write data setup time. At step 330, the DWBS structure 100 waits for the write bit switching clock to begin the write operation. At step 340, the write operation is performed using the write driver 80. During the write operation, the inverted write bit switching signal 40 is routed across the word line driver 30 and then buffered through the inverter 10. Since the inverted write bit switching signal 40 is inverted by the inverter 10, write bit switching signals 20', 20'' can be applied to the two write bit switching devices 60, 60' to turn on the two write bit switching devices 60, 60'. Specifically, the two write bit switching devices 60 and 60' include a first switching device 60 at a bit slice of the memory cell array 70 and a second bit switching device 60' at the array edge of the memory cell array 70. Finally, in step 350, after the DLTW / DLCW line 50 is routed across the memory cell array 70, the write operation is completed in the memory cell array 70.

[0024] The circuits and methods for the dual-write bit-switching structures of this disclosure can be fabricated using a variety of different tools in a variety of ways. Typically, the methods and tools are used to form structures with dimensions in the micrometer and nanometer scale. Methods (i.e., techniques) for fabricating the circuits and methods for the dual-write bit-switching structures of this disclosure have been adopted from integrated circuit (IC) technology. For example, these structures are built on a wafer and realized by a film of material patterned on top of the wafer using a photolithography process. Specifically, the fabrication of the circuits and methods for the dual-write bit-switching structures uses three basic building blocks: (i) depositing a thin film of material on a substrate, (ii) forming a patterned mask on top of the film by photolithography imaging, and (iii) selectively etching the film onto the mask.

[0025] The method described above is used for the manufacture of integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer as bare chips (i.e., as a single wafer with multiple unpackaged chips) or in package form. In the latter case, the chips are mounted in a single-chip package (such as a plastic carrier with leads attached to a motherboard or other higher-level carrier) or a multi-chip package (such as a ceramic carrier with single-sided or double-sided surface interconnects or buried interconnects). In either case, the chips are then integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of (a) an intermediate product (such as a motherboard) or (b) a final product. The final product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products with displays, keyboards or other input devices, and central processing units.

[0026] For illustrative purposes, various embodiments of this disclosure have been described, but are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein has been chosen to best explain the principles of the embodiments, practical application of technology found in the market, or technical improvements, or to enable those skilled in the art to understand the embodiments disclosed herein.

Claims

1. A dual-write bit-switching structure, comprising a dual-write bit-switching device, the dual-write bit-switching device including a plurality of bit-switching devices located at different positions in a memory cell array, and configured to perform write operations at a specific number of cells per line of the memory cell array. in, The plurality of bit switching devices includes a first switching device located on the proximal side of the memory cell array and a second bit switching device located on the distal side of the memory cell array opposite to the proximal side. Both the first switching device and the second switching device are configured to perform the write operation. The first switching device is connected to the second switching device via a digital line true write line / digital line supplement write line.

2. The dual-write bit switching structure according to claim 1, wherein, The first bit switching device is located at a bit slice of the memory cell array; and The second bit switching device is located at the edge of the memory cell array.

3. The dual write bit switching structure according to claim 2 further includes a write driver configured to perform a write operation at the memory cell array.

4. The dual-write bit switching structure according to claim 3, wherein, The write driver is connected to one of the first bit switching device and the second bit switching device via a transmission gate.

5. The dual write bit switching structure according to claim 1 further includes a word line driver configured to drive a plurality of write bit switching lines for the dual write bit switching device.

6. The dual-write bit switching structure according to claim 5, wherein, The word line driver is also configured to use multiple inverters to drive the multiple write bit switching lines for the dual write bit switching device.

7. The dual-write bit switching structure according to claim 1, wherein, At least one write line is routed from the dual write bit switching device to the memory cell array via a controlled collapse chip connection.

8. The dual-write bit switching structure according to claim 1, wherein, The memory cell array is part of a static random access memory.

9. A dual-write bit-switching structure, comprising a dual-write bit-switching device, the dual-write bit-switching device including a first switching device and a second switching device located at different positions with respect to a memory cell array, the dual-write bit-switching device being configured to perform write operations at a specific number of cells per line of the memory cell array in a static random access memory. in, The first bit switching device is located on the proximal side of the memory cell array, and the second bit switching device is located on the distal side of the memory cell array opposite to the proximal side. Both the first switching device and the second switching device are configured to perform the write operation. The first switching device is connected to the second switching device via a digital line true write line / digital line supplement write line.

10. The dual-write bit switching structure according to claim 9, wherein, The first bit switching device is located at a bit slice of the memory cell array, and the second bit switching device is located at the array edge of the memory cell array.

11. The dual write bit switching structure of claim 10 further includes a write driver configured to perform a write operation at the memory cell array.

12. The dual-write bit switching structure according to claim 11, wherein, The write driver is connected to one of the first bit switching device and the second bit switching device via a transmission gate.

13. The dual write bit switching structure of claim 9 further includes a word line driver configured to drive a plurality of write bit switching lines for the dual write bit switching device.

14. The dual-write bit switching structure according to claim 13, wherein, The word line driver is also configured to use multiple inverters to drive the multiple write bit switching lines for the dual write bit switching device.

15. The dual-write bit switching structure according to claim 13, wherein, The word line driver is also configured to drive the plurality of write bit switching lines for the dual write bit switching device via a controlled collapse chip connection.

16. The dual-write bit switching structure according to claim 9, wherein, At least one write line is routed from the dual write bit switching device to the memory cell array via a controlled collapse chip connection.

17. A method for performing a write operation using a dual write bit switching structure including a dual write bit switching device, comprising: Establish at least one write operation for the dual write bit switching device; as well as After establishing at least one write operation for the dual-write bit switching device, the at least one write operation is performed at a specific number of cells per bit line of the memory cell array. The dual-write bit switching device includes a first switching device located on the near side of the memory cell array and a second switching device located on the far side of the memory cell array opposite to the near side. Both the first switching device and the second switching device are configured to perform the at least one write operation. The first switching device is connected to the second switching device via a digital line true write line / digital line supplement write line.

18. The method of claim 17, further comprising receiving a write bit switching clock before performing the at least one write operation.

19. The method of claim 17, wherein, The first bit switching device is located at a bit slice of the memory cell array and the second bit switching device is located at the array edge of the memory cell array to accelerate the at least one write operation.

20. The method of claim 17, wherein, The memory cell array is part of a static random access memory.

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