Dynamic encryption system and method based on RISC-V architecture

Abstract

The invention relates to the technical field of encryption, and provides a dynamic encryption system and method based on an RISC-V. The system comprises a feature generation module used for generating a feature set; a configurable RISC-V processor soft core, a dynamic key generation module and a data encryption operation module are integrated in the SoC, and the data encryption operation module is connected with the dynamic key generation module and the processor soft core through a system bus. The feature generation module and the data encryption operation module establish direct data connection with the processor soft core through a symbiotic register architecture; the dynamic key generation module is used for generating a dynamic chaotic sequence based on the feature set; and the data encryption operation module is used for acquiring to-be-encrypted plaintext data, performing encryption operation on the to-be-encrypted plaintext data based on the dynamic chaotic sequence and outputting an encryption operation result. The method is based on the RISC-V architecture, the calculation overhead and efficiency are reduced, the data access and encryption speed is increased, and the method can adapt to the real-time requirement of diversified scenes.

Description

Technical Field

[0001] This application relates to the field of data encryption technology, and in particular to a dynamic encryption system and method based on RISC-V architecture. Background Technology

[0002] With the development of network technology, data security has received increasing attention. Encryption methods can transform readable plaintext information into ciphertext, thereby achieving the goal of data security.

[0003] Existing encryption systems suffer from high computational overhead, high power consumption, and poor real-time performance, making it difficult to meet the needs of running complex encryption algorithms and real-time data transmission. Summary of the Invention

[0004] To address the above technical issues, this application proposes a dynamic encryption system and method based on the RISC-V architecture.

[0005] The first aspect of this application provides a dynamic encryption system based on a RISC-V architecture, the system comprising: The feature generation module is used to generate feature sets; A system-on-a-chip (SoC) integrates a configurable RISC-V processor soft core, a dynamic key generation module, and a data encryption operation module. The data encryption operation module is connected to the dynamic key generation module and the processor soft core via a system bus. The feature generation module and the data encryption operation module establish a direct data connection with the processor soft core through a symbiotic register architecture. The dynamic key generation module is used to generate a dynamic chaotic sequence based on the feature set; The data encryption operation module is used to obtain plaintext data to be encrypted, perform encryption operation on the plaintext data to be encrypted based on the dynamic chaotic sequence, and output the encryption operation result.

[0006] In an optional embodiment, the implementation of the co-occurrence register architecture includes: The RISC-V processor soft core is divided into multiple co-occurrence registers, and the feature generation module directly writes the generated feature set into the specified co-occurrence register.

[0007] In an optional embodiment, the data encryption operation module directly reads the feature set and the dynamic chaotic sequence from the symbiotic register as operands for encryption operations.

[0008] In an optional embodiment, the plurality of co-occurring registers include a first register, a second register, and a third register; the feature set is directly written into the first register, the dynamic chaotic sequence is directly written into the second register, and the encryption operation result is directly written into the third register.

[0009] In an optional embodiment, the RISC-V processor soft core's instruction set includes dedicated encryption operation instructions, which can specify the co-occurrence register address as the source operand and destination operand, and complete data reading, encryption operation, and result write-back within a single instruction cycle.

[0010] In an optional embodiment, the system further includes: The biometric sensing module is used to collect the user's biometric signals; The feature generation module is connected to the biometric sensing module and is used to generate a feature set based on the biometric signals.

[0011] A second aspect of this application provides a dynamic encryption method based on a RISC-V architecture, applied to a dynamic encryption system based on a RISC-V architecture, the method comprising: Generate a feature set; A dynamic chaotic sequence is generated based on the aforementioned feature set; Obtain the plaintext data to be encrypted, perform encryption operation on the plaintext data to be encrypted based on the dynamic chaotic sequence, and output the encryption operation result.

[0012] In an optional embodiment, the generated feature set includes: Acquire biometric signals, including the first characteristic signal of the central node and the second characteristic signals of other nodes; Identify representative peaks in the first and second feature signals; Extract feature parameters related to the essential characteristics of the signal from the representative peaks; Scalar quantization of the feature parameters; The feature set is formed by combining the scalar quantized feature parameters. The feature set includes a first feature set of the first feature signal and a second feature set of the second feature signal.

[0013] In an optional embodiment, generating a dynamic chaotic sequence based on the feature set includes: Construct an encoding function based on the first feature set; A security template is generated based on the encoding function, and the security template includes the encoded information of the first feature set and a key for decoding; Construct a decoding function based on the second feature set; The security template is decoded using the decoding function. If the decoding function successfully decodes the security template, then the second feature set and the key are combined to generate the initial seed of the chaotic system; A dynamic chaotic sequence is generated based on the initial seed.

[0014] In an optional embodiment, the method further includes: A dedicated encryption operation instruction is set up, and the target address in the co-occurrence register is specified through the dedicated encryption operation instruction. The storage area corresponding to the target address is used as the source operand storage area and the destination operand storage area. Within a single instruction cycle, the following are completed sequentially: reading the feature set and the dynamic chaotic sequence from the source operand storage area, performing encryption operation, and writing the encryption operation result back to the destination operand storage area.

[0015] Beneficial effects: This application provides a dynamic encryption system and method based on the RISC-V architecture, which reduces computational overhead and efficiency, improves encryption speed, and can adapt to the real-time requirements of diverse scenarios. The dynamic encryption system integrates a configurable RISC-V processor soft core, a dynamic key generation module, and a data encryption operation module into a SoC (System-on-a-Chip), which has flexible hardware and software configurability and an open-source instruction set, allowing for the customization of encryption instructions according to specific encryption algorithm requirements. Furthermore, the feature extraction step, key generation step, and data encryption step are implemented in the form of hardware circuits, achieving hardware-level acceleration, significantly improving encryption speed, reducing computational overhead and power consumption, and making it suitable for battery-powered portable or implantable medical devices. The feature generation module and the data encryption operation module achieve direct data connection with the RISC-V processor soft core through a co-occurrence register architecture. The feature generation module, dynamic key generation module, or data encryption operation module can call the co-occurrence registers of the processor soft core, achieving efficient data interaction, reducing the latency of accessing external memory, and meeting the real-time requirements of diverse application scenarios. Attached Figure Description

[0016] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a block diagram of a dynamic encryption system based on the RISC-V architecture, as shown in the embodiment. Figure 2 This is a block diagram of the overall hardware architecture of a dynamic encryption system based on the RISC-V architecture, as an example. Figure 3 This is a schematic diagram illustrating the connection relationship between the processor soft core, symbiotic registers, and hardware acceleration module in an embodiment. Figure 4 An example circuit structure diagram of the feature generation module in this embodiment; Figure 5 The circuit structure example diagram of the dynamic key generation module and the data encryption operation module in the embodiment is shown below; Figure 6 This is a time-series example diagram illustrating the feature set generation effect in the embodiment. Figure 7 This is a timing example diagram illustrating the dynamic key generation and encryption operation effects in the embodiment. Figure 8 This is a schematic diagram illustrating resource usage and test results for an example. Figure 9 A flowchart illustrating a dynamic encryption method based on a RISC-V architecture, as an example; Figure 10 This is a flowchart of the biometric processing in an embodiment; Figure 11 Flowchart of the feature set generation steps in this embodiment; Figure 12 The flowchart illustrates the steps for generating a chaotic seed in this embodiment.

[0018] Figure label: 1-Feature generation module; 2-SoC; 3-Processor soft core; 4-Dynamic key generation module; 5-Data encryption and computation module; 6-Biometric sensing module. Detailed Implementation

[0019] Various embodiments of this disclosure will be described more fully below. This disclosure may have various embodiments, and adjustments and changes may be made therein. However, it should be understood that there is no intention to limit the various embodiments of this disclosure to the specific embodiments disclosed herein, but rather this disclosure should be understood to cover all adjustments, equivalents, and / or alternatives falling within the spirit and scope of the various embodiments of this disclosure.

[0020] In the following, the terms “comprising” or “may include”, which may be used in various embodiments of this disclosure, indicate the presence of the disclosed functions, operations, or elements, and do not limit the addition of one or more functions, operations, or elements. Furthermore, as used in various embodiments of this disclosure, the terms “comprising,” “having,” and their cognates are intended only to indicate a particular feature, number, step, operation, element, component, or combination of the foregoing, and should not be construed as primarily excluding the presence of one or more other features, numbers, steps, operations, elements, components, or combinations of the foregoing, or the possibility of adding one or more combinations of the foregoing.

[0021] In various embodiments of this disclosure, the expression "or" or "at least one of A and / or B" includes any combination or all combinations of the words listed simultaneously. For example, the expression "A or B" or "at least one of A and / or B" may include A, may include B, or may include both A and B.

[0022] The terms used in the various embodiments of this disclosure (such as "first," "second," etc.) may modify various components in the various embodiments, but do not limit the corresponding components. For example, the above terms do not limit the order and / or importance of the components. The above terms are only used for the purpose of distinguishing one component from others. For example, a first user device and a second user device refer to different user devices, although both are user devices. For example, a first component may be referred to as a second component without departing from the scope of the various embodiments of this disclosure, and similarly, a second component may also be referred to as a first component.

[0023] The term "user" as used in various embodiments of this disclosure may refer to a person using an electronic device or a device using an electronic device (e.g., an artificial intelligence electronic device).

[0024] The terminology used in the various embodiments of this disclosure is for the purpose of describing particular embodiments only and is not intended to limit the various embodiments of this disclosure. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which the various embodiments of this disclosure pertain. Terms (such as those defined in a generally used dictionary) are to be interpreted as having the same meaning as in the context of the relevant technical field and are not to be interpreted as having an idealized or overly formal meaning, unless clearly defined in the various embodiments of this disclosure.

[0025] With the widespread adoption of the Internet of Things (IoT) and wearable devices, achieving high-strength data encryption on resource-constrained terminal devices has become a key challenge. Traditional software encryption schemes, running on a central processing unit (CPU), suffer from high computational overhead, high power consumption, and poor real-time performance. While fixed hardware encryption modules are fast, key management and updates are inconvenient, and they are also vulnerable to being cracked.

[0026] Existing technologies utilize the uniqueness of biometric features (such as fingerprints, irises, and electrocardiogram signals) to generate encryption keys. However, most of these schemes suffer from the following drawbacks: Poor feature stability: The collection of biometric features is easily interfered with, resulting in deviations in the feature values ​​extracted each time, making it difficult to accurately match between the two ends.

[0027] Low software implementation efficiency: Running complex feature extraction and encryption algorithms on general-purpose processors cannot meet the needs of real-time data transmission.

[0028] Low system integration: Modules such as biosensing, feature extraction, and encryption operations are independent of each other, resulting in a complex system architecture, high power consumption, and high latency.

[0029] Therefore, there is an urgent need for a solution that can deeply integrate biometric recognition and high-strength encrypted computing at the hardware level, combining high security, high real-time performance, and low power consumption.

[0030] Example 1 RISC-V is an open-source instruction set architecture based on the Reduced Instruction Set Computing (RISC) principle, characterized by openness, modularity, and simplicity.

[0031] SoC (System on Chip) is a technology that integrates multiple key components required for a complete information processing system onto a single chip. It not only represents a high degree of hardware integration, but also a SoC design methodology that includes software and hardware co-design.

[0032] Reference Figure 1 As shown in the figure, this application proposes a dynamic encryption system based on the RISC-V architecture, the system comprising: Feature generation module 1 is used to generate feature sets; The system-on-a-chip (SoC) SoC2 integrates a configurable RISC-V processor soft core 3, a dynamic key generation module 4, and a data encryption operation module 5. The data encryption operation module 5 is connected to the dynamic key generation module 4 and the processor soft core 3 through the system bus. The feature generation module 1 and the data encryption operation module 5 establish a direct data connection with the processor soft core 3 through a symbiotic register architecture.

[0033] Among them, the feature generation module 1 generates a feature set based on biometric signals, which may include fingerprints, iris scans, or electrocardiogram signals, etc.

[0034] For example, the configurable RISC-V processor soft core 3 can be PicoRV32, VexRiscv, Rocket, BOOM, or Sodor, etc.

[0035] Preferably, in some embodiments of this application, the soft core of the configurable processor is selected from the RISC-V architecture CVA6 open-source soft core.

[0036] Preferably, in some embodiments of this application, the feature generation module 1 is implemented by hardware circuitry, and the feature generation module 1, the dynamic key generation module 4, and the data encryption operation module 5 establish a direct data connection with the processor soft core 3 through a symbiotic register architecture.

[0037] Understandably, the feature generation module 1 is implemented through hardware circuitry, which is a hardware acceleration module and has parallel processing capabilities, significantly improving data processing speed. Integrating any one of the dynamic key generation module 4, data encryption operation module 5, and processor soft core 3 into a single SoC2 is also a hardware acceleration design. Together, they reduce the processor's clock frequency requirements, optimize clock gating and power management, and can adapt to the needs of battery-powered portable or implantable medical devices, thereby improving the encryption processing speed and reducing the encryption processing power consumption.

[0038] Dynamic key generation module 4 is used to generate dynamic chaotic sequences based on feature sets; A chaotic system is a complex system that is described by completely deterministic mathematical rules (such as a formula or a system of equations), but whose long-term behavior exhibits unpredictable, stochastic-like characteristics.

[0039] Understandably, the feature set is generated based on the user's biometrics. Biometrics are closely related to the user and are characterized by real-time and dynamic changes. Binding key generation to biometrics solves the problems of traditional security systems relying on pre-allocated and stored keys, which are statically stored and vulnerable to theft, cracking, or loss. Furthermore, because biometric features such as electrocardiogram signals exhibit minute and random fluctuations even at different points within the same person, and chaotic systems possess extreme sensitivity, these fluctuations cause the generated key to change each time, exhibiting a "one-time key" characteristic. This achieves dynamic encryption and significantly improves data security.

[0040] The data encryption operation module 5 is used to acquire plaintext data to be encrypted, perform encryption operations on the plaintext data to be encrypted based on a dynamic chaotic sequence, and output the encryption operation results.

[0041] For example, in some embodiments of this application, the encryption operation for the plaintext data to be encrypted can be an XOR operation. Specifically, the plaintext data is XORed bit by bit with a chaotic sequence (keystream) of the same length to produce a ciphertext result. During decryption, the original plaintext data can be recovered by XORing the chaotic sequence with the ciphertext result again.

[0042] Specifically, in some embodiments of this application, reference is made to Figure 2 As shown, the feature generation module 1 is connected to the SoC2 via a first bus, and the system is connected to external devices via a second bus. Several interfaces are mounted on the second bus, which are used to realize data interaction between the system and external devices. The interface includes one or more of the following: GPIO interface, UART interface, SPI interface, and I2C interface.

[0043] Specifically, in some embodiments of this application, the feature generation module 1 is connected to the SoC 2 via an AXI bus, the data encryption operation module 5 is connected to the dynamic key generation module 4 and the processor soft core 3 via an AXI bus, and the biometric sensing module 6 is connected to the feature generation module 1 via an APB bus and an SPI interface.

[0044] For example, the external device can be a PC, a monitor, or a sensor, enabling data interaction between the system and the external device. Of course, there is no limitation on the specific type of external device.

[0045] More specifically, in some embodiments of this application, reference may be made to Figure 3 As shown, plaintext data enters the system from the PC via the UART interface, and ciphertext results are also transmitted to the PC via the UART interface.

[0046] Furthermore, in some embodiments of this application, such as Figure 4 As shown, the feature generation module 1 mainly includes a random access memory, an electrocardiogram (ECG) signal generator, and an ECG feature extractor. It may also include a row buffer, a peak detection state machine, and an arithmetic logic unit (ALU) to extract ECG signal features. The peak detection state machine is connected to the ALU, and the ALU is connected to the row buffer. The circuit architecture of the dynamic key generation module 4 and the data encryption operation module 5 can be referred to... Figure 5 As shown.

[0047] Among them, the peak detection state machine is used to identify peaks in the electrocardiogram signal, such as the R wave; the arithmetic logic unit is used to quantize and encode the relevant features of the identified peaks, such as the RR interval; and the line buffer is used to buffer multiple consecutive lines of data, such as biometric signals.

[0048] In one optional embodiment, the implementation of the co-occurrence register architecture includes: The RISC-V processor soft core 3 has multiple co-occurrence registers. The feature generation module 1 directly writes the generated feature set into the specified co-occurrence register.

[0049] Understandably, the RISC-V processor soft core 3 has general-purpose registers, which are high-speed storage units inside the processor used to temporarily store data, addresses, and control information. They are the foundation for the CPU to execute instructions efficiently. Multiple co-occurrence registers are divided in the general-purpose registers. Among them, the co-occurrence registers are used to store the feature set generated by feature generation module 1. This realizes a direct speed connection between feature generation module 1 and RISC-V processor soft core 3, which improves data storage and access speed, reduces time latency, and meets the real-time usage requirements.

[0050] Specifically, in some embodiments of this application, the division of multiple co-occurring registers from general-purpose registers can be achieved through software-defined strategies or by physically adding multiple sets of independent register files through microarchitecture extension (shadow registers).

[0051] In an optional embodiment, the data encryption operation module 5 directly reads the feature set and dynamic chaotic sequence from the symbiotic register as operands for encryption operations.

[0052] Understandably, the feature set and dynamic chaotic sequence of the data encryption operation module 5 are obtained through the symbiotic register, establishing a direct data connection between the data encryption operation module 5 and the RISC-V processor soft core 3. This is part of the symbiotic register architecture and can also improve the running speed and data access and storage speed.

[0053] Understandably, the RISC-V architecture, with its open-source instruction set, allows for the customization of encryption instructions based on specific encryption algorithm requirements. Furthermore, the feature generation, key generation, and data encryption steps are implemented in hardware circuitry, achieving hardware-level acceleration, significantly improving encryption speed, and reducing computational overhead and power consumption. The feature generation, key generation, and data encryption steps utilize the processor's co-occurrence registers, enabling efficient data interaction compared to accessing external memory. This reduces access latency and meets the real-time requirements of diverse application scenarios.

[0054] In an optional embodiment, the multiple co-occurring registers include a first register, a second register, and a third register; the feature set is directly written into the first register, the dynamic chaotic sequence is directly written into the second register, and the encryption operation result is directly written into the third register.

[0055] For example, multiple co-occurring registers can be divided from general-purpose registers through a software-defined strategy. Specifically, the compiler can statically allocate a fixed subset of general-purpose registers to different modules according to the ABI specification. For example, registers a0-a3 can be designated as the first registers and allocated to feature generation module 1, registers t0-t3 can be designated as the second registers and allocated to dynamic key generation module 4, and registers s0-s3 can be designated as the third registers and allocated to data encryption operation module 5.

[0056] Understandably, the configuration of the first, second, and third registers facilitates the storage and retrieval of feature sets and dynamic chaotic sequences, eliminating the need for time-consuming high-speed caching, memory write and read operations, greatly reducing data access latency, and meeting the real-time requirements of dynamic encryption. Furthermore, the power consumption of register access is much lower than that of cache or memory access, reducing the number of accesses to off-chip memory, thereby significantly reducing the overall power consumption of the system, which can meet the usage requirements of battery-powered mobile and IoT devices.

[0057] Furthermore, dedicated registers are allocated for different functional modules, forming a clear data interface contract. This facilitates the addition, removal, or upgrading of hardware acceleration modules, simplifying the overall design of the SoC2. Specifically, the aforementioned design accelerates the most time-consuming feature extraction and encryption operations through hardware circuitry, and achieves efficient data interaction with the processor's soft core 3 via a "symbiotic register architecture." This avoids the latency caused by frequent access to external memory in traditional architectures, meeting the stringent real-time requirements of scenarios such as the Internet of Things and Body Area Networks.

[0058] More specifically, in some embodiments of this application, combined with Figure 3 As shown in the architecture, the feature set is directly written into the first register defined by the CVA6 soft core. The processor executes encryption operation instructions, starting the dynamic key generation module 4. The dynamic key generation module 4 (key generation IP core) reads the feature values ​​from the first register, generates a pseudo-random sequence (dynamic chaotic sequence) through a nonlinear chaotic equation (such as a Lorenz system or a digital implementation of the Logistic map), and stores it in the second register. Subsequently, plaintext data received from the UART interface is sent to the system, and the processor executes a custom "AND_ENC" instruction. This instruction instructs the data encryption operation module 5 to read operands from the second register (key source) and the data bus (plaintext data), perform combined encryption operations such as logical AND, shift, and XOR, and write the operation result directly back to the third register. Finally, the ciphertext data is sent back to the host computer from the third register through the UART interface.

[0059] In an optional embodiment, the instruction set of the RISC-V processor soft core 3 includes dedicated encryption operation instructions. These dedicated encryption operation instructions can specify co-occurrence register addresses as source operands and destination operands, and complete data reading, encryption operation, and result writing back within a single instruction cycle.

[0060] Specifically, in some embodiments of this application, the creation process of the encryption operation instruction includes: setting the source operand of the encryption operation instruction to the index first register and / or the second register; the operation of the encryption operation instruction includes data reading, encryption operation and result writing back; and setting the destination operand of the encryption operation instruction to the index third register.

[0061] Understandably, the encryption operation instructions are custom instructions that work closely with the hardware acceleration module, directly indexing co-occurring registers, achieving a tightly coupled design that can significantly improve the performance of the dynamic encryption system.

[0062] In an optional embodiment, the system further includes: Biometric sensing module 6 is used to collect the user's biometric signals; The feature generation module 1 is connected to the biometric sensing module 6 and is used to generate a feature set based on biometric signals.

[0063] The collected biometric signals may include fingerprints, iris scans, or electrocardiogram signals.

[0064] For example, in some embodiments of this application, when the biometric sensing module 6 is used to collect fingerprints, it can be implemented using an optical sensor, a capacitive sensor, or an ultrasonic sensor to acquire images of the skin ridges and valleys of the finger; when the biometric sensing module 6 is used to collect iris data, it can be implemented using a camera and / or an infrared camera to capture the complex texture features of the iris; when the biometric sensing module 6 is used to collect electrocardiogram (ECG) signals, it can be implemented using flexible electrodes to measure the skin surface potential generated by cardiac electrical activity. Of course, there are no limitations on the type of biometric signal or the specific implementation structure of the biometric sensing module 6.

[0065] Specifically, in some embodiments of this application, combined with Figure 10 As shown, the biometric sensing module 6 is used to acquire electrocardiogram (ECG) signals. The biometric sensing module 6 can be implemented using an ADS1292R sensor. The ECG data acquired by the ADS1292R sensor is transmitted to the FPGA via the SPI interface. Inside the FPGA, the ECG signal data is sent to the feature generation module 1.

[0066] For example, in fingerprint feature extraction, key features may include ridge endpoints and ridge bifurcation points, vertebral edge shape, etc.; in iris feature extraction, key features may include texture features such as half-dots, stripes, and coronal structures; in electrocardiogram signal feature extraction, key features may include features such as the amplitude, duration, and RR interval of P waves, QRS complexes, and T waves.

[0067] Of course, the above are just some examples of key feature extraction from biometric signals, and there are no restrictions on the specific key feature content extracted.

[0068] In an optional embodiment, it can be combined with Figure 2 As shown, the dynamic encryption system is implemented on a development board based on a certain brand of FPGA, using the RISC-V architecture CVA6 soft core. The operating clock frequency can be adjusted and updated. For example, it can be set to 50MHz and divided into different clock domains by the internal PLL.

[0069] In the simulation device (FPGA), the feature generation module 1 processes biometric information, and the resulting feature set can be referenced. Figure 6 As shown, the circuit design was completely successful and met expectations during the prototype verification process, demonstrating the excellent performance of feature extraction from biometric signals using feature generation module 1. The chaotic sequence results generated by dynamic key generation module 4 based on the feature set can be found in [reference needed]. Figure 7 As shown, the circuit design was completely successful and met expectations during the simulation, proving the feasibility of generating chaotic sequences using feature sets.

[0070] In the dynamic encryption system of this application embodiment, during the operation of the encryption method, the FPGA resource utilization rate is as follows: Figure 8 As shown, the utilization rate of Logic (logic resources) is 24%, the utilization rate of Register (register resources) is 4%, and the utilization rate of BSRAM (block RAM) is 12%. It can be seen that this system significantly reduces computing overhead and power consumption, and can meet the needs of small devices such as battery-powered portable or implantable medical devices.

[0071] The embodiments of this application have at least the following beneficial effects: This application provides a dynamic encryption system based on the RISC-V architecture. The dynamic encryption system integrates a configurable RISC-V processor soft core 3, a dynamic key generation module 4, and a data encryption operation module 5 into a SoC2 (System-on-a-Chip). It features flexible hardware and software configurability and an open-source instruction set, allowing for the customization of encryption instructions according to specific encryption algorithm requirements. Furthermore, the feature extraction step, key generation step, and data encryption step are implemented in the form of hardware circuits, achieving hardware-level acceleration, significantly improving encryption speed, reducing computational overhead and power consumption, and making it suitable for battery-powered portable or implantable medical devices. The feature generation module 1, dynamic key generation module 4, and data encryption operation module 5 call the co-occurrence registers of the processor soft core 3, achieving efficient data interaction, reducing the latency of accessing external memory, and meeting the real-time requirements of diverse application scenarios.

[0072] Understandably, on the one hand, integrating the configurable RISC-V processor soft core 3, dynamic key generation module 4, and data encryption operation module 5 into the SoC2 achieves miniaturization, reduces power consumption, and adapts to the needs of embedded systems, mobile devices, and IoT devices. Furthermore, the dynamic key generation module 4 and data encryption operation module 5 execute custom encryption instructions through dedicated hardware circuits and communicate with the configurable RISC-V processor soft core 3 via the chip's internal high-speed bus, effectively reducing latency, achieving hardware-level acceleration, and improving the real-time performance of encryption processing. On the other hand, the configurable processor soft core 3, using a RISC-V soft core, allows for custom instructions to direct functional modules to complete encryption operations, achieving effective hardware-software collaboration and significantly improving execution efficiency.

[0073] Example 2 This application proposes a dynamic encryption method based on the RISC-V architecture, applied to a dynamic encryption system based on the RISC-V architecture, with reference to... Figure 9 As shown, the method includes: S100, generates a feature set; S200, generating dynamic chaotic sequences based on feature sets; S300 acquires the plaintext data to be encrypted, performs encryption operations on the plaintext data based on a dynamic chaotic sequence, and outputs the encryption operation result.

[0074] When the plaintext data is a continuous data stream, the system periodically or triggerably repeats steps S100 to S300 to achieve dynamic key updates.

[0075] Specifically, in some embodiments of this application, the feature set is generated based on the user's biometric signals.

[0076] Understandably, by generating the initial seed of the chaotic system through the feature set, and generating a dynamic chaotic sequence based on the initial seed, on the one hand, the key generation is closely related to the biometric signal, and has uniqueness and non-replicability; on the other hand, the key is dynamically generated through the chaotic system, and has highly random and unpredictable characteristics, which can resist exhaustive attacks and improve the security of the key, thereby improving the security of the ciphertext result.

[0077] In an optional embodiment, the encryption calculation of the plaintext data to be encrypted based on the dynamic chaotic sequence includes one or any combination of logical AND, shift, and XOR.

[0078] For example, the encryption operation for plaintext data to be encrypted can be an OR-AND operation. Specifically, the plaintext data is XORed bit by bit with a chaotic sequence (keystream) of the same length to produce the ciphertext result. During decryption, the chaotic sequence is XORed with the ciphertext result again to restore the original plaintext data.

[0079] In an optional embodiment, Acquire biometric signals, including the first characteristic signal of the central node and the second characteristic signals of other nodes; For example, the characteristic signals of the central node and other nodes can originate from different parts of the user's body, such as the torso or limbs.

[0080] Specifically, in some embodiments of this application, such as Figure 10 As shown, the biometric signals collected can be collected from the left upper limb, right upper limb, and left lower limb; however, there are no specific restrictions on the location from which the biometric signals can be collected.

[0081] like Figure 11 As shown, generating the feature set includes: identifying representative peaks in the first feature signal and the second feature signal; Extract characteristic parameters related to the essential properties of the signal from representative peaks; Scalar quantization feature parameters; The scalar quantized feature parameters are combined to form a feature set, which includes the first feature set of the first feature signal and the second feature set of the second feature signal.

[0082] For example, in some embodiments of this application, representative peaks in the first feature signal and the second feature signal are identified respectively, that is, representative peaks are identified from the original physiological feature signal as the basis for subsequent feature extraction.

[0083] Specifically, in some embodiments of this application, for the input first feature signal X and second feature signal Y, an adaptive threshold method is used for peak detection. The detection of representative peaks of the first and second feature signals based on a preset algorithm includes: Calculate the local maxima of the first and second characteristic signals; The threshold for peak detection is dynamically adjusted based on the overall amplitude distribution and noise level of the first and second characteristic signals, respectively, in order to filter out the target peak from multiple local maxima. At the same time, the waveform morphology characteristics are combined to assist in the judgment of the target peak, so as to eliminate the interference of noise or false peaks, thereby improving the accuracy of peak detection and anti-interference ability.

[0084] The morphological characteristics of the waveform include the rising slope and / or the peak width. The peak to be detected is the R wave. In electrocardiogram signals, the amplitude of the R wave is usually much higher than that of other waves (such as the P wave and T wave). By analyzing the amplitude statistical characteristics of the signal and setting an appropriate threshold, the R wave peak can be effectively screened out.

[0085] For example, in some embodiments of this application, extracting feature parameters related to the essential characteristics of the signal from each representative peak means extracting feature parameters that can characterize the essential characteristics of the signal from the detected peak and its surrounding signals.

[0086] Characteristic parameters relating to the essential properties of a signal include time-domain features and frequency-domain features. Optionally, time-domain features include one or more of the following: peak amplitude, peak occurrence time, peak half-width at half-maximum (FWHM), and slope changes before and after the peak. Frequency-domain features include frequency components and / or spectral energy distribution. In vibration signal analysis, the fault frequency of equipment can be identified through frequency-domain features.

[0087] For example, in some embodiments of this application, scalar quantization feature parameters refer to converting the extracted continuous feature parameters into discrete scalar values ​​to facilitate subsequent encoding and matching operations.

[0088] Optionally, the scalar quantization feature parameters can be selected using uniform quantization or non-uniform quantization.

[0089] Scalar quantization of feature parameters using uniform quantization involves dividing the range of feature values ​​into multiple intervals at equal intervals, with each interval corresponding to a quantized value. Scalar quantization of feature parameters using non-uniform quantization involves further subdividing the intervals with high probability density based on the probability distribution of the feature values ​​to improve quantization accuracy.

[0090] For example, for peak amplitude characteristics, if the value range is [0, 10], uniform quantization can divide it into 10 intervals, each interval corresponding to a quantization scalar.

[0091] Combining scalar quantized feature parameters to form a feature set refers to combining multiple quantized scalar features into a coding set to form a signal feature representation with a unique identifier.

[0092] Optionally, the feature set formed by combining the scalar quantized feature parameters can be created using any one of binary encoding, Gray code encoding, or a custom encoding rule.

[0093] For example, in some embodiments of this application, binary encoding is used to convert each quantized scalar value into a binary number of a certain number of bits. These binary numbers are then concatenated sequentially to form a long binary encoded string, which serves as the feature encoding set of the signal. Furthermore, the binary encoding is combined with a hash algorithm to map the quantized feature set to a fixed-length hash value, facilitating fast storage and retrieval.

[0094] In an optional embodiment, the key features of the second feature set are set to correspond to the key features of the first feature set, that is, the key features extracted from the second feature set match the key features extracted from the first feature set. For example, if the key features extracted from the first feature set are the R-R interval (the time interval between adjacent R wave peaks), the amplitude and duration of the P wave and T wave, then the key features extracted from the second feature set should also be the R-R interval (the time interval between adjacent R wave peaks), the amplitude and duration of the P wave and T wave, so that the key features of the second feature set correspond to the key features of the first feature set.

[0095] Specifically, in some embodiments of this application, before extracting key features from biometric signals, preprocessing of the biometric signals is required, such as filtering, denoising, and switching between the biometric signals in the spatiotemporal domain using Fast Fourier Transform and Inverse Fast Fourier Transform. After key feature extraction, the key features also need to be normalized and quantized to transform them into a consistent format suitable for chaotic system inputs.

[0096] In an optional embodiment, generating the feature set further includes: matching the first feature set with the second feature set using a preset algorithm, and determining whether the first feature set and the second feature set have similar feature patterns based on the matching results.

[0097] Specifically, in some embodiments of this application, such as Figure 11 As shown, the preset matching algorithm used to match the first feature set and the second feature set is implemented based on the distinct threshold matching.

[0098] The process of matching a first feature set with a second feature set using a preset algorithm and determining whether the first feature set and the second feature set have similar feature patterns based on the matching results includes: setting a reasonable threshold; matching the first feature set with the second feature set to obtain the difference between the first feature set and the second feature set; if the difference is less than or equal to the threshold, then the feature patterns of the first feature set and the second feature set are determined to match; if the difference is greater than the threshold, then the feature patterns of the first feature set and the second feature set are determined to not match.

[0099] The feature patterns of the first feature set and the second feature set are stored in the register only when the feature patterns of the first feature set match those of the second feature set.

[0100] The specific threshold can be adjusted according to the actual application scenario to enhance the flexibility and versatility of use. If the feature pattern accuracy requirement of the feature information is high, the threshold can be lowered; if the feature pattern accuracy requirement of the feature information is low, the threshold can be raised.

[0101] Understandably, the use of a distinct threshold matching mechanism in the verification of feature patterns between the first and second feature sets has strong fault tolerance. By using fuzzy matching, it can tolerate reasonable deviations that occur during biometric collection, thus ensuring the success rate and reliability of key generation.

[0102] In an optional embodiment, refer to Figure 12 As shown, generating dynamic chaotic sequences based on feature sets includes: Construct the encoding function based on the first feature set; A security template is generated based on an encoding function. The security template includes the encoded information of the first feature set and the key used for decoding. Specifically, in some embodiments of this application, taking electrocardiogram (ECG) signals as an example, the central node constructs an encoding function based on a first set of features. This encoding function maps the ECG signal features to a set of parameters, which are used to subsequently generate a security template and serve as key parameters for the chaotic system. The encoding function is then used to generate a security template T, which is then published through a secure channel. The security template contains encoded information based on the central node's ECG features and also carries a key for decoding.

[0103] Construct a decoding function based on the second feature set; The security template is decoded using a decoding function; If the decoding function successfully decodes the secure template, it combines the second feature set with the key to generate the initial seed of the chaotic system. Generate dynamic chaotic sequences based on initial seeds.

[0104] Specifically, in some embodiments of this application, taking electrocardiogram (ECG) signals as an example, other nodes construct decoding functions based on their own second feature sets. These decoding functions are used to decode the received security templates and verify the matching of their own ECG features with those of the central node. The decoding functions are then used to decode the security templates published by the central node. If decoding is successful, it indicates that there is a certain degree of matching between the node's own ECG features and those of the central node, and the error is within the allowable error range. At this point, the key obtained during the decoding process is used, combined with the node's own ECG signal features, to generate a chaotic key seed. This seed serves as the initial value of the chaotic system. Due to individual differences in ECG signals, the chaotic key seeds generated by different nodes are unique.

[0105] The initial seed, usually referring to the initial conditions, is the starting parameter for the evolution of a chaotic system. One of the core characteristics of a chaotic system is its extreme sensitivity to initial conditions; a tiny difference in initial values ​​can lead to a huge difference in the system's output. Utilizing this property, key features can be transformed into initial values ​​for the chaotic system, generating a chaotic sequence as a key.

[0106] More specifically, in some embodiments of this application, after generating the dynamic chaotic sequence, it is also necessary to preprocess and quantize the dynamic chaos to meet the requirements of encryption.

[0107] In the preprocessing, values ​​from the start of chaotic iteration to a preset length or preset number of iterations are removed to eliminate the influence of transient effects and improve the randomness of the chaotic sequence.

[0108] The preset number of iterations can be, for example, 20. That is, the values ​​generated in the first 20 iterations are discarded, while the values ​​from the 21st iteration onwards are retained.

[0109] In quantization, the format of the preprocessed chaotic sequence is transformed.

[0110] For example, commonly used chaotic systems such as the Logistic map or the Tent map, under certain parameters, produce chaotic sequences that are real values. These real value sequences need to be converted into binary or integer sequences, such as by setting a threshold or by amplifying and rounding the real value chaotic sequence.

[0111] Understandably, combining the biometric characteristic of electrocardiogram (ECG) signals with chaotic systems leverages the uniqueness of ECG features and the initial value sensitivity of chaotic systems to achieve secure key generation and distribution, freeing the system from dependence on traditional centralized key management. Furthermore, the decoding function is constructed based on the ECG features of other nodes, adapting to the differences in ECGs among individuals, thus improving system compatibility with different users while ensuring security. In addition, the central node only publishes secure templates and does not directly distribute keys; other nodes generate chaotic key seeds based on their own ECG features and decoding process, achieving decentralized key distribution and reducing the security risks posed by attacks on the central node.

[0112] In an optional embodiment, the method further includes: A dedicated encryption operation instruction is set up. The target address in the co-occurrence register is specified through the dedicated encryption operation instruction. The storage area corresponding to the target address is used as the source operand storage area and the destination operand storage area. The operation is completed sequentially in a single instruction cycle: reading the feature set and dynamic chaotic sequence from the source operand storage area, performing encryption operation, and writing the encryption operation result back to the destination operand storage area.

[0113] Understandably, the encryption operation instructions are custom instructions that work closely with the hardware acceleration module, directly indexing co-occurring registers to achieve a tightly coupled design that significantly improves the performance of the dynamic encryption system. Specifically, reading, encryption operations, and result writing can be directly implemented through registers, improving access speed compared to memory access and effectively increasing instruction execution speed. Furthermore, this design is well-matched with the highly integrated configurable processor soft core, dynamic key generation module, and data encryption operation module into the SoC. By embedding the dynamic key generation module and data encryption operation module as execution units into the processor pipeline, hardware and software coordination is achieved, significantly improving the computational power and speed of encryption operations.

[0114] Specifically, in some embodiments of this application, the processor soft core executes dedicated encryption instructions, instructing the data encryption operation module to read the dynamic chaotic sequence and plaintext data from the symbiotic register window, complete the encryption calculation, and write the ciphertext result back to the register or output it through the peripheral interface.

[0115] Since the technical problem to be solved in this embodiment, the technical solution used to solve the technical problem, and the technical effect achieved are all the same as those in the above-described encryption system, and since the technical solution in the above-described encryption system has already been clearly and completely described, the technical details of the encryption method in this embodiment can be found in the above-described encryption system embodiment 1, and will not be repeated here.

[0116] Those skilled in the art will understand that the modules in the apparatus of the implementation scenario can be distributed within the apparatus of the implementation scenario as described, or they can be located in one or more apparatuses different from this implementation scenario, with corresponding changes. The modules of the above-described implementation scenario can be combined into one module, or they can be further divided into multiple sub-modules.

[0117] The serial numbers in this application are for descriptive purposes only and do not represent the superiority or inferiority of the implementation scenario.

[0118] The above disclosures are only a few specific implementation scenarios of this application. However, this application is not limited to these. Any variations that can be conceived by those skilled in the art should fall within the protection scope of this application.

Claims

1. A dynamic encryption system based on RISC-V architecture, characterized in that, The system comprises: a feature generation module for generating a feature set; a system on chip (SoC) integrated with a configurable RISC-V processor soft core, a dynamic key generation module and a data encryption operation module, the data encryption operation module being connected with the dynamic key generation module and the processor soft core through a system bus, the feature generation module and the data encryption operation module establishing a direct data connection with the processor soft core through a symbiotic register architecture; the dynamic key generation module is configured to generate a dynamic chaotic sequence based on the feature set; the data encryption operation module is configured to obtain to-be-encrypted plaintext data, and perform encryption operation on the to-be-encrypted plaintext data based on the dynamic chaotic sequence and output an encryption operation result.

2. The RISC-V architecture based dynamic encryption system according to claim 1, wherein, The implementation of the symbiotic register architecture comprises: a plurality of symbiotic registers are divided in the RISC-V processor soft core, and the feature generation module directly writes the generated feature set into a designated symbiotic register.

3. The RISC-V architecture based dynamic encryption system according to claim 2, wherein, The data encryption operation module directly reads the feature set and the dynamic chaotic sequence from the symbiotic register as operation numbers of the encryption operation.

4. The RISC-V architecture based dynamic encryption system according to claim 3, wherein, The plurality of symbiotic registers comprise a first register, a second register and a third register; the feature set is directly written into the first register, the dynamic chaotic sequence is directly written into the second register, and the encryption operation result is directly written into the third register.

5. The RISC-V architecture based dynamic encryption system according to any one of claims 1 to 4, characterized in that, The instruction set of the RISC-V processor soft core comprises a special encryption operation instruction, the special encryption operation instruction can specify the symbiotic register address as a source operation number and a destination operation number, and complete data reading, encryption operation and result writing in a single instruction cycle.

6. The RISC-V architecture based dynamic encryption system according to claim 5, wherein, The system further comprises: a biometric feature sensing module for collecting a biometric feature signal of a user; the feature generation module is connected with the biometric feature sensing module and configured to generate a feature set based on the biometric feature signal.

7. A dynamic encryption method based on RISC-V architecture, characterized in that, The method is applied to a dynamic encryption system based on a RISC-V architecture, and the method comprises: generating a feature set; generating a dynamic chaotic sequence based on the feature set; obtaining to-be-encrypted plaintext data, and performing encryption operation on the to-be-encrypted plaintext data based on the dynamic chaotic sequence and outputting an encryption operation result.

8. The dynamic encryption method based on RISC-V architecture according to claim 7, characterized in that, The generating of the feature set comprises: obtaining a biometric feature signal, including a first feature signal of a central node and a second feature signal of other nodes; identifying representative wave crests in the first feature signal and the second feature signal; extracting feature parameters related to the nature of the signal from the representative wave crests; scalar quantizing the feature parameters; combining the scalar quantized feature parameters to form the feature set, the feature set comprising a first feature set of the first feature signal and a second feature set of the second feature signal.

9. The dynamic encryption method based on RISC-V architecture according to claim 8, characterized in that, The generating of the dynamic chaotic sequence based on the feature set comprises: constructing an encoding function according to the first feature set; generating a security template based on the encoding function, the security template comprising encoding information of the first feature set and a key for decoding; constructing a decoding function according to the second feature set; decoding the security template by the decoding function; if the decoding function successfully decodes the security template, combining the second feature set and the key to generate an initial seed of a chaotic system; generating a dynamic chaotic sequence based on the initial seed.

10. The dynamic encryption method based on RISC-V architecture according to any one of claims 7 to 9, characterized in that, The method further includes: setting a special encryption operation instruction, specifying a target address in a symbiotic register through the special encryption operation instruction, taking a storage area corresponding to the target address as a source operand storage area and a destination operand storage area, and sequentially completing, in a single instruction cycle, reading the feature set and the dynamic chaotic sequence from the source operand storage area, performing an encryption operation, and writing the encryption operation result back to the destination operand storage area.

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