Parallel detection system and parallel detection method of battery alternating current impedance spectroscopy

Abstract

The invention discloses a parallel detection system for a battery alternating current impedance spectrum. The parallel detection system comprises a microcontroller, a plurality of impedance detection chips and a plurality of current control sub-circuits, the current control sub-circuit and the battery to be detected form an excitation loop, and the impedance detection chip is in signal connection with the current control sub-circuit; the plurality of impedance detection chips are sequentially connected in series in a differential communication manner through the daisy chain topology; the first impedance detection chip is in serial communication connection with the microcontroller. On the other hand, the invention discloses a parallel detection method for the alternating-current impedance spectrum of the battery. The parallel detection method comprises the steps of circuit initialization, parameter configuration, synchronous excitation starting, battery response signal collection, same-frequency signal component extraction, complex impedance calculation, data summarization and alternating-current impedance spectrum generation. The frequency division multiplexing (FDM) technology is adopted, excitation and detection of multiple frequency points are carried out at the same time, the EIS measurement time is shortened from the minute level to the second level or even the millisecond level, and the method is particularly suitable for rapid full detection of a battery production line.

Description

Technical Field

[0001] This invention relates to the field of battery testing technology, and in particular to a parallel detection system and method for battery AC impedance spectroscopy. Background Technology

[0002] Electrochemical impedance spectroscopy (EIS) is an important tool for analyzing the state of health (SOH), state of charge (SOC), and internal chemical reaction mechanisms of batteries. Traditional EIS testing equipment, such as electrochemical workstations, is expensive and bulky, making it difficult to apply to online testing on battery production lines, on-site repair, or embedded battery management systems. Although some simplified EIS testing schemes exist, such as using a single microprocessor (MCU) to generate excitation and analyze the response, this method requires high MCU performance, complex software algorithms, and is slow (requiring sequential scanning of different frequencies), failing to meet the needs of rapid testing. Therefore, providing a low-cost, high-efficiency, easy-to-implement, and flexibly adaptable EIS testing scheme for different batteries is an urgent problem to be solved. Summary of the Invention

[0003] In view of this, the purpose of this invention is to simultaneously excite the battery using multiple excitation circuits operating under excitation signals at different frequencies, and to collect the battery's response voltage signal. The signal components are extracted according to the frequency of each excitation signal, the complex impedance is calculated and summarized, and the AC impedance spectrum is rapidly generated through non-scanning multi-channel synchronous detection. This results in a low-cost, high-efficiency, easy-to-implement EIS detection scheme that can be flexibly adapted to different batteries.

[0004] To achieve the above objectives, the present invention provides a parallel detection system for the AC impedance spectrum of a battery, comprising a microcontroller, multiple impedance detection chips, and multiple current control sub-circuits.

[0005] The number of current control sub-circuits corresponds to the impedance detection chip. The current control sub-circuit includes a gating load unit and a frequency modulation unit. The gating load unit includes a power resistor, and the frequency modulation unit includes an excitation loop switch. The gating load unit and the frequency modulation unit are used to form an excitation loop with the battery under test.

[0006] The impedance detection chip is used to: control the corresponding excitation circuit switch by sending an excitation signal of a preset frequency, collect the response voltage signal across the battery under test, extract the signal component in the response voltage signal corresponding to the preset frequency, and calculate the complex impedance data corresponding to the preset frequency; the impedance detection chip and the corresponding control sub-circuit are connected by signals.

[0007] The multiple impedance detection chips are connected in series via differential communication through a daisy-chain topology.

[0008] The plurality of impedance detection chips includes a first impedance detection chip, and the first impedance detection chip and the microcontroller are connected by an SPI communication connection.

[0009] The microcontroller is used to send configuration parameters to the impedance detection chip and collect the complex impedance data calculated by the impedance detection chip to form the AC impedance spectrum of the battery under test; the configuration parameters include the preset frequency of the impedance detection chip, and the preset frequency of each impedance detection chip is different.

[0010] Preferably, the gating load unit includes multiple parallel branches, each of the parallel branches including a gating control switch and a power resistor; in the gating load unit of a current control sub-circuit, each parallel branch is provided with a power resistor of different resistance value; the impedance detection chip is also used to: control the gating control switch by sending a gating signal, so that one of the parallel branches is connected to the excitation circuit.

[0011] Preferably, the current control sub-circuit further includes a gating logic circuit, which includes a first multiplexer unit, a multiplexer unit, and a second multiplexer unit. The first multiplexer unit and the multiplexer unit are electrically connected. The multiplexer unit and the second multiplexer unit are also electrically connected. The gating logic circuit is used for decoding the gating signal.

[0012] Preferably, the configuration parameters further include a startup time; the startup time is used to enable each impedance detection chip to synchronously start sending excitation signals.

[0013] Preferably, the impedance detection chip is provided with a multiplexed interface and a differential communication output interface; the multiplexed interface can be configured as either an SPI communication interface or a differential communication input interface; the multiplexed interface of the first impedance detection chip is configured as an SPI communication interface, and the multiplexed interfaces of the impedance detection chips other than the first impedance detection chip are configured as differential communication input interfaces; in every two adjacent impedance detection chips in the daisy-chain topology, the differential communication output interface of the preceding impedance detection chip and the differential communication input interface of the following impedance detection chip are connected.

[0014] Preferably, the impedance detection chip is provided with a diagnostic signal interface, which is electrically connected to the circuit node between the selected load unit and the frequency modulation unit in the corresponding current control sub-circuit. The diagnostic signal interface is used to determine whether there is a fault in the current control sub-circuit based on the voltage change at the circuit node.

[0015] Preferably, in each current control subunit, the load selection unit is provided with four parallel branches; the selection signal includes two high and low level signals.

[0016] Another aspect of the present invention provides a parallel detection method for the AC impedance spectrum of a battery, comprising the following steps:

[0017] Circuit initialization: The circuit initialization includes connecting the battery under test to multiple parallel excitation loops. Each excitation loop includes an excitation loop switch and a power resistor. Each excitation loop is frequency controlled by a corresponding impedance detection chip. Each impedance detection chip is electrically connected to both ends of the battery under test. Each impedance detection chip is connected sequentially through differential communication to form a daisy-chain topology network. The impedance detection chip located at one end of the daisy-chain topology network is serially connected to a microcontroller.

[0018] Parameter configuration: The microcontroller sends configuration parameters to enable each impedance detection chip to use different preset frequency excitation signals to control the frequency of the excitation circuit;

[0019] Synchronous excitation: Each impedance detection chip simultaneously begins to send excitation signals to the excitation circuit, controlling the corresponding opening and closing of each excitation circuit, acting on the battery under test, and generating a multi-frequency composite excitation current;

[0020] Signal acquisition: Each impedance detection chip simultaneously acquires the response voltage signal generated across the two ends of the battery under test;

[0021] Calculate complex impedance: Each impedance detection chip extracts the signal component corresponding to the preset frequency from the response voltage signal, and calculates the complex impedance data at the preset frequency based on the signal component and the corresponding power resistor value;

[0022] Data aggregation: Each impedance detection chip aggregates the complex impedance data to the microcontroller through a daisy-chain topology network and serial communication connection;

[0023] In addition, the AC impedance spectrum is generated: the microcontroller generates the AC impedance spectrum of the battery under test based on the aggregated complex impedance data.

[0024] Preferably, during the signal acquisition process, the impedance detection chip determines whether an open-circuit or short-circuit fault has occurred in the excitation circuit by monitoring the voltage change of the circuit node between the corresponding excitation circuit switch and the power resistor.

[0025] Preferably, the battery under test can be connected to the aforementioned parallel detection system to implement this method.

[0026] In summary, the present invention has the following beneficial effects:

[0027] (1) The present invention uses frequency division multiplexing (FDM) technology, which allows excitation and detection at multiple frequency points to be performed simultaneously, reducing the EIS measurement time from minutes to seconds or even milliseconds, making it particularly suitable for rapid full inspection of battery production lines;

[0028] (2) The daisy-chain topology communication network of the present invention greatly saves the hardware interface resources of the MCU (only one SPI port is needed), the wiring is simple, and more detection channels can be easily expanded by setting more chips, and the cost can be greatly reduced; and the MCU only needs to perform simple communication control, without having to undertake complex signal generation and calculation tasks, which reduces the difficulty of software development;

[0029] (3) This invention uses MCU to unify timing and precisely control the start time of the excitation signal of each chip, avoiding synchronization errors caused by internal clock deviation of the chip, ensuring the phase accuracy of parallel measurement data, and laying the foundation for accurate EIS analysis.

[0030] (4) The programmable multiple gating positions of the present invention provide a mechanism for different excitation currents, which enables the system to intelligently adapt to different battery models (avoiding over-excitation of small batteries and under-excitation of large batteries) and different frequency band measurement requirements (high frequency small current to prevent interference, low frequency large current to improve signal), significantly improving the dynamic range and signal-to-noise ratio of the measurement, and enhancing the versatility and reliability of the system.

[0031] (5) The hardware diagnostic circuit of the present invention (by monitoring the level reversal between the power resistor and the N-channel field-effect transistor) can determine whether the current path is normal in real time at the hardware level, thereby improving the system's fault self-detection capability and reliability. Attached Figure Description

[0032] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0033] Figure 1 This is a schematic diagram of the circuit structure according to an embodiment of the present invention;

[0034] Figure 2 This is a chip pin configuration diagram according to an embodiment of the present invention;

[0035] Figure 3 This is a block diagram of the current control sub-circuit structure according to an embodiment of the present invention; Figure 4 This is a flowchart of a method according to an embodiment of the present invention. Detailed Implementation

[0036] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0037] Figure 1 The schematic diagram of the parallel detection system of this embodiment is shown, including a microcontroller 1 (MCU), n impedance detection chips 2 and n current control sub-circuits 3, where n is a positive integer greater than or equal to 2;

[0038] In this embodiment, the microcontroller 1 is a microcontroller based on the ARM Cortex-M3 core;

[0039] The n impedance detection chips 2 include a first impedance detection chip 2a, which is connected to the microcontroller 1 via SPI communication. The n impedance detection chips 2 are connected in series via differential communication (DIO) to form a daisy-chain topology. The composite communication network of SPI communication + differential communication daisy-chain topology formed by the impedance detection chips 2 greatly saves the hardware interface resources of the MCU (only one SPI interface of the MCU is needed), the wiring is simple, and the differential communication has stronger noise immunity and is more conducive to the series expansion of more detection channels.

[0040] The current control sub-circuit 3 and the impedance detection chip 2 are in one-to-one correspondence, and multiple signal lines are electrically connected between them; each current control sub-circuit 3 is provided with an excitation positive terminal 36 and an excitation negative terminal 37, which are electrically connected to the positive and negative electrodes of the battery under test 4, respectively; each impedance detection chip 2 is provided with a sampling positive pin VCH and a sampling negative pin VCL, which are electrically connected to the positive and negative electrodes of the battery under test 4, respectively.

[0041] When detecting the AC impedance spectrum of the battery under test 4, the impedance detection chip 2 sends a square wave excitation signal of a preset frequency to the corresponding current control sub-circuit 3. The current control sub-circuit 3 controls the connection and disconnection of the corresponding excitation circuit according to the excitation signal, thereby generating a load that jumps at the corresponding frequency. The response signals generated by the battery under test 4 under the action of the excitation circuits of each current control sub-circuit 3 are collected by each impedance detection chip 2, and the component of the response signal with the same frequency as the excitation signal generated by itself is extracted to further calculate the impedance at that frequency point. Each impedance detection chip 2 starts detection simultaneously, and the analysis results are summarized to the microcontroller 1 through the communication network to obtain the AC impedance spectrum data of the battery under test 4. The internal structure of the impedance detection chip 2 can be obtained by those skilled in the art by referring to other relevant technical documents, and is omitted here.

[0042] Figure 2 The pin layout of the impedance detection chip 2 in this embodiment is shown. The impedance detection chip 2 is provided with a multiplexed interface SPI / DIO-BOT, a differential communication output interface DIO-BOT, a positive power supply pin Vbat, a positive acquisition pin VCH, a strobe signal interface GPIO1 / GPIO2, a diagnostic signal pin VDR, a frequency signal output pin VSW, a negative power supply pin VSS, and a negative acquisition pin VCL. The specific functions of each interface and pin are as follows:

[0043] Vbat, VSS: Positive and negative power supply pins of the chip;

[0044] SPI / DIO-TOP: Since both the SPI communication protocol and the differential communication protocol can use a four-wire transmission interface, for the first impedance detection chip 2a, this interface is configured as an SPI slave interface, which communicates directly with the SPI master interface of the microcontroller 1; for the remaining impedance detection chips 2, this interface is configured as the input terminal of the differential communication interface, which is used to connect to the previous chip in the daisy-chain topology network.

[0045] DIO-BOT: This interface is the output of the differential communication interface, used to connect to the next chip in a daisy-chain topology network. Since the differential communication connection between each impedance detection chip 2 undertakes the functions of sending configuration parameters and summarizing complex impedance data during the detection process, although the interface name distinguishes between input and output terminals, data transmission can be performed in both directions. Through this hybrid topology of "SPI + daisy chain", the microcontroller 1 only needs one SPI interface to control any number of chips, which is simple in wiring and easy to expand.

[0046] VCH and VCL are the positive and negative input pins for acquiring signals, respectively. They are directly connected to the two ends of the battery under test 4 and are used to acquire the response voltage signal of the battery under test 4 with high precision.

[0047] GPIO1 / GPIO2: Two general-purpose input / output pins, configured as output mode in this embodiment. The combination of high and low levels of the output is used as a strobe signal to control the selection of different power resistor channels in the current control sub-circuit 3.

[0048] VDR: Diagnostic signal pin, used to monitor the operating status of current control sub-circuit 3;

[0049] VSW: Frequency signal output pin, used to output a square wave excitation signal of a specific frequency as the original frequency source of the excitation circuit.

[0050] Figure 3The structure of the current control sub-circuit 3 in this embodiment is shown, including a gating logic circuit, a gating load unit 34, and a frequency modulation unit 35. The excitation positive terminal 36, the gating load unit 34, the frequency modulation unit 35, and the excitation negative terminal 37 are connected in series. When the battery under test 4 is connected to the system, the gating load unit 34, the frequency modulation unit 35, and the battery under test 4 form an excitation loop. The gating load unit 34 includes four parallel branches, each of which is equipped with a P-type field-effect transistor (PMOS) and a power resistor. The power resistor is connected in series with the drain of the PMOS. The gate of the PMOS is electrically connected to the gating logic circuit and is controlled by it for gating. The power of the four parallel branches is... Different resistor values ​​allow different power resistors to be connected to the excitation circuit when different parallel branches are selected, generating excitation currents of different magnitudes. This enables the function of adaptively adjusting the excitation amplitude according to battery type and frequency, optimizing the signal-to-noise ratio at different frequency points. The frequency modulation unit 35 includes an N-type field-effect transistor (NMOS) as an excitation circuit switch. The gate of the NMOS is driven and controlled by the excitation signal output from the frequency signal output pin VSW of the impedance detection chip 2. When the PMOS and power resistor of a certain parallel branch are selected, and the NMOS switches under the drive of the excitation signal, an AC excitation current of corresponding frequency and amplitude is generated in the excitation circuit.

[0051] The gating logic circuit receives the gating signal output from the gating signal interface GPIO1 / GPIO2 of the impedance detection chip 2 and decodes it into a set of levels to control the gating load unit 34. At any given time, only one PMOS transistor is selected and turned on, while the others are turned off. Specifically, the gating logic circuit includes a two-way NOT gate unit 31, a four-way AND gate unit 32, and a four-way NOT gate unit 33. The two gating signals are set as P1 and P2. The two-way NOT gate unit 31 receives P1 and P2, inverts them to ¬P1 and ¬P2, and transmits them to the four-way AND gate unit 32. The four-way AND gate unit receives P1, P2, ¬P1, and ¬P2, and performs an AND operation on them to obtain P1&P2, (¬P1)&P2, P1&(¬P2), and (¬P1)&P2. The signal is transmitted to the four-way NOT gate unit 33. At this time, the four signals are at the "three low and one high" level. The four-way NOT gate unit 33 receives the "three low and one high" level and inverts it to the "three high and one low" level, which is used to control the selection of the load unit 34. At this time, the parallel branch where the PMOS corresponding to the low level is located is selected and connected to the excitation circuit, while the other three parallel branches are not connected to the excitation circuit. Different combinations of high and low levels of P1 and P2 correspond to different control signals that are low and active after the above decoding operation.

[0052] The circuit node between the selected load unit 34 and the frequency modulation unit 35 is electrically connected to the diagnostic signal pin VDR of the impedance detection chip 2 to provide a diagnostic signal. When the circuit is working normally, the level of this circuit node will change high or low as the NMOS is turned on and off. If the level of this circuit node remains at a high or low level, the impedance detection chip 2 can determine that the current control circuit 3 has an open circuit or short circuit fault, realizing hardware-level real-time diagnosis.

[0053] like Figure 4 As shown, the AC impedance spectroscopy detection method for the battery 4 under test in this embodiment includes the following steps:

[0054] S1: Circuit initialization: according to... Figure 1 The circuit diagram shown completes the circuit connection and connects to the battery under test 4; the first impedance detection chip 2a and the microcontroller 1 are connected in serial communication; n impedance detection chips 2 are connected in series in a daisy-chain topology through differential communication to form a high noise immunity communication network; the microcontroller 1 assigns a unique identification ID to each impedance detection chip in the daisy-chain topology;

[0055] S2: Parameter Configuration: Then, microcontroller 1 sends configuration parameters to each chip, including configuration frequency, gating signal configuration code, and start timestamp. In a preferred embodiment, taking n = 5 as an example, the five impedance detection chips 2 can be configured as follows: ① Frequency 1 kHz, start time T+10ms (T is the time when microcontroller 1 sends the configuration parameters), gating a small current channel (corresponding to a larger power resistor); ② Frequency 100 Hz, start time T+10ms, gating a medium current channel; ③ Frequency 10 Hz, start time T+10ms, gating a medium current channel; ④ Frequency 1 Hz, start time T+10ms, gating a medium current channel; ⑤ Frequency 0.1 Hz, start time T+10ms, gating a large current channel (corresponding to a smaller power resistor). Configuring a small current channel at high frequencies can reduce signal interference, while configuring a large current channel at low frequencies can improve signal strength.

[0056] S3: Synchronous excitation start: Upon reaching the preset start time, each impedance detection chip 2 sends an excitation signal in strict synchronization. The gating load unit 34 connects the corresponding parallel circuit to the excitation circuit according to the gating signal. All excitation circuits jointly excite the battery under test 4, thereby causing the superimposed current of multiple AC excitation currents with different frequencies and amplitudes to flow through the battery under test 4. This synchronization and the current magnitude that can be adjusted by the load resistance ensure that high-quality measurement data can be obtained throughout the entire frequency range.

[0057] S4: Signal acquisition: Each impedance detection chip 2 simultaneously acquires the response voltage signal across the two ends of the battery under test 4;

[0058] S5: Calculate complex impedance: Each impedance detection chip 2 extracts the signal component with the same frequency as its own excitation signal from the response voltage signal of the mixed frequency according to the internal algorithm, and calculates the complex impedance data at that frequency point.

[0059] S6: Data summarization: Each impedance detection chip 2 transmits the calculated complex impedance data back to the microcontroller 1 through the communication network;

[0060] S7: Generate AC impedance spectrum: Microcontroller 1 summarizes the complex impedance data at each frequency point to form a complete AC impedance spectrum of the battery under test 4.

[0061] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A parallel detection system for the AC impedance spectrum of a battery, characterized in that, It includes a microcontroller, multiple impedance detection chips, and multiple current control sub-circuits; The number of current control sub-circuits corresponds to the impedance detection chip. The current control sub-circuit includes a gating load unit and a frequency modulation unit. The gating load unit includes a power resistor, and the frequency modulation unit includes an excitation loop switch. The gating load unit and the frequency modulation unit are used to form an excitation loop with the battery under test. The impedance detection chip is used to: control the corresponding excitation circuit switch by sending an excitation signal of a preset frequency, collect the response voltage signal across the battery under test, extract the signal component in the response voltage signal corresponding to the preset frequency, and calculate the complex impedance data corresponding to the preset frequency; the impedance detection chip and the corresponding control sub-circuit are connected by signals. The multiple impedance detection chips are connected in series via differential communication through a daisy-chain topology. The plurality of impedance detection chips includes a first impedance detection chip, and the first impedance detection chip and the microcontroller are connected by an SPI communication connection. The microcontroller is used to send configuration parameters to the impedance detection chip and collect the complex impedance data calculated by the impedance detection chip to form the AC impedance spectrum of the battery under test; the configuration parameters include the preset frequency of the impedance detection chip, and the preset frequency of each impedance detection chip is different.

2. The parallel detection system according to claim 1, characterized in that, The selected load unit includes multiple parallel branches, each of which includes a selection control switch and a power resistor; in the selected load unit of a current control sub-circuit, each parallel branch is provided with a power resistor of different resistance value; the impedance detection chip is also used to: control the selection control switch by sending a selection signal, so that one of the parallel branches is connected to the excitation circuit.

3. The parallel detection system according to claim 2, characterized in that, The current control sub-circuit further includes a gating logic circuit, which includes a first multiplexer unit, a multiplexer unit, and a second multiplexer unit. The first multiplexer unit and the multiplexer unit are electrically connected. The multiplexer unit and the second multiplexer unit are also electrically connected. The gating logic circuit is used for decoding the gating signal.

4. The parallel detection system according to claim 1, characterized in that, The configuration parameters also include startup time; the startup time is used to enable each impedance detection chip to synchronously start sending excitation signals.

5. The parallel detection system according to claim 1, characterized in that, The impedance detection chip is provided with a multiplexed interface and a differential communication output interface; the multiplexed interface can be configured as either an SPI communication interface or a differential communication input interface; the multiplexed interface of the first impedance detection chip is configured as an SPI communication interface, and the multiplexed interfaces of the impedance detection chips other than the first impedance detection chip are configured as differential communication input interfaces; in every two adjacent impedance detection chips in the daisy-chain topology, the differential communication output interface of the preceding impedance detection chip and the differential communication input interface of the following impedance detection chip are connected.

6. The parallel detection system according to claim 1, characterized in that, The impedance detection chip is provided with a diagnostic signal interface, which is electrically connected to the circuit node between the selected load unit and the frequency modulation unit in the corresponding current control sub-circuit. The diagnostic signal interface is used to determine whether there is a fault in the current control sub-circuit based on the voltage change at the circuit node.

7. The parallel detection system according to claim 2, characterized in that, In each of the current control subunits, the load selection unit is provided with four parallel branches; the selection signal includes two high and low level signals.

8. A parallel detection method for the AC impedance spectrum of a battery, characterized in that, Includes the following steps: Circuit initialization: The circuit initialization includes connecting the battery under test to multiple parallel excitation loops. Each excitation loop includes an excitation loop switch and a power resistor. Each excitation loop is frequency controlled by a corresponding impedance detection chip. Each impedance detection chip is electrically connected to both ends of the battery under test. Each impedance detection chip is connected sequentially through differential communication to form a daisy-chain topology network. The impedance detection chip located at one end of the daisy-chain topology network is serially connected to a microcontroller. Parameter configuration: The microcontroller sends configuration parameters to enable each impedance detection chip to use different preset frequency excitation signals to control the frequency of the excitation circuit; Synchronous excitation: Each impedance detection chip simultaneously begins to send excitation signals to the excitation circuit, controlling the corresponding opening and closing of each excitation circuit, acting on the battery under test, and generating a multi-frequency composite excitation current; Signal acquisition: Each impedance detection chip simultaneously acquires the response voltage signal generated across the two ends of the battery under test; Calculate complex impedance: Each impedance detection chip extracts the signal component corresponding to the preset frequency from the response voltage signal, and calculates the complex impedance data at the preset frequency based on the signal component and the corresponding power resistor value; Data aggregation: Each impedance detection chip aggregates the complex impedance data to the microcontroller through a daisy-chain topology network and serial communication connection; In addition, the AC impedance spectrum is generated: the microcontroller generates the AC impedance spectrum of the battery under test based on the aggregated complex impedance data.

9. The parallel detection method according to claim 8, characterized in that, During the signal acquisition process, the impedance detection chip determines whether there is an open circuit or short circuit fault in the excitation circuit by monitoring the voltage change of the circuit node between the corresponding excitation circuit switch and the power resistor.

10. The parallel detection method according to claim 8, characterized in that, During circuit initialization, the battery under test is connected to the parallel detection system as described in any one of claims 1 to 7.

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