Multi-queue task efficient interaction method and system of multi-core architecture
By configuring independent storage space and hardware acceleration units for each CPU core to manage task interaction, the problems of low task interaction efficiency and lock contention in multi-core processor architecture are solved, achieving efficient and low-latency task processing, which is suitable for network packet processing and data center computing.
Patent Information
- Application Number
- CN202511804721.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-03
- Publication Date
- 2026-03-20
AI Technical Summary
In multi-core processor architectures, the task interaction efficiency between CPU cores and hardware acceleration units is low, and performance bottlenecks are generated when multiple cores compete for the same queue, resulting in a decrease in CPU processing performance.
Each CPU core is configured with independent storage space, and task interaction is managed through hardware acceleration units to reduce system bus access. Batch processing and status write-back mechanisms are adopted to avoid lock contention.
It improves task interaction efficiency, reduces CPU core waiting time, enhances system parallel processing capabilities and data throughput, solves lock contention issues, and is suitable for network packet processing and data center computing with stringent performance requirements.
Smart Images
Figure CN121704973A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of task interaction technology, and in particular to a method and system for efficient interaction of multi-queue tasks with a multi-core architecture. Background Technology
[0002] With the continuous development of integrated circuit technology, multi-core processor architecture has become the mainstream solution for improving the performance of computing systems.
[0003] In collaborative computing scenarios involving CPU cores and hardware acceleration units, the interaction efficiency of tasks (such as network packet descriptors, computation requests and results from acceleration units) directly affects the overall system performance. In existing technologies, CPU cores need to directly manage the production and consumption pointers of each queue, requiring frequent reading and writing of hardware states, which leads to lower CPU core processing performance. Furthermore, when multiple CPU cores compete for the same queue, locking is required to control the queue, resulting in performance bottlenecks caused by resource contention between CPU cores. Summary of the Invention
[0004] The purpose of this invention is to provide a method and system for efficient interaction of multi-queue tasks in a multi-core architecture, which improves the task interaction efficiency between the CPU core and the hardware acceleration unit, avoids the delay caused by the CPU sending and receiving tasks from the hardware acceleration unit through the system interconnect bus, thus affecting the CPU's processing performance, and solves the lock contention problem of queues in multi-core mode.
[0005] To achieve the above objectives, this invention provides an efficient interaction method for multi-queue tasks in a multi-core architecture, comprising the following steps: Each CPU core is configured with a directly accessible storage space that does not pass through the system bus; Multiple CPU cores issue task receive instructions or task send instructions; The hardware acceleration unit receives task sending instructions or task receiving instructions from multiple CPU cores. If it is a task receiving instruction, the hardware acceleration unit and the CPU core work together to execute the corresponding task receiving process; If it is a task sending instruction, the hardware acceleration unit and the CPU core work together to execute the corresponding task sending process.
[0006] The storage space is either a CPU cache or a dedicated RAM space.
[0007] Specifically, in the task receiving instruction, where the hardware acceleration unit and the CPU core collaboratively execute the corresponding task receiving process, the method includes: The hardware acceleration unit retrieves tasks from the queue specified by the CPU core and moves the tasks to the memory space specified by the CPU core; The hardware acceleration unit writes the actual number of tasks to be moved to a fixed address in the storage space; The CPU core retrieves the actual number of tasks to be moved from a fixed address in the storage space, and then retrieves the tasks in the storage space based on the actual number of tasks moved, thus completing the task reception.
[0008] Specifically, in the task sending instruction, where the hardware acceleration unit and the CPU core collaboratively execute the corresponding task sending process, the method includes: The hardware acceleration unit retrieves tasks from the memory space specified by the CPU core and writes the tasks into the queue specified by the CPU core; The hardware acceleration unit writes the task transfer completion status to a fixed address in the storage space; The CPU core retrieves the task transfer completion status from a fixed address in the storage space and completes the task transmission.
[0009] The task receiving instruction includes the queue number of the task queue that the CPU core is ready to acquire, the number of tasks to acquire, and the destination for task relocation by the hardware acceleration unit, which is the address of the storage space.
[0010] The hardware acceleration unit receives the task receiving instruction from the CPU core and reads the task from the corresponding task queue according to the task queue number in the instruction. When the number of tasks in the task queue is less than the number of tasks the CPU core is ready to receive, all tasks in the queue are read and sent. Otherwise, tasks are read and sent according to the number of tasks the CPU core is ready to receive.
[0011] On the other hand, the present invention also includes a multi-core architecture multi-queue task high-efficiency interaction system, including multiple CPU cores, hardware acceleration units and storage modules; Multiple CPU cores: used to issue task sending instructions or task receiving instructions to the hardware acceleration unit; Hardware acceleration unit: In response to task receiving instructions, it retrieves tasks from the designated queue and moves them to the memory space designated by the CPU core, and writes back the actual number of tasks moved to a fixed address in the memory space; In response to task sending instructions, it retrieves tasks from the memory space designated by the CPU core and writes them to the designated queue, and writes back the task moving completion status to a fixed address in the memory space. Storage module: Provides each CPU core with independent storage space that is not directly accessible through the system bus.
[0012] This invention discloses a method and system for efficient interaction of multi-queue tasks in a multi-core architecture. By configuring each CPU core with a local direct-access storage space that does not require traversing the system bus, the operation that originally required frequent access to remote hardware queues via the system bus is transformed into fast access to the local storage space. The hardware acceleration unit centrally handles the cross-domain data transfer, thereby significantly reducing the CPU core's waiting time and improving task interaction efficiency. Since the CPU core no longer directly manages and maintains the hardware queue's production / consumption pointers, all access requests to the hardware queue are uniformly received and arbitrated by the hardware acceleration unit. Even if multiple CPU cores concurrently access the same task queue, there is no need for coordination through software lock mechanisms, significantly improving the parallel processing capability of the multi-core system. A CPU core can continuously write multiple tasks into its local storage space in batches and then notify the hardware acceleration unit to perform centralized transfer with a single instruction; similarly, it can also request to retrieve tasks in batches with a single instruction. This batch processing mode reduces the number of instruction interactions, further reducing overhead and increasing data throughput. By using a hardware acceleration unit to write back the task transfer status (such as completion flags and the actual number of tasks) to a fixed address in the CPU core's local storage space, and having the CPU core poll and detect this, a state synchronization method with extremely low overhead and no need for complex interrupt mechanisms is achieved, ensuring the smooth completion of the process.
[0013] In summary, this invention, through its innovative architecture, liberates the CPU core from cumbersome queue management and high-frequency small-data-volume bus access, achieving efficient task interaction with low latency, high throughput, and lock-free contention. It is suitable for scenarios with stringent performance requirements, such as network packet processing and data center computing. Attached Figure Description
[0014] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below.
[0015] Figure 1 This is a flowchart of the efficient interaction method for multi-queue tasks in a multi-core architecture according to the present invention.
[0016] Figure 2 This is a schematic flowchart illustrating the task receiving process performed collaboratively by the hardware acceleration unit and the CPU core according to the present invention.
[0017] Figure 3 This is a schematic diagram of the task sending process in which the hardware acceleration unit and the CPU core of the present invention work together.
[0018] Figure 4 This is a schematic diagram of the structure of the multi-core architecture multi-queue task high-efficiency interaction system of the present invention.
[0019] Figure 5 This is a schematic diagram of the data structure in the storage module when the CPU core sends a task according to the present invention.
[0020] Figure 6 This is a schematic diagram of the data structure in the storage module when the CPU core receives a task according to the present invention.
[0021] In the diagram: 101 - CPU core, 102 - Hardware acceleration unit, 103 - Storage module. Detailed Implementation
[0022] The embodiments of the present invention are described in detail below. Examples of the embodiments are shown in the accompanying drawings. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present invention, but should not be construed as limiting the present invention.
[0023] Please see Figures 1 to 3 ,in Figure 1 This is a flowchart of an efficient interaction method for multi-queue tasks in a multi-core architecture. Figure 2 This is a flowchart illustrating the task receiving process performed collaboratively by the hardware acceleration unit and the CPU core. Figure 3 This is a flowchart illustrating the task sending process in which the hardware acceleration unit and the CPU core work together to execute the corresponding task.
[0024] This invention provides an efficient interaction method for multi-queue tasks in a multi-core architecture, comprising the following steps: S1: Configure a directly accessible storage space for each CPU core, which does not pass through the system bus.
[0025] Specifically, the storage space is a CPU cache or a dedicated RAM space.
[0026] In this embodiment, in order to improve the interaction efficiency between the CPU core and the hardware acceleration unit and reduce the latency overhead of CPU core read and write tasks, a storage space is allocated for each CPU core that can be directly accessed by the CPU core without going through the system bus. This space can be the CPU cache or an independent RAM space.
[0027] S2: Multiple CPU cores issue task receive instructions or task send instructions.
[0028] Specifically, the task sending instruction includes the task storage address and the number of tasks, and reads all task data from the storage space; the task receiving instruction includes the queue number of the task queue that the CPU core is ready to acquire, the number of tasks to acquire, and the destination for the task relocation that the hardware acceleration unit needs to perform, the destination being the address of the storage space.
[0029] In this embodiment, when performing task interaction, the CPU core generates corresponding instructions based on the operation type. When it needs to submit a task to the hardware acceleration unit, the CPU core generates a task sending instruction; when it needs to retrieve a task from the hardware acceleration unit, the CPU core generates a task receiving instruction.
[0030] S3: The hardware acceleration unit receives task sending instructions or task receiving instructions from multiple CPU cores.
[0031] In this embodiment, the hardware acceleration unit receives instruction requests from each CPU core through its instruction interface; since multiple CPU cores may initiate access requests simultaneously, the hardware acceleration unit uses a polling arbitration mechanism to schedule and process these concurrent requests.
[0032] S4: If it is a task receiving instruction, the hardware acceleration unit and the CPU core work together to execute the corresponding task receiving process.
[0033] Specifically, S41: The hardware acceleration unit obtains tasks from the queue specified by the CPU core and moves the tasks to the memory space specified by the CPU core; S42: The hardware acceleration unit writes the actual number of tasks to be moved to a fixed address in the storage space; S43: The CPU core retrieves the actual number of tasks to be moved from a fixed address in the storage space, and then retrieves the tasks in the storage space based on the actual number of tasks moved, thus completing the task reception.
[0034] In this embodiment, when the CPU core needs to obtain tasks from the hardware acceleration unit, it does not need to maintain the state of the task queue. The CPU core can initiate a task acquisition request to the hardware acceleration unit through a task reception instruction. The task reception instruction includes the queue number of the task queue that the CPU core is ready to acquire, the number of tasks to be acquired, and the destination for the task relocation by the hardware acceleration unit, which is the address of the storage space. After receiving the task reception instruction from the CPU core, the hardware acceleration unit reads tasks from the corresponding task queue according to the task queue number in the instruction. When the number of tasks in the task queue is less than the number of tasks that the CPU core is ready to acquire, all tasks in the queue are read and sent; otherwise, tasks are read and sent according to the number of tasks that the CPU core is ready to acquire. The address for task relocation is the storage space address in the task reception instruction. After the hardware acceleration unit moves the tasks to the storage space, it writes the actual number of tasks sent into a fixed address in the storage space. The CPU core obtains the number of tasks sent by the hardware acceleration unit from the fixed address in the storage space and retrieves all tasks from the storage space based on this number to complete the task reception.
[0035] S5: If it is a task sending instruction, the hardware acceleration unit and the CPU core work together to execute the corresponding task sending process.
[0036] Specifically, S51: The hardware acceleration unit retrieves tasks from the memory space specified by the CPU core and writes the tasks into the queue specified by the CPU core; S52: The hardware acceleration unit writes the task transfer completion status to a fixed address in the storage space; S53: The CPU core retrieves the task transfer completion status from a fixed address in the storage space and completes the task transmission.
[0037] In this embodiment, the CPU core does not need to maintain the state of the task queue when issuing tasks. The CPU core can write multiple tasks into the storage space in batches. Then, it notifies the hardware acceleration unit of the storage address of these tasks in the storage space, the number of stored tasks, and the task queue number that the tasks need to enter by issuing a task sending instruction. After the hardware acceleration unit receives the task sending instruction issued by the CPU core, it reads all the task data from the storage space according to the task storage address and the number of tasks in the task sending instruction. It writes these tasks into the designated task queue according to the task queue number in the task sending instruction. Afterwards, the hardware acceleration unit writes back the completion status flag to a fixed address in the storage space to notify the CPU core that the current task transfer is complete. After the CPU core reads the completed status flag written back to the fixed address in the storage space, it completes the issuance of the current task.
[0038] In this invention, when multiple CPU cores simultaneously initiate operations to acquire or distribute tasks to the same task queue of the hardware acceleration unit, since the CPU cores do not need to maintain the state of the task queue, the CPU cores do not need to compete for control of a certain queue through locks, thus solving the problem that multiple CPU cores need to control the same task queue through locks.
[0039] This invention provides a high-efficiency interaction method for multi-queue tasks in a multi-core architecture. By establishing an independent local storage space for each CPU core, task data is locally cached. When CPU cores interact with tasks, they only need to exchange data at high speed with the local storage space, while the cross-domain data transfer work is handled by a dedicated hardware acceleration unit. This avoids the latency overhead caused by frequent access to remote hardware devices via the system bus, and supports continuous processing of batch tasks, significantly improving the system's data throughput. The hardware acceleration unit centrally manages the state maintenance of all task queues, eliminating the need for traditional locking mechanisms when multiple CPU cores concurrently access the same task queue. This eliminates performance bottlenecks caused by lock contention, allowing the system's parallel processing capability to scale linearly with the number of CPU cores, making it suitable for task processing in high-concurrency scenarios. The hardware acceleration unit employs an intelligent processing strategy when performing task transfer. In the task receiving scenario, when the number of requested tasks exceeds the actual number of available tasks in the queue, it automatically adjusts the actual number of tasks transferred, ensuring effective utilization of system resources. Simultaneously, a state write-back mechanism is used to synchronize the state at a fixed address in the local storage space.
[0040] On the other hand, please see Figures 4 to 6 , Figure 4 This is a schematic diagram of the structure of a multi-queue task high-efficiency interaction system. Figure 5 This is a schematic diagram of the data structure in the storage module when the CPU core sends a task. Figure 6 This is a schematic diagram of the data structure in the storage module when the CPU core receives a task.
[0041] The present invention also includes a multi-core architecture multi-queue task high-efficiency interaction system, including multiple CPU cores 101, hardware acceleration unit 102 and storage module 103, wherein the hardware acceleration unit 102 is connected to the CPU cores 101, and the storage module 103 is connected to both the CPU cores 101 and the storage module 103. Multiple CPU cores 101: used to issue task sending instructions or task receiving instructions to the hardware acceleration unit 102; Hardware acceleration unit 102: In response to a task receiving instruction, it retrieves a task from a specified queue and moves it to the storage space specified by the CPU core 101, and writes back the actual number of tasks moved to a fixed address in the storage space; In response to a task sending instruction, it retrieves a task from the storage space specified by the CPU core 101 and writes it to a specified queue, and writes back the task moving completion status to a fixed address in the storage space. Storage module 103: Provides each CPU core 101 with independent storage space that can be accessed directly without going through the system bus.
[0042] Example: The multi-core architecture multi-queue task high-efficiency interactive system of the present invention has a total of 8 CPU cores 101, and the hardware acceleration unit 102 includes 32 task dispatch queues and 32 task upload queues; wherein each CPU core 101 has a storage module 103 (RAM space) that can be directly accessed by the CPU core 101 without going through the system bus.
[0043] CPU core 101 can batch write no more than 64 tasks continuously into the aforementioned storage module 103, and then send a task sending instruction to hardware acceleration unit 102 through the register access interface. The task sending instruction contains a 64-bit storage module 103 address, a 7-bit number of tasks to be stored, and a 5-bit task queue number. Hardware acceleration unit 102 arbitrates the task sending instructions from the eight CPU cores 101 in a polling manner and caches these requests for subsequent processing. Hardware acceleration unit 102 reads all task data from storage module 103 according to the storage module 103 address and the number of tasks to be stored in the task sending instruction, and writes these tasks into one of the 32 designated task queues according to the task queue number in the task sending instruction. Afterwards, hardware acceleration unit 102 marks the write-back completion status in storage module 103. The write-back storage module 103 address is the position of the byte preceding the storage module 103 address in the task sending instruction. After CPU core 101 polls the storage module 103 address and obtains that the write-back status mark is valid, it completes the sending of the current task.
[0044] CPU core 101 can send a task request to hardware acceleration unit 102 via a task receiving instruction. The maximum number of tasks requested at a time is 64. The task receiving instruction includes a 5-bit task queue number, a 7-bit number of tasks, and a 64-bit address of storage module 103. Hardware acceleration unit 102 arbitrates task receiving instructions from the eight CPU cores 101 in a round-robin manner and caches these requests for later processing. Hardware acceleration unit 102 reads tasks from the corresponding task queue according to the task queue number in the task receiving instruction. When the number of tasks in the task queue is less than the number of tasks that CPU core 101 is ready to acquire, ... The CPU core 101 reads all tasks from the queue and sends them up; otherwise, it reads and sends tasks according to the number of tasks that the CPU core 101 is ready to acquire. The address for sending tasks is the address of the storage module 103 in the task receiving instruction. After the hardware acceleration unit 102 moves the tasks to the storage module 103, it writes back the actual number of tasks sent to the storage module 103. The address of the storage module 103 written back is the position of the byte preceding the address of the storage module 103 in the task receiving instruction. The CPU core 101 polls the address of the storage module 103 to obtain the number of tasks sent by the hardware acceleration unit 102, and obtains all tasks from the storage module 103 according to the number of tasks to complete the task reception.
[0045] The above-disclosed embodiments are merely one or more preferred embodiments of this application and should not be construed as limiting the scope of this application. Those skilled in the art can understand that all or part of the processes for implementing the above embodiments and equivalent changes made in accordance with the claims of this application still fall within the scope of this application.
Claims
1. A method for efficient interaction of multi-queue tasks in a multi-core architecture, characterized in that, Includes the following steps: Each CPU core is configured with a directly accessible storage space that does not pass through the system bus; Multiple CPU cores issue task receive instructions or task send instructions; The hardware acceleration unit receives task sending instructions or task receiving instructions from multiple CPU cores. If it is a task receiving instruction, the hardware acceleration unit and the CPU core work together to execute the corresponding task receiving process; If it is a task sending instruction, the hardware acceleration unit and the CPU core work together to execute the corresponding task sending process.
2. The efficient interaction method for multi-queue tasks in a multi-core architecture as described in claim 1, characterized in that, The storage space is either a CPU cache or a dedicated RAM space.
3. The efficient interaction method for multi-queue tasks in a multi-core architecture as described in claim 2, characterized in that, In the case of a task receiving instruction, where the hardware acceleration unit and the CPU core collaboratively execute the corresponding task receiving process, the method specifically includes: The hardware acceleration unit retrieves tasks from the queue specified by the CPU core and moves the tasks to the memory space specified by the CPU core; The hardware acceleration unit writes the actual number of tasks to be moved to a fixed address in the storage space; The CPU core retrieves the actual number of tasks to be moved from a fixed address in the storage space, and then retrieves the tasks in the storage space based on the actual number of tasks moved, thus completing the task reception.
4. The efficient interaction method for multi-queue tasks in a multi-core architecture as described in claim 2, characterized in that, In the task sending instruction, where the hardware acceleration unit and the CPU core collaboratively execute the corresponding task sending process, the method specifically includes: The hardware acceleration unit retrieves tasks from the memory space specified by the CPU core and writes the tasks into the queue specified by the CPU core; The hardware acceleration unit writes the task transfer completion status to a fixed address in the storage space; The CPU core retrieves the task transfer completion status from a fixed address in the storage space and completes the task transmission.
5. The efficient interaction method for multi-queue tasks in a multi-core architecture as described in claim 3, characterized in that, The task receiving instruction includes the queue number of the task queue that the CPU core is ready to acquire, the number of tasks to acquire, and the destination for task relocation by the hardware acceleration unit, which is the address of the storage space.
6. The efficient interaction method for multi-queue tasks in a multi-core architecture as described in claim 4, characterized in that, After the hardware acceleration unit receives the task receiving instruction from the CPU core, it reads the task from the corresponding task queue according to the task queue number in the instruction. When the number of tasks in the task queue is less than the number of tasks that the CPU core is ready to acquire, it reads all the tasks in the queue and sends them up; otherwise, it reads the tasks according to the number of tasks that the CPU core is ready to acquire and sends them up.
7. A high-efficiency interactive system for multi-queue tasks with a multi-core architecture, used to implement the method as described in any one of claims 1-6, characterized in that, Includes multiple CPU cores, hardware acceleration units, and storage modules; Multiple CPU cores: used to issue task sending instructions or task receiving instructions to the hardware acceleration unit; Hardware acceleration unit: In response to task receiving instructions, it retrieves tasks from the designated queue and moves them to the memory space designated by the CPU core, and writes back the actual number of tasks moved to a fixed address in the memory space; In response to task sending instructions, it retrieves tasks from the memory space designated by the CPU core and writes them to the designated queue, and writes back the task moving completion status to a fixed address in the memory space. Storage module: Provides each CPU core with independent storage space that is not directly accessible through the system bus.