High-linearity differential low-noise amplifier

Abstract

The invention relates to the technical field of differential amplifiers, in particular to a high-linearity differential low-noise amplifier. Comprising a positive half main branch, a negative half main branch, a positive half auxiliary branch, a negative half auxiliary branch, a positive input matching module, a negative input matching module, a positive output matching module and a negative output matching module. The positive output matching module is connected with the negative half auxiliary branch; the positive output matching module is connected with the positive half main branch; the front half main branch is connected with the front half auxiliary branch; the positive input matching module is connected with the positive half main branch; the negative output matching module is connected with the negative half auxiliary branch; the negative output matching module is connected with the positive half main branch; the negative half main branch is connected with the negative half auxiliary branch; and the negative input matching module is connected with the negative half main branch. According to the invention, the third-order intermodulation amount is eliminated through the derivative superposition technology, so that additional noise brought by the auxiliary branch is compressed by the gain of the main branch, and noise deterioration is effectively slowed down.

Description

Technical Field

[0001] This invention relates to the field of differential amplifier technology, and more particularly to a high-linearity, low-noise differential amplifier. Background Technology

[0002] In modern communication systems, low-noise amplifiers (LNAs) are core modules of the radio frequency (RF) front-end circuit, and their performance plays a decisive role in the signal reception quality of the communication system. With the continuous expansion of communication frequency bands and the increasing complexity of signals, the linearity requirements for LNAs are becoming increasingly stringent. High linearity can effectively suppress nonlinear distortion during signal amplification, avoid intermodulation interference, and ensure signal integrity when multiple frequency signals are amplified simultaneously, thereby improving the overall performance of the communication system.

[0003] To meet this requirement, differential amplifiers are widely used in low-noise amplifier design due to their ability to effectively eliminate second-order intermodulation signals. By cleverly utilizing the symmetry of the differential structure, differential amplifiers can cancel out second-order intermodulation components in the input signal, improving the amplifier's linearity to some extent. However, facing increasingly complex communication signal environments, simply eliminating second-order intermodulation is no longer sufficient to meet practical needs. The presence of third-order intermodulation signals still significantly impacts signal quality, limiting further improvements in amplifier linearity.

[0004] To more effectively suppress third-order intermodulation, derivative superposition techniques have been increasingly introduced into low-noise amplifier designs. This technique, by introducing an auxiliary branch in conjunction with the main branch, can theoretically eliminate third-order intermodulation and further improve the amplifier's linearity. However, traditional derivative superposition techniques have a serious drawback: the main branch transistor and the auxiliary branch transistor share the same input, causing the auxiliary transistor's noise to be directly superimposed on the overall circuit noise, severely degrading noise performance and failing to meet the stringent low-noise requirements of modern communication systems.

[0005] Therefore, how to overcome the noise degradation problem caused by traditional derivative superposition technology while effectively utilizing differential amplifiers to eliminate second-order intermodulation and derivative superposition technology to eliminate third-order intermodulation, and develop a low-noise amplifier with both high linearity and low noise characteristics, has become a key technical problem that urgently needs to be solved in the field of integrated circuit design. Summary of the Invention

[0006] The present invention aims to at least solve one of the technical problems existing in related technologies. To this end, the present invention provides a high-linearity differential low-noise amplifier that achieves third-order intermodulation cancellation at the output.

[0007] This invention provides a high-linearity differential low-noise amplifier, comprising: Positive half main branch, negative half main branch, positive half auxiliary branch, negative half auxiliary branch, positive input matching module, negative input matching module, positive output matching module and negative output matching module; The positive output matching module is connected to the negative half auxiliary branch; The positive output matching module is connected to the positive half-side main branch; The positive half-side auxiliary branch is connected to the positive output matching module; The positive half main branch and the positive half auxiliary branch are connected; The positive input matching module is connected to the positive half-side main branch; The positive input matching module is connected to the positive input; The positive output matching module is connected to the positive output; The negative output matching module is connected to the negative half-side auxiliary branch; The negative output matching module is connected to the positive half-side main branch; The negative half-side auxiliary branch is connected to the negative output matching module; The negative half main branch and the negative half auxiliary branch are connected; The negative input matching module is connected to the negative half-side main branch; The negative input matching module is connected to the negative input; The negative output matching module is connected to the negative output.

[0008] According to the present invention, a high linearity differential low noise amplifier is provided, wherein the positive half main branch includes a first common source transistor, a first resistor, and a first source inductor. The source of the first common-source transistor is connected to one end of the first source inductor; The drain of the first common-source transistor is connected to the positive output matching module; The drain of the first common-source transistor is connected to the other end of the first resistor; One end of the first resistor is connected to the first bias voltage; The other end of the first resistor is connected to the positive input matching module; The other end of the first source inductor is grounded; The first common-source transistor is an NMOS transistor; The negative half of the main branch includes the second common-source transistor, the second resistor, and the second source inductor; The source of the second common-source transistor is connected to one end of the second source inductor; The drain of the second common-source transistor is connected to the negative output matching module; The drain of the second common-source transistor is connected to the other end of the second resistor; One end of the second resistor is connected to the second bias voltage; The other end of the second resistor is connected to the negative input matching module; The other end of the second source inductor is grounded; The second common-source transistor is an NMOS transistor.

[0009] According to the present invention, a high linearity differential low-noise amplifier is provided, wherein the first common source transistor is replaced with a parallel connection and the second common source transistor is replaced with a parallel connection.

[0010] The high linearity differential low-noise amplifier provided by the present invention further includes a first feedback module and a second feedback module: One end of the first feedback module is connected to the positive half of the main branch; The other end of the first feedback module is connected to the positive output matching module; One end of the second feedback module is connected to the negative half of the main branch; The other end of the second feedback module is connected to the negative output matching module.

[0011] According to the present invention, a high linearity differential low-noise amplifier is provided, wherein the positive input matching module includes a first capacitor and a first inductor; One end of the first inductor is connected to the positive input; The other end of the first inductor is connected to one end of the first capacitor; The other end of the first capacitor is connected to the positive half of the main branch; The negative input matching module includes a second capacitor and a second inductor; One end of the second inductor is connected to the negative input; The other end of the second inductor is connected to one end of the second capacitor; The other end of the second capacitor is connected to the negative half of the main branch; The negative input matching module includes a second capacitor and a second inductor; One end of the second inductor is connected to the negative input; The other end of the second inductor is connected to one end of the second capacitor; The other end of the second capacitor is connected to the negative half of the main branch.

[0012] According to the present invention, a high linearity differential low noise amplifier is provided, wherein the positive output matching module includes a first output inductor, a second output inductor, and a first output capacitor; One end of the first output inductor is connected to an external power supply; The other end of the first output inductor is connected to one end of the second output inductor; One end of the second output inductor is connected to the negative half of the auxiliary branch; The other end of the second output inductor is connected to the positive half of the main branch; One end of the first output capacitor is connected to the positive output connection; The other end of the first output capacitor is connected to one end of the second output inductor; The negative output matching module includes a third output inductor, a fourth output inductor, and a second output capacitor; One end of the third output inductor is connected to an external power supply; The other end of the third output inductor is connected to one end of the fourth output inductor; One end of the fourth output inductor is connected to the positive half of the auxiliary branch; The other end of the fourth output inductor is connected to the negative half of the main branch; One end of the second output capacitor is connected to the negative output; The other end of the second output capacitor is connected to one end of the fourth output inductor.

[0013] According to the present invention, a Cascode circuit is formed by adding a plurality of NMOS transistors between the first output inductor and the second output inductor in a high linearity differential low noise amplifier. Several NMOS transistors are added between the third and fourth output inductors to form a Cascode circuit.

[0014] According to the present invention, a high linearity differential low-noise amplifier is provided, wherein the positive half-side auxiliary branch includes a third common-source transistor, a third capacitor, and a third resistor: The drain of the third common source transistor is connected to the negative output matching module; The source of the third common-source transistor is grounded; The gate of the third common source transistor is connected to the other end of the third resistor; One end of the third resistor is connected to the third bias voltage; One end of the third capacitor is connected to the positive output matching module; The other end of the third capacitor is connected to the other end of the third resistor; The third common-source transistor is an NMOS transistor; The negative half-side auxiliary branch includes a fourth common-source transistor, a fourth capacitor, and a fourth resistor: The drain of the fourth common source transistor is connected to the positive output matching module; The source of the fourth common-source transistor is grounded; The gate of the fourth common source transistor is connected to the other end of the fourth resistor; One end of the fourth resistor is connected to the fourth bias voltage; One end of the fourth capacitor is connected to the negative output matching module; The other end of the fourth capacitor is connected to the other end of the fourth resistor; The fourth common-source transistor is an NMOS transistor.

[0015] According to the present invention, a high linearity differential low noise amplifier is provided, wherein the positive half-side auxiliary branch further includes a positive source degenerate inductor; One end of the positive source degraded inductor is connected to the source of the third common source transistor; The other end of the positive source degraded inductor is grounded; The negative half-side auxiliary branch also includes a negative source degraded inductor; One end of the negative source degraded inductor is connected to the source of the fourth common source transistor; The other end of the negative source degraded inductor is grounded; or, The positive half-side auxiliary branch also includes a positive source resistor; One end of the positive source resistor is connected to the source of the third common source transistor; The other end of the positive source resistor is grounded; The negative half-side auxiliary branch also includes a negative source resistor; One end of the negative source resistor is connected to the source of the fourth common source transistor; The other end of the negative source resistor is grounded.

[0016] According to the present invention, a high linearity differential low-noise amplifier is provided, wherein the positive half-side auxiliary branch and the negative half-side auxiliary branch operate in the subthreshold region without introducing additional power consumption.

[0017] The above-described one or more technical solutions in the embodiments of the present invention have at least one of the following technical effects: This invention provides a high-linearity differential low-noise amplifier. Compared with traditional differential low-noise amplifiers, it combines derivative superposition technology to eliminate third-order intermodulation, further improving linearity. Compared with the traditional derivative superposition method, the inputs of the positive and negative auxiliary branch tubes are not directly connected to the inputs of the positive and negative main branch amplifier tubes, so that the additional noise brought by the auxiliary branches is compressed by the gain of the main branches, effectively mitigating noise degradation.

[0018] Furthermore, the high linearity differential low-noise amplifier disclosed in this application has at least the following advantages compared to the prior art: 1. Low power consumption: The auxiliary tubes of the positive and negative auxiliary branches operate in the subthreshold region, and the operating current is generally in the microampere level. The additional power consumption is negligible, which helps to realize a low-power, low-noise amplifier.

[0019] 2. High linearity: The differential structure eliminates second-order intermodulation, and the derivative superposition technique eliminates third-order intermodulation in the positive and negative half-branch main circuits. The combination of the two eliminates both second-order and third-order intermodulation in the circuit proposed in this patent, further improving linearity.

[0020] 3. Low noise: Since the positive and negative auxiliary branches are not directly connected to the input of the corresponding positive and negative main branches, the noise is not directly superimposed, but compressed by the gain, which further reduces the noise compared with the traditional derivative superposition method.

[0021] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0023] Figure 1 The circuit diagram of the high linearity differential low noise amplifier provided in the embodiment of the present invention.

[0024] Figure 2 The circuit diagram of the high linearity Cascode / Stacked differential low-noise amplifier provided in the embodiments of the present invention.

[0025] Figure 3 The circuit diagram of the multi-stage high linearity differential low noise amplifier provided in the embodiments of the present invention.

[0026] Figure 4 A circuit diagram showing the introduction of a source degradation inductor into the secondary main body of a high linearity differential low noise amplifier provided in an embodiment of the present invention.

[0027] Figure 5 A circuit diagram showing the introduction of a source resistor in the secondary main body of a high linearity differential low noise amplifier provided in an embodiment of the present invention.

[0028] Figure 6 The circuit diagram of the broadband high linearity differential low noise amplifier provided in the embodiment of the present invention.

[0029] Figure 7 The main amplifying transistor and auxiliary transistor of the high linearity differential low noise amplifier provided in the embodiments of the present invention can be connected in parallel.

[0030] Figure 8A simulation diagram of second-order transconductance with the main amplifier tube and auxiliary tube biased within different gate-source voltage ranges.

[0031] Figure 9 This is a schematic diagram of the phase of a third-order intermodulation quantity.

[0032] Figure 10 This is a schematic diagram of the amplitude of the third-order intermodulation quantity. Detailed Implementation

[0033] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention. The following embodiments are used to illustrate this invention but cannot be used to limit the scope of this invention.

[0034] In the description of the embodiments of the present invention, it should be noted that the terms "center," "longitudinal," "lateral," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing the embodiments of the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the embodiments of the present invention. In addition, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0035] In the description of the embodiments of the present invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "connected" and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms in the embodiments of the present invention based on the specific circumstances.

[0036] In embodiments of the present invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can mean that the first feature is in direct contact with the second feature, or that the first feature is in indirect contact with the second feature through an intermediate medium. Furthermore, "above," "on top of," and "over" the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0037] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0038] The following is combined Figures 1 to 10 This invention is described.

[0039] Example 1 like Figure 1 As shown, Figure 1 The circuit diagram of the high linearity differential low noise amplifier provided in the embodiment of the present invention includes: a positive half main branch, a negative half main branch, a positive half auxiliary branch, a negative half auxiliary branch, a positive input matching module, a negative input matching module, a positive output matching module, and a negative output matching module; The positive output matching module is connected to the negative half auxiliary branch; The positive output matching module is connected to the positive half-side main branch; The positive half-side auxiliary branch is connected to the positive output matching module; The positive half main branch and the positive half auxiliary branch are connected; The positive input matching module is connected to the positive half-side main branch; The positive input matching module is connected to the positive input; The positive output matching module is connected to the positive output; The negative output matching module is connected to the negative half-side auxiliary branch; The negative output matching module is connected to the positive half-side main branch; The negative half-side auxiliary branch is connected to the negative output matching module; The negative half main branch and the negative half auxiliary branch are connected; The negative input matching module is connected to the negative half-side main branch; The negative input matching module is connected to the negative input; The negative output matching module is connected to the negative output.

[0040] Specifically, the positive half of the main branch includes the first common source transistor M1, the first resistor R1, and the first source inductor Ls1; The source of the first common-source transistor M1 is connected to one end of the first source inductor Ls1; The drain of the first common source transistor M1 is connected to the positive output matching module; in this embodiment of the invention, the drain of the first common source transistor M1 is connected to the other end of the second output inductor Ld11. The drain of the first common-source transistor M1 is connected to the other end of the first resistor R1; One end of the first resistor R1 is connected to the first bias voltage Vb1; The other end of the first resistor R1 is connected to the positive input matching module; in this embodiment of the invention, the other end of the first resistor R1 is connected to the first capacitor Cb1. The other end of the first source inductor Ls1 is grounded; The first common-source transistor M1 is an NMOS transistor.

[0041] Specifically, the negative half of the main branch includes the second common source transistor M2, the second resistor R2, and the second source inductor Ls2; The source of the second common-source transistor M2 is connected to one end of the second source inductor Ls2; The drain of the second common-source transistor M2 is connected to the negative output matching module; in this embodiment of the invention, the drain of the second common-source transistor M2 is connected to the fourth output inductor L21. The drain of the second common-source transistor M2 is connected to the other end of the second resistor R2; One end of the second resistor R2 is connected to the second bias voltage Vb2; The other end of the second resistor R2 is connected to the negative input matching module; in this embodiment of the invention, the other end of the second resistor R2 is connected to the second capacitor Cb2; The other end of the second source inductor Ls2 is grounded; The second common-source transistor M2 is an NMOS transistor.

[0042] Specifically, the positive input matching module includes a first capacitor Cb1 and a first inductor L1; One end of the first inductor L1 is connected to the positive input Vin1; The other end of the first inductor L1 is connected to one end of the first capacitor Cb1; The other end of the first capacitor Cb1 is connected to the positive half of the main branch. In this embodiment of the invention, the other end of the first capacitor Cb1 is connected to the other end of the first resistor R1; Specifically, the negative input matching module includes a second capacitor Cb2 and a second inductor L2; One end of the second inductor L2 is connected to the negative input Vin2; The other end of the second inductor L2 is connected to one end of the second capacitor Cb2; The other end of the second capacitor Cb2 is connected to the negative half of the main branch. In this embodiment of the invention, the other end of the second capacitor Cb2 is connected to the second resistor R2; The positive output matching module includes a first output inductor Ld12, a second output inductor Ld11, and a first output capacitor Co1; One end of the first output inductor Ld12 is connected to the external power supply VDD; The other end of the first output inductor Ld12 is connected to one end of the second output inductor Ld11; One end of the second output inductor Ld11 is connected to the negative half of the auxiliary branch; The other end of the second output inductor Ld11 is connected to the positive half of the main branch; One end of the first output capacitor Co1 is connected to the positive output connection Vout1; The other end of the first output capacitor Co1 is connected to one end of the second output inductor Ld11.

[0043] The negative output matching module includes a third output inductor Ld22, a fourth output inductor Ld21, and a second output capacitor Co2; One end of the third output inductor Ld22 is connected to the external power supply VDD; The other end of the third output inductor Ld22 is connected to one end of the fourth output inductor Ld21; One end of the fourth output inductor Ld21 is connected to the positive half auxiliary branch; The other end of the fourth output inductor Ld21 is connected to the negative half of the main branch; One end of the second output capacitor Co2 is connected to the negative output connection Vout2; The other end of the second output capacitor Co2 is connected to one end of the fourth output inductor Ld21.

[0044] The positive half-side auxiliary branch includes a third common-source transistor M3, a third capacitor Cb3, and a third resistor R3: The drain of the third common-source transistor M3 is connected to the negative output matching module; The source of the third common-source transistor M3 is grounded; The gate of the third common source transistor M3 is connected to the other end of the third resistor R3; One end of the third resistor R3 is connected to the third bias voltage Vb3; One end of the third capacitor Cb3 is connected to the positive output matching module; The other end of the third capacitor Cb3 is connected to the other end of the third resistor R3; The third common-source transistor M3 is an NMOS transistor.

[0045] The negative half-side auxiliary branch includes the fourth common-source transistor M4, the fourth capacitor R4, and the fourth resistor Cb4: The drain of the fourth common source transistor M4 is connected to the positive output matching module; The source of the fourth common-source transistor M4 is grounded; The gate of the fourth common source transistor M4 is connected to the other end of the fourth resistor R4; One end of the fourth resistor R4 is connected to the fourth bias voltage Vb4; One end of the fourth capacitor Cb4 is connected to the negative output matching module; The other end of the fourth capacitor Cb4 is connected to the other end of the fourth resistor R4; The fourth common-source transistor M4 is an NMOS transistor.

[0046] In this invention, both the main amplifying transistor and the auxiliary transistor can be connected in parallel in the circuit diagram. The specific circuit diagram is shown below. Figure 7 As shown, all NMOS transistors are connected in parallel.

[0047] Specifically, the simulation results of the second-order transconductance bias of the main amplifier transistor and the auxiliary transistor under different gate-source voltages are as follows: Figure 8 As shown. Through the N-type field-effect transistor: in, For source and leakage current, For transconductance, Gate-source voltage, The first derivative of the transconductance, It is the second derivative of the transconductance.

[0048] It can be seen that by performing a Taylor series expansion of the third harmonic current and the drain current of the second stage, ignoring harmonics above the third, the derivatives show a linear relationship. The third harmonic directions of an N-type field-effect transistor (FET) are opposite in the saturation and subthreshold regions. If two FETs operating in the saturation and subthreshold regions respectively are connected in parallel, and their dimensions are adjusted so that the third harmonic amplitudes of the two paths are the same, the third harmonic of the output signal can be canceled at the output, thereby increasing the compression point by 1 dB. Through intermodulation analysis of the FET, assuming the input signal is expressed as: in, For input signal, The first amplitude, The second amplitude, The first angular frequency, The second angular frequency, For time, The two third-order intermodulation quantities of interest in practical applications can be output as follows: and This shows that the third-order intermodulation of the field-effect transistor is linearly related to its second-order transconductance. Similarly, the component parameters can be adjusted to make the amplitudes of the third-order intermodulation of the main branch and the auxiliary branch consistent, thus canceling them out at the output and improving the third-order linearity.

[0049] Specifically, in a preferred embodiment, the phase difference between the positive and negative auxiliary branches and the negative and positive main branches, as well as the amplitudes of the third-order intermodulation currents of the three paths—the positive and negative auxiliary branches, the negative and positive main branches, and the negative and positive output terminals—simulated using 45nm SOI technology in Cadence software, are shown below. Figure 9 and Figure 10 As shown, when the phase difference is around 180 degrees, and the third-order intermodulation current amplitudes of the positive and negative auxiliary branches and the negative / positive main branches are equal, the third-order intermodulation current amplitudes at both output terminals are almost zero. This simulation result further verifies the feasibility of the high-linearity differential low-noise amplifier proposed in this invention.

[0050] Example 2 like Figure 2 The diagram shows a circuit diagram of a high-linearity Cascode / Stacked differential low-noise amplifier according to an embodiment of the present invention. In this embodiment, a positive half-side cascode transistor M5 is added between the first output inductor Ld12 and the second output inductor Ld11 to form a Cascode circuit, where Cg1 is the first bias capacitor and Vg5 is the fifth bias voltage.

[0051] A Cascode circuit is formed by adding a negative half-side cascode transistor M6 between the third output inductor Ld22 and the fourth output inductor Ld21. Here, Cg2 is the second bias capacitor, and Vg6 is the sixth bias voltage.

[0052] Example 3 like Figure 3 As shown, Figure 3 This is a circuit diagram of a multi-stage high-linearity differential low-noise amplifier provided in an embodiment of the present invention. In this embodiment, a multi-stage positive half-side cascode transistor is added between the first output inductor Ld12 and the second output inductor Ld11 to form a Cascode circuit, wherein Cg1 is the first bias capacitor, Vg5 is the fifth bias voltage, Cgn is the nth bias capacitor, Vgn is the nth bias voltage, and M5, ..., Mn are all positive half-side cascode transistors.

[0053] A Cascode circuit is formed by adding multiple negative half-side cascode transistors between the third output inductor Ld22 and the fourth output inductor Ld21. Here, Cg2 is the second bias capacitor, Vg6 is the sixth bias voltage, Cg(n+1) is the (n+1)th bias capacitor, and Vg(n+1) is the (n+1)th bias voltage. M6, ..., M(n+1) are all negative half-side cascode transistors.

[0054] Example 4 like Figure 4 As shown, the positive half-side auxiliary branch also includes a positive source degenerate inductor Lg3; One end of the positive source degraded inductor Lg3 is connected to the source of the third common source transistor; The other end of the positive source degraded inductor Lg3 is grounded; The negative half-side auxiliary branch also includes a negative source degraded inductor Lg4; One end of the negative source degraded inductor Lg4 is connected to the source of the fourth common source transistor; The other end of the negative source degraded inductor Lg4 is grounded.

[0055] Example 5 like Figure 5 As shown, the positive half-side auxiliary branch also includes a positive source resistor Rs3; One end of the positive source resistor Rs3 is connected to the source of the third common source transistor; The other end of the positive source resistor Rs3 is grounded; The negative half-side auxiliary branch also includes a negative source resistor Rs4; One end of the negative source resistor is connected to the source Rs4 of the fourth common source transistor; The other end of the negative source resistor Rs4 is grounded.

[0056] Example 6 like Figure 6 As shown, it also includes a first feedback module and a second feedback module: One end of the first feedback module is connected to the positive half of the main branch; The other end of the first feedback module is connected to the positive output matching module; Specifically, the first feedback module includes a first feedback resistor Rf1 and a first feedback capacitor Cf1; One end of the first feedback resistor Rf1 is connected to the positive half of the main branch; The other end of the first feedback resistor Rf1 is connected to the first feedback capacitor Cf1; The first feedback capacitor Cf1 is connected to the positive output matching module; One end of the second feedback module is connected to the negative half of the main branch; The other end of the second feedback module is connected to the negative output matching module; Specifically, the second feedback module includes a second feedback resistor Rf2 and a second feedback capacitor Cf2. One end of the second feedback resistor Rf2 is connected to the positive half of the main branch; The other end of the second feedback resistor Rf2 is connected to the second feedback capacitor Cf2; The second feedback capacitor Cf2 is connected to the positive output matching module.

[0057] The working principle of the high linearity differential low-noise amplifier disclosed in this invention is as follows: The output current of the main branch (positive and negative halves) is generated by a common-source transistor, and the output current of the auxiliary branches (positive and negative halves) is also generated by a common-source transistor. Specifically, assuming the current flowing to ground is the positive direction, when an AC positive voltage is input to the first input terminal, because the common-source transistor is biased in the saturation region, its... Since the value is negative, the corresponding third-order intermodulation is negative. Furthermore, a negative AC voltage is generated at the drain of the common-source transistor. This negative AC voltage acts on the gate of the auxiliary transistor, thus affecting the auxiliary common-source transistor. The voltage is an AC negative voltage, and since the auxiliary tube operates in the subthreshold region, A positive value corresponds to a negative third-order intermodulation. Similarly, when an AC negative voltage is input to the second input terminal, the third-order intermodulation of the negative half-main branch is positive, and the third-order intermodulation of the negative half-auxiliary branch is also positive. By adjusting the parameters of the circuit components, the amplitudes of the third-order intermodulation of the positive and negative half-main branches and the positive and negative half-auxiliary branches are made equal. Since the outputs of the positive half-main branch and the negative half-auxiliary branch are connected, and the outputs of the negative half-main branch and the positive half-auxiliary branch are connected, the third-order intermodulation of the positive and negative half-main branches and the negative and positive half-auxiliary branches cancel each other out, achieving high linearity. In addition, since the inputs of the positive and negative half-auxiliary branches are connected to the outputs of the positive and negative half-main branches, the noise of the auxiliary path is compressed by the gain of the common-source transistor, further reducing the introduced noise. Therefore, compared with the traditional derivative superposition method, the differential low-noise amplifier proposed in this invention can simultaneously achieve high linearity and low noise.

[0058] While this disclosure has been described with reference to several specific embodiments, it should be understood that this disclosure is not limited to the specific embodiments disclosed. This disclosure is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims

1. A high-linearity differential low-noise amplifier, characterized in that, include: Positive half main branch, negative half main branch, positive half auxiliary branch, negative half auxiliary branch, positive input matching module, negative input matching module, positive output matching module and negative output matching module; The positive output matching module is connected to the negative half auxiliary branch; The positive output matching module is connected to the positive half-side main branch; The positive half-side auxiliary branch is connected to the positive output matching module; The positive half main branch and the positive half auxiliary branch are connected; The positive input matching module is connected to the positive half-side main branch; The positive input matching module is connected to the positive input; The positive output matching module is connected to the positive output; The negative output matching module is connected to the negative half-side auxiliary branch; The negative output matching module is connected to the positive half-side main branch; The negative half-side auxiliary branch is connected to the negative output matching module; The negative half main branch and the negative half auxiliary branch are connected; The negative input matching module is connected to the negative half-side main branch; The negative input matching module is connected to the negative input; The negative output matching module is connected to the negative output.

2. The high linearity differential low-noise amplifier according to claim 1, characterized in that, The positive half of the main branch includes the first common source transistor, the first resistor, and the first source inductor; The source of the first common-source transistor is connected to one end of the first source inductor; The drain of the first common-source transistor is connected to the positive output matching module; The drain of the first common-source transistor is connected to the other end of the first resistor; One end of the first resistor is connected to the first bias voltage; The other end of the first resistor is connected to the positive input matching module; The other end of the first source inductor is grounded; The first common-source transistor is an NMOS transistor; The negative half of the main branch includes the second common-source transistor, the second resistor, and the second source inductor; The source of the second common-source transistor is connected to one end of the second source inductor; The drain of the second common-source transistor is connected to the negative output matching module; The drain of the second common-source transistor is connected to the other end of the second resistor; One end of the second resistor is connected to the second bias voltage; The other end of the second resistor is connected to the negative input matching module; The other end of the second source inductor is grounded; The second common-source transistor is an NMOS transistor.

3. A high-linearity differential low-noise amplifier according to claim 2, characterized in that, The first common-source transistor is replaced with a parallel connection, and the second common-source transistor is replaced with a parallel connection.

4. A high linearity differential low-noise amplifier according to claim 1, characterized in that, It also includes a first feedback module and a second feedback module: One end of the first feedback module is connected to the positive half of the main branch; The other end of the first feedback module is connected to the positive output matching module; One end of the second feedback module is connected to the negative half of the main branch; The other end of the second feedback module is connected to the negative output matching module.

5. A high-linearity differential low-noise amplifier according to claim 1, characterized in that, The positive input matching module includes a first capacitor and a first inductor; One end of the first inductor is connected to the positive input; The other end of the first inductor is connected to one end of the first capacitor; The other end of the first capacitor is connected to the positive half of the main branch; The negative input matching module includes a second capacitor and a second inductor; One end of the second inductor is connected to the negative input; The other end of the second inductor is connected to one end of the second capacitor; The other end of the second capacitor is connected to the negative half of the main branch; The negative input matching module includes a second capacitor and a second inductor; One end of the second inductor is connected to the negative input; The other end of the second inductor is connected to one end of the second capacitor; The other end of the second capacitor is connected to the negative half of the main branch.

6. A high-linearity differential low-noise amplifier according to claim 1, characterized in that, The positive output matching module includes a first output inductor, a second output inductor, and a first output capacitor; One end of the first output inductor is connected to an external power supply; The other end of the first output inductor is connected to one end of the second output inductor; One end of the second output inductor is connected to the negative half of the auxiliary branch; The other end of the second output inductor is connected to the positive half of the main branch; One end of the first output capacitor is connected to the positive output connection; The other end of the first output capacitor is connected to one end of the second output inductor; The negative output matching module includes a third output inductor, a fourth output inductor, and a second output capacitor; One end of the third output inductor is connected to an external power supply; The other end of the third output inductor is connected to one end of the fourth output inductor; One end of the fourth output inductor is connected to the positive half of the auxiliary branch; The other end of the fourth output inductor is connected to the negative half of the main branch; One end of the second output capacitor is connected to the negative output; The other end of the second output capacitor is connected to one end of the fourth output inductor.

7. A high-linearity differential low-noise amplifier according to claim 6, characterized in that, Several NMOS transistors are added between the first output inductor and the second output inductor to form a Cascode circuit; Several NMOS transistors are added between the third and fourth output inductors to form a Cascode circuit.

8. A high-linearity differential low-noise amplifier according to claim 1, characterized in that, The positive half-side auxiliary branch includes a third common-source transistor, a third capacitor, and a third resistor: The drain of the third common source transistor is connected to the negative output matching module; The source of the third common-source transistor is grounded; The gate of the third common source transistor is connected to the other end of the third resistor; One end of the third resistor is connected to the third bias voltage; One end of the third capacitor is connected to the positive output matching module; The other end of the third capacitor is connected to the other end of the third resistor; The third common-source transistor is an NMOS transistor; The negative half-side auxiliary branch includes a fourth common-source transistor, a fourth capacitor, and a fourth resistor: The drain of the fourth common source transistor is connected to the positive output matching module; The source of the fourth common-source transistor is grounded; The gate of the fourth common source transistor is connected to the other end of the fourth resistor; One end of the fourth resistor is connected to the fourth bias voltage; One end of the fourth capacitor is connected to the negative output matching module; The other end of the fourth capacitor is connected to the other end of the fourth resistor; The fourth common-source transistor is an NMOS transistor.

9. A high linearity differential low-noise amplifier according to claim 8, characterized in that, The positive half-side auxiliary branch also includes a positive source degraded inductor; One end of the positive source degraded inductor is connected to the source of the third common source transistor; The other end of the positive source degraded inductor is grounded; The negative half-side auxiliary branch also includes a negative source degraded inductor; One end of the negative source degraded inductor is connected to the source of the fourth common source transistor; The other end of the negative source degraded inductor is grounded; or, The positive half-side auxiliary branch also includes a positive source resistor; One end of the positive source resistor is connected to the source of the third common source transistor; The other end of the positive source resistor is grounded; The negative half-side auxiliary branch also includes a negative source resistor; One end of the negative source resistor is connected to the source of the fourth common source transistor; The other end of the negative source resistor is grounded.

10. A high-linearity differential low-noise amplifier according to claim 1, characterized in that, The positive half-side auxiliary branch and the negative half-side auxiliary branch operate in the subthreshold region and do not introduce additional power consumption.

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