Trench-type semiconductor field effect transistor and method for manufacturing the same

Abstract

The application relates to a trench type semiconductor field effect tube and a preparation method thereof, which comprises the following steps: a substrate with a first conductive type; a drift region located on the substrate and having the first conductive type; a first well region located on a side of the drift region away from the substrate and having a second conductive type; a second well region located on a side of the drift region away from the substrate and arranged in a spaced mode with the first well region and having the second conductive type; a trench gate located between the first well region and the second well region; a carrier extraction structure penetrating the trench gate in a first direction and covering at least part of a surface of the trench gate on a side close to the substrate and having the second conductive type; the first direction is along the thickness direction of the substrate; and a source metal layer covering the first well region, the second well region, the trench gate and the carrier extraction structure. The trench type semiconductor field effect tube provided by the application has high SEE resistance.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a trench semiconductor field-effect transistor and its fabrication method. Background Technology

[0002] Silicon carbide (SiC) MOSFETs have broad application prospects in new energy, aerospace and other fields due to their high voltage resistance, low loss and high temperature resistance.

[0003] Single-event effect (SEE) refers to the phenomenon where a single high-energy particle passes through a sensitive area of ​​a microelectronic device, causing abnormal device state or functional failure, such as single-event burn-out or single-event gate penetration. SEE mainly occurs in space radiation environments. For trench silicon carbide MSOFETs, when a single-event event occurs, a large number of holes will accumulate at the gate oxide, posing a significant challenge to their reliability and stability. Summary of the Invention

[0004] Therefore, it is necessary to provide a trench-type semiconductor field-effect transistor with high SEE resistance and its fabrication method.

[0005] In a first aspect, this application provides a trench-type semiconductor field-effect transistor, comprising:

[0006] The substrate has a first type of conductivity;

[0007] A drift region, located on the substrate, has a first conductivity type;

[0008] The first well region, located on the side of the drift region away from the substrate, has a second conductivity type;

[0009] The second well region is located on the side of the drift region away from the substrate, and is spaced apart from the first well region, and has a second conductivity type;

[0010] A trench gate is located between the first well region and the second well region;

[0011] A carrier extraction structure extends through the trench gate along a first direction and covers at least a portion of the surface of the trench gate near the substrate, and has a second conductivity type; the first direction is along the thickness direction of the substrate;

[0012] A source metal layer covers the first well region, the second well region, the trench gate, and the carrier extraction structure.

[0013] In one embodiment, the cell structure further includes:

[0014] The JFET region, located on the side of the first well region near the substrate and the side of the second well region near the substrate, has a first conductivity type.

[0015] In one embodiment, the carrier extraction structure is in contact with the JFET region;

[0016] The ion doping concentration of the carrier extraction structure is greater than the ion doping concentration of the JFET region.

[0017] In one embodiment, the ion doping concentration of the JFET region is 1 × 10⁻⁶. 16 cm -3 ~1×10 18 cm -3 The ion doping concentration of the carrier extraction structure is greater than 1 × 10⁻⁶. 18 cm -3 .

[0018] In one embodiment, the trench gate includes a first sub-gate and a second sub-gate;

[0019] Wherein, the first sub-gate extends along the second direction, the second sub-gate extends along the third direction, and the first sub-gate intersects with the second sub-gate; the second direction is perpendicular to the first direction, and the third direction is perpendicular to the first direction and perpendicular to the second direction.

[0020] In one embodiment, the carrier extraction structure includes:

[0021] The first extraction section covers the surface of the first sub-gate near the substrate and the surface of the second sub-gate near the substrate;

[0022] The second extraction section penetrates the first sub-gate along the first direction and extends along the second direction;

[0023] The third extraction section penetrates the second sub-gate along the first direction and extends along the second direction, intersecting with the second extraction section.

[0024] In one embodiment, the carrier extraction structure includes:

[0025] The first extraction section covers the surface of the first sub-gate near the substrate and the surface of the second sub-gate near the substrate;

[0026] The fourth extraction section extends along the first direction through the intersection region of the first sub-gate and the second sub-gate.

[0027] In one embodiment, the carrier extraction structure includes:

[0028] The first extraction section covers the surface of the first sub-gate near the substrate and the surface of the second sub-gate near the substrate;

[0029] The fourth extraction section extends through the intersection region of the first sub-gate and the second sub-gate along the first direction;

[0030] The fifth extraction section extends through the first sub-gate along the first direction and is spaced apart from the fourth extraction section;

[0031] The sixth extraction section extends through the second sub-gate along the first direction and is spaced apart from the fourth extraction section.

[0032] In one embodiment, the carrier extraction structure includes:

[0033] The first extraction section covers the intersection area of ​​the first sub-gate and the second sub-gate, and the surface near the substrate.

[0034] The fourth extraction section extends along the first direction through the intersection region of the first sub-gate and the second sub-gate.

[0035] Secondly, this application also provides a method for fabricating a trench-type metal-oxide-semiconductor field-effect transistor, comprising:

[0036] Provide a substrate of the first conductivity type;

[0037] A drift region of a first conductivity type is formed on the substrate;

[0038] A doped pillar of the second conductivity type is formed within the drift region;

[0039] A first trench and a second trench are formed within the doped pillar, the first trench and the second trench are spaced apart, and a doped pillar is provided between the first trench and the second trench; wherein, the doped pillars at the bottom of the first trench and the bottom of the second trench, and the doped pillars between the first trench and the second trench constitute a carrier extraction structure;

[0040] A first split gate is formed in the first trench, and a second split gate is formed in the second trench. The first split gate and the second split gate constitute a trench gate.

[0041] A first well region is formed on the side of the first split gate away from the second split gate, and a second well region is formed on the side of the second split gate away from the first split gate;

[0042] A source metal layer is formed on the exposed surfaces of the first well region, the second well region, the trench gate, and the carrier extraction structure.

[0043] In the above-mentioned trench-type semiconductor field-effect transistor and its fabrication method, the carrier extraction structure penetrates through the trench gate and covers at least a portion of the bottom surface of the trench gate, and is also in contact with the source metal layer. Thus, when SEE occurs, electrons will quickly migrate to the drain metal layer, while holes can be quickly extracted to the source metal layer by the carrier extraction structure. This can prevent holes from accumulating at the bottom of the trench gate, reduce the risk of gate breakdown, improve the device's SEE resistance, and improve the device's reliability. Attached Figure Description

[0044] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0045] Figure 1 One of the schematic diagrams of the cross-sectional structure of a trench-type semiconductor field-effect transistor provided in one embodiment;

[0046] Figure 2 for Figure 1 A schematic diagram of the cross-sectional structure after cutting along the dashed line Aa;

[0047] Figure 3 This is a second schematic diagram of the cross-sectional structure of a trench-type semiconductor field-effect transistor provided in one embodiment;

[0048] Figure 4 for Figure 3 A schematic diagram of the cross-sectional structure after cutting along the dashed line Aa;

[0049] Figure 5 The third schematic diagram of the cross-sectional structure of a trench-type semiconductor field-effect transistor provided in one embodiment;

[0050] Figure 6 for Figure 5 A schematic diagram of the cross-sectional structure after cutting along the dashed line Aa;

[0051] Figure 7 This is a cross-sectional schematic diagram of the structure obtained in step S300 of the method for fabricating a trench-type semiconductor field-effect transistor according to an embodiment;

[0052] Figure 8 for Figure 7 A schematic diagram of the cross-sectional structure after cutting along the dashed line Aa;

[0053] Figure 9 This is a cross-sectional schematic diagram of the structure obtained in step S500 of the method for fabricating a trench-type semiconductor field-effect transistor according to an embodiment;

[0054] Figure 10 for Figure 9 A schematic diagram of the cross-sectional structure after cutting along the dashed line Aa;

[0055] Figure 11 This is a cross-sectional schematic diagram of the structure obtained in step S700 of the fabrication method of a trench-type semiconductor field-effect transistor provided in one embodiment;

[0056] Figure 12 This is a current density distribution diagram of a trench-type semiconductor field-effect transistor in one embodiment.

[0057] Explanation of reference numerals in the attached figures:

[0058] 100 - Substrate, 200 - Drift region, 310 - First well region, 320 - Second well region, 400 - Trench gate, 401 - First split gate, 402 - Second split gate, 410 - First sub-gate, 420 - Second sub-gate, 500 - Carrier extraction structure, 501 - Doped pillar, 510 - First extraction section, 520 - Second extraction section, 530 - Third extraction section, 540 - Fourth extraction section, 550 - Fifth extraction section, 560 - Sixth extraction section, 600 - Source metal layer, 700 - JFET region, 800 - Source doped region, 900 - Heavily doped region, 1000 - Drain metal layer, 1100 - Insulating layer. Detailed Implementation

[0059] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0060] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application.

[0061] It is understood that the terms "first," "second," etc., used herein may be used to describe various films, regions, and structures, but these films, regions, and structures are not limited by these terms. These terms are only used to distinguish one film, region, or structure from another. For example, without departing from the scope of this application, a first sub-gate may be referred to as a second sub-gate, and similarly, a second sub-gate may be referred to as a first sub-gate. Both the first sub-gate and the second sub-gate are sub-gates, but they are not the same sub-gate.

[0062] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, the term “and / or” as used in this specification includes any and all combinations of the associated listed items.

[0063] When SEE occurs, a large number of electron-hole pairs are generated inside the trench MOSFET device. Since the mobility of electrons is much higher than that of holes, electrons are instantly removed from the drain, while holes slowly move to the vicinity of the trench gate and accumulate, resulting in an increase in the gate electric field strength, which can easily lead to gate breakdown.

[0064] Based on this, this application provides a trench-type semiconductor field-effect transistor, such as... Figure 1 As shown, it includes a substrate 100, a drift region 200, a first well region 310, a second well region 320, a trench gate 400, a carrier extraction structure 500, and a source metal layer 600.

[0065] The substrate 100 has a first conductivity type. The material of the substrate 100 may be silicon carbide doped with ions of the first conductivity type.

[0066] The drift region 200 is located on the substrate 100 and has a first conductivity type. The material of the drift region 200 can be any suitable drift region 200 material in the art, which can be the same as or different from the material of the substrate 100.

[0067] The first well region 310 is located on the side of the drift region 200 away from the substrate 100 and has a second conductivity type. The second conductivity type is the opposite of the first conductivity type. For example, the first conductivity type is N-type and the second conductivity type is P-type. The second well region 320 is located on the side of the drift region 200 away from the substrate 100, spaced apart from the first well region 310, and has a second conductivity type. The first well region 310 and the second well region 320 can be formed by ion implantation into the drift region 200.

[0068] The trench gate 400 is located between the first well region 310 and the second well region 320.

[0069] The carrier extraction structure 500 extends through the trench gate 400 along a first direction and covers at least a portion of the surface of the trench gate 400 near the substrate 100, and has a second conductivity type. The first direction is along the thickness direction of the substrate 100. The carrier extraction structure 500 can also be formed by ion implantation of the drift region 200.

[0070] The source metal layer 600 covers the first well region 310, the second well region 320, the trench gate 400, and the carrier extraction structure 500. The source metal layer 600 can be any suitable conductive material known in the art, such as copper, titanium, aluminum, etc.

[0071] In this embodiment, a current extraction structure is provided that penetrates the trench gate 400, and the current extraction structure 500 covers at least a portion of the bottom surface of the trench gate 400 and is in contact with the source metal layer 600. In this way, when SEE occurs, holes can be quickly extracted to the source metal layer 600 by the current extraction structure 500, which can prevent holes from accumulating at the bottom of the trench gate 400 and improve the device's SEE resistance.

[0072] In one embodiment, such as Figure 1 As shown, the cell structure also includes a JFET region 700. The JFET region 700 is located on the side of the first well region 310 near the substrate 100 and the side of the second well region 320 near the substrate 100, respectively, and has a first conductivity type. The JFET region 700 can also be formed by ion doping the drift region 200.

[0073] In one embodiment, the carrier extraction structure 500 is in contact with the JFET region 700, and the ion doping concentration of the carrier extraction structure 500 is greater than the ion doping concentration of the JFET region 700.

[0074] The ion doping concentration of the carrier extraction structure 500 is greater than that of the JFET region 700 and also greater than that of the drift region 200. Since the carrier extraction structure 500 has a second conductivity type, while the JFET region 700 and the drift region 200 have a first conductivity type, a built-in electric field is formed between the carrier extraction structure 500, the JFET region 700, and the drift region 200. Under the action of this built-in electric field, holes are more efficiently attracted to the carrier extraction structure 500, thus achieving rapid hole extraction.

[0075] In one embodiment, the ion doping concentration of JFET region 700 is 1×10⁻⁶. 16 cm -3 ~1×10 18 cm -3 For example, the ion doping concentration of JFET region 700 can be 1 × 10⁻⁶. 16 cm -3 5×10 16 cm -3 1×10 17 cm -3 5×10 16 cm -3 1×10 18 cm-3 Etc. The ion doping concentration of carrier extraction structure 500 is greater than 1 × 10⁻⁶. 18 cm -3 For example, it can be 2×10 18 cm -3 1×10 19 cm -3 1×10 20 cm -3 wait.

[0076] In one embodiment, such as Figure 1 As shown, the trench-type semiconductor field-effect transistor also includes a source doped region 800 of a first conductivity type. The source doped regions 800 are located on the side of the first well region 310 away from the JFET region 700 and the side of the second well region 320 away from the JFET region 700, respectively.

[0077] In one embodiment, such as Figure 1 As shown, the trench-type semiconductor field-effect transistor also includes a heavily doped region 900 of a second conductivity type, which is located on the side of the source doped region 800 away from the trench gate 400.

[0078] In one embodiment, such as Figure 1 As shown, the trench-type semiconductor field-effect transistor also includes a drain metal layer 1000. The drain metal layer 1000 is located on the side of the substrate 100 away from the drift region 200.

[0079] In one embodiment, such as Figure 2 As shown, the trench gate 400 includes a first sub-gate 410 and a second sub-gate 420. The first sub-gate 410 extends along a second direction, and the second sub-gate 420 extends along a third direction, intersecting each other. The second direction is perpendicular to the first direction, and the third direction is perpendicular to both the first and second directions.

[0080] The first sub-gate 410 and the second sub-gate 420 form a grid-like structure, and the first well region 310 and the second well region 320 are alternately disposed within the grid of the grid-like structure.

[0081] Both the first sub-gate 410 and the second sub-gate 420 include an oxide layer and a gate dielectric layer. The gate dielectric layer is located between the carrier extraction structure 500 and the well region, and the oxide layer surrounds the gate dielectric layer. The material of the gate dielectric layer can be a suitable gate dielectric material in the art, such as High-K dielectric, Low-K dielectric, polysilicon, etc. The material of the oxide layer can be silicon oxide, silicon oxycarbide, silicon oxynitride, etc. The oxide layer located between the gate dielectric layer and the carrier extraction structure, and between the gate dielectric layer and the well region, can serve as the gate oxide layer.

[0082] In one embodiment, such as Figure 1 and Figure 2 As shown, the carrier extraction structure 500 includes a first extraction section 510, a second extraction section 520, and a third extraction section 530.

[0083] The first extraction portion 510 covers the surface of the first sub-gate 410 near the substrate 100 and the surface of the second sub-gate 420 near the substrate 100. The second extraction portion 520 penetrates the first sub-gate 410 along a first direction and extends along a second direction. The third extraction portion 530 penetrates the second sub-gate 420 along the first direction and extends along the second direction, intersecting with the second extraction portion 520.

[0084] In one embodiment, such as Figure 3 and Figure 4 As shown, the carrier extraction structure 500 includes a first extraction section 510 and a fourth extraction section 540.

[0085] The first extraction portion 510 is located on the surface of the first sub-gate 410 near the substrate 100 and the surface of the second sub-gate 420 near the substrate 100. The fourth extraction portion 540 extends through the intersection region of the first sub-gate 410 and the second sub-gate 420 along the first direction.

[0086] In one embodiment, such as Figure 5 and Figure 6 As shown, the carrier extraction structure 500 includes a first extraction section 510, a fourth extraction section 540, a fifth extraction section 550, and a sixth extraction section 560.

[0087] The first extraction portion 510 is located on the surface of the first sub-gate 410 near the substrate 100 and the surface of the second sub-gate 420 near the substrate 100. The fourth extraction portion 540 penetrates the intersection region of the first sub-gate 410 and the second sub-gate 420 along a first direction. The fifth extraction portion 550 penetrates the first sub-gate 410 along the first direction and is spaced apart from the fourth extraction portion 540. The sixth extraction portion 560 penetrates the second sub-gate 420 along the first direction and is spaced apart from the fourth extraction portion 540.

[0088] In one embodiment, the carrier extraction structure 500 includes a first extraction section 510 and a fourth extraction section 540. Figure 3 and Figure 4 Unlike the trench-type semiconductor field-effect transistor shown, in this embodiment, the fourth extraction portion 540 still penetrates the intersection region of the first sub-gate 410 and the second sub-gate 420 along the first direction, but the first extraction portion 510 is located in the intersection region of the first sub-gate 410 and the second sub-gate 420, on the surface near the substrate 100.

[0089] Based on the same inventive concept, this application also provides a method for fabricating a trench-type semiconductor field-effect transistor, which includes steps S100-S700.

[0090] S100 provides a substrate of the first conductivity type.

[0091] S200, a drift region of the first conductivity type is formed on the substrate.

[0092] like Figure 7 and Figure 8 As shown, the drift region 200 can be formed on the substrate 100 by an epitaxial growth process.

[0093] S300, a doped pillar of the second conductivity type is formed in the drift region.

[0094] like Figure 7 and Figure 8 As shown, a doped column 501 can be formed in the drift region through ion implantation and annealing.

[0095] S400, a first trench and a second trench are formed in the doped column, the first trench and the second trench are spaced apart, and a doped column is located between the first trench and the second trench.

[0096] The doped pillars at the bottom of the first trench and the bottom of the second trench, and the doped pillars between the first trench and the second trench, constitute the carrier extraction structure 500. The first trench and the second trench can be formed by etching within the doped pillars using photolithography and etching processes. Optionally, a portion of the drift region 200 near the doped pillars can also be etched to form the first channel and the second trench.

[0097] S500, a first split gate is formed in a first trench, and a second split gate is formed in a second trench, the first split gate and the second split gate constituting a trench gate.

[0098] like Figure 9 and Figure 10 As shown, a first split gate 401 can be formed in the first trench and a second split gate 402 can be formed in the second trench through a deposition process.

[0099] S600, a first well region is formed on the side of the first split gate away from the second split gate, and a second well region is formed on the side of the second split gate away from the first split gate.

[0100] like Figure 11 As shown, a first well region 310 can be formed on the side of the first split gate 401 away from the second split gate 402 by ion implantation, and a second well region 320 can be formed on the side of the second split gate 402 away from the first split gate 401.

[0101] Before step S600, a JFET region 700 can be formed on the side of the first split gate 401 away from the second split gate 402 and on the side of the second split gate 402 away from the first split gate 401 by an ion implantation process.

[0102] After S600, a heavily doped region 900 and a source doped region 800 can be formed on the side of the first well region 310 and the second well region 320 away from the JFET region 700 by ion implantation process.

[0103] Subsequently, an insulating layer 1100 can be formed on the surface of the heavily doped region 900, the source doped region 800, the trench gate 400, and the carrier extraction structure 500 by a deposition process.

[0104] S700 forms a source metal layer on the exposed surfaces of the first well region, the second well region, the trench gate, and the carrier extraction structure.

[0105] like Figure 1 and Figure 2 As shown, the insulating layer 1100 can be etched first, leaving only a portion of the insulating layer on the surface of the trench gate 400, and the source metal layer 600 can be formed in the area where the insulating layer 1100 has been removed. Then, the drain metal layer 1000 can be formed on the side of the substrate 100 away from the drift region 200.

[0106] In this embodiment, a substrate 100 of a first conductivity type is provided, a drift region 200 of the first conductivity type is formed on the substrate 100, a doped pillar 501 of the second conductivity type is formed within the drift region 200, a first trench and a second trench are formed within the doped pillar 501, a first split gate 401 is formed within the first trench, and a second split gate 402 is formed within the second trench. The first split gate 401 and the second split gate 402 constitute a trench gate 400. The doped pillar at the bottom of the trench gate 400 and the doped pillar between the first trench and the second trench constitute a carrier extraction structure 500. A first well region 310 is formed on the side of the split gate 401 away from the second split gate 402, and a second well region 320 is formed on the side of the second split gate 402 away from the first split gate 401. A source metal layer 600 is formed on the exposed surfaces of the first well region 310, the second well region 320, the trench gate 400, and the carrier extraction structure 500. The fabrication process is simple. Furthermore, when SEE occurs, holes can be quickly extracted to the source metal layer 600 by the carrier extraction structure 500, which can prevent holes from accumulating at the bottom of the trench gate 400, improve the device's SEE resistance, and enhance the device's reliability.

[0107] In one embodiment, the trench-type semiconductor field-effect transistor of this application was tested, and the current density distribution obtained was as follows: Figure 12As shown, it can be clearly seen that when SEE occurs, the hole current flows through the carrier extraction structure 500 to the source metal layer 600, which avoids the accumulation of holes at the bottom of the trench gate 400, improves the device's SEE resistance, and enhances the device's reliability.

[0108] In the description of this specification, references to terms such as "some embodiments," "other embodiments," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0109] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0110] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these modifications and improvements all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A trench-type semiconductor field-effect transistor, characterized in that, include: The substrate has a first type of conductivity; A drift region, located on the substrate, has a first conductivity type; The first well region, located on the side of the drift region away from the substrate, has a second conductivity type; The second well region is located on the side of the drift region away from the substrate, and is spaced apart from the first well region, and has a second conductivity type; A trench gate is located between the first well region and the second well region; the trench gate includes a first sub-gate and a second sub-gate; wherein the first sub-gate extends along a second direction, the second sub-gate extends along a third direction, and the first sub-gate intersects with the second sub-gate; the second direction is perpendicular to the first direction, and the first direction is the thickness direction of the substrate; the third direction is perpendicular to the first direction and perpendicular to the second direction; A carrier extraction structure extends through the trench gate along a first direction and covers at least a portion of the surface of the trench gate near the substrate, and has a second conductivity type; the first direction is along the thickness direction of the substrate; the carrier extraction structure includes at least an extraction portion extending through the intersection region of the first sub-gate and the second sub-gate along the first direction. A source metal layer covers the first well region, the second well region, the trench gate, and the carrier extraction structure; In particular, when the single-event effect occurs, the holes are quickly extracted to the source metal layer by the carrier extraction structure, thus preventing the holes from accumulating at the bottom of the trench gate.

2. The trench-type semiconductor field-effect transistor according to claim 1, characterized in that, The trench-type semiconductor field-effect transistor also includes: The JFET region, located on the side of the first well region near the substrate and the side of the second well region near the substrate, has a first conductivity type.

3. The trench-type semiconductor field-effect transistor according to claim 2, characterized in that, The carrier extraction structure is in contact with the JFET region; The ion doping concentration of the carrier extraction structure is greater than the ion doping concentration of the JFET region.

4. The trench-type semiconductor field-effect transistor according to claim 3, characterized in that, The ion doping concentration of the JFET region is 1×10⁻⁶. 16 cm -3 ~1×10 18 cm -3 The ion doping concentration of the carrier extraction structure is greater than 1 × 10⁻⁶. 18 cm -3 .

5. The trench-type semiconductor field-effect transistor according to claim 1, characterized in that, The carrier extraction structure includes: The first extraction section covers the surface of the first sub-gate near the substrate and the surface of the second sub-gate near the substrate; The second extraction section penetrates the first sub-gate along the first direction and extends along the second direction; The third extraction section penetrates the second sub-gate along the first direction and extends along the third direction, intersecting with the second extraction section.

6. The trench-type semiconductor field-effect transistor according to claim 1, characterized in that, The carrier extraction structure includes: The first extraction section covers the surface of the first sub-gate near the substrate and the surface of the second sub-gate near the substrate; The fourth extraction section extends along the first direction through the intersection region of the first sub-gate and the second sub-gate.

7. The trench-type semiconductor field-effect transistor according to claim 1, characterized in that, The carrier extraction structure includes: The first extraction section covers the surface of the first sub-gate near the substrate and the surface of the second sub-gate near the substrate; The fourth extraction section extends through the intersection region of the first sub-gate and the second sub-gate along the first direction; The fifth extraction section extends through the first sub-gate along the first direction and is spaced apart from the fourth extraction section; The sixth extraction section extends through the second sub-gate along the first direction and is spaced apart from the fourth extraction section.

8. The trench-type semiconductor field-effect transistor according to claim 1, characterized in that, The carrier extraction structure includes: The first extraction section covers the intersection area of ​​the first sub-gate and the second sub-gate, and the surface near the substrate. The fourth extraction section extends along the first direction through the intersection region of the first sub-gate and the second sub-gate.

9. A method for fabricating a trench-type semiconductor field-effect transistor, characterized in that, include: Provide a substrate of the first conductivity type; A drift region of a first conductivity type is formed on the substrate; A doped pillar of the second conductivity type is formed within the drift region; A first trench and a second trench are formed within the doped pillar, the first trench and the second trench are spaced apart, and a doped pillar is provided between the first trench and the second trench; wherein, the doped pillars at the bottom of the first trench and the bottom of the second trench, and the doped pillars between the first trench and the second trench constitute a carrier extraction structure; A first split gate is formed in the first trench, and a second split gate is formed in the second trench, the first split gate and the second split gate constituting a trench gate; the trench gate includes a first sub-gate and a second sub-gate; wherein, the first sub-gate extends along a second direction, the second sub-gate extends along a third direction, and the first sub-gate intersects with the second sub-gate; the second direction is perpendicular to the first direction, the first direction being the thickness direction of the substrate; the third direction is perpendicular to the first direction and perpendicular to the second direction; the carrier extraction structure includes at least an extraction portion that penetrates the intersection region of the first sub-gate and the second sub-gate along the first direction; A first well region is formed on the side of the first split gate away from the second split gate, and a second well region is formed on the side of the second split gate away from the first split gate; A source metal layer is formed on the exposed surfaces of the first well region, the second well region, the trench gate, and the carrier extraction structure; In particular, when the single-event effect occurs, the holes are quickly extracted to the source metal layer by the carrier extraction structure, thus preventing the holes from accumulating at the bottom of the trench gate.

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