SiC power semiconductor module adaptive active drive and control method thereof

Abstract

The application belongs to but is not limited to the technical field of power electronics, and particularly relates to a SiC power semiconductor module adaptive active drive and a control method thereof. A system acquires a drain current signal of a power device (SiC MOSFET) in real time through a current sampling circuit, and converts the drain current signal into a voltage signal Vmode. The Vmode is input into a control signal generation circuit. The control signal generation circuit is based on a multi-path hysteresis comparator, and classifies and identifies the current through preset multi-stage threshold values, and outputs corresponding control signals according to the identified overload grades. The control signals are respectively sent to a drive circuit (used for switching off negative voltage from-5V to-2V under strong overload conditions) and a parallel capacitor dynamic switching circuit (used for sequentially inputting gate-source parallel capacitors with different capacitance values according to the overload degree). Finally, through the synergistic effect of the switching off negative voltage adjustment and the parallel capacitor switching, the switching off overvoltage and gate cross talk under strong overload conditions are effectively inhibited.

Description

Technical Field

[0001] This invention belongs to, but is not limited to, the field of power electronic devices, and particularly relates to an adaptive active drive for SiC power semiconductor modules and its control method. Background Technology

[0002] Currently, power electronic devices based on new energy power generation and flexible DC transmission technology have been widely applied in the power generation, transmission, distribution, and consumption segments of my country's power system. The proportion of power electronic equipment based on converters continues to rise, gradually replacing traditional electromagnetic conversion-based power generation and transmission equipment, becoming a key force in building the future power grid voltage support system.

[0003] However, the overcurrent withstand capability of power electronic equipment currently used in engineering practice is generally only 1 to 1.5 times its rated value. This limitation makes it difficult to effectively provide voltage support during system transients, easily leading to problems such as the expansion of the fault range and chain reactions, specifically manifested as the blocking of flexible DC transmission systems or large-scale disconnection of renewable energy generation units from the grid. For example, when a short circuit occurs in the system, renewable energy and flexible DC systems can only provide short-circuit currents close to the load level, causing a severe voltage drop in the sending-end grid. In addition, in a typical symmetrical bipolar flexible DC grid, if a blocking fault occurs in one pole during rated operation, its transmission power will transfer to the other pole within milliseconds, causing the healthy pole converter to quickly block due to overcurrent, thereby causing AC system voltage collapse and disconnection of renewable energy units from the grid. Therefore, after a power system fault, power electronic equipment must have a strong overcurrent operating capability to achieve rapid construction and stable support of transient voltage. To achieve this goal, the equipment needs to have an instantaneous overcurrent capability of 3 to 5 times.

[0004] Power semiconductor devices, as core components for enabling high-current operation in power electronic devices, face severe performance challenges. Currently, commercially available devices have an overcurrent capability of only about 1.2 times their rated current within a millisecond timescale, far short of the 3 to 5 times rated current required for high-current operation. In engineering, multiple devices are often connected in parallel to improve the overcurrent level, but this leads to resource waste and reduced economic efficiency. Therefore, research into key technologies for power semiconductor devices under high-current conditions is extremely urgent.

[0005] Under strong overcurrent operating conditions, the power device turn-off voltage spikes caused by package parasitic parameters are particularly prominent, easily inducing avalanche breakdown or even secondary breakdown, ultimately leading to overvoltage failure. Existing traditional power module packages have large and complex parasitic parameters, and the switching process of SiC MOSFETs is extremely short (nanosecond-level). This means that the delay in the feedback loop and computation stage in existing active gate drive (AGD) technologies may exceed the switching cycle itself, making it difficult for their control strategies, timing sequences, and sampling circuit designs to meet such stringent speed requirements. Current SiC MOSFET AGD technologies are mainly divided into two categories:

[0006] One approach is open-loop AGD control, which relies on device switching trajectory or loss models. It optimizes the switching process by injecting auxiliary current to suppress overshoot and losses, or by using negative feedback to suppress crosstalk. This type of method depends on high-precision models, and the high-order calculations involved in complex models place a heavy burden on the controller.

[0007] Secondly, there is AGD with feedback control, which dynamically adjusts the switching trajectory through multi-level drive voltage or current. Multi-level output is often achieved using a high-speed programmable level shifter array. To match the high-speed switching characteristics of SiC devices, high-speed detection components such as GHz-level broadband amplifiers and PCB Rogowski coils are required, along with logic circuits or PI control to minimize delay. However, this significantly increases system cost and structural complexity.

[0008] Other studies have proposed schemes to automatically adjust switching speed based on bus voltage or load current (e.g., FPGA-based controllable current source drivers or self-regulating voltage source drivers). However, these schemes are mostly verified under rated current or lower conditions, without in-depth investigation of the performance of power devices under extreme conditions of high bus voltage and large turn-off current. Their overvoltage suppression effect is limited, and they lack adaptive voltage regulation capability, making it difficult to cope with the severe turn-off overvoltage challenge under strong overcurrent conditions. Therefore, developing an active drive technology that can effectively suppress power device turn-off overvoltage under short-term high current conditions is of great significance for ensuring the safe and stable operation of new power systems under grid fault conditions.

[0009] Based on the above analysis, the urgent technical problems that need to be solved in the existing technology are as follows: In the existing technology, the active gate drive technology for SiCMOSFET is difficult to match its nanosecond-level high-speed switching characteristics. Under strong overcurrent conditions, there are problems such as feedback and calculation delay exceeding the switching cycle, reliance on high-precision models or the need for high-speed and expensive components leading to high cost, complex structure, limited overvoltage suppression effect and lack of voltage adaptive regulation capability. It cannot effectively solve the risk of turn-off voltage spikes and device overvoltage failure caused by package parasitic parameters, and it is difficult to meet the requirements of power electronic equipment for transient voltage support during strong overcurrent operation. Summary of the Invention

[0010] To address the problems existing in the prior art, this invention provides an adaptive active drive and control method for SiC power semiconductor modules. The method determines the overload condition by real-time detection of the drain current of the power device and automatically adjusts the turn-off negative voltage and dynamically switches the parallel gate-source capacitor in stages to synergistically suppress turn-off overvoltage and gate crosstalk.

[0011] This invention is implemented as follows: an adaptive active drive for a SiC power semiconductor module, comprising:

[0012] Current sampling circuit: Converts the operating current signal of SiC MOSFET into a voltage signal suitable for processing. Specific components include sampling resistor Rs, operational amplifier OP1, negative feedback resistor Rf, grounding resistor R1, and load resistor R2.

[0013] Control signal generation circuit: A multi-threshold hysteresis comparator structure is used to realize graded overload detection and generation of multiple control signals. The components include five hysteresis comparators CP1, CP2, CP3, CP4, and CP5, and different threshold voltage sources. , The typical hysteresis of each comparator is 0.1V;

[0014] Drive circuit: The drive circuit adopts an adaptive negative voltage switching mechanism to optimize the turn-off process of SiC MOSFETs under strong overload conditions and suppress turn-off overvoltage. The components include three isolated DC power supplies, a signal isolation unit, a push-pull output stage composed of MOSFETs, and two parallel MOSFET switches S1 and S2.

[0015] Parallel capacitor dynamic switching circuit: used to dynamically adjust the value of the parallel capacitance between the gate and source of SiC MOSFET according to the overload level, so as to suppress crosstalk and turn off overvoltage. The components include four capacitors C1, C2, C3 and C4 with successively increasing capacitance values, and C1 < C2 < C3 < C4, and MOSFET switching transistors Q1, Q2, Q3 and Q4 connected in series with each capacitor respectively.

[0016] Furthermore, in the current sampling circuit, the sampling resistor Rs is connected in series between the source of the SiC MOSFET and the power ground. The voltage drop Vs across Rs serves as the input signal, which is connected to the non-inverting input of operational amplifier OP1. OP1 forms a non-inverting proportional amplifier circuit, with its inverting input grounded through R1. The amplification factor is set through a feedback network, and the output generates a voltage signal Vmode, which is output to the control signal generation circuit.

[0017] Furthermore, in the control signal generation circuit, the voltage signal Vmode output by the current sampling circuit is simultaneously connected to the non-inverting input of these five hysteresis comparators. The inverting input of each comparator is connected to a resistor network with different voltage division ratios to obtain an increasing reference voltage. In comparator CP1, its output Flag1 is connected to the gate control circuits of two MOSFETs via a buffer and an inverter. The drain of the MOSFET connected to the gate and inverter is connected to the negative terminal of the +5V power supply, and the source is connected to the power input terminal of the lower MOSFET in the push-pull output stage of the drive circuit. The drain of the MOSFET connected to the buffer is connected to the negative terminal of the +2V power supply, and the source is also connected to the power input terminal of the lower MOSFET in the push-pull output stage of the drive circuit. The gate drive circuits of the two MOSFETs are designed with complementary logic to ensure that only one MOSFET is turned on at any given time. The outputs Flag2, Flag3, Flag4, and Flag5 of all comparators except CP1 are connected to the gates of the corresponding MOSFET switches in the parallel capacitor dynamic switching circuit via buffers. The threshold values ​​of the five hysteresis comparators are set according to the rated current and overload protection requirements of the SiC MOSFETs. Threshold voltage and Triggered when drain current reaches twice the rated current. Triggered when drain current reaches 3 times rated current. Triggered when drain current reaches 4 times rated current. Triggered when the drain current reaches 5 times the rated current. On one hand, when a specific overload level is detected, CP1 outputs a high level, which switches the turn-off negative voltage from -5V to -2V through the MOSFET switch in the drive circuit; on the other hand, as the overload level increases, the other comparators output high levels in sequence, driving the corresponding MOSFET switches in the parallel capacitor switching circuit to turn on, thereby achieving a step-by-step increase in the capacitance value.

[0018] Furthermore, in the drive circuit, the PWM signal from the controller, after passing through the signal isolation unit, drives the two MOSFETs in the push-pull output stage respectively. The source of the upper MOSFET in the push-pull stage is connected to power ground, and its drain is connected to the positive terminal of the +15V power supply through a pull-up resistor; the drain of the lower MOSFET is connected to the negative terminals of the +5V and +2V power supplies respectively through two parallel MOSFET switches, and its source is connected to power ground. The gate of S1 is directly controlled by the Flag1 signal output from the control signal generation circuit through a buffer, while the gate of S2 is controlled by Flag1 through an inverter, ensuring that the two switches are in a complementary conduction state. The negative terminal of the +15V power supply, the positive terminal of the +5V power supply, and the positive terminal of the +2V power supply are all connected to the source of the SiC MOSFET. The +15V power supply provides a +15V voltage to ensure that the SiC MOSFET operates in the fully saturated region; the -5V provided by the +5V power supply is the normal turn-off negative voltage, used to provide sufficient turn-off reliability; the -2V provided by the +2V power supply is a special turn-off negative voltage for strong overload, used to slow down the turn-off speed. S1 and S2 are MOSFETs with low on-resistance and fast switching characteristics to minimize switching delay.

[0019] Furthermore, in the parallel capacitor dynamic switching circuit, each capacitor-switch series branch (e.g., C1 and Q1 in series) is connected in parallel between the gate and source of the SiC MOSFET. The gate of each switch is connected to the hierarchical output flag terminal of the control signal generation circuit via a buffer, the drain is connected to the corresponding capacitor, and the source is connected to the source of the SiC MOSFET. The capacitance values ​​are determined based on suppression requirements and the influence of switching speed; for example, C1 = 1nF, C2 = 2.2nF, C3 = 4.7nF, and C4 = 10nF. Under normal operating conditions, Vmode... All Flag signals are low, Q1, Q2, Q3, and Q4 are all off, and no capacitor is connected in parallel with the gate and source of the SiC MOSFET. The drive circuit operates at optimal speed. When a strong overload condition occurs, Vmode... When Flag1 goes high, Q1 turns on, and capacitor C1 is connected in parallel between the gate and source to slow down the charging and discharging speed of GS, suppressing overvoltage and crosstalk. As the overload increases, Vmode gradually exceeds... Q2, Q3, and Q4 are turned on sequentially, and capacitors C2, C3, and C4 are connected in parallel between the gate and source. The total parallel capacitance between the gate and source increases sequentially from C1 to C1+C2, C1+C2+C3, and C1+C2+C3+C4. The technical effect of the parallel capacitor dynamic switching circuit is mainly reflected in the step-like increase of the parallel capacitance between the gate and source of the SiC MOSFET as the overload level increases. During the turn-off process, it can significantly suppress the gate crosstalk voltage spike and slow down the rate of gate voltage drop. In conjunction with the -2V turn-off negative voltage switched by the drive circuit, the turn-off process is made smoother, and together they suppress the turn-off overvoltage caused by high di / dt.

[0020] Another object of the present invention is to provide an adaptive active drive control method for SiC power semiconductor modules using the aforementioned adaptive active drive, comprising:

[0021] S1, the system acquires the drain current signal of the power device (SiC MOSFET) in real time through the current sampling circuit and converts it into a voltage signal Vmode.

[0022] S2, Vmode is input to the control signal generation circuit. This circuit is based on a multi-channel hysteresis comparator, which classifies the current by preset multi-level thresholds and outputs the corresponding control signal according to the identified overload level.

[0023] S3, the control signal is sent to the drive circuit (used to switch the turn-off negative voltage from -5V to -2V under strong overload conditions) and the parallel capacitor dynamic switching circuit (used to sequentially switch gate-source parallel capacitors of different capacitance values ​​according to the degree of overload).

[0024] S4, through the synergistic effect of turn-off negative voltage regulation and parallel capacitor switching, effectively suppresses turn-off overvoltage and gate crosstalk under strong overload conditions.

[0025] Another object of the present invention is to provide a computer device, the computer device including a memory and a processor, the memory storing a computer program, and when the computer program is executed by the processor, causing the processor to perform the steps of the SiC power semiconductor module adaptive active drive control method.

[0026] Another object of the present invention is to provide a computer-readable storage medium storing a computer program, which, when executed by a processor, causes the processor to perform the steps of the adaptive active drive control method for the SiC power semiconductor module.

[0027] Another objective of this invention is to provide an information data processing terminal, which includes the aforementioned SiC power semiconductor module adaptive active drive.

[0028] Based on the above technical solutions and the technical problems solved, the advantages and positive effects of the technical solution to be protected by this invention are as follows:

[0029] The dynamic parallel capacitor of this invention effectively suppresses crosstalk and turn-off overvoltage: Traditional gate drive circuits typically employ fixed gate resistors or single-stage adjustable structures, which struggle to handle turn-off overvoltage spikes caused by the combined effects of high di / dt and parasitic inductance under strong overcurrent conditions. They also fail to suppress crosstalk voltage coupled to the gate due to high dv / dt. The proposed parallel capacitor dynamic switching circuit uses a multi-stage hysteresis comparator to detect the overload level in real time and sequentially connects capacitors of different values ​​between the gate and source of the SiC MOSFET according to the overcurrent level. As the overload level increases, the parallel capacitor value gradually increases, effectively slowing down the gate voltage change rate and reducing crosstalk caused by sudden changes in drain-source voltage. Simultaneously, the increased capacitance also slows down the gate discharge rate during turn-off, thereby suppressing the rise slope and overshoot amplitude of the turn-off voltage, achieving dual suppression of crosstalk and turn-off overvoltage.

[0030] This invention offers highly flexible graded control, and the system exhibits excellent overvoltage suppression capability, adaptability, and operational reliability under strong overload conditions. Unlike traditional single-threshold overcurrent protection or fixed negative voltage shutdown methods, this technology employs a multi-threshold hysteresis comparator to form a graded detection mechanism. This mechanism can identify different levels of overload states based on current sampling signals and output corresponding control signals. In terms of the drive circuit, once a strong overload is detected, the shutdown negative voltage is switched from the conventional -5V to a higher negative voltage of -2V, slowing down the rate of gate potential decline during shutdown. This reduces the di / dt of the current decline phase, effectively suppressing the shutdown overvoltage spike caused by parasitic inductance in the circuit. Under normal operating conditions, the original negative voltage strategy is maintained to avoid unnecessary increases in losses. Regarding capacitor switching, different overload levels correspond to different sized capacitors, achieving a smooth transition from suppressing crosstalk to suppressing overvoltage. This "graded detection and graded response" control strategy enables the system to automatically adapt to the optimal drive parameters and auxiliary capacitors under different overload conditions. This not only achieves coordinated optimization and suppression of turn-off overvoltage and gate crosstalk, but also improves the overall operational flexibility and reliability.

[0031] The all-analog hardware implementation of this invention features a simple structure, fast response, and low cost. The entire control loop is built on analog circuitry, including current sampling and amplification, multi-channel hysteresis comparison, push-pull drive, and capacitor switching network. It eliminates the need for high-speed ADCs, FPGAs, or high-performance digital processors, avoiding the complex software algorithm development, parameter tuning, and significant loop delays associated with digital solutions. The response time of the analog comparators and switching devices is on the order of nanoseconds, enabling timely capture of rapid current changes in SiC MOSFETs under strong overload and immediate execution of control actions, ensuring real-time control during high-speed switching transients. Furthermore, the all-analog architecture reduces system complexity and manufacturing costs, making it easier to integrate and apply in practical engineering projects.

[0032] This invention fills a technological gap in the domestic and international industry: existing commercial SiC MOSFET driving solutions mainly focus on optimizing switching performance and crosstalk immunity under normal operating conditions, with overcurrent protection often limited to single-threshold shutdown or current limiting functions. While there is extensive research on "active drive (AGD)" in academic studies and cutting-edge patents, its technical paths mainly fall into two categories: one is open-loop feedforward control based on complex models, which is difficult to implement practically; the other is closed-loop control relying on high-speed digital processors (such as FPGAs) and complex algorithms, which is costly and difficult to develop. This invention proposes and implements for the first time a fully analog adaptive drive architecture based on "multi-threshold analog comparison and voltage-capacitance hybrid graded adjustment." This architecture, while ensuring nanosecond-level response speed, achieves accurate identification and gradient suppression of strong overload levels in pure hardware, filling a key gap between research and product in the technical direction of "implementing strong overload adaptive drive with simple and reliable analog circuits."

[0033] This invention solves a long-standing but unresolved technical problem: how to ensure that SiC MOSFETs maintain safe and controllable voltage stress during turn-off when subjected to transient overload currents several times their rated value. Traditional solutions cannot balance speed, reliability, and cost. This invention successfully solves this problem through the core principle of "real-time current grading - synchronous matching of drive parameters." Specifically, it uses multiple analog hysteresis comparators to grade the current signal without delay and directly uses this graded signal to control the analog switches for gate negative voltage switching and capacitor switching. This allows the drive system to automatically adjust to a "strong suppression mode" that matches the overload level when an overload occurs, suppressing turn-off overvoltage spikes and gate crosstalk within a safe range. This fully analog, software-free solution overcomes the core challenge of dynamic stress management under strong overloads in a simple and reliable manner favored by engineering. Attached Figure Description

[0034] Figure 1This is a schematic diagram of the adaptive active drive principle of the SiC power semiconductor module provided in an embodiment of the present invention;

[0035] Figure 2 This is an adaptive active drive topology diagram of a SiC power semiconductor module provided in an embodiment of the present invention;

[0036] Figure 3 This is a flowchart of the adaptive active drive control method for SiC power semiconductor modules provided in an embodiment of the present invention. Detailed Implementation

[0037] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0038] The overall synergistic relationship between the adaptive active drive hardware topology and control strategy of SiC power semiconductor modules is as follows: Figure 1 (Schematic diagram) Figure 2 As shown in the topology diagram, the overall hardware architecture mainly consists of four functional modules: a current sampling circuit, a control signal generation circuit, a drive circuit, and a parallel capacitor dynamic switching circuit. The system acquires the drain current signal of the power device (SiC MOSFET) in real time through the current sampling circuit and converts it into a voltage signal Vmode. Vmode is input to the control signal generation circuit, which, based on a multi-channel hysteresis comparator, classifies the current through preset multi-level thresholds and outputs corresponding control signals according to the identified overload level. The control signals are sent to the drive circuit (used to switch the turn-off negative voltage from -5V to -2V under strong overload conditions) and the parallel capacitor dynamic switching circuit (used to sequentially switch gate-source parallel capacitors of different capacitance values ​​according to the overload level). Finally, through the synergistic effect of turn-off negative voltage regulation and parallel capacitor switching, effective suppression of turn-off overvoltage and gate crosstalk under strong overload conditions is achieved.

[0039] 1. Current Sampling Circuit: The core function of this circuit is to convert the operating current signal of the SiC MOSFET into a voltage signal suitable for processing. Specific components include a sampling resistor Rs, an operational amplifier OP1, a negative feedback resistor Rf, a grounding resistor R1, and a load resistor R2. In terms of connection, the sampling resistor Rs is connected in series between the source of the SiC MOSFET and power ground. The voltage drop Vs across Rs serves as the input signal, connected to the non-inverting input of the operational amplifier OP1. OP1 forms a non-inverting proportional amplifier circuit, with its inverting input grounded through R1. The amplification factor is set through a feedback network, and the output generates a voltage signal Vmode, which is output to the control signal generation circuit. In terms of working principle, according to Ohm's law and the "virtual short, virtual open" principle of operational amplifiers, the voltage drop Vs across the sampling resistor Rs = Id × Rs, where Id is the drain current of the SiC MOSFET. After the weak voltage signal Vs is amplified by OP1, the output voltage signal Vmode satisfies the relationship: Vmode = (1 + Rf / R1) × Vs. By selecting an extremely small Rs (typically 1mΩ) to reduce losses and setting (1 + Rf / R1) = 25, the millivolt-level sampled signal can be amplified to a volt-level Vmode signal. The current sampling circuit achieves accurate and linear sampling of large currents, converting the current signal Id into a voltage signal Vmode that can be processed by subsequent circuits without distortion. Simultaneously, through a fixed gain amplification of 25x, it ensures that Vmode has sufficient amplitude and signal-to-noise ratio under normal and overload conditions, providing a reliable input for accurate identification of overload levels and overcoming the shortcomings of direct processing of weak signals, which are susceptible to noise interference and lack accuracy.

[0040] 2. Control Signal Generation Circuit: This circuit uses a multi-threshold hysteresis comparator structure to achieve graded overload detection and generation of multiple control signals. The components include five hysteresis comparators (CP1, CP2, CP3, CP4, CP5) and different threshold voltage sources (…). , The typical hysteresis of each comparator is 0.1V. In terms of connection, the voltage signal Vmode output from the current sampling circuit is simultaneously connected to the non-inverting input of these five hysteresis comparators. The inverting input of each comparator is connected to a resistor network with different voltage division ratios to obtain an increasing reference voltage. Taking comparator CP1 as an example, its output Flag1 is connected to the gate control circuits of two MOSFETs via a buffer and an inverter. The drain of the MOSFET connected to the gate and inverter is connected to the negative terminal of the +5V power supply, and the source is connected to the power input terminal of the lower MOSFET in the push-pull output stage of the drive circuit. The drain of the MOSFET connected to the buffer is connected to the negative terminal of the +2V power supply, and the source is also connected to the power input terminal of the lower MOSFET in the push-pull output stage of the drive circuit. The gate drive circuits of the two MOSFETs are designed with complementary logic to ensure that only one MOSFET is turned on at any given time. The outputs of all comparators except CP1 (Flag2, Flag3, Flag4, Flag5) are connected to the gates of the corresponding MOSFET switches in the parallel capacitor dynamic switching circuit via buffers. Regarding key parameters, the threshold values ​​of the five hysteresis comparators are set according to the rated current and overload protection requirements of the SiC MOSFETs. Threshold voltage and Triggered when drain current reaches twice the rated current. Triggered when drain current reaches 3 times rated current. Triggered when drain current reaches 4 times rated current. Triggered when the drain current reaches 5 times the rated current. On one hand, when a specific overload level (such as 2 times the rated current) is detected, CP1 outputs a high level. This signal switches the turn-off negative voltage from -5V to -2V through the MOSFET switch in the drive circuit. On the other hand, as the overload level increases, the other comparators output high levels in sequence, driving the corresponding MOSFET switches in the parallel capacitor switching circuit to turn on, thus achieving a step-by-step increase in the capacitance value. Through this level triggering mechanism based on multi-level thresholds, adaptive coordinated control is achieved, where "the deeper the overload, the stronger the turn-off negative voltage regulation and parallel capacitor compensation."

[0041] 3. Drive Circuit: The drive circuit employs an adaptive negative voltage switching mechanism to optimize the turn-off process of the SiC MOSFETs under strong overload conditions and suppress turn-off overvoltage. The components include three isolated DC power supplies (outputting +15V, -5V, and -2V voltages respectively), a signal isolation unit, a push-pull output stage composed of MOSFETs, and two parallel MOSFET switches S1 and S2. In terms of connection, the PWM signal from the controller, after passing through the signal isolation unit, drives the two MOSFETs in the push-pull output stage. The source of the upper MOSFET in the push-pull stage is connected to power ground, and its drain is connected to the positive terminal of the +15V power supply through a pull-up resistor; the drain of the lower MOSFET is connected to the negative terminals of the +5V and +2V power supplies respectively through two parallel MOSFET switches, and its source is connected to power ground. The gate of S1 is directly controlled by the Flag1 signal output from the control signal generation circuit via a buffer, while the gate of S2 is controlled by Flag1 through an inverter, ensuring that the two switches are in a complementary conduction state. The negative terminal of the +15V power supply, the positive terminal of the +5V power supply, and the positive terminal of the +2V power supply are all connected to the source of the SiC MOSFET. Regarding key parameters, the +15V power supply provides a +15V voltage to ensure the SiC MOSFET operates in full saturation; the -5V power supply provides a normal turn-off voltage to provide sufficient turn-off reliability; and the -2V power supply provides a dedicated turn-off voltage for strong overload conditions to slow down the turn-off speed. S1 and S2 are MOSFETs with low on-resistance and fast switching characteristics to minimize switching delay. In terms of operating principle, under normal operating conditions, the Flag1 signal output by the control signal generation circuit is low. At this time, S1 is off, S2 is on, and the +5V power supply is connected to the drive circuit. When the PWM signal is high, the drive circuit outputs +15V, turning on the SiC MOSFET; when the PWM signal is low, the drive circuit outputs -5V, achieving fast turn-off. Under strong overload conditions, the Flag1 signal becomes high. At this time, S1 is on and S2 is off, and the +2V power supply is connected to the drive circuit. The drive circuit outputs -2V during the off-state. The core function of the drive circuit is to adaptively switch the off-state negative voltage by detecting whether the overall circuit is under strong overload conditions.

[0042] 4. Parallel Capacitor Dynamic Switching Circuit: This circuit dynamically adjusts the parallel capacitance value between the gate and source of the SiC MOSFET based on the overload level to suppress crosstalk and turn off overvoltage. The components include four capacitors with progressively increasing capacitance values ​​(C1, C2, C3, C4, where C1 < C2 < C3 < C4) and MOSFET switches (Q1, Q2, Q3, Q4) connected in series with each capacitor. In terms of connection, each capacitor-switch series branch (e.g., C1 and Q1 in series) is connected in parallel between the gate and source of the SiC MOSFET. The gate of each switch is connected to the hierarchical output flag terminal of the control signal generation circuit via a buffer, the drain is connected to the corresponding capacitor, and the source is connected to the source of the SiC MOSFET. The capacitance values ​​are determined based on suppression requirements and switching speed considerations; for example, C1 = 1nF, C2 = 2.2nF, C3 = 4.7nF, and C4 = 10nF. In terms of working principle, the parallel capacitor dynamic switching circuit operates according to the logic of "the greater the overload, the larger the capacitor being switched on." Under normal operating conditions, Vmode... All Flag signals are low, Q1, Q2, Q3, and Q4 are all off, and no capacitor is connected in parallel with the gate and source of the SiC MOSFET. The drive circuit operates at optimal speed. When a strong overload condition occurs, Vmode... When Flag1 goes high, Q1 turns on, and capacitor C1 is connected in parallel between the gate and source to slow down the charging and discharging speed of GS, suppressing overvoltage and crosstalk. As the overload increases, Vmode gradually exceeds... Q2, Q3, and Q4 are turned on sequentially, and capacitors C2, C3, and C4 are connected in parallel between the gate and source, increasing the total parallel capacitance between the gate and source to C1+C2, C1+C2+C3, and C1+C2+C3+C4. The technical effect of the parallel capacitor dynamic switching circuit is mainly reflected in the step-like increase of the parallel capacitance between the gate and source of the SiC MOSFET as the overload level increases. During turn-off, it can significantly suppress gate crosstalk voltage spikes and slow down the rate of gate voltage decline. Combined with the -2V turn-off negative voltage switched by the drive circuit, it makes the turn-off process smoother and jointly suppresses the turn-off overvoltage caused by high di / dt.

[0043] like Figure 3 As shown, the adaptive active drive control method for SiC power semiconductor modules provided in this embodiment of the invention includes:

[0044] S1, the system acquires the drain current signal of the power device in real time through the current sampling circuit and converts it into a voltage signal Vmode;

[0045] S2, Vmode is input to the control signal generation circuit. This circuit is based on a multi-channel hysteresis comparator, which classifies the current by preset multi-level thresholds and outputs the corresponding control signal according to the identified overload level.

[0046] S3, the control signal is sent to the drive circuit and the parallel capacitor dynamic switching circuit respectively. The drive circuit is used to switch the turn-off negative voltage from -5V to -2V under strong overload conditions. The parallel capacitor dynamic switching circuit is used to sequentially switch gate-source parallel capacitors of different capacitance values ​​according to the degree of overload.

[0047] S4, through the synergistic effect of turn-off negative voltage regulation and parallel capacitor switching, effectively suppresses turn-off overvoltage and gate crosstalk under strong overload conditions.

[0048] This voltage-capacitor hybrid adaptive active drive technology is applicable to the synergistic suppression of turn-off overvoltage and gate crosstalk in SiC MOSFETs under strong overload conditions. The following describes the specific operation of the C3M0075120K1 (1200V withstand voltage) device under strong overload conditions of 2-5 times the rated current (64A to 160A). This device has a rated current of 32A. Under a 600V bus voltage, a strong overload condition causes a sharp increase in the rate of change of current (di / dt). The induced voltage generated by the interaction of the circuit parasitic inductance and the high di / dt significantly increases. Traditional fixed gate resistance drive schemes struggle to suppress turn-off overshoot under strong overload conditions. This solution, however, effectively suppresses turn-off overvoltage and crosstalk by dynamically adjusting the turn-off negative voltage and staged switching of parallel capacitors, ensuring reliable device operation.

[0049] The hardware configuration needs to be specifically designed for the characteristics of the C3M0075120K1. The current sampling circuit uses a 1mΩ manganese copper sampling resistor (accuracy ±1%), and the operational amplifier is an ADA4807-1 (gain-bandwidth product 180MHz), which, together with 24.9kΩ and 1kΩ thick film resistors (accuracy ±0.1%), achieves a fixed gain amplification of 25 times. The control signal generation circuit uses a five-channel TLV3501 high-speed hysteresis comparator (propagation delay 4.5ns), operating in a 5V single-supply mode. Its threshold voltage is precisely set according to the transfer function Vmode = Id × 0.001 × 25 of the current sampling circuit: when the drain current is twice the rated value (64A), the theoretical value of Vmode is 1.6V; when the current is three times the rated value (96A), the theoretical value of Vmode is 2.4V; when the current is four times the rated value (128A), the theoretical value of Vmode is 3.2V; and when the current is five times the rated value (160A), the theoretical value of Vmode is 4.0V. The threshold voltage is set accordingly. = =1.6V, =2.4V, =3.2V, =4.0V, all comparators are configured with 0.1V hysteresis to enhance noise immunity. and All voltage levels are set to 1.6V. When a 2x overload is detected, the high-level output of comparator CP1 is dedicated to controlling the shutdown of the negative voltage switching of the drive circuit, while the high-level output of comparator CP2 is dedicated to controlling the connection of the first-stage parallel capacitor C1. Each comparator is equipped with a ±0.1V hysteresis voltage to enhance anti-interference capability, and all thresholds are within the comparator's allowable 0-5V input range. The drive circuit uses a three-channel isolated DC / DC power supply module to provide +15V, -5V, and -2V voltages. The push-pull output stage uses the SI8235 isolated driver chip, and the negative voltage switching switch uses an FDMC8622 MOSFET. The parallel capacitor dynamic switching circuit uses a four-stage C0G ceramic capacitor array: C1=1nF, C2=2.2nF, C3=4.7nF, C4=10nF, and the switching transistor connected in series with each capacitor is an FDMC8610 MOSFET.

[0050] The implementation process first involved setting up a dual-pulse test circuit. A current sampling resistor was connected in series with the source of the C3M0075120K1. The output of the control signal generation circuit was connected to the drive circuit and the capacitor switching switch. The parallel capacitor branch was directly connected between the gate and source of the device. A standard current signal was injected using a high-precision programmable current source for system calibration, ensuring that at four key current points (64A, 96A, 128A, and 160A), the sampled output Vmode was 1.6V±2%, 2.4V±2%, 3.2V±2%, and 4.0V±2%, respectively, with each comparator triggering error less than ±3%. After calibration, continuous testing was initiated at a 600V bus voltage, with the switching frequency set to 100kHz. The device initially operated at its rated current of 32A, at which point Vmode was approximately 0.8V, below all thresholds. The drive circuit output a -5V turn-off negative voltage, all capacitor switches were disconnected, and the system entered a high-efficiency operating mode.

[0051] After stable operation, the device was brought into a 2x overload condition (64A) via the electronic load module and operated continuously for 200ms. At this time, Vmode rose above 1.6V, and the first and second comparators in the control signal generation circuit simultaneously output high levels. The high level output of comparator CP1 drove the negative voltage switching circuit to turn off S2 and turn on S1, switching the turn-off negative voltage from -5V to -2V; the high level output of comparator CP2 drove Q1 to turn on, connecting C1 (1nF) in parallel between the gate and source. In actual operation, the peak turn-off voltage dropped from 780V in the traditional fixed 10Ω gate resistor scheme to 620V, a reduction of 20.5%, and the peak-to-peak gate crosstalk voltage dropped from 10V to below 3.5V.

[0052] The load was then changed to put the device into a 3x overload condition (96A), running for 200ms. At this time, Vmode reached 2.4V, triggering comparator CP3 to output a high level. This signal drove Q2 to conduct, connecting C2 (2.2nF) in parallel between the gate and source, increasing the total parallel capacitance between the gate and source to 3.2nF. Under the combined effect of the -2V turn-off negative voltage and the parallel capacitance, the turn-off voltage spike was suppressed to around 690V, which is only 57.5% of the device's rated withstand voltage.

[0053] The load was further increased to 4 times the overload condition (128A). When Vmode reached 3.2V, the comparator CP4 was triggered to output a high level, driving Q3 to conduct and connect C3 (4.7nF). The total parallel capacitance between the gate and source reached 7.9nF. At this time, the turn-off voltage spike stabilized below 800V (66.7% of the device's withstand voltage), and the overshoot waveform was smooth without oscillation.

[0054] Finally, under a 5x overload condition (160A), Vmode reached 4.0V, triggering comparator CP5 to output a high level, driving Q4 to conduct and connecting C4 (10nF). The total parallel capacitance between the gate and source reached 17.9nF. Under this condition, traditional fixed gate resistor solutions suffer from avalanche breakdown due to turn-off voltage spikes exceeding 1300V. However, this solution successfully limited the turn-off voltage spike to 880V, which is 73.3% of the device's withstand voltage, and suppressed the gate crosstalk voltage to below 2.5V.

[0055] Comparative experimental data shows that the traditional 10Ω fixed gate resistor scheme achieves a turn-off transient peak voltage of over 1300V under 5 times overload, significantly exceeding the device's withstand voltage and causing device breakdown. In contrast, this scheme can suppress the turn-off overvoltage to within 900V under a full range of overload conditions from 2 to 5 times, with the highest value being only 73.3% of the device's withstand voltage. System response time measurements show that the entire process delay from current sampling to capacitor connection is less than 50ns, enabling adaptive adjustment within a single switching cycle (10μs).

[0056] This implementation scheme achieves dynamic adaptation of the C3M0075120K1 within a strong overload range of 64A to 160A through a collaborative mechanism of five-level overload identification, adaptive negative voltage switching, and four-level capacitor dynamic switching. Test data demonstrates that this scheme can suppress turn-off overvoltage to below 75% of the device's withstand voltage under 2-5 times overload conditions, while reducing gate crosstalk by more than 65%, without affecting normal operating efficiency. This provides effective assurance for the reliable operation of SiC MOSFETs during system fault transients.

[0057] An application embodiment of the present invention provides a computer device, which includes a memory and a processor. The memory stores a computer program, and when the computer program is executed by the processor, the processor performs the steps of an adaptive active drive control method for a SiC power semiconductor module.

[0058] An application embodiment of the present invention provides a computer-readable storage medium storing a computer program, which, when executed by a processor, causes the processor to perform the steps of an adaptive active drive control method for a SiC power semiconductor module.

[0059] An application embodiment of the present invention provides an information data processing terminal, which includes an adaptive active drive for a SiC power semiconductor module.

[0060] Evidence related to the technical effects obtained by the embodiments of the present invention:

[0061] The technical effects achieved by the embodiments of the present invention can be theoretically supported from three aspects: the core physical mechanism of shutdown transients, the dynamic adaptability of hierarchical control strategies, and the inherent reliability of the fully analog hardware architecture.

[0062] At the physical mechanism level, turn-off overvoltage originates from the release of stored energy by the parasitic inductance of the power circuit when the current drops sharply, while gate crosstalk is caused by displacement current injected into the gate due to the rapidly changing drain-source voltage coupled through Miller capacitance. This invention directly intervenes in the above process by adaptively switching the turn-off negative voltage: switching the negative voltage from -5V to a higher -2V essentially reduces the amplitude of the drive voltage of the gate discharge circuit, thereby effectively slowing down the rate of gate potential decline and suppressing the rate of change of drain current di / dt. According to ΔV = Lσ × di / dt, the reduction of di / dt directly and proportionally suppresses the turn-off overvoltage spike, forming the first active mechanism for overvoltage suppression. Meanwhile, the dynamically switched parallel capacitor reshapes the gate transient response in two ways: First, the capacitor is directly connected in parallel between the gate and source, increasing the total capacitance of the gate node to ground and providing a low-impedance shunt path for the displacement current coupled by Miller capacitance, significantly attenuating the amplitude of the crosstalk voltage formed on the gate; second, the increased gate-source capacitance further helps to slow down the slope of the gate voltage change, working in conjunction with the adjusted turn-off negative voltage to form a second auxiliary mechanism for suppressing di / dt. These two mechanisms together constitute the composite physical basis for the synergistic suppression of turn-off overvoltage and gate crosstalk.

[0063] The hierarchical control strategy fundamentally enhances the system's flexibility and adaptability in handling complex overload conditions. Its core advantage lies in establishing a dynamic mapping relationship between "overload level" and "suppression parameters," achieving precise adaptation throughout the entire process from detection to execution. Traditional fixed-parameter driven schemes, when facing varying overload currents, employ a singular and rigid suppression strategy, unable to distinguish between minor overloads and severe faults, often falling into the dilemma of "insufficient suppression leading to risk" or "excessive suppression affecting dynamic response." This invention, by introducing a multi-threshold hysteresis comparator, constructs a real-time, fine-grained overload state perception layer. The system can distinguish different overload levels from 2 to 5 times the rated current and trigger differentiated composite responses accordingly. Specifically, upon detecting an overload, the system does not immediately activate the strongest suppression measures, but rather adjusts the shutdown negative voltage level in a stepwise manner and gradually adds gate-source parallel capacitors based on the severity of the overload. This "level-by-level matching and progressive reinforcement" mechanism gives the system unprecedented control flexibility.

[0064] The all-analog hardware implementation architecture provides an indispensable guarantee of reliability for the superior performance of this solution. Compared to solutions that rely on digital processors and complex software algorithms, the pure analog control loop has a deterministic nanosecond-level response delay, perfectly matching the high-speed switching transients of SiC MOSFETs. This ensures that every protection action is completed within a defined physical time, avoiding the unpredictable microsecond-level delays caused by sampling, calculation, and task scheduling in digital systems. Furthermore, since the system functions are entirely implemented in hardware circuitry, potential failure modes such as software crashes and memory overflows are eliminated. Its reliability is directly determined by the lifespan and inherent properties of the hardware components. This inherent simplicity and determinism provide crucial protection for high-reliability power drive scenarios.

[0065] This invention not only effectively suppresses the two key stress sources—di / dt and gate coupling coefficient—in principle, but also achieves dynamic optimal control through a hierarchical strategy, and ensures extreme speed and reliability through fully analog hardware. Theoretical analysis shows that its technical effects are inevitable and universal, and can systematically solve the dynamic reliability challenges faced by SiC MOSFETs under strong overload conditions.

[0066] Example 1: Basic Structure Implementation

[0067] This embodiment constructs a voltage-capacitor hybrid adaptive active gate driving system, including a current sampling unit, a control signal generation unit, a driving unit, and a parallel capacitor dynamic switching unit. The current sampling unit obtains the source current of the power device through a sampling resistor and converts it into a voltage signal Vmode. The control signal generation unit uses a multi-channel hysteresis comparator structure to hierarchically identify Vmode and outputs control signals for the driving unit and the parallel capacitor unit.

[0068] The drive unit switches different turn-off negative voltages between normal and strong overload conditions according to the control signal. The parallel capacitor dynamic switching unit connects gate-source parallel capacitors of different capacitance values ​​in stages according to the overload level, thereby achieving turn-off overvoltage suppression and crosstalk suppression under abnormal conditions without affecting the normal switching speed.

[0069] Example 2: Implementation of Current Sampling and Signal Generation

[0070] In this embodiment, the current sampling unit connects a sampling resistor in series between the source of the power device and the power ground. The voltage across the sampling resistor serves as an analog quantity reflecting changes in the drain current. After being amplified by a non-inverting amplifier, it forms a Vmode signal which is then sent to the control signal generation unit. This structure enables the system to acquire high-bandwidth current change information without introducing an additional current loop.

[0071] The control signal generation unit adopts a multi-channel hysteresis comparator structure to perform multiple threshold comparisons on the same Vmode signal, forming multiple hierarchical control signals with hysteresis characteristics. This avoids control signal jitter caused by noise near the threshold, thereby ensuring the stability and reliability of the negative voltage switching and capacitor switching process.

[0072] Example 3: Implementation of Adaptive Adjustment for Negative Pressure Shutdown:

[0073] In this embodiment, the drive unit is equipped with two levels of shutdown negative pressure. Under normal operating conditions, a larger shutdown negative pressure is used to ensure rapid and reliable shutdown, while under strong overload conditions, the shutdown negative pressure is switched to a smaller amplitude to slow down the shutdown speed. The selection of the shutdown negative pressure is directly controlled by the control signal output by the control signal generation unit.

[0074] By automatically reducing the shutdown negative voltage when the overload level reaches a set threshold, the rise slope of the shutdown voltage is effectively suppressed, thereby reducing overvoltage spikes caused by parasitic inductance, reducing transient stress on the device, and improving system reliability.

[0075] Example 4: Implementation of parallel capacitor step-by-step adjustment:

[0076] In this embodiment, multiple sets of capacitor-switch series branches are connected in parallel between the gate and source of the power device, with the capacitance value of each branch increasing sequentially. The control signal generation unit drives the corresponding switches to turn on sequentially according to the overload level, so that the total parallel capacitance increases in a stepwise manner.

[0077] Under normal operating conditions, no parallel capacitors are involved, so the switching speed is not affected. When the overload deepens, larger capacitors are gradually added in parallel to effectively reduce the gate voltage change rate, thereby suppressing turn-off overvoltage and gate crosstalk, and realizing flexible control of abnormal states.

[0078] Example 5: Coordinated Implementation of Negative Pressure Regulation and Capacitor Regulation:

[0079] This embodiment combines negative voltage regulation with parallel capacitor regulation, rather than using either method alone. When the system detects a primary overload, it prioritizes switching off the negative voltage, and as the overload worsens, it gradually connects the parallel capacitors.

[0080] This collaborative mechanism avoids the problem of incomplete shutdown that may be caused by simply reducing the negative voltage, and also avoids the problem of significantly increasing switching losses due to simply increasing the capacitor, thus achieving a balance between protection effect and efficiency in the system.

[0081] Example 6: Hysteresis and Anti-interference Implementation:

[0082] In this embodiment, a fixed hysteresis is set in each comparison channel so that the comparator can only switch the output after the input signal crosses the threshold, thus avoiding frequent switching due to noise and ripple when the current is close to the threshold.

[0083] This hysteresis mechanism ensures that the negative voltage switching and capacitor switching processes have clear trigger boundaries, improves the stability of the system in high-frequency and high-interference environments, and prevents unnecessary power consumption and device stress caused by false triggering.

[0084] Example 7 Method Flow Implementation:

[0085] In this embodiment, the system periodically acquires the drain current and generates Vmode, performs multi-level comparisons on Vmode to identify the overload level, outputs the corresponding control signal according to the level, and simultaneously adjusts the shutdown negative voltage and parallel capacitor configuration to ultimately suppress abnormal operating conditions.

[0086] This process can run continuously in each switching cycle without relying on an external control system. It can adaptively adjust the drive state of power devices in real time to achieve online protection and optimization.

[0087] Example 8: Engineering Application Implementation:

[0088] This embodiment applies the drive system to a high-frequency, high-power conversion system, operating under conditions of large load changes and short-term overload. Actual measurements show that the turn-off overvoltage is significantly reduced at the moment of overload, and the gate voltage oscillation is significantly weakened.

[0089] The system maintains its original switching speed and efficiency under normal load and automatically enters protection and regulation state under abnormal load, achieving a balance between performance and reliability, and is suitable for applications with high power density and high reliability requirements.

[0090] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any modifications, equivalent substitutions, and improvements made by those skilled in the art within the scope of the technology disclosed in the present invention, and within the spirit and principles of the present invention, should be covered within the scope of protection of the present invention.

Claims

1. An adaptive active drive for a SiC power semiconductor module, comprising a current sampling circuit, a control signal generation circuit, a drive circuit, and a parallel capacitor dynamic switching circuit, wherein: The current sampling circuit is used to convert the drain current of the power device into a voltage signal Vmode. The control signal generation circuit is used to perform multi-level threshold comparisons on Vmode and output hierarchical control signals. The drive circuit is used to switch the power device's turn-off negative voltage according to the control signal; The parallel capacitor dynamic switching circuit is used to adjust the equivalent capacitance value between the gate and source of the power device according to the control signal. The driving circuit and the parallel capacitor dynamic switching circuit work together to suppress turn-off overvoltage and gate crosstalk under overload conditions. The current sampling circuit includes a sampling resistor Rs connected in series between the source of the power device and the power ground. The voltage drop across Rs is used as an input signal and connected to the non-inverting input of the operational amplifier. The operational amplifier forms a non-inverting proportional amplifier circuit, and its output generates a voltage signal Vmode, which is sent to the control signal generation circuit.

2. A control signal generation and negative pressure switching system for active drive as described in claim 1, characterized in that: It includes multiple hysteresis comparators, with each hysteresis comparator receiving Vmode at its non-inverting input and receiving different threshold voltages at its inverting input. The threshold voltages are set in increments according to the overload level. When Vmode exceeds the set threshold, a corresponding level of control signal is output, where the first level control signal is used to control the drive circuit to switch off the negative voltage.

3. The system according to claim 2, characterized in that: It is equipped with 5 hysteresis comparators, and the threshold voltage is triggered step by step according to 2 times, 3 times, 4 times and 5 times the rated value of the drain current of the power device. The hysteresis is set to 0.1 volts, and when an overload is detected, the switching off negative voltage is switched from -5 volts to -2 volts.

4. A parallel capacitor dynamic switching circuit for active driving as described in claim 1, characterized in that: It includes multiple sets of capacitor-switch series branches connected in parallel between the gate and source of the power device. The capacitance value of each branch increases sequentially. The switch control terminal of each branch receives graded control signals from the control signal generation circuit, which are used to connect the corresponding capacitors in parallel according to the overload level.

5. The circuit according to claim 4, characterized in that: The capacitance values ​​are 1 nanofarad, 2.2 nanofarad, 4.7 nanofarad, and 10 nanofarad, respectively. Under normal operating conditions, all switches are turned off. When the overload level is increased, the corresponding capacitors are connected in parallel between the gate and source.

6. A control method based on the active drive as described in claim 1, characterized in that... include: S1 acquires the drain current of the power device and generates Vmode; S2 performs multi-level threshold comparisons on Vmode and identifies overload levels; S3 switches to shut off the negative voltage and connects the gate-source parallel capacitor step by step according to the overload level. S4 suppresses overvoltage and crosstalk through negative voltage regulation and capacitor switching.

7. The method according to claim 6, characterized in that: When Vmode exceeds the first threshold, the system will shut down the negative voltage and switch it from -5 volts to -2 volts.

8. The method according to claim 6, characterized in that: When Vmode successively exceeds the higher-level threshold, the corresponding switch is turned on in sequence, so that multiple parallel capacitors are stacked between the gate and source in stages.

9. The method according to claim 6, characterized in that: By coordinating the reduction of turn-off negative voltage with the increase of gate-source parallel capacitance, the voltage rise rate of power devices under strong overload conditions is reduced, thereby suppressing turn-off overvoltage and gate crosstalk.

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