Semiconductor devices and their manufacturing methods

Abstract

This application relates to a semiconductor device and a method for manufacturing the same, comprising: providing a substrate; forming a sacrificial layer on the substrate covering non-silicide regions and exposing silicide regions; forming a metal material layer on the substrate within the silicide regions, the metal material layer extending and covering the sacrificial layer, and the metal element of the metal material layer including at least platinum metal; subjecting the metal material layer to rapid thermal processing to form a metal silicide layer; performing a first wet etching process using an SPM solution to remove at least a portion of the metal material layer covering the sacrificial layer; performing a second wet etching process using a phosphoric acid solution to remove a portion of the sacrificial layer, thereby increasing the contact area between the sacrificial layer and the remaining metal material layer; and performing a third wet etching process using a mixed solution of an APM solution and an anionic surfactant to remove the remaining metal material layer. This application improves the efficiency and effectiveness of wet etching processes in removing metal material layers and reduces the risk of residual metal material layers within the semiconductor device.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor device and a method for manufacturing the same. Background Technology

[0002] The fabrication process of self-aligned metal silicides is a key process in semiconductor manufacturing. By fabricating self-aligned metal silicides, the sheet resistance of the gate and active regions can be reduced, thereby improving the performance of semiconductor devices. However, metal silicides are detrimental to electrostatic discharge protection devices (ESD) and high-impedance resistance devices. Therefore, in the fabrication of these devices, it is usually necessary to utilize the property that metals only react with silicon to deposit a self-aligned block (SAB) film in the high-impedance resistance region to form a non-metallic silicide region, thereby preventing the metal from reacting and bonding with silicon.

[0003] After the formation of non-metallic silicide regions, the self-aligned silicide barrier layer is typically removed using a wet etching process to facilitate subsequent fabrication steps. For example, wet etching of nickel-platinum alloys usually requires aqua regia or high-temperature sulfuric acid-hydrogen peroxide solutions as etchants, placing high demands on the wet etching conditions. However, these etchants may not completely clean the nickel-platinum alloy and can easily damage the nickel-silicon compounds generated during the wet etching process. Furthermore, aqua regia or high-temperature sulfuric acid-hydrogen peroxide solutions cause significant environmental pollution, increasing the difficulty and cost of wastewater treatment in wet etching processes. Summary of the Invention

[0004] Therefore, it is necessary to provide a semiconductor device and its manufacturing method that improves the removal efficiency of the metal material layer by wet etching process during the removal of the metal material layer remaining after the formation of the metal silicide layer.

[0005] This application provides a method for manufacturing a semiconductor device, comprising:

[0006] A substrate is provided, and a sacrificial layer is formed on the substrate, the sacrificial layer covering non-silicide regions of the substrate and exposing silicide regions within the substrate;

[0007] A metal material layer is formed on the substrate within the silicide region, the metal material layer extending and covering the sacrificial layer, and the metal element of the metal material layer includes at least platinum metal;

[0008] The metal material layer is subjected to rapid heat treatment to form a metal silicide layer at the junction of the metal material layer and the substrate;

[0009] A first wet etching process using SPM solution is employed to remove at least a portion of the metal material layer covering the sacrificial layer.

[0010] A second wet etching process using phosphoric acid solution is employed to remove part of the sacrificial layer, thereby increasing the contact area between the sacrificial layer and the remaining metal material layer.

[0011] A third wet etching process is performed using a mixture of APM solution and anionic surfactant to remove the remaining metal material layer.

[0012] In one embodiment, the temperature range of the phosphoric acid solution includes 120°C to 160°C.

[0013] In one embodiment, after the second wet etching process, the remaining thickness of the sacrificial layer is 20% to 80% of the total thickness of the sacrificial layer.

[0014] In one embodiment, the anionic surfactant comprises sodium dodecyl sulfate.

[0015] In one embodiment, the sacrificial layer is made of silicon nitride, the metal material layer is made of a nickel-platinum alloy, and the metal silicide layer is made of a nickel-silicon compound.

[0016] In one embodiment, after completing the third wet etching process, the method for manufacturing the semiconductor device further includes:

[0017] Remove the remaining sacrificial layer.

[0018] In one embodiment, after completing the third wet etching process, the method for manufacturing the semiconductor device further includes:

[0019] The metal silicide layer is subjected to rapid heat treatment to reduce the ratio of silicon to metal in the metal silicide layer.

[0020] In one embodiment, the process of forming the sacrificial layer includes:

[0021] A sacrificial layer is formed on the substrate;

[0022] A patterned photoresist layer is formed on the sacrificial layer, exposing a portion of the sacrificial layer located within the silicide region.

[0023] The sacrificial layer is etched using the photoresist layer as a mask, so that the sacrificial layer covers the non-silicide region and exposes the substrate in the silicide region.

[0024] In one embodiment, prior to forming the sacrificial layer on the substrate, the method of manufacturing the semiconductor device further includes:

[0025] When an oxide layer is formed on the substrate, the sacrificial layer is formed on the oxide layer;

[0026] Using the photoresist layer as a mask, the portion of the sacrificial layer and the oxide layer located within the silicide region is etched to expose the substrate within the silicide region.

[0027] Accordingly, this application also provides a semiconductor device manufactured using the semiconductor device manufacturing method described above.

[0028] An unexpected effect of this application is that by forming a sacrificial layer on the substrate that covers the non-silicide region and exposes the silicide region, the portion of the metal material layer located in the non-silicide region is formed on the side of the sacrificial layer away from the substrate. This ensures that other semiconductor structures covered by the sacrificial layer in the non-silicide region are not damaged by etching during subsequent wet etching processes. After forming the metal silicide layer in the silicide region, the remaining metal material layer and part of the sacrificial layer are removed by three wet etching processes to ensure that the metal material layer in the non-silicide region is completely removed. This improves the efficiency and effectiveness of the wet etching process in removing the metal material layer and reduces or avoids the risk of residual metal material layers in the semiconductor device after the wet etching process. Attached Figure Description

[0029] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0030] Figure 1 A flowchart illustrating a method for manufacturing a semiconductor device according to one embodiment of this application.

[0031] Figure 2 This is a schematic diagram of the structure corresponding to the step of providing a substrate and forming a sacrificial layer on the substrate in a method for manufacturing a semiconductor device according to one embodiment of this application.

[0032] Figure 3 This is a schematic diagram of the structure corresponding to the step of patterning the sacrificial layer in the manufacturing method of a semiconductor device provided in one embodiment of this application.

[0033] Figure 4This is a schematic diagram of the structure corresponding to the step of forming a metal material layer on a substrate in a method for manufacturing a semiconductor device according to one embodiment of this application.

[0034] Figure 5 This is a schematic diagram of the structure corresponding to the step of forming a metal silicide layer at the junction of a metal material layer and a substrate in a method for manufacturing a semiconductor device according to one embodiment of this application.

[0035] Figure 6 This is a schematic diagram of the structure corresponding to the first wet etching process in the manufacturing method of a semiconductor device provided in one embodiment of this application.

[0036] Figure 7 This is a schematic diagram of the structure corresponding to the step of the second wet etching process in the manufacturing method of a semiconductor device provided in one embodiment of this application.

[0037] Figure 8 This is a schematic diagram of the structure corresponding to the third wet etching process in the manufacturing method of a semiconductor device provided in one embodiment of this application.

[0038] The reference numerals in the figures include: 100-substrate; 101-oxide layer; 110-sacrificial layer; 111-photoresist layer; 112-recess; 120-metal material layer; 121-metal silicide layer; X1-silicide region; X2-non-silicide region. Detailed Implementation

[0039] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0040] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application.

[0041] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this application, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0042] Spatial relation terms such as “below,” “under,” “below,” “below,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, an element or feature described as “below,” “below,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0043] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.

[0044] Figure 1 A flowchart illustrating a method for manufacturing a semiconductor device according to one embodiment of this application. See also... Figure 1 One embodiment of this application provides a method for manufacturing a semiconductor device, which includes the following steps S01 to S06.

[0045] Step S01: Provide a substrate and form a sacrificial layer on the substrate, the sacrificial layer covering the non-silicide regions of the substrate and exposing the silicide regions within the substrate.

[0046] It should be noted that by forming a sacrificial layer that covers the non-silicide region and exposes the silicide region, other semiconductor structures in the non-silicide region can be protected during the formation of the metal silicide layer. This reduces or even avoids the negative impact of related process steps during the formation of the metal silicide layer on other semiconductor structures in the non-silicide region, thereby helping to improve the yield and stability of the final semiconductor device.

[0047] Step S02: A metal material layer is formed on the substrate within the silicide region, the metal material layer extending and covering the sacrificial layer, and the metal element of the metal material layer includes at least platinum metal.

[0048] Step S03: Perform rapid heat treatment on the metal material layer to form a metal silicide layer at the junction of the metal material layer and the substrate.

[0049] Step S04: Perform a first wet etching process using an SPM solution to remove at least part of the metal material layer covering the sacrificial layer.

[0050] It should be noted that, due to the limited reactivity of SPM solution (i.e., a mixture of sulfuric acid and hydrogen peroxide) with platinum metal (Pt), a metal material layer will still remain on the surface of the sacrificial layer after the first wet etching process. Furthermore, if a residual metal material layer exists on the metal silicide layer within the silicide region, at least a portion of the remaining metal material layer on the metal silicide layer will also be removed during the first wet etching process.

[0051] Step S05: A second wet etching process is performed using a phosphoric acid solution to remove part of the sacrificial layer, thereby increasing the contact area between the sacrificial layer and the remaining metal material layer.

[0052] It should be noted that during the second wet etching process using phosphoric acid solution, the platinum metal in the remaining metal material layer on the sacrificial layer can act as a catalyst during the removal of the sacrificial layer, resulting in a higher etching rate for the portion of the sacrificial layer located below the metal material layer, thereby helping to increase the contact area between the sacrificial layer and the remaining metal material layer.

[0053] Step S06: A third wet etching process is performed using a mixture of APM solution and anionic surfactant to remove the remaining metal material layer.

[0054] It should be noted that the APM solution is a mixture of ammonia, hydrogen peroxide, and deionized water. The third wet etching process provides an alkaline APM solution environment, making the zeta potential (a key parameter characterizing the charge state of particles in a liquid, reflecting the electrostatic stability of Kluwer and the strength of interactions between particles) negatively charged between the remaining metal material layer and the sacrificial layer. This results in electrostatic repulsion between the remaining metal material layer and the sacrificial layer. Simultaneously, because the second wet etching process in step S05 increases the contact area between the sacrificial layer and the remaining metal material layer, the increased contact area leads to an increase in the amount of anionic surfactant adsorbed on the surface of the metal material layer (anionic surfactants can adsorb on the surface of the metal material layer and provide a negative charge). This correspondingly increases the electrostatic repulsion between the metal material layer and the sacrificial layer, thereby improving the efficiency and effectiveness of the third wet etching process in removing the metal material layer.

[0055] As can be seen, the semiconductor device manufacturing method described above forms a sacrificial layer on a substrate that covers the non-silicide region and exposes the silicide region. This allows the portion of the metal material layer located in the non-silicide region to be formed on the side of the sacrificial layer away from the substrate. This ensures that other semiconductor structures covered by the sacrificial layer in the non-silicide region are not damaged by etching during subsequent wet etching processes. After forming the metal silicide layer in the silicide region, the remaining metal material layer and part of the sacrificial layer are removed by a three-stage wet etching process. This ensures that the metal material layer in the non-silicide region is completely removed, improving the efficiency and effectiveness of the wet etching process in removing the metal material layer and reducing or avoiding the risk of residual metal material layers in the semiconductor device after the wet etching process.

[0056] See Figure 2 and Figure 3 In one embodiment, a substrate 100 is provided, and a sacrificial layer 110 is formed on the substrate 100. The sacrificial layer 110 covers a non-silicide region X2 of the substrate 100 and exposes a silicide region X1 within the substrate 100. Optionally, the substrate 100 is made of silicon (Si), and the sacrificial layer 110 is made of silicon nitride (SiN). Optionally, an oxide layer 101 is also formed between the substrate 100 and the sacrificial layer 110 within the non-silicide region X2.

[0057] Continue reading Figure 2 and Figure 3In one embodiment, the formation process of the sacrificial layer 110 includes: forming the sacrificial layer 110 on the substrate 100; forming a patterned photoresist layer 111 on the sacrificial layer 110, exposing a portion of the sacrificial layer 110 located within the silicide region X1; and etching the sacrificial layer 110 using the photoresist layer 111 as a mask, so that the sacrificial layer 110 covers the non-silicide region X2 and exposes the substrate 100 within the silicide region X1. It should be noted that when an oxide layer 101 is formed on the substrate 100, the sacrificial layer 110 is formed on the oxide layer 101, and during the etching process of the sacrificial layer 110 using the photoresist layer 111 as a mask, the portion of the oxide layer 101 located within the silicide region X1 is removed along with it, thereby exposing the substrate 100 within the silicide region X1 for subsequent metal silicide layer fabrication processes.

[0058] See Figure 3 In one embodiment, after etching the sacrificial layer 110 using the photoresist layer 111 as a mask, the semiconductor device manufacturing method further includes removing the photoresist layer 111. Optionally, the photoresist layer 111 is removed using an ashing process and a wet cleaning process.

[0059] See Figure 4 In one embodiment, a metal material layer 120 is formed on a substrate 100 within a silicide region X1. The metal material layer 120 extends and covers the sacrificial layer 110, and the metal element of the metal material layer 120 includes at least platinum (Pt). Optionally, the material of the metal material layer 120 includes a nickel-platinum alloy (NiPt).

[0060] See Figure 5 In one embodiment, the metal material layer 120 is subjected to rapid thermal processing (RPT) to form a metal silicide layer 121 at the junction of the metal material layer 120 and the substrate 100. Optionally, when the substrate 100 is a silicon substrate and the metal material layer 120 is a nickel-platinum alloy, the metal silicide layer 121 is a nickel silicide layer.

[0061] See Figure 6 In one embodiment, an SPM solution is used for a first wet etching process to remove at least part of the metal material layer 120 covering the sacrificial layer 110. It should be noted that, since SPM has limited reactivity with platinum (Pt), some metal material layer 120 will still remain on the surface of the sacrificial layer 110 after the first wet etching process.

[0062] In one embodiment, there may also be a residual metal material layer on the metal silicide layer in the silicide region. In this case, at least a portion of the residual metal material layer on the metal silicide layer will also be removed during the first wet etching process.

[0063] See Figure 7 In one embodiment, a second wet etching process using a phosphoric acid solution is employed to remove a portion of the sacrificial layer 110, thereby increasing the contact area between the sacrificial layer 110 and the remaining metal material layer 120. Optionally, the temperature range of the phosphoric acid solution includes 120°C to 160°C. Optionally, after the second wet etching process, the remaining thickness of the sacrificial layer is 20% to 80% of the total thickness of the sacrificial layer.

[0064] It is important to emphasize that during the second wet etching process using phosphoric acid solution, the platinum metal in the metal layer can act as a catalyst during the removal of the sacrificial layer, resulting in a higher etching rate for the portion of the sacrificial layer located below the metal layer. This helps to increase the contact area between the sacrificial layer and the remaining metal layer. For example, see [link to relevant documentation]. Figure 7 Since the etching rate of the sacrificial layer 110 located below the metal material layer 120 is faster, a recess 112 is formed in the portion of the sacrificial layer 110 located below the metal material layer 120, so that the remaining metal material layer 120 is embedded in the recess 112, thereby increasing the contact area between the sacrificial layer 110 and the metal material layer 120.

[0065] See Figure 8 In one embodiment, a third wet etching process is performed using a mixture of APM solution and an anionic surfactant to remove the remaining metal material layer 120. Optionally, the anionic surfactant includes sodium dodecyl sulfate (SDS).

[0066] It is important to emphasize that the third wet etching process provides an alkaline APM solution environment, making the zeta potential between the remaining metal layer (i.e., platinum metal residue) and the sacrificial layer negatively charged, thus creating electrostatic repulsion between them. Simultaneously, because the second wet etching process increases the contact area between the sacrificial layer and the remaining metal layer, the amount of anionic surfactants adsorbed on the surface of the metal layer increases (anionic surfactants can adsorb on the surface of the metal layer and provide a negative charge), and the electrostatic repulsion between the metal layer and the sacrificial layer also increases accordingly. This improves the efficiency and effectiveness of the third wet etching process in removing the metal layer.

[0067] In one embodiment, after completing the third wet etching process, the semiconductor device manufacturing method further includes removing the remaining sacrificial layer to facilitate subsequent process steps in the non-silicide region.

[0068] In one embodiment, after completing the third wet etching process, the semiconductor device manufacturing method further includes: performing rapid thermal processing (RPT) on the metal silicide layer to reduce the ratio of silicon to metal in the metal silicide layer. For example, when the metal silicide layer is a nickel silicide, performing rapid thermal processing on the metal silicide layer can reduce the ratio of silicon to nickel in the nickel silicide layer, for example, converting it from NiSi2 to NiSi.

[0069] Accordingly, this application also provides a semiconductor device manufactured using the semiconductor device manufacturing method described above, to improve the yield and performance stability of the semiconductor device. In other embodiments of this application, other semiconductor devices with the same or similar structures can also be manufactured using the semiconductor device manufacturing method described above, and this application does not impose any limitations on this.

[0070] An unexpected effect of this application is that by forming a sacrificial layer on the substrate that covers the non-silicide region and exposes the silicide region, the portion of the metal material layer located in the non-silicide region is formed on the side of the sacrificial layer away from the substrate. This ensures that other semiconductor structures covered by the sacrificial layer in the non-silicide region are not damaged by etching during subsequent wet etching processes. After forming the metal silicide layer in the silicide region, the remaining metal material layer and part of the sacrificial layer are removed by three wet etching processes to ensure that the metal material layer in the non-silicide region is completely removed. This improves the efficiency and effectiveness of the wet etching process in removing the metal material layer and reduces or avoids the risk of residual metal material layers in the semiconductor device after the wet etching process.

[0071] In the description of this specification, the references to terms such as "some embodiments," "other embodiments," "ideal embodiments," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example that are included in at least one embodiment or example of this application. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0072] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0073] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, include: A substrate is provided, and a sacrificial layer is formed on the substrate, the sacrificial layer covering non-silicide regions of the substrate and exposing silicide regions within the substrate; A metal material layer is formed on the substrate within the silicide region, the metal material layer extending and covering the sacrificial layer, and the metal element of the metal material layer includes at least platinum metal; The metal material layer is subjected to rapid heat treatment to form a metal silicide layer at the junction of the metal material layer and the substrate; A first wet etching process using SPM solution is employed to remove at least a portion of the metal material layer covering the sacrificial layer. A second wet etching process using phosphoric acid solution is employed to remove part of the sacrificial layer, thereby increasing the contact area between the sacrificial layer and the remaining metal material layer. A third wet etching process is performed using a mixture of APM solution and anionic surfactant to remove the remaining metal material layer.

2. The method for manufacturing a semiconductor device according to claim 1, characterized in that, The temperature range of the phosphoric acid solution is 120℃~160℃.

3. The method for manufacturing a semiconductor device according to claim 1, characterized in that, After the second wet etching process, the remaining thickness of the sacrificial layer is 20% to 80% of the total thickness of the sacrificial layer.

4. The method for manufacturing a semiconductor device according to claim 1, characterized in that, The anionic surfactant includes sodium dodecyl sulfate.

5. The method for manufacturing a semiconductor device according to claim 1, characterized in that, The sacrificial layer is made of silicon nitride, the metal material layer is made of a nickel-platinum alloy, and the metal silicide layer is made of a nickel-silicon compound.

6. The method for manufacturing a semiconductor device according to claim 1, characterized in that, After completing the third wet etching process, the method for manufacturing the semiconductor device further includes: Remove the remaining sacrificial layer.

7. The method for manufacturing a semiconductor device according to claim 1, characterized in that, After completing the third wet etching process, the method for manufacturing the semiconductor device further includes: The metal silicide layer is subjected to rapid heat treatment to reduce the ratio of silicon to metal in the metal silicide layer.

8. The method for manufacturing a semiconductor device according to claim 1, characterized in that, The formation process of the sacrificial layer includes: A sacrificial layer is formed on the substrate; A patterned photoresist layer is formed on the sacrificial layer, exposing a portion of the sacrificial layer located within the silicide region. The sacrificial layer is etched using the photoresist layer as a mask, so that the sacrificial layer covers the non-silicide region and exposes the substrate in the silicide region.

9. The method for manufacturing a semiconductor device according to claim 8, characterized in that... Before forming the sacrificial layer on the substrate, the method for manufacturing the semiconductor device further includes: When an oxide layer is formed on the substrate, the sacrificial layer is formed on the oxide layer; Using the photoresist layer as a mask, the portion of the sacrificial layer and the oxide layer located within the silicide region is etched to expose the substrate within the silicide region.

10. A semiconductor device, characterized in that, It is manufactured using the manufacturing method of any one of claims 1 to 9.

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