Cross-clock domain data transmission method, apparatus and semiconductor device

Abstract

This disclosure provides a method, apparatus, and semiconductor device for cross-clock domain data transmission, relating to the field of electronic information technology, particularly to the field of integrated circuit design. The implementation scheme is as follows: based on a reset operation, the rising edge of the clock signal in the first clock domain is aligned with the rising edge of the clock signal in the second clock domain; in a first transmission mode, the first input data is sampled in response to the effective rising edge of the first clock signal, and the sampled data is transmitted to the first target register within the same clock signal period; in a second transmission mode, the first input data is sampled and buffered in response to the effective rising edge of the first clock signal, the buffered first input data remains unchanged within at least one subsequent first clock signal period, and the buffered first input data is read in response to the effective rising edge of the first clock signal and the read data is transmitted to the second target register.

Description

Technical Field

[0001] This disclosure relates to the field of electronic information technology, particularly to the field of integrated circuit design, and especially to a method, apparatus and semiconductor device for cross-clock domain data transmission. Background Technology

[0002] In multi-clock-domain digital systems, different functional modules typically operate under the control of different clock signals. Due to differences in frequency, phase, and period among these clock signals, data integrity must be guaranteed when data needs to be transmitted between different clock domains. Therefore, cross-clock-domain data transmission has become a key technology in integrated circuit design. Existing cross-clock-domain data transmission schemes typically employ methods such as dual-flip-flop synchronous, asynchronous FIFO, or handshake mechanisms. However, these schemes do not fully utilize the timing correlation between clocks when dealing with fast and slow clock domains with fixed frequency multiples, resulting in high hardware resource overhead. Therefore, how to achieve highly efficient data transmission based on actual timing requirements in a cross-clock-domain environment has become an important technical direction. Summary of the Invention

[0003] This disclosure provides a method, apparatus, and semiconductor device for cross-clock domain data transmission.

[0004] According to one aspect of this disclosure, a method for cross-clock domain data transmission is provided, comprising: aligning the rising edge of a first clock signal in a first clock domain with the rising edge of a second clock signal in a second clock domain based on a reset operation, wherein the clock frequency of the first clock signal is an integer multiple of the clock frequency of the second clock signal; in response to transmitting a first input data from the second clock domain to the first clock domain: in a first transmission mode, sampling the first input data in response to a valid rising edge of the first clock signal, and transmitting the sampled data to a first target register within the same clock signal period; in a second transmission mode, sampling and buffering the first input data in response to a valid rising edge of the first clock signal, wherein the buffered first input data remains unchanged within at least one subsequent first clock signal period, and reading the buffered first input data and transmitting the read data in response to a valid rising edge of the first clock signal. The data is input to a second target register, wherein the second transmission mode adds a transmission delay of at least one cycle of the first clock signal compared to the first transmission mode; in response to transmitting the second input data from the first clock domain to the second clock domain, the first quantity is determined by a multiple relationship between the clock frequency of the first clock signal and the clock frequency of the second clock signal: in the first transmission mode, the second input data is sampled in response to the effective rising edge of the second clock signal, and the sampled data is transmitted to a first quantity of third target registers within the same clock signal cycle; and in the second transmission mode, the second input data is sampled and buffered in response to the effective rising edge of the first clock signal, the buffered second input data remains unchanged for at least one subsequent cycle of the first clock signal, and the buffered second input data is read in response to the effective rising edge of the second clock signal and the read data is transmitted to a first quantity of fourth target registers.

[0005] In some embodiments, in response to transmitting the first input data of the second clock domain to the first clock domain, a second number of first input registers are set in the second clock domain, wherein the second number is determined by a multiple relationship between the clock frequency of the first clock signal and the clock frequency of the second clock signal, and each bit of the first input data is transmitted bit by bit to the second number of first input registers.

[0006] In some embodiments, in a first transmission mode, sampling the first input data in response to the effective rising edge of the first clock signal and transmitting the sampled data to the first target register within the same clock signal period includes: sampling a second number of data bits in the first input register bit by bit in response to the effective rising edge of the first clock signal and transmitting the sampled data to the first target register of the first clock domain within the same clock signal period.

[0007] In some embodiments, in the second transmission mode, sampling and buffering first input data in response to the effective rising edge of the first clock signal, wherein the buffered first input data remains unchanged for at least one subsequent period of the first clock signal, and reading the buffered first input data in response to the effective rising edge of the first clock signal and transmitting the read data to the second target register, includes: sampling data in a second number of first input registers bit by bit in response to the effective rising edge of the first clock signal and buffering it in a second number of first intermediate registers, wherein the data state of the second number of first intermediate registers remains unchanged for at least one subsequent period of the first clock signal, and the data in the second number of first input registers has a one-to-one correspondence with the data in the second number of first intermediate registers; and reading data in the second number of first intermediate registers bit by bit in response to the effective rising edge of the first clock signal and transmitting the read data to the second target register in the first clock domain.

[0008] In some embodiments, in response to transmitting a second input data from a first clock domain to a second clock domain, a second input register is set in the first clock domain, and each bit of the second input data is transmitted bit by bit to the second input register.

[0009] In some embodiments, in a first transmission mode, sampling the second input data in response to the effective rising edge of the second clock signal and transmitting the sampled data to a first number of third target registers within the same clock signal period includes: sampling the data in the second input register bit by bit in response to the effective rising edge of the first clock signal and buffering it in a first number of second intermediate registers, wherein the second input register and the first number of second intermediate registers are cascaded, and in the cascaded relationship, the next-level register reads and buffers the data in the previous-level register in response to the effective rising edge of the first clock signal; and reading the data in the first number of second intermediate registers in response to the effective rising edge of the second clock signal, and transmitting the read data to a first number of third target registers in the second clock domain, wherein the data in the first number of third target registers and the data obtained by reading the data in the first number of second intermediate registers have a one-to-one correspondence.

[0010] In some embodiments, in the second transmission mode, sampling and buffering the second input data in response to the effective rising edge of the first clock signal, the buffered second input data remaining unchanged for at least one subsequent period of the first clock signal, and reading the buffered second input data in response to the effective rising edge of the second clock signal and transmitting the read data to a first number of fourth target registers, includes: sampling the data in the second input register bit by bit in response to the effective rising edge of the first clock signal and buffering it in a first number of third intermediate registers respectively, the data state of the first number of third intermediate registers remaining unchanged for at least one subsequent period of the first clock signal; and reading the data in the first number of third intermediate registers bit by bit in response to the effective rising edge of the second clock signal and transmitting the read data to a first number of fourth target registers in the second clock domain, wherein the data in the first number of fourth target registers has a one-to-one correspondence with the data in the first number of third intermediate registers.

[0011] In some embodiments, the cross-clock domain data transmission method further includes: selecting a transmission mode from a first transmission mode and a second transmission mode for data transmission based on at least one of circuit timing convergence state information and hardware operating environment information.

[0012] According to one aspect of this disclosure, a cross-clock domain data transmission apparatus is provided, comprising: a clock alignment module configured to, based on a reset operation, align the rising edge of a first clock signal in a first clock domain with the rising edge of a second clock signal in a second clock domain, wherein the clock frequency of the first clock signal is an integer multiple of the clock frequency of the second clock signal; and, in response to transmitting a first input data from the second clock domain to the first clock domain: a first transmission module configured to, in a first transmission mode, sample the first input data in response to a valid rising edge of the first clock signal, and transmit the sampled data to a first target register within the same clock signal period; and a second transmission module configured to, in a second transmission mode, sample and buffer the first input data in response to a valid rising edge of the first clock signal, wherein the buffered first input data remains unchanged for at least one subsequent first clock signal period, and read the buffered first input data in response to a valid rising edge of the first clock signal and transmit the read data to a first target register. The data is then transmitted to a second target register, wherein the second transmission mode adds a transmission delay of at least one cycle of the first clock signal compared to the first transmission mode; in response to transmitting the second input data from the first clock domain to the second clock domain, the first quantity is determined by a multiple relationship between the clock frequency of the first clock signal and the clock frequency of the second clock signal; a third transmission module is configured to, in the first transmission mode, sample the second input data in response to the effective rising edge of the second clock signal, and transmit the sampled data to the first quantity of third target registers within the same clock signal cycle; and a fourth transmission module is configured to, in the second transmission mode, sample and buffer the second input data in response to the effective rising edge of the first clock signal, wherein the buffered second input data remains unchanged for at least one subsequent cycle of the first clock signal, and read the buffered second input data in response to the effective rising edge of the second clock signal and transmit the read data to the first quantity of fourth target registers.

[0013] According to another aspect of this disclosure, a semiconductor device is provided, comprising: logic circuitry for transmitting data between two clock domains, wherein the clock frequencies of the clock signals of the two clock domains are integer multiples of each other, wherein the logic circuitry transmits data between the two clock domains according to the method provided above in this disclosure.

[0014] According to one or more embodiments of this disclosure, data transmission can be achieved between two clock domains whose clock frequencies are integer multiples of each other.

[0015] These and other aspects of this disclosure will be apparent from the embodiments described below, and will be elucidated with reference to the embodiments described below. Attached Figure Description

[0016] The accompanying drawings exemplify embodiments and form part of the specification, serving together with the textual description to explain exemplary implementations of the embodiments. The illustrated embodiments are for illustrative purposes only and do not limit the scope of this disclosure. Throughout the drawings, the same reference numerals refer to similar but not necessarily identical elements.

[0017] Figure 1 This is a flowchart illustrating a cross-clock domain data transmission method according to an exemplary embodiment.

[0018] Figure 2 This is a schematic diagram illustrating a first transmission mode from a slow clock domain to a fast clock domain according to an exemplary embodiment.

[0019] Figure 3 This is a schematic diagram illustrating a second transmission mode from a slow clock domain to a fast clock domain according to an exemplary embodiment.

[0020] Figure 4 This is a schematic diagram illustrating a first transmission mode from a fast clock domain to a slow clock domain according to an exemplary embodiment.

[0021] Figure 5 This is a schematic diagram illustrating a second transmission mode from a fast clock domain to a slow clock domain according to an exemplary embodiment.

[0022] Figure 6 This is a schematic block diagram illustrating a cross-clock domain data transmission apparatus according to an exemplary embodiment.

[0023] Figure 7 This is a schematic diagram illustrating a semiconductor device according to an exemplary embodiment. Detailed Implementation

[0024] The exemplary embodiments of this disclosure are described below with reference to the accompanying drawings, including various details of the embodiments to aid understanding, and should be considered merely exemplary. Therefore, those skilled in the art will recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope of this disclosure. Similarly, for clarity and brevity, descriptions of well-known functions and structures are omitted in the following description.

[0025] In this disclosure, unless otherwise stated, the use of terms such as "first," "second," etc., to describe various elements is not intended to limit the positional, temporal, or importance relationships of these elements; such terms are merely used to distinguish one element from another. In some examples, the first element and the second element may refer to the same instance of that element, while in other cases, based on the context, they may refer to different instances.

[0026] The terminology used in the description of the various examples described in this disclosure is for the purpose of describing particular examples only and is not intended to be limiting. Unless the context explicitly indicates otherwise, an element may be one or more unless the number of elements is specifically limited. As used herein, the term "multiple" means two or more, and the term "based on" should be interpreted as "at least partially based on". Furthermore, the terms "and / or" and "at least one of..." cover any one of the listed items and all possible combinations thereof.

[0027] In related technologies, with the development of integrated circuit processes and the increasing complexity of on-chip systems, chips typically contain multiple clock domains operating at different frequencies. Cross-clock domain data transmission technology is crucial for enabling data interaction between different clock domains. Existing technologies, to ensure data reliability, usually introduce additional synchronization structures or buffering mechanisms, which can lead to increased data transmission latency and power consumption.

[0028] First, in many practical applications, clock domains are not completely asynchronous but have specific frequency and phase ratios; for example, one clock is derived by dividing another. Existing solutions often treat this as a general asynchronous clock relationship, failing to fully utilize the inherent frequency and phase relationships between clocks. This leads to the introduction of additional waiting cycles or redundant control logic during data transmission, thereby increasing overall latency and hardware resource consumption.

[0029] Secondly, chips face complex changes in the hardware operating environment during actual operation, such as voltage fluctuations and temperature rises. Different systems have different requirements for timing constraints and stability. Existing cross-clock domain solutions lack flexibility in adapting to different operating conditions and cannot balance transmission efficiency and timing stability.

[0030] To address this, embodiments of this disclosure propose a more efficient method for cross-clock domain data transmission. By establishing stable timing relationships between multiple clock domains with frequency multiples, and selecting different data transmission modes based on the system's timing convergence state or hardware environment state, the method provides unified control over data sampling, buffering, and output timing during cross-clock domain transmission. This approach can reduce latency caused by cross-clock domain transmission while meeting data transmission reliability requirements, reduce power consumption, and improve the data transmission efficiency of multi-clock domain digital systems in complex operating environments.

[0031] Exemplary embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0032] Figure 1 This is a flowchart illustrating a cross-clock domain data transmission method according to an exemplary embodiment.

[0033] like Figure 1 As shown, the cross-clock domain data transmission method includes steps S101 to S105.

[0034] In step S101, based on the reset operation, the rising edge of the first clock signal in the first clock domain is aligned with the rising edge of the second clock signal in the second clock domain, wherein the clock frequency of the first clock signal is an integer multiple of the clock frequency of the second clock signal.

[0035] In this example, to ensure the timing controllability of cross-clock domain data transmission, a defined phase relationship between the clock signals of the two clock domains needs to be established first. When the clock frequency of the first clock signal is an integer multiple of the clock frequency of the second clock signal, for example, twice the clock frequency of the second clock signal, a unified reset control signal can be introduced during system power-on or software reset to synchronously reset the clock generation circuits in both the first and second clock domains. This ensures that the first and second clock signals have a defined initial phase relationship upon reset release, thereby aligning the rising edge of the first clock signal with the rising edge of the second clock signal. Since the clock frequency of the first clock signal is an integer multiple of the clock frequency of the second clock signal, after reset, multiple consecutive clock cycles of the first clock signal can form a stable timing correspondence with one clock cycle of the second clock signal. In this way, a fixed timing reference can be established between the two clock domains without introducing complex control logic, providing a defined timing reference for subsequent cross-clock domain data transmission.

[0036] In step S102, in response to transmitting the first input data from the second clock domain to the first clock domain: in the first transmission mode, the first input data is sampled in response to the effective rising edge of the first clock signal, and the sampled data is transmitted to the first target register within the same clock signal period.

[0037] In the example, when the first input data is transferred from the second clock domain to the first clock domain, it signifies a transfer from a slow clock domain to a fast clock domain. Two modes are available. In the first transmission mode, the core objective is to achieve low-latency data transmission. In this mode, in response to the valid rising edge of the first clock signal, the first input data from the second clock domain is sampled. Simultaneously, within the same first clock signal cycle as the sampling, the sampled data is written to the first target register in the first clock domain, thus completing the data transfer process from the second clock domain to the first clock domain. During this process, the control logic remains continuously active without inserting additional wait cycles, allowing the sampled data to be directly transferred to the first target register within the same first clock signal cycle via the combinational logic path.

[0038] In step S103, in response to transmitting the first input data from the second clock domain to the first clock domain: in the second transmission mode, the first input data is sampled and buffered in response to the effective rising edge of the first clock signal, the buffered first input data remains unchanged for at least one subsequent period of the first clock signal, and the buffered first input data is read in response to the effective rising edge of the first clock signal and the read data is transmitted to the second target register, wherein the second transmission mode adds a transmission delay of at least one period of the first clock signal compared to the first transmission mode.

[0039] In the example, when the first input data is transmitted from the second clock domain to the first clock domain, a second transmission mode can be selected to relax the timing convergence requirements for cross-clock domain transmission. In this mode, on the effective rising edge of the first clock signal, the first input data is first sampled and latched into an intermediate buffer unit. Subsequently, the control logic can keep the buffered first input data in an unchanged output state for at least one subsequent first clock signal cycle. During this data holding period, the subsequent circuitry can stably read the buffered data on the effective rising edge of the first clock signal and transmit it to the second target register. This process adds a transmission delay of at least one first clock signal cycle to the second transmission mode compared to the first transmission mode, thereby relaxing the timing constraints of cross-clock domain transmission, reducing the requirements for instantaneous sampling and transmission, and improving the reliability of data transmission in complex scenarios.

[0040] In step S104, in response to transmitting the second input data from the first clock domain to the second clock domain, the first quantity is determined by the multiple relationship between the clock frequency of the first clock signal and the clock frequency of the second clock signal. In the first transmission mode, in response to the effective rising edge of the second clock signal, the second input data is sampled, and the sampled data is transmitted to the first quantity of the third target register within the same clock signal period.

[0041] In the example, when the second input data is transferred from the first clock domain to the second clock domain, it means a transfer from a fast clock domain to a slow clock domain. In the first transmission mode, to maintain the balance of data input and output when the frequency decreases, a multi-bit parallel sampling strategy can be adopted. Specifically, a first number of third target registers can be set in the second clock domain. This number can be determined by the multiple relationship between the clock frequency of the first clock signal and the clock frequency of the second clock signal. For example, if the clock frequency of the first clock signal is twice the clock frequency of the second clock signal, then two third target registers can be set in the second clock domain. In response to the valid rising edge of the second clock signal, the second input data from the first clock domain can be sampled, and within the same second clock signal cycle in which the sampling occurs, the sampled data is transmitted in parallel to the first number of third target registers in the second clock domain, thus enabling multiple sets of data from the first clock domain to be received within one second clock signal cycle.

[0042] In step S105, in response to transferring the second input data from the first clock domain to the second clock domain, the first quantity is determined by the multiple relationship between the clock frequency of the first clock signal and the clock frequency of the second clock signal. In the second transmission mode, in response to the effective rising edge of the first clock signal, the second input data is sampled and buffered. The buffered second input data remains unchanged for at least one subsequent period of the first clock signal. In response to the effective rising edge of the second clock signal, the buffered second input data is read and the read data is transferred to the first quantity of the fourth target register.

[0043] In the example, when the second input data is transferred from the first clock domain to the second clock domain (i.e., from the fast clock domain to the slow clock domain), a second transmission mode can be selected to relax the timing convergence requirements for cross-clock domain transmission. In this mode, a first number of fourth target registers can also be set in the second clock domain. This number can be determined by the multiple relationship between the clock frequency of the first clock signal and the clock frequency of the second clock signal. First, at the effective rising edge of the first clock signal, the second input data from the first clock domain can be sampled and latched into an intermediate buffer unit. Then, control logic keeps the buffered second input data in a constant state for at least one subsequent first clock signal cycle, thereby forming a stable level signal over multiple fast clock cycles. During this data holding period, the receiving logic in the second clock domain reads the stable buffered data at the effective rising edge of the second clock signal and transmits it to the first number of fourth target registers, ultimately enabling the reception of multiple sets of data from the first clock domain within one second clock signal cycle.

[0044] In some embodiments, in response to transmitting the first input data of the second clock domain to the first clock domain, a second number of first input registers are set in the second clock domain, wherein the second number is determined by a multiple relationship between the clock frequency of the first clock signal and the clock frequency of the second clock signal, and each bit of the first input data is transmitted bit by bit to the second number of first input registers.

[0045] In the example, since the operating rate of the fast clock domain is an integer multiple of that of the slow clock domain, it means that within one cycle window of the slow clock domain, the fast clock domain can process that integer multiple of data units. Therefore, on the slow clock domain side, a single-channel data stream can be pre-expanded into multiple parallel data streams matching the frequency multiple, allowing the fast clock domain to fully utilize its frequency characteristics to read these data in subsequent operations. Specifically, the specific number of first input registers can be determined based on the frequency multiple relationship between the first clock signal and the second clock signal. For example, if the clock frequency of the fast clock is four times that of the slow clock, then four parallel input registers can be configured on the slow clock domain side. Subsequently, during the transmission preparation phase, each bit of the first input data is transmitted sequentially to these four first input registers.

[0046] Therefore, this method can fully utilize the frequency multiple relationship between the first clock signal and the second clock signal, providing a data foundation for subsequent sampling and processing based on the first clock signal.

[0047] In some embodiments, in a first transmission mode, sampling the first input data in response to the effective rising edge of the first clock signal and transmitting the sampled data to the first target register within the same clock signal period includes: sampling a second number of data bits in the first input register bit by bit in response to the effective rising edge of the first clock signal and transmitting the sampled data to the first target register of the first clock domain within the same clock signal period.

[0048] In the example, in the first transmission mode, a direct sampling mechanism can be used to achieve fast data transmission from the second clock domain to the first clock domain. In response to a valid rising edge of the first clock signal, the receiving logic of the first clock domain directly samples the data held in the second number of first input registers bit by bit. This operation utilizes the timing window provided by the phase alignment of the two clock domains, allowing the data to pass through the combinational logic path within the same first clock signal cycle without intermediate delay, and ultimately be transmitted to the first destination register in the first clock domain.

[0049] Figure 2 This is a schematic diagram illustrating a first transmission mode from a slow clock domain to a fast clock domain according to an exemplary embodiment.

[0050] like Figure 2 As shown, the clock frequency of the first clock signal is twice the clock frequency of the second clock signal, meaning that the two first input registers can be set in the second clock domain. A reset operation aligns the rising edge of the first clock signal with the rising edge of the second clock signal. The data "A0, A1, B0, B1, C0, C1" are the first input data to be transmitted. Each bit of the first input data is transmitted bit-by-bit to the two first input registers; that is, the data to be transmitted in first input register 1 is "A0, B0, C0", and the data to be transmitted in first input register 2 is "A1, B1, C1". In the first clock domain, the data "A0", "A1", "B0", "B1", "C0", and "C1" can be sampled at the effective rising edge of the first clock signal, and the sampled data is transmitted to the first target register within the same period of the first clock signal. Therefore, the first target register in the first clock domain can receive the data A0, A1, B0, B1, C0, etc., transmitted from the second clock domain.

[0051] Therefore, this method can significantly reduce the latency of cross-clock domain communication while ensuring good circuit timing convergence, thus ensuring that the fast clock domain can acquire data input from the slow clock domain in a timely manner and thereby improving the overall transmission efficiency.

[0052] In some embodiments, in the second transmission mode, sampling and buffering first input data in response to the effective rising edge of the first clock signal, wherein the buffered first input data remains unchanged for at least one subsequent period of the first clock signal, and reading the buffered first input data in response to the effective rising edge of the first clock signal and transmitting the read data to the second target register, includes: sampling data in a second number of first input registers bit by bit in response to the effective rising edge of the first clock signal and buffering it in a second number of first intermediate registers, wherein the data state of the second number of first intermediate registers remains unchanged for at least one subsequent period of the first clock signal, and the data in the second number of first input registers has a one-to-one correspondence with the data in the second number of first intermediate registers; and reading data in the second number of first intermediate registers bit by bit in response to the effective rising edge of the first clock signal and transmitting the read data to the second target register in the first clock domain.

[0053] In the example, for the second transmission mode of transmitting data from the second clock domain (slow clock domain) to the first clock domain (fast clock domain), to relax the timing convergence requirements for cross-clock domain transmission and ensure data transmission stability, a first intermediate register group of the same number (i.e., the second number) as the slow clock domain side can be configured. In response to the valid rising edge of the first clock signal, the parallel data output from the second number of first input registers is first synchronously sampled, and each sampled bit is buffered one-to-one into the second number of first intermediate registers, so that each first input register corresponds to one first intermediate register. After sampling, the control logic can control the data state of the intermediate registers to remain unchanged for at least the next first clock cycle, used to temporarily store the sampled data, thereby establishing a stable data window in the fast clock domain. During this period, multiplexing logic can be used in response to the first clock signal to read these buffered intermediate data bit by bit in a preset order, and then transmit the read data uniformly to the second target register in the first clock domain.

[0054] Figure 3 This is a schematic diagram illustrating a second transmission mode from a slow clock domain to a fast clock domain according to an exemplary embodiment.

[0055] like Figure 3As shown, the clock frequency of the first clock signal is twice the clock frequency of the second clock signal, meaning the two first input registers can be set in the second clock domain. A reset operation aligns the rising edge of the first clock signal with the rising edge of the second clock signal. The data "A0, A1, B0, B1, C0, C1, D0, D1" is the first input data to be transmitted. Each bit of the first input data is transmitted bit-by-bit to the two first input registers; that is, the data to be transmitted in first input register 1 is "A0, B0, C0, D0", and the data to be transmitted in first input register 2 is "A1, B1, C1, D1". In the first clock domain, the data in the two first input registers can be sampled at the effective rising edge of the first clock signal, and the data is transmitted one-to-one to the two first intermediate registers. Specifically, the data in first input register 1 is sampled and transmitted to first intermediate register 1, and the data in first input register 2 is sampled and transmitted to first intermediate register 2. Simultaneously, the control logic can ensure that the data states of the two first intermediate registers remain unchanged for at least the next first clock cycle. Finally, in response to the first clock signal, the multiplexing logic can be used to read these buffered intermediate data bit by bit in the order of reading first intermediate register 1 first and then first intermediate register 2, and transmit the read data to the second target register of the first clock domain. That is, the second target register of the first clock domain can receive data A0, A1, B0, B1, C0, etc. transmitted from the second clock domain.

[0056] Therefore, the second transmission mode described above can introduce a deterministic timing buffer using intermediate registers, relax the timing convergence requirements for cross-clock domain transmission, and thus improve the stability of data transmission.

[0057] In some embodiments, in response to transmitting a second input data from a first clock domain to a second clock domain, a second input register is set in the first clock domain, and each bit of the second input data is transmitted bit by bit to the second input register.

[0058] In the example, in the scenario of transmitting data from the first clock domain (fast clock domain) to the second clock domain (slow clock domain), to standardize the signal timing at the transmitting end, a second input register can be specifically configured on the first clock domain side for transmitting the second input data. Specifically, each bit of the second input data can be transmitted sequentially into the second input register.

[0059] Therefore, by setting the second input register in the first clock domain, the input data can be sorted bit by bit before the data is transmitted across clock domains, providing a stable data source for subsequent data sampling.

[0060] In some embodiments, in a first transmission mode, sampling the second input data in response to the effective rising edge of the second clock signal and transmitting the sampled data to a first number of third target registers within the same clock signal period includes: sampling the data in the second input register bit by bit in response to the effective rising edge of the first clock signal and buffering it in a first number of second intermediate registers, wherein the second input register and the first number of second intermediate registers are cascaded, and in the cascaded relationship, the next-level register reads and buffers the data in the previous-level register in response to the effective rising edge of the first clock signal; and reading the data in the first number of second intermediate registers in response to the effective rising edge of the second clock signal, and transmitting the read data to a first number of third target registers in the second clock domain, wherein the data in the first number of third target registers and the data obtained by reading the data in the first number of second intermediate registers have a one-to-one correspondence.

[0061] In the example, to address the rate matching issue when transmitting data from a fast clock domain to a slow clock domain, a serial-to-parallel conversion logic based on cascaded registers can be constructed at the transmitting end. Specifically, a first number of second intermediate registers can be set in the first clock domain, and the second input registers are connected to the first number of second intermediate registers to form a cascaded relationship. In response to a valid rising edge of the first clock signal, data undergoes a step-by-step shift operation in the register chain: new data bits enter the second input register, while previous data bits are sequentially passed and latched into the next-level second intermediate register. Through this cascading mechanism, data can be transferred step-by-step along the cascading direction and maintained in a stable state in each register level over multiple consecutive first clock cycles.

[0062] In the example, in response to the valid rising edge of the second clock signal, the data in the first number of second intermediate registers is read, and the read data is transmitted to the first number of third target registers set in the second clock domain, thereby ensuring that the data obtained in each target register corresponds one-to-one with the data read from the intermediate register.

[0063] Figure 4 This is a schematic diagram illustrating a first transmission mode from a fast clock domain to a slow clock domain according to an exemplary embodiment.

[0064] like Figure 4As shown, the clock frequency of the first clock signal is twice that of the second clock signal, allowing two third target registers to be set in the second clock domain. A reset operation aligns the rising edge of the first clock signal with the rising edge of the second clock signal. The data "A0, A1, B0, B1, C0, C1, D0, D1, E0" is the second input data to be transmitted. Each bit of the second input data is transmitted bit-by-bit to the second input register, meaning the data to be transmitted in the second input register is "A0, A1, B0, B1, C0, C1, D0, D1, E0". In the first clock domain, the data in the second input register can be sampled at the effective rising edge of the first clock signal and transmitted to the second intermediate register 1. Subsequently, at the next effective rising edge of the first clock signal, the data in the second intermediate register 1 is read and transmitted to the second intermediate register 2, thus enabling data to be transmitted step-by-step along the cascading direction. Finally, in response to the rising edge of the second clock signal, data is read from the two second intermediate registers and transmitted to the two corresponding third destination registers in the second clock domain. For example, in response to the rising edge of the second clock signal, the value "A1" in second intermediate register 1 is transmitted to third destination register 1, and the value "A0" in second intermediate register 2 is transmitted to third destination register 2. The two third destination registers in the second clock domain can then receive data A0, A1, B0, B1, C0, C1, etc., transmitted from the first clock domain.

[0065] Therefore, by using cascaded registers for transmission, the slow clock domain can receive data generated by the fast clock domain in multiple cycles within one slow clock cycle, thus enabling data transmission across clock domains without data loss.

[0066] In some embodiments, in the second transmission mode, sampling and buffering the second input data in response to the effective rising edge of the first clock signal, the buffered second input data remaining unchanged for at least one subsequent period of the first clock signal, and reading the buffered second input data in response to the effective rising edge of the second clock signal and transmitting the read data to a first number of fourth target registers, includes: sampling the data in the second input register bit by bit in response to the effective rising edge of the first clock signal and buffering it in a first number of third intermediate registers respectively, the data state of the first number of third intermediate registers remaining unchanged for at least one subsequent period of the first clock signal; and reading the data in the first number of third intermediate registers bit by bit in response to the effective rising edge of the second clock signal and transmitting the read data to a first number of fourth target registers in the second clock domain, wherein the data in the first number of fourth target registers has a one-to-one correspondence with the data in the first number of third intermediate registers.

[0067] In the example, in the second transmission mode where data is transmitted from the first clock domain (fast clock domain) to the second clock domain (slow clock domain), a first number of third intermediate registers can be configured on the first clock domain side for temporary storage control of the sampled data. Specifically, in response to the valid rising edge of the first clock signal, the data in the second input register can be sampled bit by bit, and these data can be buffered in the corresponding first number of third intermediate registers. After this buffering is completed, the control logic controls the data state of these third intermediate registers to remain unchanged for at least one subsequent first clock signal cycle, thereby keeping each bit of data in a stable state within the first clock domain.

[0068] In the example, during the data hold period, in response to a valid rising edge of the second clock signal, the receive logic on the second clock domain side reads the data from the first number of third intermediate registers bit by bit. Since there is a one-to-one correspondence between the first number of third intermediate registers and the first number of fourth destination registers configured in the second clock domain, the read data can be transmitted to the corresponding fourth destination register.

[0069] Figure 5 This is a schematic diagram illustrating a second transmission mode from a fast clock domain to a slow clock domain according to an exemplary embodiment.

[0070] like Figure 5As shown, the clock frequency of the first clock signal is twice the clock frequency of the second clock signal, allowing two fourth target registers to be set in the second clock domain. A reset operation aligns the rising edge of the first clock signal with the rising edge of the second clock signal. The data "A0, A1, B0, B1, C0, C1, D0, D1" is the second input data to be transmitted. Each bit of the second input data is transmitted bit-by-bit to the second input register; that is, the data to be transmitted in the second input register is "A0, A1, B0, B1, C0, C1, D0, D1". In the first clock domain, the data in the second input register can be sampled bit-by-bit on the effective rising edge of the first clock signal, and the sampling results are transmitted to two third intermediate registers respectively. For example, A0, B0, C0, etc., are transmitted to third intermediate register 2, and A1, B1, C1, etc., are transmitted to third intermediate register 1. Subsequently, the data state of these third intermediate registers remains unchanged for at least one subsequent first clock signal cycle. During the data holding period, in response to the valid rising edge of the second clock signal, the receiving logic on the second clock domain side reads the data from the two third intermediate registers bit by bit, and transmits the read data to the two corresponding fourth destination registers set in the second clock domain. That is, the data of third intermediate register 1 is transmitted to fourth destination register 1, and the data of third intermediate register 2 is transmitted to fourth destination register 2. Finally, the two fourth destination registers in the second clock domain can receive data A0, A1, B0, B1, etc. transmitted from the first clock domain.

[0071] Therefore, by using intermediate registers for timing buffering, the timing convergence requirements for cross-clock domain transmission can be relaxed, thereby improving the stability of data transmission.

[0072] Understandable Figure 2 , Figure 3 , Figure 4 and Figure 5 The embodiments described herein are based on the example of a clock frequency multiple of 2 and a portion of data transmission. However, the embodiments disclosed herein are not limited to this, and there are no restrictions on the integer multiples of the clock frequency or the data to be transmitted.

[0073] In some embodiments, the method for cross-clock domain data transmission further includes: selecting a transmission mode from a first transmission mode and a second transmission mode for data transmission based on at least one of circuit timing convergence state information and hardware operating environment information.

[0074] In this example, to ensure the data transmission mechanism can flexibly adapt to various physical conditions, a transmission mode can be selected based on different information. Specifically, the timing convergence status of the circuit or hardware operating environment information can be collected in real time, such as voltage amplitude, junction temperature, or process corner PVT data. Based on this real-time information, when the judgment indicates that the circuit timing margin is sufficient and the hardware operating environment is stable, the first transmission mode can be selected to reduce transmission delay; when the result indicates that the timing margin is insufficient or the hardware operating environment fluctuates greatly, the second transmission mode can be selected to increase transmission delay, thereby improving the stability and reliability of the data transmission process.

[0075] Therefore, by selecting the transmission mode, the data transmission method can be matched with the timing convergence state of the current circuit or the hardware operating environment, thereby ensuring the stability of cross-clock domain data transmission under different operating conditions.

[0076] Embodiments of this disclosure also provide a cross-clock domain data transmission device.

[0077] Figure 6 This is a schematic block diagram illustrating a cross-clock domain data transmission device 600 according to an exemplary embodiment.

[0078] In some embodiments, the cross-clock domain data transmission device 600 may include a clock alignment module 601, a first transmission module 602, a second transmission module 603, a third transmission module 604, and a fourth transmission module 605.

[0079] The clock alignment module 601 is configured to align the rising edge of the clock signal of the first clock signal in the first clock domain with the rising edge of the clock signal of the second clock signal in the second clock domain based on a reset operation, wherein the clock frequency of the first clock signal is an integer multiple of the clock frequency of the second clock signal.

[0080] The first transmission module 602 is configured to, in response to transmitting a first input data from a second clock domain to a first clock domain, sample the first input data in response to a valid rising edge of a first clock signal in a first transmission mode, and transmit the sampled data to a first target register within the same clock signal period.

[0081] The second transmission module 603 is configured to, in response to transmitting a first input data from a second clock domain to a first clock domain, in a second transmission mode, sample and buffer the first input data in response to a valid rising edge of a first clock signal, wherein the buffered first input data remains unchanged for at least one subsequent period of a first clock signal, and read the buffered first input data in response to a valid rising edge of the first clock signal and transmit the read data to a second target register, wherein the second transmission mode adds a transmission delay of at least one period of a first clock signal compared to the first transmission mode.

[0082] The third transmission module 604 is configured to, in response to transmitting a second input data from a first clock domain to a second clock domain, wherein the first quantity is determined by a multiple relationship between the clock frequency of the first clock signal and the clock frequency of the second clock signal, in a first transmission mode, sample the second input data in response to a valid rising edge of the second clock signal, and transmit the sampled data to a first quantity of third target registers within the same clock signal period.

[0083] The fourth transmission module 605 is configured to, in response to transmitting a second input data from a first clock domain to a second clock domain, wherein the first quantity is determined by a multiple relationship between the clock frequency of the first clock signal and the clock frequency of the second clock signal, in a second transmission mode, sample and buffer the second input data in response to a valid rising edge of the first clock signal, wherein the buffered second input data remains unchanged for at least one subsequent period of the first clock signal, and read the buffered second input data in response to a valid rising edge of the second clock signal and transmit the read data to a first quantity of fourth target registers.

[0084] It should be understood that Figure 6 The clock alignment module 601, first transmission module 602, second transmission module 603, third transmission module 604, and fourth transmission module 605 shown can respectively correspond to, as follows: Figure 1 The operations of steps S101, S102, S103, S104, and S105 are shown. Therefore, the details of each aspect will not be elaborated here.

[0085] In some embodiments, the first transmission module 602 may include a sampling transmission module 6021. The sampling transmission module 6021 may be configured to sample a second number of data bits in the first input register in response to a valid rising edge of a first clock signal, and transmit the sampled data to a first target register in the first clock domain within the same clock signal period.

[0086] In some embodiments, the second transmission module 603 may include a first sampling buffer module 6031 and a first data reading module 6032. The first sampling buffer module 6031 may be configured to sample data bit-by-bit in a second number of first input registers in response to a valid rising edge of a first clock signal and buffer the data in a second number of first intermediate registers, wherein the data state of the second number of first intermediate registers remains unchanged during at least one subsequent period of the first clock signal, and there is a one-to-one correspondence between the data in the second number of first input registers and the data in the second number of first intermediate registers. The first data reading module 6032 may be configured to read data bit-by-bit in the second number of first intermediate registers in response to a valid rising edge of the first clock signal and transmit the read data to a second target register in the first clock domain.

[0087] In some embodiments, the third transmission module 604 may include a second sampling buffer module 6041 and a second data reading module 6042. The second sampling buffer module 6041 may be configured to sample data bit-by-bit in the second input register in response to a valid rising edge of the first clock signal and buffer it in a first number of second intermediate registers. The second input register and the first number of second intermediate registers are cascaded, and in this cascaded relationship, in response to a valid rising edge of the first clock signal, the next-level register reads and buffers data from the previous-level register. The second data reading module 6042 may be configured to read data from the first number of second intermediate registers respectively in response to a valid rising edge of the second clock signal, and transmit the read data to a first number of third target registers in the second clock domain. The data in the first number of third target registers has a one-to-one correspondence with the data obtained by reading data from the first number of second intermediate registers.

[0088] In some embodiments, the fourth transmission module 605 may include a third sampling buffer module 6051 and a third data reading module 6052. The third sampling buffer module 6051 may be configured to sample the data in the second input register bit by bit in response to the effective rising edge of the first clock signal and buffer it in a first number of third intermediate registers, wherein the data state of the first number of third intermediate registers remains unchanged during at least one subsequent cycle of the first clock signal. The third data reading module 6052 may be configured to read the data in the first number of third intermediate registers bit by bit in response to the effective rising edge of the second clock signal and transmit the read data to a first number of fourth target registers in the second clock domain, wherein the data in the first number of fourth target registers has a one-to-one correspondence with the data in the first number of third intermediate registers.

[0089] In some embodiments, the cross-clock domain data transmission device 600 may further include a mode selection module 606. The mode selection module 606 may be configured to select a transmission mode from a first transmission mode and a second transmission mode for data transmission based on at least one of circuit timing convergence state information and hardware operating environment information.

[0090] Figure 7 This is a schematic diagram illustrating a semiconductor device according to an exemplary embodiment.

[0091] In embodiments of this disclosure, the semiconductor device may include, for example, a semiconductor chip. Figure 7 As shown, a semiconductor device may include logic circuitry for data transmission between two clock domains, wherein the clock frequencies of the clock signals in the two clock domains are integer multiples of each other. The logic circuitry performs data transmission between the two clock domains according to the cross-clock domain data transmission method described above. The cross-clock domain data transmission method provided according to embodiments of this disclosure can select different data transmission modes based on the system's timing convergence state or hardware environment state, thereby reducing latency caused by cross-clock domain transmission and minimizing power consumption while satisfying data transmission requirements.

[0092] Although the present disclosure has been described and illustrated in detail in the accompanying drawings and the foregoing description, such description and illustration should be considered illustrative and schematic, not restrictive, and the present disclosure is not limited to the disclosed embodiments.

Claims

1. A method for cross-clock domain data transmission, characterized in that, The method includes: Based on the reset operation, the rising edge of the clock signal of the first clock signal in the first clock domain is aligned with the rising edge of the clock signal of the second clock domain, wherein the clock frequency of the first clock signal is an integer multiple of the clock frequency of the second clock signal. In response to transmitting the first input data of the second clock domain to the first clock domain: In the first transmission mode, in response to the effective rising edge of the first clock signal, the first input data is sampled, and the sampled data is transmitted to the first target register within the same clock signal period; In the second transmission mode, in response to the effective rising edge of the first clock signal, the first input data is sampled and buffered, the buffered first input data remains unchanged for at least one subsequent cycle of the first clock signal, and in response to the effective rising edge of the first clock signal, the buffered first input data is read and the read data is transmitted to the second target register, wherein the second transmission mode adds a transmission delay of at least one cycle of the first clock signal compared to the first transmission mode. In response to transmitting the second input data from the first clock domain to the second clock domain, the first quantity is determined via a multiple relationship between the clock frequency of the first clock signal and the clock frequency of the second clock signal: In the first transmission mode, in response to the valid rising edge of the second clock signal, the second input data is sampled, and the sampled data is transmitted to a first number of third target registers within the same clock signal period; and In the second transmission mode, in response to a valid rising edge of the first clock signal, the second input data is sampled and buffered, the buffered second input data remains unchanged for at least one subsequent period of the first clock signal, and in response to a valid rising edge of the second clock signal, the buffered second input data is read and the read data is transferred to a first number of fourth target registers.

2. The method according to claim 1, characterized in that, In response to transmitting the first input data of the second clock domain to the first clock domain, a second number of first input registers are set in the second clock domain, wherein the second number is determined by a multiple relationship between the clock frequency of the first clock signal and the clock frequency of the second clock signal, and each bit of the first input data is transmitted bit by bit to the second number of first input registers.

3. The method according to claim 2, characterized in that, In the first transmission mode, the step of sampling the first input data in response to the effective rising edge of the first clock signal, and transmitting the sampled data to the first target register within the same clock signal period, includes: In response to the effective rising edge of the first clock signal, the data in the second number of the first input registers is sampled bit by bit, and the sampled data is transmitted to the first target register of the first clock domain within the same clock signal period.

4. The method according to claim 2, characterized in that, In the second transmission mode, the sampling and buffering of the first input data in response to a valid rising edge of the first clock signal, wherein the buffered first input data remains unchanged for at least one subsequent cycle of the first clock signal, and the reading of the buffered first input data and the transmission of the read data to the second target register in response to a valid rising edge of the first clock signal, includes: In response to a valid rising edge of the first clock signal, data in the second number of first input registers is sampled bit by bit and buffered in a second number of first intermediate registers, wherein the data state of the second number of first intermediate registers remains unchanged during at least one subsequent cycle of the first clock signal, and there is a one-to-one correspondence between the data in the second number of first input registers and the data in the second number of first intermediate registers; and In response to the valid rising edge of the first clock signal, the data in the second quantity of the first intermediate register is read bit by bit, and the read data is transferred to the second target register in the first clock domain.

5. The method according to claim 1, characterized in that, In response to transmitting the second input data from the first clock domain to the second clock domain, a second input register is set in the first clock domain, and each bit of the second input data is transmitted bit by bit to the second input register.

6. The method according to claim 5, characterized in that, In the first transmission mode, the step of sampling the second input data in response to the effective rising edge of the second clock signal, and transmitting the sampled data to a first number of third target registers within the same clock signal period, includes: In response to a valid rising edge of the first clock signal, the data in the second input register is sampled bit by bit and buffered in a first number of second intermediate registers, wherein the second input register and the first number of second intermediate registers are cascaded, and in this cascaded relationship, in response to a valid rising edge of the first clock signal, a next-level register reads and buffers data from the previous-level register; and In response to the effective rising edge of the second clock signal, the data in the first number of second intermediate registers is read respectively, and the read data is transmitted to the first number of third target registers in the second clock domain respectively, wherein the data in the first number of third target registers has a one-to-one correspondence with the data obtained by reading the data in the first number of second intermediate registers respectively.

7. The method according to claim 5, characterized in that, In the second transmission mode, the sampling and buffering of the second input data in response to a valid rising edge of the first clock signal, wherein the buffered second input data remains unchanged for at least one subsequent period of the first clock signal, and the reading of the buffered second input data and the transmission of the read data to a first number of fourth target registers in response to a valid rising edge of the second clock signal, includes: In response to a valid rising edge of the first clock signal, the data in the second input register is sampled bit by bit and buffered in a first number of third intermediate registers, the data state of the first number of third intermediate registers remaining unchanged for at least one subsequent cycle of the first clock signal; and In response to the effective rising edge of the second clock signal, the data in the first number of third intermediate registers is read bit by bit, and the read data is transmitted to the first number of fourth target registers in the second clock domain, wherein the data in the first number of fourth target registers has a one-to-one correspondence with the data in the first number of third intermediate registers.

8. The method according to any one of claims 1 to 7, characterized in that, The method further includes: selecting a transmission mode from the first transmission mode and the second transmission mode for data transmission based on at least one of the timing convergence state information of the circuit and the hardware operating environment information.

9. A cross-clock domain data transmission device, characterized in that, The device includes: The clock alignment module is configured to align the rising edge of the clock signal of the first clock signal in the first clock domain with the rising edge of the clock signal of the second clock signal in the second clock domain based on a reset operation, wherein the clock frequency of the first clock signal is an integer multiple of the clock frequency of the second clock signal. In response to transmitting the first input data of the second clock domain to the first clock domain: The first transmission module is configured to, in a first transmission mode, sample the first input data in response to the effective rising edge of the first clock signal, and transmit the sampled data to the first target register within the same clock signal period. The second transmission module is configured to, in a second transmission mode, sample and buffer the first input data in response to a valid rising edge of the first clock signal, wherein the buffered first input data remains unchanged for at least one subsequent period of the first clock signal, and in response to a valid rising edge of the first clock signal, read the buffered first input data and transmit the read data to a second target register, wherein the second transmission mode adds a transmission delay of at least one period of the first clock signal compared to the first transmission mode. In response to transmitting the second input data from the first clock domain to the second clock domain, the first quantity is determined via a multiple relationship between the clock frequency of the first clock signal and the clock frequency of the second clock signal: The third transmission module is configured to, in the first transmission mode, sample the second input data in response to a valid rising edge of the second clock signal, and transmit the sampled data to a first number of third target registers within the same clock signal period; and The fourth transmission module is configured to, in the second transmission mode, sample and buffer the second input data in response to a valid rising edge of the first clock signal, wherein the buffered second input data remains unchanged for at least one subsequent period of the first clock signal, and read the buffered second input data and transmit the read data to a first number of fourth target registers in response to a valid rising edge of the second clock signal.

10. A semiconductor device, characterized in that, The semiconductor device includes: A logic circuit for transmitting data between two clock domains, wherein the clock frequencies of the clock signals of the two clock domains are integer multiples of each other, wherein the logic circuit transmits data between the two clock domains using the method of any one of claims 1 to 8.

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