An address mapping method and device based on a non-transparent bridge and a mapping lookup cache

Abstract

This invention discloses an address mapping method and apparatus based on a non-transparent bridge and a mapping lookup table cache, relating to the field of address mapping technology. The method includes: receiving an access request from a first bus domain through a non-transparent bridge module; decomposing the target address into a page number and an intra-page offset through an address resolution module, and extracting access attributes; querying a mapping lookup table cache module based on the page number to determine the extraction method for the page-level mapping item; verifying the extracted page-level mapping item and access attributes; if a cache miss occurs but the verification passes, cache backfilling is performed; generating a local target address based on the target page base address and intra-page offset in the page-level mapping item; and forwarding the access request to a second bus domain connected to the non-transparent bridge module through an access forwarding module. This invention, after the access request enters the non-transparent bridge module, extracts the page number based on the request address and obtains the target address information through a lookup table, enabling rapid redirection of the access address.

Description

Technical Field

[0001] This invention relates to the field of address mapping technology, and in particular to an address mapping method and apparatus based on a non-transparent bridge and a mapping lookup table cache. Background Technology

[0002] PCIe NTB (PCIe, Peripheral Component Interconnect Express, a high-speed serial point-to-point dual-channel high-bandwidth transmission standard; NTB, Non-Transparent Bridging) is an important interconnect component connecting two independent PCIe bus domains. It is the core carrier for realizing cross-bus domain data interaction and is widely used in scenarios such as dual-machine interconnection, server interconnection, storage interconnection, and communication between high-performance computing nodes.

[0003] In existing technologies, NTBs commonly employ address mapping using memory windows (MWs) exposed to the peer to achieve cross-domain address redirection. Specifically, this involves exposing the local address space to the peer through several pre-configured memory windows. After the remote host accesses these pre-configured windows, the NTB executes statically preset fixed rules to complete the address remapping. The characteristics of this existing method are: it uses a fixed number of memory windows to complete address exposure and access redirection; each window uniquely corresponds to a continuous address range; the address translation rules are all statically configured and cannot be flexibly adjusted at runtime; the number of mappable regions is rigidly limited by the number of windows provided by the hardware itself; and when practical applications require mapping large-scale, non-contiguous, page-distributed address spaces, the configuration process of this scheme is extremely complex and even difficult to implement.

[0004] With the rapid development of emerging applications such as high-performance computing, memory pooling, remote device access, and cross-host shared accelerators, systems are placing higher demands on the address mapping capabilities of NTB. However, existing NTB address mapping methods based on fixed accessible address windows lack fine-grained mapping capabilities, making it difficult to support massive address mappings, and their mapping scalability is also insufficient.

[0005] Therefore, existing technologies still need improvement and development. Summary of the Invention

[0006] The technical problem to be solved by the present invention is to provide an address mapping method and apparatus based on non-transparent bridge and mapping lookup table cache, which addresses the above-mentioned defects of the prior art. The aim is to solve the problem that the existing NTB address mapping method based on fixed accessible address window has insufficient fine-grained mapping capability and is difficult to support massive address mapping.

[0007] The technical solution adopted by this invention to solve the problem is as follows:

[0008] In a first aspect, embodiments of the present invention provide an address mapping method based on a non-transparent bridge and a mapping lookup table cache, the method comprising:

[0009] Access requests from the first bus domain are received via a non-transparent bridge module;

[0010] The address resolution module decomposes the target address in the access request into page number and page offset according to a preset page granularity, and extracts the access attributes in the access request.

[0011] The mapping lookup table cache module within the non-transparent bridge module is queried according to the page number. The data extraction method is determined based on the query result, and the page-level mapping item is extracted.

[0012] The page-level mapping item and the access attribute are validated. If the query result is a cache miss and the validation result is passed, the page-level mapping item is written into the mapping lookup table cache module to complete the cache backfilling.

[0013] A local target address is generated based on the target page base address in the page-level mapping entry and the page offset. The access forwarding module then forwards the access request to the second bus domain connected by the non-transparent bridge module based on the local target address.

[0014] In one implementation, the step of decomposing the target address into page number and page offset at a preset page granularity using an address resolution module, and extracting access attributes from the access request, includes:

[0015] The address resolution module uses the integer quotient of the target address calculated based on the page granularity as the page number and the remainder of the calculated target address as the page offset.

[0016] Simultaneously, the access attributes in the access request are extracted; the access attributes include read / write type and access priority.

[0017] In one implementation, the steps of querying the mapping lookup table cache module within the non-transparent bridge module according to the page number, determining the data extraction method based on the query result, and extracting the page-level mapping item include:

[0018] The page number is matched bit by bit with the pre-stored mapping item tags in the mapping lookup table cache module. If a completely matching mapping item exists, the query result is determined to be a cache hit; otherwise, it is determined to be a cache miss.

[0019] If the query result is a cache hit, then the corresponding page-level mapping item is extracted from the mapping lookup table cache module.

[0020] In one implementation, after the step of matching the page number with the pre-stored mapping item tags in the mapping lookup table cache module, the method further includes:

[0021] If the query result is a cache miss, the conversion control module initiates a read request to the external mapping table storage module, and extracts the corresponding page-level mapping item from the mapping table storage module according to the page number.

[0022] In one implementation, the step of validating the page-level mapping item and the access attribute includes:

[0023] Perform validity and permission checks on the page-level mapping items;

[0024] When both the validity check and the permission check pass, the check is deemed successful.

[0025] In one embodiment, the method further includes:

[0026] When any of the following situations occur: invalid page-level mapping entry, incompatible access permissions, or memory table lookup exception, an exception handling strategy is triggered. The exception handling strategy includes one or more of the following: returning an error response, discarding the request, interrupting the report, or entering the exception handling process.

[0027] In one embodiment, the method further includes:

[0028] The configuration management module, based on external configuration commands, can perform one or more operations on page-level mapping items and permission attributes, including creating, deleting, modifying, and refreshing.

[0029] Secondly, embodiments of the present invention also provide an address mapping apparatus based on a non-transparent bridge and a mapping lookup table cache, the apparatus comprising:

[0030] A non-transparent bridge module is used to receive access requests from the first bus domain;

[0031] The address resolution module is used to decompose the target address in the access request into page number and page offset according to a preset page granularity, and extract the access attributes in the access request.

[0032] The address mapping module is used to query the mapping lookup table cache module in the non-transparent bridge module according to the page number, determine the data extraction method and extract the page-level mapping item according to the query result;

[0033] The verification module is used to verify the page-level mapping item and the access attribute. If the query result is a cache miss and the verification result is passed, the page-level mapping item is written into the mapping lookup table cache module to complete the cache backfill.

[0034] The address generation and forwarding module is used to generate a local target address based on the target page base address in the page-level mapping item and the page offset, and to forward the access request to the second bus domain connected by the non-transparent bridge module based on the local target address through the access forwarding module.

[0035] Thirdly, embodiments of the present invention also provide a terminal, the terminal including a memory and one or more processors; the memory storing one or more programs; the programs including instructions for executing the address mapping method based on non-transparent bridges and mapping lookup table caches as described in any of the preceding claims; the processors being used to execute the programs.

[0036] Fourthly, embodiments of the present invention also provide a computer-readable storage medium having stored thereon a plurality of instructions adapted to be loaded and executed by a processor to implement the steps of the address mapping method based on a non-transparent bridge and a mapping lookup table cache as described in any of the preceding claims.

[0037] The beneficial effects of this invention are as follows: In this embodiment, the non-transparent bridge module receives access requests from the first bus domain; the address resolution module decomposes the target address into a page number and an intra-page offset, and extracts the access attributes; the mapping lookup cache module is queried based on the page number to determine the extraction method for the page-level mapping item; the extracted page-level mapping item and access attributes are verified; if the cache misses but the verification passes, cache backfilling is performed; a local target address is generated based on the target page base address and intra-page offset in the page-level mapping item, and the access request is forwarded to the second bus domain connected to the non-transparent bridge module via the access forwarding module. This invention, after the access request enters the non-transparent bridge module, extracts the page number based on the request address and obtains the target address information through a lookup table, enabling rapid redirection of the access address. Attached Figure Description

[0038] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0039] Figure 1 This is a flowchart illustrating the address mapping method based on a non-transparent bridge and a mapping lookup table cache provided in an embodiment of the present invention.

[0040] Figure 2 This is a schematic diagram illustrating the working principle of the address mapping module provided in this embodiment of the invention.

[0041] Figure 3 This is a schematic diagram of an address mapping device based on a non-transparent bridge and a mapping lookup table cache provided in an embodiment of the present invention.

[0042] Figure 4 This is a schematic diagram of the terminal provided in the embodiment of the present invention. Detailed Implementation

[0043] This invention discloses an address mapping method and apparatus based on a non-transparent bridge and a mapping lookup table cache. To make the objectives, technical solutions, and effects of this invention clearer and more explicit, the invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only for explaining the invention and are not intended to limit the invention.

[0044] Those skilled in the art will understand that, unless specifically stated otherwise, the singular forms “a,” “an,” “the,” and “the” used herein may also include the plural forms. It should be further understood that the term “comprising” as used in this specification means the presence of the stated features, integers, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. It should be understood that when we say an element is “connected” or “coupled” to another element, it can be directly connected or coupled to the other element, or there may be intermediate elements. Furthermore, “connected” or “coupled” as used herein can include wireless connections or wireless coupling. The term “and / or” as used herein includes all or any units and all combinations of one or more associated listed items.

[0045] It will be understood by those skilled in the art that, unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. It should also be understood that terms such as those defined in general dictionaries should be understood to have the same meaning as in the context of the prior art, and should not be interpreted in an idealized or overly formal sense unless specifically defined as herein.

[0046] To address the aforementioned deficiencies in existing technologies, this invention provides an address mapping method based on a non-transparent bridge and a mapping lookup table cache. The method includes: receiving an access request from a first bus domain via a non-transparent bridge module; decomposing the target address in the access request into a page number and an intra-page offset at a preset page granularity via an address resolution module, and extracting access attributes from the access request; querying the mapping lookup table cache module within the non-transparent bridge module based on the page number, determining the data extraction method based on the query result, and extracting a page-level mapping item; validating the page-level mapping item and the access attributes; if the query result is a cache miss and the validation result is successful, writing the page-level mapping item into the mapping lookup table cache module to complete cache backfilling; generating a local target address based on the target page base address and the intra-page offset in the page-level mapping item, and forwarding the access request to a second bus domain connected to the non-transparent bridge module based on the local target address via an access forwarding module. This invention replaces the static mapping method, which relies on a limited accessible address window, with a dynamic direct address translation method based on a page-level mapping table. After an access request enters the non-transparent bridge module, its internal mechanism extracts the page number based on the requested address and retrieves the target address information through a table lookup, thus achieving rapid redirection of the access address. This hierarchical address translation mechanism effectively solves the problems of limited window quantity, reliance on continuous mapping, difficulty in supporting massive independent page-level mappings, and insufficient flexibility in existing technologies.

[0047] like Figure 1 As shown, the method specifically includes the following steps:

[0048] Step S100: Receive an access request from the first bus domain through a non-transparent bridge module; the non-transparent bridge module connects the first bus domain and the second bus domain.

[0049] Specifically, the method in this embodiment requires the use of the hardware functionality of a non-transparent bridge module (i.e., a PCIe NTB bridge module). The non-transparent bridge module connects two independent PCIe bus domains and receives access requests from one of the PCIe bus domains. In practical applications, this access request is not a single address data item, but rather a complete interactive data set containing the target address, access type, data length, and request identification information. This provides the data foundation for subsequent address resolution, lookup table translation, and other address mapping-related operations.

[0050] Step S200: The address resolution module decomposes the target address in the access request into page number and page offset according to the preset page granularity, and extracts the access attributes in the access request.

[0051] Furthermore, the step of decomposing the target address into page number and page offset at a preset page granularity using the address resolution module, and extracting the access attributes from the access request, includes:

[0052] The address resolution module uses the integer quotient of the target address calculated based on the page granularity as the page number and the remainder of the calculated target address as the page offset.

[0053] Simultaneously, the access attributes in the access request are extracted; the access attributes include read / write type and access priority.

[0054] Specifically, the address resolution module is dedicated to structurally decomposing the target address in the access request and accurately extracting access attributes. During execution, the address resolution module breaks down the target address into two parts according to a preset page granularity: the integer quotient obtained by dividing the target address by the page granularity is used as the page number, and the remainder is used as the page offset. This calculation method achieves page-level splitting of the target address. Simultaneously, the module extracts access attributes, including read / write type and access priority, from the access request, providing a data foundation for subsequent permission verification. This embodiment uses the address resolution module for page number extraction, allowing for independent configuration of each page number and its corresponding page, setting the target address base address, valid or invalid attributes, and read / write access permissions for each page. This fine-grained page-level design provides greater flexibility than traditional fixed window mapping, eliminating the dependence on continuous address ranges in traditional mapping methods, thus better adapting to various practical application scenarios such as device sharing, memory pools, accelerator interconnection, and cross-host resource access.

[0055] Step S300: Query the mapping lookup table cache module in the non-transparent bridge module according to the page number, determine the data extraction method according to the query result, and extract the page-level mapping item.

[0056] In summary, this embodiment employs an on-chip cache to implement high-speed table lookup, enabling page-level mapping and page-independent mapping. Specifically, this embodiment incorporates a mapping lookup cache module within the non-transparent bridge module to implement a translation cache. This mapping lookup cache module is a high-speed cache implemented on the FPGA (Programmable Logic Device) / ASIC (Application Programmable Integrated Circuit) chip. Its function is to cache recently accessed or frequently accessed page-level mapping entries, thereby reducing memory lookup latency. Page-level mapping establishes address mapping relationships based on fixed-granularity pages (e.g., 4KB, 16KB, 64KB, etc.), and is the basis for page-independent mapping. Page-independent mapping means that each page can be configured with its own target address, permission attributes, valid bits, routing information, etc., without requiring large contiguous windows. In the actual execution process, the page number extracted from the target address of the access request by the address resolution module is used as the unique query index to perform a matching query on the mapping lookup cache module within the non-transparent bridge module. Then, based on whether the query result is a cache hit or a cache miss, the corresponding page-level mapping item data extraction method is determined and the page-level mapping item extraction is completed. For cache hits, address translation can be completed directly; for cache misses, the mapping item can be retrieved by accessing the cache and then backfilled, thus balancing large-capacity mapping capability and high translation performance.

[0057] In one implementation, the steps of querying the mapping lookup table cache module within the non-transparent bridge module according to the page number, determining the data extraction method based on the query result, and extracting the page-level mapping item include:

[0058] The page number is matched bit by bit with the pre-stored mapping item tags in the mapping lookup table cache module. If a completely matching mapping item exists, the query result is determined to be a cache hit; otherwise, it is determined to be a cache miss.

[0059] If the query result is a cache hit, then the corresponding page-level mapping item is extracted from the mapping lookup table cache module.

[0060] Furthermore, if the query result is a cache miss, the conversion control module initiates a read request to the external mapping table storage module, and extracts the corresponding page-level mapping item from the mapping table storage module according to the page number.

[0061] Specifically, the mapping lookup cache module can adopt a direct mapping, set-associative, or fully associative structure, and the cache entries (i.e., pre-stored mapping entries) can store mapping relationships on a page-by-page basis. The page number extracted by the address resolution module is matched bit-by-bit with the pre-stored mapping entries in the mapping lookup cache module. If a completely matching mapping entry exists, it is considered a cache hit; otherwise, it is a cache miss. For different query results, a differentiated page-level mapping entry retrieval process is implemented using a translation control module: when there is a cache hit, address translation is performed directly; when there is a cache miss, the memory is accessed to retrieve the mapping entry and it is written back to the mapping lookup cache module.

[0062] Specifically, when the query result is a cache hit, the corresponding page-level mapping item is directly retrieved from the mapping lookup table cache module, i.e., Figure 2 As shown, the cache in the diagram is used to retrieve page-level mapping entries. The mapping lookup cache module dynamically caches mapping entries based on access hotspots and can be combined with strategies such as Least Recently Used (LRU), First-In-First-Out (FIFO), and random replacement to effectively improve the lookup hit rate and reduce memory access frequency. When access is locale-dependent, many requests do not need to access external memory again, which can significantly reduce the address translation latency of the non-transparent bridge module and achieve the effect of high-speed on-chip cache lookup.

[0063] Specifically, when the query result is a cache miss, the conversion control module initiates a read request to the external mapping table storage module, retrieving the corresponding page-level mapping entry from the mapping table storage module based on the page number, i.e. Figure 2 As shown, the memory in the diagram is used to retrieve page-level mapping entries. A mapping table is a data structure that records the correspondence between "peer access address or page number" and "local target address or physical page"; the mapping table storage module is specifically designed to store large-scale page-level address mapping relationships. In this embodiment, memory is used as the mapping table carrier. The capacity of the mapping entries is mainly determined by the memory space; for example, at a 4KB page granularity, a 100GB address space corresponds to approximately 25.6 million pages. By rationally designing the mapping entry encoding format, paging organization method, and multi-level table structure, independent page-level mapping of a 100GB-level space can be achieved, providing a large-capacity, highly scalable storage foundation for retrieving mapping entries when a cache miss occurs.

[0064] This embodiment employs a differentiated page-level mapping extraction method, which decentralizes address translation granularity to the page level. It shifts from configuring several static windows to dynamically searching and translating the target address for each accessed page. Combined with a mapping table and cache for fast lookup, this approach breaks through the limitations of traditional window mechanisms at the architectural level. It solves the problem of traditional NTB schemes where mapping capabilities are limited by the number of windows provided by the hardware, enabling large-scale mapping of non-contiguous address regions. This embodiment allows each page to be configured with its own target address and access attributes, thus supporting various application scenarios such as non-contiguous address mapping, sparse mapping, dynamic remapping, multi-tenant isolated mapping, remote memory pool mapping, and large-scale device resource sharing. Ultimately, it achieves an NTB address mapping system without an upper limit on the number of windows.

[0065] Step S400: Verify the page-level mapping item and the access attribute. If the query result is a cache miss and the verification result is passed, then write the page-level mapping item into the mapping lookup table cache module to complete the cache backfilling.

[0066] Further, the step of validating the page-level mapping item and the access attribute includes:

[0067] Perform validity and permission checks on the page-level mapping items;

[0068] When both the validity check and the permission check pass, the check is deemed successful.

[0069] Specifically, the verification operation in this embodiment requires dual verification of the extracted page-level mapping items and the parsed access attributes, namely, validity verification and permission verification of the page-level mapping items. Validity verification confirms that the page-level mapping item itself is a validly configured mapping relationship, while permission verification determines whether the access attributes of the current access request meet the preset access permission requirements of the page-level mapping item. Only when both validity and permission verifications pass will the overall verification be considered successful; if either verification fails, subsequent exception handling procedures will be triggered. Furthermore, cache backfilling is only performed when the query result is a cache miss, and the overall verification result for the page-level mapping item and access attributes is successful: the page-level mapping item extracted from the external mapping table storage module is written into the mapping lookup cache module within the non-transparent bridge module, completing cache backfilling. Cache backfilling enables dynamic updates of the mapping items in the mapping lookup cache module, caching the first accessed valid page-level mapping item to on-chip high-speed storage resources, providing a high-speed lookup basis for subsequent access requests with the same page number, thereby improving the lookup hit rate and reducing the overall latency of address translation.

[0070] Step S500: Generate a local target address based on the target page base address and the page offset in the page-level mapping item, and forward the access request to the second bus domain connected by the non-transparent bridge module based on the local target address through the access forwarding module.

[0071] Specifically, based on the target page base address stored in the page-level mapping entry after validity and authorization checks, and combined with the intra-page offset obtained by the address resolution module from the target address of the access request, a local target address is generated through address reconstruction. This local target address is the actual target address corresponding to the access request in the second bus domain. Subsequently, the access forwarding module performs the final request forwarding operation.

[0072] The access forwarding module's function is to forward access requests from one side of the non-transparent bridge module's bus domain to the corresponding target address or resource in the other side's bus domain, based on the translation result. Using the generated local target address as the translation result, the access forwarding module accurately forwards the original access request from the first bus domain to the resource corresponding to that local target address in the second bus domain. At this point, the entire cross-PCIe bus domain address mapping and access request forwarding process is essentially complete, achieving rapid redirection of access addresses and ensuring effective cross-domain access from the first bus domain to resources in the second bus domain.

[0073] To facilitate understanding of the method in this embodiment, the following provides an overall execution process of the method in this embodiment, which can reflect the address direct translation process for PCIe NTB: for access requests entering through the non-transparent bridge module, instead of relying on a limited number of fixed windows for static address redirection, the request address is directly converted to the target address through the mapping lookup table caching module.

[0074] First, the non-transparent bridge module receives the access request for the first PCIe bus domain, which includes information such as the target address, access type, length, and request identifier.

[0075] Next, address decomposition is performed, breaking down the request address into page number and page offset;

[0076] Subsequently, the mapping lookup cache module performs a table lookup, using the page number as an index or tag to query the on-chip mapping lookup cache;

[0077] Next, branching is performed based on the lookup result. If the lookup cache is hit, the mapping entry is read directly to generate the target address, which can be formed by the target page base address plus the page offset. If the lookup cache is not hit, a read request is sent to the memory mapping table to obtain the corresponding page-level mapping entry.

[0078] After the page-level mapping entries are extracted, the mapping entries are validated to check their validity and access permissions. If the cache miss is detected and the validation passes, the cache backfilling step is executed, and the valid mapping entries read from memory are written into the on-chip mapping lookup cache.

[0079] Finally, address translation and forwarding are completed. The target address is generated based on the mapping item, and the access request of the first PCIe bus domain is forwarded to the target resource of the corresponding second PCIe bus domain.

[0080] In one implementation, the method further includes:

[0081] When any of the following situations occur: invalid page-level mapping entry, incompatible access permissions, or memory table lookup exception, an exception handling strategy is triggered. The exception handling strategy includes one or more of the following: returning an error response, discarding the request, interrupting the report, or entering the exception handling process.

[0082] Specifically, if any of the following three situations occur: invalid page-level mapping entry, incompatible access permissions, or memory table lookup exception, the system will immediately trigger the preset exception handling strategy. The exception handling strategy is not a single handling method, but includes one or more of the following: returning an error response, discarding the request, interrupting the report, or entering the exception handling process. The appropriate handling method can be flexibly selected to deal with various exception situations according to the actual application scenario, system configuration requirements, and the severity of the exception.

[0083] In one implementation, the method further includes:

[0084] The configuration management module, based on external configuration commands, can perform one or more operations on page-level mapping items and permission attributes, including creating, deleting, modifying, and refreshing.

[0085] Specifically, the configuration management module is used to create, delete, modify, and refresh page-level mapping items and permission attributes. Based on the specific requirements of external configuration instructions, the configuration management module flexibly performs one or more of the following operations on page-level mapping items and their corresponding permission attributes: creation, deletion, modification, and refresh. This gives the page-level address mapping system flexible dynamic configuration capabilities, allowing adjustments to page-level mapping relationships and access permissions at any time according to actual cross-bus domain access needs.

[0086] The advantages of this invention include, but are not limited to:

[0087] 1. Breaking through the window number limitation of traditional non-transparent bridges, achieving address mapping without quantity constraints: This invention adopts the implementation form of memory mapping table, which can support a massive number of page-level mapping entries, creating a PCIe NTB bridge address mapping scheme that is not limited by the number of traditional memory windows.

[0088] 2. Supports 100GB-level page-independent mapping, enabling large-scale mapping expansion: This invention stores the mapping relationship in memory and realizes large-scale expansion of address mapping based on the storage mapping relationship, creating an NTB address translation method that supports 100GB-level page-independent mapping. It can support page-independent mapping of 100GB-level or even larger address spaces, and can accurately adapt to application scenarios with practical needs for large-scale address mapping, such as large-scale shared memory, remote memory pools, and distributed accelerator access.

[0089] 3. Balancing large-capacity mapping with high-performance conversion to achieve low-latency address translation: This invention achieves high-speed table lookup and low-latency address translation by setting up an on-chip mapping lookup cache. It successfully combines large-capacity memory with low-latency cache technology, maintaining high address translation performance even in large-scale mapping application scenarios, and effectively realizing direct address translation for NTB access.

[0090] 4. Supports multiple mapping methods and has highly flexible address mapping capabilities: This invention supports configuring target addresses and attributes for each page individually at the page level, thus supporting non-contiguous mapping, sparse mapping, and dynamic updates of mapping relationships at runtime, which greatly improves the overall flexibility of PCIe NTB address mapping.

[0091] 5. Wide range of applications, adaptable to various cross-domain interconnection application scenarios: This invention can be flexibly applied to various scenarios such as dual-machine interconnection, cross-host device sharing, remote memory access, storage acceleration, GPU / FPGA / AI accelerator sharing, and cross-domain resource access in trusted computing or isolated computing environments, and can meet the address mapping requirements of different high-performance computing and heterogeneous interconnection scenarios.

[0092] 6. Strong engineering feasibility and practical engineering implementation value: The technical solution of this invention has strong adaptability and is suitable for implementation in FPGA, ASIC (integrated circuit customized for specific applications or functions), and SoC (system-on-a-chip) interconnect modules. It is also easy to integrate with the existing PCIe NTB system without requiring major modifications to the existing PCIe NTB system. It has strong engineering implementation value and practical industrial application potential.

[0093] Based on the above embodiments, the present invention also provides an address mapping device based on a non-transparent bridge and a mapping lookup table cache, such as... Figure 3 As shown, the device includes:

[0094] Non-transparent bridge module 01 is used to receive access requests from the first bus domain;

[0095] Address resolution module 02 is used to decompose the target address in the access request into page number and page offset according to a preset page granularity, and extract the access attributes in the access request;

[0096] Address mapping module 03 is used to query the mapping lookup table cache module in the non-transparent bridge module according to the page number, determine the data extraction method and extract the page-level mapping item according to the query result;

[0097] The verification module 04 is used to verify the page-level mapping item and the access attribute. If the query result is a cache miss and the verification result is a pass, the page-level mapping item is written into the mapping lookup table cache module to complete the cache backfill.

[0098] Address generation and forwarding module 05 is used to generate a local target address based on the target page base address in the page-level mapping item and the page offset, and to forward the access request to the second bus domain connected by the non-transparent bridge module based on the local target address through the access forwarding module.

[0099] Based on the above embodiments, the present invention also provides a terminal, the principle block diagram of which can be as follows: Figure 4 As shown, the terminal includes a processor, memory, network interface, and display screen connected via a system bus. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system and computer programs. The internal memory provides the environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The network interface is used to communicate with external terminals via a network connection. When the computer program is executed by the processor, it implements an address mapping method based on a non-transparent bridge and a lookup table cache. The display screen can be a liquid crystal display (LCD) or an e-ink display.

[0100] Those skilled in the art will understand that Figure 4 The schematic diagram shown is merely a partial structural diagram related to the present invention and does not constitute a limitation on the terminal to which the present invention is applied. A specific terminal may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0101] In one implementation, the terminal's memory stores one or more programs, and these programs are configured to be executed by one or more processors. The programs include instructions for performing an address mapping method based on a non-transparent bridge and a mapped lookup table cache.

[0102] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments of the above methods. Any references to memory, storage, databases, or other media used in the embodiments provided by this invention can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), Rambus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

[0103] In summary, this invention discloses an address mapping method and apparatus based on a non-transparent bridge and a mapping lookup table cache, relating to the field of address mapping technology. The method includes: receiving an access request from a first bus domain through a non-transparent bridge module; decomposing the target address in the access request into a page number and an intra-page offset at a preset page granularity through an address resolution module, and extracting access attributes from the access request; querying the mapping lookup table cache module within the non-transparent bridge module based on the page number, determining the data extraction method based on the query result, and extracting a page-level mapping item; verifying the page-level mapping item and the access attributes; if the query result is a cache miss and the verification result is successful, writing the page-level mapping item into the mapping lookup table cache module to complete cache backfilling; generating a local target address based on the target page base address and the intra-page offset in the page-level mapping item, and forwarding the access request to a second bus domain connected to the non-transparent bridge module based on the local target address through an access forwarding module. This invention replaces the static mapping method, which relies on a limited Memory Window, with a dynamic address direct conversion method based on a page-level mapping table. After an access request enters the non-transparent bridge module, it extracts the page number based on the request address and retrieves the target address information by looking up a table, thus enabling fast redirection of the access address.

[0104] It should be understood that the application of the present invention is not limited to the examples above. Those skilled in the art can make improvements or modifications based on the above description, and all such improvements and modifications should fall within the protection scope of the appended claims.

Claims

1. A method for address mapping based on a non-transparent bridge and a mapping lookup cache, characterized in that, The method includes: Access requests from the first bus domain are received via a non-transparent bridge module; The address resolution module decomposes the target address in the access request into page number and page offset according to a preset page granularity, and extracts the access attributes in the access request. The mapping lookup table cache module within the non-transparent bridge module is queried according to the page number. Based on the query result, a data extraction method is determined, and page-level mapping items are extracted. This includes: matching the page number bit-by-bit with the pre-stored mapping item tags in the mapping lookup table cache module; if a completely matching mapping item exists, the query result is considered a cache hit; otherwise, it is considered a cache miss. If the query result is a cache hit, the corresponding page-level mapping item is extracted from the mapping lookup table cache module. If the query result is a cache miss, a read request is initiated to the external mapping table storage module through the conversion control module, and the corresponding page-level mapping item is extracted from the mapping table storage module based on the page number. The mapping lookup table cache module dynamically caches mapping items based on access hotspots, and employs Least Recently Used, First-In-First-Out, and Random Replacement strategies. The mapping table is a data structure that records the correspondence between the peer access address or page number and the local target address or physical page. The mapping table storage module is specifically used to store large-scale page-level address mapping relationships. The page-level mapping item and the access attribute are validated. If the query result is a cache miss and the validation result is passed, the page-level mapping item is written into the mapping lookup table cache module to complete the cache backfilling. A local target address is generated based on the target page base address in the page-level mapping entry and the page offset. The access forwarding module then forwards the access request to the second bus domain connected by the non-transparent bridge module based on the local target address.

2. The address mapping method based on a non-transparent bridge and a mapping lookup table cache according to claim 1, characterized in that, The steps of decomposing the target address into page number and page offset according to a preset page granularity using the address resolution module, and extracting the access attributes from the access request, include: The address resolution module calculates the integer quotient of the target address based on the page granularity as the page number, and calculates the remainder of the target address as the page offset; Simultaneously, the access attributes in the access request are extracted; the access attributes include read / write type and access priority.

3. The address mapping method based on a non-transparent bridge and a mapping lookup table cache according to claim 1, characterized in that, The steps for validating the page-level mapping item and the access attribute include: Perform validity and permission checks on the page-level mapping items; When both the validity check and the permission check pass, the check is deemed successful.

4. The address mapping method based on a non-transparent bridge and a mapping lookup table cache according to claim 1, characterized in that, The method further includes: When any of the following situations occur: invalid page-level mapping entry, incompatible access permissions, or memory table lookup exception, an exception handling strategy is triggered. The exception handling strategy includes one or more of the following: returning an error response, discarding the request, interrupting the report, or entering the exception handling process.

5. The address mapping method based on a non-transparent bridge and a mapping lookup table cache according to claim 1, characterized in that, The method further includes: The configuration management module, based on external configuration commands, can perform one or more operations on page-level mapping items and permission attributes, including creating, deleting, modifying, and refreshing.

6. An address mapping device based on a non-transparent bridge and a mapping lookup table cache, characterized in that, The device includes: A non-transparent bridge module is used to receive access requests from the first bus domain; The address resolution module is used to decompose the target address in the access request into page number and page offset according to a preset page granularity, and extract the access attributes in the access request. The address mapping module is used to query the mapping lookup table cache module within the non-transparent bridge module based on the page number, determine the data extraction method based on the query result, and extract the page-level mapping item. This includes: matching the page number bit-by-bit with the pre-stored mapping item tags in the mapping lookup table cache module; if a completely matching mapping item exists, the query result is considered a cache hit; otherwise, it is considered a cache miss. If the query result is a cache hit, the corresponding page-level mapping item is extracted from the mapping lookup table cache module. If the query result is a cache miss, a read request is initiated to the external mapping table storage module through the conversion control module, and the corresponding page-level mapping item is extracted from the mapping table storage module based on the page number. The mapping lookup table cache module dynamically caches mapping items based on access hotspots, and employs Least Recently Used, First-In-First-Out, and random replacement strategies. The mapping table is a data structure that records the correspondence between the peer access address or page number and the local target address or physical page. The mapping table storage module is specifically used to store large-scale page-level address mapping relationships. The verification module is used to verify the page-level mapping item and the access attribute. If the query result is a cache miss and the verification result is passed, the page-level mapping item is written into the mapping lookup table cache module to complete the cache backfill. The address generation and forwarding module is used to generate a local target address based on the target page base address in the page-level mapping item and the page offset, and to forward the access request to the second bus domain connected by the non-transparent bridge module based on the local target address through the access forwarding module.

7. A terminal, characterized in that, The terminal includes a memory and one or more processors; the memory stores one or more programs; the programs contain instructions for executing the address mapping method based on a non-transparent bridge and a mapping lookup table cache as described in any one of claims 1 to 5; the processor is used to execute the programs.

8. A computer-readable storage medium storing a plurality of instructions, characterized in that, The instructions are applicable to being loaded and executed by a processor to implement the steps of the address mapping method based on a non-transparent bridge and a mapped lookup table cache as described in any one of claims 1 to 5.

Images