Method for improving feedback coefficient of residual error amplifier in double-capacitor sampling residual gain unit

Abstract

The invention provides a method for improving a feedback coefficient of a residual error amplifier in a double-capacitor sampling margin gain unit. A circuit comprises a sampling circuit module, a DAC module and a switched capacitor amplifier module. According to the circuit disclosed by the invention, a novel DAC control time sequence can be adopted under the condition of ensuring the same amplification times of residual error signals, so that the sampling capacitance of the DAC can be halved, the feedback coefficient of the RA can be increased, the noise suppression capability of the circuit can be improved, the design difficulty of the RA can be reduced, the power consumption of the circuit can be reduced, and the circuit performance can be improved.

Description

Technical Field

[0001] This invention relates to the field of analog-to-digital converter design, and more specifically to a method for improving the feedback coefficient of the residual amplifier in a dual-capacitor sampling margin gain unit. Background Technology

[0002] The statements in this section are merely to provide background information in relation to the present invention to aid in understanding the invention, and such background information does not necessarily constitute prior art.

[0003] Traditional pipelined ADCs use single-capacitor sampling for the margin gain unit: the sampling capacitor for the input signal is shared with the sampling capacitor for the DAC. This method increases the feedback coefficient of the residual amplifier (RA), thus reducing the design complexity of the RA. However, this method suffers from a memory effect, meaning the DAC's sampling signal can affect the establishment of the input signal during the sampling phase. To address this effect, the sampling capacitor can be reset before the sampling phase begins, but this reduces the sampling time and increases design complexity. To solve this problem, a dual-capacitor sampling method can be used, separating the DAC's sampling capacitor from the input signal's sampling capacitor. This method avoids the memory effect. Furthermore, separating the DAC's sampling capacitor from the signal's sampling capacitor allows us to set a desired reference voltage value without requiring the signal and the DAC's reference voltage to operate within the same range. However, this method has a drawback: it reduces the feedback coefficient of the RA, thus increasing the design complexity of the residual amplifier (RA). Summary of the Invention

[0004] To address the problems existing in the above-mentioned traditional technologies, the present invention aims to propose a method for improving the feedback coefficient of the residual amplifier in a dual-capacitor sampling margin gain unit. Under the premise of ensuring the same residual signal amplification factor, the method improves the feedback coefficient of the RA, enhances the circuit's noise suppression capability, reduces the design difficulty of the RA, reduces the power consumption of the circuit, and improves the circuit performance.

[0005] The present invention provides the following technical solution: a method for improving the feedback coefficient of the residual amplifier in a dual-capacitor sampling margin gain unit, characterized in that it includes a sampling circuit, a DAC circuit, and a switched capacitor amplifier circuit.

[0006] The method for improving the feedback coefficient of the residual amplifier in a dual-capacitor sampling margin gain unit according to the present invention includes a sampling circuit comprising a first transistor NMOS1, a second transistor NMOS2, a first gate voltage bootstrap circuit BTSP1, a second gate voltage bootstrap circuit BTSP2, and a body effect modulation circuit BEM. The first gate voltage bootstrap circuit BTSP1 and the second gate voltage bootstrap circuit BTSP2 provide constant gate-source voltage drops for the first transistor NMOS1 and the second transistor NMOS2, respectively. The body effect modulation circuit BEM provides bias voltages for the first transistor NMOS1 and the second transistor NMOS2 to mitigate their body effect. The function of the sampling circuit is to acquire external input signals.

[0007] According to the method of improving the feedback coefficient of the residual amplifier in the dual-capacitor sampling margin gain unit of the present invention, the DAC circuit samples the output signal of the external FLASH ADC and converts it into an analog signal, which is then input to the first feedback capacitor C3 and the second feedback capacitor C4. Subsequently, in the amplification stage, the difference between the signal and the input signal is amplified.

[0008] The method for improving the feedback coefficient of the residual amplifier in the dual-capacitor sampling margin gain unit according to the present invention includes a switched-capacitor amplifier circuit comprising a third transistor NMOS3, a fourth transistor NMOS4, a fifth transistor NMOS5, a sixth transistor NMOS6, a seventh transistor NMOS7, an eighth transistor NMOS8, a ninth transistor NMOS9, a tenth transistor NMOS10, an eleventh transistor NMOS11, a twelfth transistor NMOS12, a thirteenth transistor NMOS13, a fourteenth transistor NMOS14, a fifteenth transistor NMOS15, a sixteenth transistor NMOS16, a seventeenth transistor PMOS1, an eighteenth transistor PMOS2, a first sampling capacitor C1, a second sampling capacitor C2, a first feedback capacitor C3, a second feedback capacitor C4, and a residual amplifier RA, which amplifies the input signal by subtracting the output voltage of the DAC.

[0009] The method for improving the feedback coefficient of the residual amplifier in the dual-capacitor sampling margin gain unit according to the present invention includes a gate voltage bootstrap circuit in the sampling circuit comprising an inverter INV1, a first transistor NMOS1, a second transistor NMOS2, a third transistor NMOS3, a fourth transistor NMOS4, a fifth transistor NMOS5, a sixth transistor NMOS6, a seventh transistor PMOS1, an eighth transistor PMOS2, a ninth transistor PMOS3, a tenth transistor PMOS4, and a first capacitor C1.

[0010] The method for improving the feedback coefficient of the residual amplifier in the dual-capacitor sampling margin gain unit according to the present invention includes a bulk effect modulation circuit BEM comprising a first transistor NMOS1, a second transistor NMOS2, a third transistor NMOS3, and a fourth transistor NMOS4.

[0011] The method for improving the feedback coefficient of the residual amplifier in the dual-capacitor sampling margin gain unit according to the present invention includes a DAC circuit comprising a first output control module OUT_CTRL0, a second output control module OUT_CTRL1, a third output control module OUT_CTRL2, a fourth output control module OUT_CTRL3, a fifth output control module OUT_CTRL4, a sixth output control module OUT_CTRL5, a seventh output control module OUT_CTRL6, an eighth output control module OUT_CTRL7, a first level shift circuit LS1, a second level shift circuit LS2, a third level shift circuit LS3, a fourth level shift circuit LS4, and a fifth level shift circuit LS5. Circuits LS5, LS6 (sixth level shifter), LS7 (seventh level shifter), LS8 (eighth level shifter), LS9 (ninth level shifter), LS10 (tenth level shifter), LS11 (eleventh level shifter), LS12 (twelfth level shifter), LS13 (thirteenth level shifter), LS14 (fourteenth level shifter), LS15 (fifteenth level shifter), LS16 (sixteenth level shifter), OUT1 (first output module), OUT2 (second output module), OUT3 (third output module), OUT4 (fourth output module), OUT5 (fifth output module), OUT6 (sixth output module), OUT7 (seventh output module), and OUT8 (eighth output module).

[0012] The method for improving the feedback coefficient of the residual amplifier in the dual-capacitor sampling margin gain unit according to the present invention includes the following RA circuit: a first transistor NMOS1, a second transistor NMOS2, a third transistor NMOS3, a fourth transistor NMOS4, a fifth transistor NMOS5, a sixth transistor NMOS6, a seventh transistor NMOS7, an eighth transistor NMOS8, a ninth transistor NMOS9, a tenth transistor PMOS1, an eleventh transistor PMOS2, a twelfth transistor PMOS3, a thirteenth transistor PMOS4, a fourteenth transistor PMOS5, a fifteenth transistor PMOS6, a first Miller compensation capacitor C1, a second Miller compensation capacitor C2, a first zero-adjustment resistor R1, a second zero-adjustment resistor R2, a first gain boosting circuit GBST1, a second gain boosting circuit GBST2, and a fully differential gain boosting circuit FDGBST.

[0013] The method for improving the feedback coefficient of the residual amplifier in the dual-capacitor sampling margin gain unit according to the present invention includes a DAC output control module OUT_CTRL comprising a first inverter INV1, a second inverter INV2, a first AND gate AND1, and a second AND gate AND2.

[0014] The method for improving the feedback coefficient of the residual amplifier in the dual-capacitor sampling margin gain unit according to the present invention includes a level shifting circuit LS comprising a first inverter INV1, a second inverter INV2, an output buffer BUF, a first transistor NMOS1, a second transistor NMOS2, a third transistor NMOS3, a fourth transistor NMOS4, a fifth transistor PMOS1, and a sixth transistor PMOS2.

[0015] The method for improving the feedback coefficient of the residual amplifier in the dual-capacitor sampling margin gain unit according to the present invention includes a DAC output module comprising a first transistor NMOS1, a second transistor NMOS2, a third transistor NMOS3, a fourth transistor NMOS4, a fifth transistor NMOS5, a sixth transistor NMOS6, a seventh transistor NMOS7, an eighth transistor NMOS8, a ninth transistor NMOS9, a tenth transistor NMOS10, a first capacitor C1, and a second capacitor C2.

[0016] The method for improving the feedback coefficient of the residual amplifier in the dual-capacitor sampling margin gain unit according to the present invention describes a gain boosting circuit (GBST) in the residual amplifier (RA). The GBST circuit comprises a first transistor NMOS1, a second transistor NMOS2, a third transistor NMOS3, a fourth transistor NMOS4, a fifth transistor NMOS5, a sixth transistor PMOS1, a seventh transistor PMOS2, an eighth transistor PMOS3, and a ninth transistor PMOS4. The function of this module is to improve the performance of the RA.

[0017] The FDGBST circuit in the residual amplifier RA of the dual-capacitor sampling margin gain unit according to the present invention includes a first transistor NMOS1, a second transistor NMOS2, a third transistor NMOS3, a fourth transistor NMOS4, a fifth transistor NMOS5, a sixth transistor NMOS6, a seventh transistor NMOS7, an eighth transistor NMOS8, a ninth transistor PMOS1, a tenth transistor PMOS2, an eleventh transistor PMOS3, a twelfth transistor PMOS4, a thirteenth transistor PMOS5, a fourteenth transistor PMOS6, a fifteenth transistor PMOS7, a sixteenth transistor PMOS8, a seventeenth transistor PMOS9, and an eighteenth transistor PMOS10. The function of this module is to improve the gain of RA.

[0018] The technical effects and advantages of this invention are as follows:

[0019] In this invention, the gate voltage bootstrap circuit BTSP and the bulk effect modulation circuit BEM are... Figure 1 In the sampling phase, the first transistor NMOS1 and the second transistor NMOS2 provide a constant gate-source voltage VGS and a constant source-substrate voltage VSB, resulting in a nearly constant on-resistance for these two transistors throughout the signal input range, thus increasing the linearity of the sampling circuit. This invention employs a dual-capacitor sampling technique, avoiding the memory effect caused by the DAC circuit and sampling circuit sharing the sampling capacitor. Furthermore, the DAC circuit uses a novel timing sequence, allowing the DAC sampling capacitor to sample the reference voltage during both the sampling and amplification phases. This halves the size of the DAC sampling capacitor, thereby reducing the DAC circuit area, increasing the feedback coefficient of the residual amplifier RA, halving the noise amplification effect, improving the circuit's noise suppression capability, reducing the design difficulty of the RA, and lowering circuit power consumption.

[0020] Other features and advantages of the invention will be set forth in the following description, or some features and advantages may be inferred from the description or determined without doubt, or may be learned by practicing the techniques described above.

[0021] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0022] Figure 1 This is a circuit structure diagram in a specific embodiment of the present invention;

[0023] Figure 2 This is a structural diagram of the gate voltage bootstrap circuit BTSP in a specific embodiment of the present invention;

[0024] Figure 3 This is a BEM structure diagram of the body effect modulation circuit in a specific embodiment of the present invention;

[0025] Figure 4 This is a structural diagram of the DAC in a specific embodiment of the present invention;

[0026] Figure 5 This is a structural diagram of the residual amplifier RA in today's example of the present invention;

[0027] Figure 6 This is a structural diagram of the output control module OUT_CTRL in the DAC module of this invention;

[0028] Figure 7 This is a structural diagram of the level shifting circuit LS in the DAC module of the present invention;

[0029] Figure 8 This is a structural diagram of the output module OUT in the DAC module of the present invention;

[0030] Figure 9 This is a structural diagram of the gain boosting circuit GBST in the residual amplifier RA module of the present invention;

[0031] Figure 10 This is a structural diagram of the fully differential gain boosting circuit FDGBST in the residual amplifier RA of the present invention;

[0032] Explanation of reference numerals in the attached figures

[0033] 1. Sampling Circuit

[0034] 2. DAC Circuit

[0035] 3 Switched-capacitor amplifier module

[0036] VDD power supply

[0037] RA residual amplifier Detailed Implementation

[0038] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Preferred embodiments of the invention are shown in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0039] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0040] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and is not limited to the embodiments set forth herein.

[0041] Please see Figures 1 to 10 As shown, this invention proposes a method for improving the feedback coefficient of the residual amplifier in a dual-capacitor sampling margin gain unit, and introduces ten specific circuit structures: the overall circuit structure, the gate voltage bootstrap circuit structure, the bulk effect modulation circuit structure, the DAC structure, the residual amplifier RA structure, the output control circuit structure in the DAC, the level shift circuit LS structure in the output, the output module structure in the DAC, the GABT structure in the RA, and the FDGBST structure in the RA.

[0042] In one example, the overall circuit structure is as follows: Figure 1As shown, the input terminal CLK of the first gate voltage bootstrap circuit BTSP1 is connected to the input signal VSAMPLE, the input terminal CLK of the second gate voltage bootstrap circuit BTSP2, the input terminal CLK of the bulk effect modulation circuit BEM, the DAC input terminal VSAMPLE, the gate of the twelfth transistor NMOS12, and the gate of the sixteenth transistor NMOS16. The input terminal VIN of the first gate voltage bootstrap circuit BTSP1 is connected to the input signal VIP, the input terminal VIP of the bulk effect modulation circuit BEM, and the source of the first transistor NMOS1. The output terminal VG of the first gate voltage bootstrap circuit BTSP1 is connected to the input terminal VG1 of the bulk effect modulation circuit BEM and the first transistor NMOS1. The gate of NMOS1 is connected to the ground plane. The input terminal VIN of the second gate voltage bootstrap circuit BTSP2 is connected to the input signal VIN, the input terminal VIN of the bulk effect modulation circuit BEM, and the source of the second transistor NMOS2. The output terminal VG of the second gate voltage bootstrap circuit BTSP2 is connected to the input terminal VG2 of the bulk effect modulation circuit BEM and the gate of the second transistor NMOS2. The output terminal OUTP of the bulk effect modulation circuit BEM is connected to the substrate of the first transistor NMOS1. The output terminal OUTN of the bulk effect modulation circuit BEM is connected to the substrate of the second transistor NMOS2. The input terminal VREFH of the DAC is connected to the input signal VREFH. The DAC input terminals INP<7:0> are connected to the input signal FLASH_OUTP<7:0>. The DAC input terminal VSAMPLE_VDD is connected to the input signal VSAMPLE_VDDD. The DAC input terminal VCM is connected to the input signal VCM1. The DAC input terminal VSAMPLE_B is connected to the input signal VSAMPLE_B. The DAC input terminal VSAMPLE_B_VDD is connected to the input signal VSAMPLE_B_VDDD. The DAC input terminal INN<7:0> is connected to the input signal FLASH_OUTN<7:0>. The DAC input terminal VREFL is connected to the input signal FLASH_OUTP<7:0>. The signal VREFL is connected; the RA input terminal VREF is connected to the input signal VREF; the RA input terminal VN is connected to the drain of the eighth transistor NMOS8, the drain of the tenth transistor NMOS10, and the drain of the eleventh transistor NMOS11; the RA input terminal VBP<4:0> is connected to the input signal VBP<4:0>; the RA input terminal VBN<2:0> is connected to the input signal VBN<2:0>; the RA input terminal VP is connected to the drain of the seventh transistor NMOS7, the drain of the ninth transistor NMOS9, and the source of the tenth transistor NMOS10; the RA input terminal CMFB1 is connected to the input signal CMFB1; the RA input terminal CMFB2 is connected to the input signal CMFB2; and the RA input terminal CMFB3 is connected to the input signal CMFB3.The drain of the first transistor NMOS1 is connected to the lower plate of the first sampling capacitor C1 and the drain of the third transistor NMOS3. The drain of the second transistor NMOS2 is connected to the lower plate of the second sampling capacitor C2 and the source of the third transistor NMOS3. The gate of the third transistor NMOS3 is connected to the input signal VHOLD, the gate of the seventh transistor NMOS7, the gate of the eighth transistor NMOS8, the gate of the thirteenth transistor NMOS13, and the gate of the fifteenth transistor NMOS15. The gate of the fourth transistor NMOS4 is connected to the input signal VSAMPLE_A, the gate of the fifth transistor NMOS5, and the gate of the sixth transistor NMOS6. The drain of transistor S4 is connected to the source of the fifth transistor NMOS5, the source of the seventh transistor NMOS7, the upper plate of the second sampling capacitor C2, the lower plate of the first feedback capacitor C3, and the DAC output terminal OUTN<7:0>. The source of the fourth transistor NMOS4 is connected to the input signal VCM2 and the source of the sixth transistor NMOS6. The drain of the sixth transistor NMOS6 is connected to the drain of the fifth transistor NMOS5, the source of the eighth transistor NMOS8, the upper plate of the first sampling capacitor C1, the lower plate of the second feedback capacitor C4, and the DAC output terminal OUTP<7:0>. The gate of the ninth transistor NMOS9 is connected to the input signal VSAMPLE_DELAY and the tenth transistor NMOS10. The gates of the eleventh transistor NMOS11, the fourteenth transistor NMOS14, the seventeenth transistor PMOS1, and the eighteenth transistor PMOS2 are connected. The source of the ninth transistor NMOS9 is connected to the input signal VCM3 and the source of the eleventh transistor NMOS11. The drain of the twelfth transistor NMOS12 is connected to the source of the thirteenth transistor NMOS13, the source of the seventeenth transistor PMOS1, and the upper plate of the first feedback capacitor C3. The source of the twelfth transistor NMOS12 is connected to the input signal VCM4 and the source of the sixteenth transistor NMOS16. The drain of the thirteenth transistor NMOS13 is connected to the gate of the fourteenth transistor NMOS14. The source of OS14, the drain of the seventeenth transistor PMOS1, the RA output terminal VON, and the output terminal OUTN are connected. The drain of the fifteenth transistor NMOS15 is connected to the drain of the fourteenth transistor NMOS14, the drain of the eighteenth transistor PMOS2, the RA output terminal VOP, and the output terminal OUTP. The drain of the sixteenth transistor NMOS16 is connected to the source of the fifteenth transistor NMOS15, the source of the eighteenth transistor PMOS2, and the upper plate of the second feedback capacitor C4. The first transistor NMOS1, the second transistor NMOS2, the first gate voltage bootstrap circuit BTSP1, the second gate voltage bootstrap circuit BTSP2, and the body effect modulation circuit BEM together constitute the sampling circuit.The first gate voltage bootstrap circuit BTSP1 and the second gate voltage bootstrap circuit BTSP2 provide constant gate-source voltage drops for the first transistor NMOS1 and the second transistor NMOS2, respectively. The body effect modulation circuit BEM provides bias voltages for the first transistor NMOS1 and the second transistor NMOS2 to mitigate their body effect. The DAC circuit samples external FLASH memory. The ADC outputs a signal and converts it into an analog signal, which is then input to the first feedback capacitor C3 and the second feedback capacitor C4. The third transistor NMOS3, fourth transistor NMOS4, fifth transistor NMOS5, sixth transistor NMOS6, seventh transistor NMOS7, eighth transistor NMOS8, ninth transistor NMOS9, tenth transistor NMOS10, eleventh transistor NMOS11, twelfth transistor NMOS12, thirteenth transistor NMOS13, fourteenth transistor NMOS14, fifteenth transistor NMOS15, sixteenth transistor NMOS16, seventeenth transistor PMOS1, eighteenth transistor PMOS2, the first sampling capacitor C1, the second sampling capacitor C2, the first feedback capacitor C3, the second feedback capacitor C4, and the residual amplifier RA together constitute a switched-capacitor amplifier, which amplifies the difference between the input signal and the DAC output voltage.

[0043] In one example, the gate voltage bootstrap circuit structure is as follows: Figure 2As shown, the gate of the first transistor NMOS1 is connected to the output signal VOUT, the gate of the second transistor NMOS2, the drain of the fifth transistor NMOS5, the gate of the eighth transistor PMOS2, and the drain of the ninth transistor PMOS3. The drain of the first transistor is connected to the source of the second transistor NMOS2, the source of the third transistor NMOS3, the drain of the fourth transistor NMOS4, and the lower plate of the first capacitor C1. The source of the first transistor NMOS1 is connected to the input signal VIN. The drain of the second transistor NMOS2 is connected to the drain of the third transistor NMOS3, the drain of the seventh transistor PMOS1, and the gate of the ninth transistor PMOS3. The gate of the third transistor NMOS3 is connected to the input signal PHI, the input of the first inverter INV1, and the gate of the seventh transistor PMOS1. The gate of the fourth transistor NMOS4 is connected to the output PHIB of the first inverter, the gate of the sixth transistor NMOS6, and the gate of the tenth transistor PMOS4. The source of the fourth transistor NMOS4 is connected to ground. The gate of the fifth transistor NMOS5 is connected to the power supply VDD. The source of the fifth transistor NMOS5 is connected to the drain of the sixth transistor NMOS6 and the drain of the tenth transistor PMOS4. The source of the sixth transistor is connected to ground. The source of the seventh transistor PMOS1 is connected to the power supply VDD. The drain of the eighth transistor PMOS2 is connected to its substrate, the source of the ninth transistor PMOS3, the substrate of the ninth transistor PMOS3, and the upper plate of the first capacitor C1. The source of the eighth transistor is connected to the power supply VDD. The source of the tenth transistor is connected to the power supply VDD.

[0044] In one example, the bulk effect modulation circuit (BEM) structure is as follows: Figure 3 As shown, the gate of the first transistor NMOS1 is connected to the input signal VSAMPLE and the gate of the third transistor NMOS3. The drain of the first transistor NMOS1 is connected to the output signal OUTP and the drain of the second transistor NMOS2. The source of the first transistor NMOS1 is connected to its substrate and ground. The gate of the second transistor NMOS2 is connected to the input signal VG1. The source of the second transistor NMOS2 is connected to the input signal VIP and its substrate. The drain of the third transistor NMOS3 is connected to the output signal OUTN and the drain of the fourth transistor NMOS4. The source of the third transistor NMOS3 is connected to its substrate and ground. The gate of the fourth transistor NMOS4 is connected to the input signal VG2. The source of the fourth transistor NMOS4 is connected to the input signal VIN and its substrate.

[0045] In one example, the DAC circuit structure is as follows: Figure 4As shown, the input terminal INP of the first output control module OUT_CTRL0 is connected to the input signal INP0, and the input terminal INN of the first output control module is connected to the input signal INN0. The input terminal VSAMPLE_B_VDD of the first output control module OUT_CTRL0 is connected to the input signal VSAMPLE_B_VDD, the input terminal VSAMPLE_B_VDD of the second output control module OUT_CTRL1, the input terminal VSAMPLE_B_VDD of the third output control module OUT_CTRL2, the input terminal VSAMPLE_B_VDD of the fourth output control module OUT_CTRL3, and the fifth output control module OUT_CTRL4... Input terminal VSAMPLE_B_VDD, input terminal VSAMPLE_B_VDD of the sixth output control module OUT_CTRL5, input terminal VSAMPLE_B_VDD of the seventh output control module OUT_CTRL6, input terminal VSAMPLE_B_VDD of the eighth output control module OUT_CTRL7, input terminal VSAMPLE_B_VDD of the first output module OUT1, input terminal VSAMPLE_B_VDD of the second output module OUT2, input terminal VSAMPLE_B_VDD of the third output module OUT3, input terminal VSAMPLE_B_VDD of the fourth output module OUT4, and input terminal VSAMPLE_B_VDD of the fifth output module OUT... The input terminals VSAMPLE_B_VDD of T5, VSAMPLE_B_VDD of the sixth output module OUT6, VSAMPLE_B_VDD of the seventh output module OUT7, and VSAMPLE_B_VDD of the eighth output module OUT8 are connected. The output terminal L of the first output control module OUT_CTRL0 is connected to the input terminal VIN of the first level shift circuit LS1. The output terminal R of the first output control module OUT_CTRL0 is connected to the input terminal VIN of the second level shift circuit LS2. The input terminal INP of the second output control module OUT_CTRL1 is connected to the input signal INP1. The second output control module OUT_CTRL1 has its input terminal INN connected to the input signal INN1. The output terminal L of the second output control module OUT_CTRL1 is connected to the input terminal VIN of the third level shift circuit LS3. The output terminal R of the second output control module OUT_CTRL1 is connected to the input terminal VIN of the fourth level shift circuit LS4. The input terminal INP of the third output control module OUT_CTRL2 is connected to the input signal INP2. The input terminal INN of the third output control module OUT_CTRL2 is connected to the input signal INN2. The output terminal L of the third output control module OUT_CTRL2 is connected to the input terminal VIN of the fifth level shift circuit LS5.The output terminal R of the third output control module OUT_CTRL2 is connected to the input terminal VIN of the sixth level shift circuit LS6. The input terminal INP of the fourth output control module OUT_CTRL3 is connected to the input signal INP3. The input terminal INN of the fourth output control module OUT_CTRL3 is connected to the input signal INN3. The output terminal L of the fourth output control module OUT_CTRL3 is connected to the input terminal VIN of the seventh level shift circuit LS7. The output terminal R of the fourth output control module OUT_CTRL3 is connected to the input terminal VIN of the eighth level shift circuit LS8. The input terminal INP of the fifth output control module OUT_CTRL4 is connected to the input signal INP4. The fifth output control module OUT_CTRL4 has its input terminal INN connected to the input signal INN4. Its output terminal L is connected to the input terminal VIN of the ninth level shift circuit LS9. Its output terminal R is connected to the input terminal VIN of the tenth level shift circuit LS10. The sixth output control module OUT_CTRL5 has its input terminal INP connected to the input signal INP5. Its input terminal INN is connected to the input signal INN5. Its output terminal L is connected to the input terminal VIN of the eleventh level shift circuit LS11. The output terminal R of the sixth output control module OUT_CTRL5 is connected to the input terminal VIN of the twelfth level shift circuit LS12. The input terminal INP of the seventh output control module OUT_CTRL6 is connected to the input signal INP6. The input terminal INN of the seventh output control module OUT_CTRL6 is connected to the input signal INN6. The output terminal L of the seventh output control module OUT_CTRL6 is connected to the input terminal VIN of the thirteenth level shift circuit LS13. The output terminal R of the seventh output control module OUT_CTRL6 is connected to the input terminal VIN of the fourteenth level shift circuit LS14. The input terminal INP of the eighth output control module OUT_CTRL7 is connected to the input signal... INP7, the input terminal INN of the eighth output control module OUT_CTRL7 is connected to the input signal INN7, the output terminal L of the eighth output control module OUT_CTRL7 is connected to the input terminal VIN of the fifteenth level shift circuit LS15, the output terminal R of the eighth output control module OUT_CTRL7 is connected to the input terminal VIN of the sixteenth level shift circuit LS16, the output terminal OUT of the first level shift circuit LS1 is connected to the input terminal INP of the first output module OUT1, the output terminal OUT of the second level shift circuit LS2 is connected to the input terminal INN of the first output module OUT1, and the output terminal OUT of the third level shift circuit LS3 is connected to the input terminal INP of the second output module OUT2.The output terminal OUT of the fourth level shift circuit LS4 is connected to the input terminal INN of the second output module OUT2; the output terminal OUT of the fifth level shift circuit LS5 is connected to the input terminal INP of the third output module OUT3; the output terminal OUT of the sixth level shift circuit LS6 is connected to the input terminal INN of the third output module OUT3; the output terminal OUT of the seventh level shift circuit LS7 is connected to the input terminal INP of the fourth output module OUT4; the output terminal OUT of the eighth level shift circuit LS8 is connected to the input terminal INN of the fourth output module OUT4; the output terminal OUT of the ninth level shift circuit LS9 is connected to the input terminal INP of the fifth output module OUT5; the output terminal OUT of the tenth level shift circuit LS10 is connected to the input terminal INN of the fifth output module OUT5; the output terminal OUT of the eleventh level shift circuit LS11 is connected to the input terminal INP of the sixth output module OUT6; the output terminal OUT of the twelfth level shift circuit LS12 is connected to the input terminal INN of the sixth output module OUT6; the thirteenth level shift circuit... The output terminal OUT of the level shifting circuit LS13 is connected to the input terminal INP of the seventh output module OUT7. The output terminal OUT of the fourteenth level shifting circuit LS14 is connected to the input terminal INN of the seventh output module OUT7. The output terminal OUT of the fifteenth level shifting circuit LS15 is connected to the input terminal INP of the eighth output module OUT8. The output terminal OUT of the sixteenth level shifting circuit LS16 is connected to the input terminal INN of the eighth output module OUT8. The input terminal VSAMPLE of the first output module OUT1 is connected to the input signal VSAMPLE, the input terminal VSAMPLE of the second output module OUT2, the input terminal VSAMPLE of the third output module OUT3, the input terminal VSAMPLE of the fourth output module OUT4, the input terminal VSAMPLE of the fifth output module OUT5, the input terminal VSAMPLE of the sixth output module OUT6, the input terminal VSAMPLE of the seventh output module OUT7, and the input terminal VSAMPLE of the eighth output module OUT8. The input terminal VSAMPLE_VDD of the first output module OUT1 is connected to the input signal VSAMPLE_VDD, the input terminal VSAMPLE_VDD of the second output module OUT2, the input terminal VSAMPLE_VDD of the third output module OUT3, the input terminal VSAMPLE_VDD of the fourth output module OUT4, the input terminal VSAMPLE_VDD of the fifth output module OUT5, the input terminal VSAMPLE_VDD of the sixth output module OUT6, the input terminal VSAMPLE_VDD of the seventh output module OUT7, and the input terminal VSAMPLE_VDD of the eighth output module OUT8.The input terminal VREFH of the first output module OUT1 is connected to the input signal VREFH, the input terminal VREFH of the second output module OUT2, the input terminal VREFH of the third output module OUT3, the input terminal VREFH of the fourth output module OUT4, the input terminal VREFH of the fifth output module OUT5, the input terminal VREFH of the sixth output module OUT6, the input terminal VREFH of the seventh output module OUT7, and the input terminal VREFH of the eighth output module OUT8. The input terminal VREFL of the first output module OUT1 is connected to the input signal VREFL, the input terminal VREFL of the second output module OUT2, and the input terminal VREFH of the third output module OUT3. The input terminal VREFL of the first output module OUT1, the input terminal VREFL of the fourth output module OUT4, the input terminal VREFL of the fifth output module OUT5, the input terminal VREFL of the sixth output module OUT6, the input terminal VREFL of the seventh output module OUT7, and the input terminal VREFL of the eighth output module OUT8 are connected. The input terminal VSAMPLE_B of the first output module OUT1 is connected to the input signal VSAMPLE_B, the input terminal VSAMPLE_B of the second output module OUT2, the input terminal VSAMPLE_B of the third output module OUT3, the input terminal VSAMPLE_B of the fourth output module OUT4, and the input terminal VSA of the fifth output module OUT5 are connected to the input terminal VREFL of the fifth output module OUT5. The input terminals VSAMPLE_B of the sixth output module OUT6, OUT7, and OUT8 are connected. The output terminal OUTP of the first output module OUT1 is connected to the output signal OUTP0. The output terminal OUTN of the first output module OUT1 is connected to the output signal OUTN0. The output terminal OUTP of the second output module OUT2 is connected to the output signal OUTP1. The output terminal OUTN of the second output module OUT2 is connected to the output signal OUTN1. The output terminal OUTP of the third output module OUT3 is connected to the output signal OUTN0. The output terminals of the third output module OUT3 (OUTN) and the fourth output module OUT4 (OUTP) and the fifth output module OUT5 (OUTN) are connected to the output signal OUTP4 and OUTP5, respectively. The output terminals of the sixth output module OUT6 (OUTP) and the seventh output module OUT7 (OUTP) are also connected to the output signal OUTP6.The output terminal OUTN of the seventh output module OUT7 is connected to the output signal OUTN6, the output terminal OUTP of the eighth output module OUT8 is connected to the output signal OUTP7, and the output terminal OUTN of the eighth output module OUT8 is connected to the output signal OUTN7.

[0046] In one example, the residual amplifier RA is as follows: Figure 5As shown, the gate of the first transistor NMOS1 is connected to the input signal CMFB1. The drain of the first transistor NMOS1 is connected to the source of the second transistor NMOS2 and the source of the third transistor NMOS3. The source of the first transistor NMOS1 is connected to ground. The gate of the second transistor NMOS2 is connected to the input signal VP. The drain of the second transistor NMOS2 is connected to the source of the fourth transistor NMOS4 and the input terminal VN of the first gain boost circuit GBST1. The gate of the third transistor NMOS3 is connected to the input signal VN. The drain of the third transistor NMOS3 is connected to the source of the fifth transistor NMOS5 and the input terminal VN of the second gain boost circuit GBST2. The gate of the fourth transistor NMOS4 is connected to the output terminal OUT of the first gain boost circuit GBST1. The drain of the fourth transistor NMOS4 is connected to the gate of the ninth transistor NMOS9, the drain of the tenth transistor PMOS1, and the lower end of the second zero-adjustment resistor R2. The gate of the fifth transistor NMOS5 is connected to the output terminal OUT of the second gain boost circuit GBST2. The drain of the fifth transistor NMOS5 is connected to the gate of the eighth transistor NMOS8, the drain of the eleventh transistor PMOS2, and the lower end of the first zero-adjustment resistor R1. The gate of the sixth transistor NMOS6 is connected to the input signal CMFB2 and the gate of the seventh transistor NMOS7. The drain of the sixth transistor NMOS6 is connected to the drain of the seventh transistor NMOS7, the source of the eighth transistor NMOS8, and the source of the ninth transistor NMOS9. The source of the sixth transistor NMOS6 is connected to ground. The source of the seventh transistor NMOS7 is connected to ground. The drain of the eighth transistor NMOS8 is connected to the drain of the fourteenth transistor PMOS5, the upper plate of the first Miller compensation capacitor C1, and the output signal VON. The drain of the ninth transistor NMOS9 is connected to the fifteenth transistor PMOS5. The drain of MOS6, the upper plate of the second Miller compensation capacitor C2, and the output signal VOP are connected. The gate of the tenth transistor PMOS1 is connected to the output terminal ON of the fully differential gain boost circuit FDGBST. The source of the tenth transistor PMOS1 is connected to the drain of the twelfth transistor PMOS3 and the input terminal VP of the fully differential gain boost circuit FDGBST. The gate of the eleventh transistor PMOS2 is connected to the output terminal OP of the fully differential gain boost circuit FDGBST. The source of the eleventh transistor PMOS11 is connected to the drain of the thirteenth transistor PMOS4 and the input terminal VN of the fully differential gain boost circuit FDGBST. The gate of the twelfth transistor PMOS3 is connected to the input signal VBP0 and the gate of the thirteenth transistor PMOS4. The source of the twelfth transistor PMOS3 is connected to the power supply VDD. The source of the thirteenth transistor PMOS4 is also connected to the power supply VDD.The gate of the fourteenth transistor PMOS5 is connected to the input signal VBP1 and the gate of the fifteenth transistor PMOS6. The source of the fourteenth transistor PMOS5 is connected to the power supply, and the source of the fifteenth transistor PMOS6 is connected to the power supply. The upper end of the first zero-adjustment resistor R1 is connected to the lower plate of the first Miller compensation capacitor C1, and the upper end of the second zero-adjustment resistor R2 is connected to the lower plate of the second Miller compensation capacitor C2. The input terminal VP of the first gain boost circuit GBST1 is connected to the input signal VREF and the input terminal VP of the second gain boost circuit GBST2. The input terminal VBP of the first gain boost circuit GBST1 is connected to the input signal VBP2 and the input terminal VBP of the second gain boost circuit GBST2. The input terminal VBN2 of the first gain boosting circuit GBST1 is connected to the input signal VBN2 and the input terminal VBN2 of the second gain boosting circuit GBST2. The input terminal VBN1 of the first gain boosting circuit GBST1 is connected to the input signal VBN1 and the input terminal VBN1 of the second gain boosting circuit GBST2. The input terminal VBN of the fully differential gain boosting circuit FDGBST is connected to the input signal VBN3. The input terminal VM of the fully differential gain boosting circuit FDGBST is connected to the input signal CMFB3. The input terminal VBP1 of the fully differential gain boosting circuit FDGBST is connected to the input signal VBP3. The input terminal VBP2 of the fully differential gain boosting circuit FDGBST is connected to the input signal VBP4.

[0047] In one example, the OUT_CTRL structure of the output control circuit in the DAC is as follows: Figure 6 As shown, the input of the first inverter INV1 is connected to the input signal INN and the input C of the second AND gate AND2. The output of the first inverter INV1 is connected to the input C of the first AND gate AND1. The input of the second inverter INV2 is connected to the input signal INP and the input B of the first AND gate AND1. The output of the second inverter INV2 is connected to the input B of the second AND gate AND2. The input A of the first AND gate AND1 is connected to the input signal VSAMPLE_B_VDD and the input A of the second AND gate AND2.

[0048] In one example, the level shifting circuit LS structure in the DAC is as follows: Figure 7The input terminal of the first inverter INV1 is connected to the input signal VIN. The output of the first inverter INV1 is connected to the input of the second inverter INV2 and the gate of the second transistor NMOS2. The output of the second inverter INV2 is connected to the gate of the first transistor NMOS1. The drain of the first transistor NMOS1, the source of the third transistor NMOS3, the gate of the fourth transistor NMOS4, and the gate of the sixth transistor PMOS2 are connected. The source of the first transistor NMOS1 is connected to ground. The drain of the second transistor NMOS2 is connected to the gate of the third transistor NMOS3, the source of the fourth transistor NMOS4, the gate of the fifth transistor PMOS1, and the input of the output buffer BUF. The source of the second transistor NMOS2 is connected to ground. The drain of the third transistor NMOS3 is connected to the drain of the fifth transistor PMOS1. The drain of the fourth transistor NMOS4 is connected to the drain of the sixth transistor PMOS2. The source of the fifth transistor PMOS1 is connected to the power supply VDD. The source of the sixth transistor PMOS2 is connected to the power supply VDD. The output of the input buffer is connected to the output signal OUT.

[0049] In one example, the DAC output module OUT is as follows: Figure 8As shown, the gate of the first transistor NMOS1 is connected to the input signal VSAMPLE, the gate of the fifth transistor NMOS5, and the gate of the sixth transistor NMOS6. The drain of the first transistor NMOS1 is connected to the drain of the second transistor NMOS2, and the lower plate of the first capacitor C1 is connected. The source of the first transistor NMOS1 is connected to the input signal VREFH and the source of the third transistor NMOS3. The gate of the second transistor NMOS2 is connected to the input signal VSAMPLE_B_VDD. The source of the second transistor NMOS2 is connected to the input signal VREFL and the source of the fourth transistor NMOS4. The gate of the third transistor NMOS3 is connected to the input signal VSAMPLE_B. The drain of the third transistor NMOS3 is connected to the drain of the fourth transistor NMOS4, and the lower plate of the second capacitor C2 is connected. The gate of the fourth transistor NMOS4 is connected to the input signal VSAMPLE_B. The transistors are connected to LE_VDD. The drain of the fifth transistor NMOS5 is connected to the drain of the seventh transistor NMOS7, the drain of the eighth transistor NMOS8, and the upper plate of the first capacitor C1. The source of the fifth transistor NMOS5 is connected to the input signal VCM and the source of the sixth transistor NMOS6. The drain of the sixth transistor NMOS6 is connected to the drain of the ninth transistor NMOS9, the drain of the tenth transistor NMOS10, and the upper plate of the second capacitor C2. The gate of the seventh transistor NMOS7 is connected to the input signal L and the gate of the ninth transistor NMOS9. The source of the seventh transistor NMOS7 is connected to the output signal OUTN and the source of the tenth transistor NMOS10. The gate of the eighth transistor NMOS8 is connected to the input signal R and the gate of the tenth transistor NMOS10. The source of the eighth transistor NMOS8 is connected to the output signal OUTP and the source of the ninth transistor NMOS9.

[0050] In one example, the GBST circuit in the residual amplifier RA is as follows: Figure 9As shown, the gate of the first transistor NMOS1 is connected to the input signal VBN1, the drain of the first transistor NMOS1 is connected to the source of the second transistor NMOS2 and the source of the third transistor NMOS3, the source of the first transistor NMOS1 is connected to ground, the gate of the second transistor NMOS2 is connected to the input signal VP, the drain of the second transistor NMOS2 is connected to the source of the fourth transistor NMOS4, the gate of the third transistor NMOS3 is connected to the input signal VN, the drain of the third transistor NMOS3 is connected to the source of the fifth transistor NMOS5, and the gate of the fourth transistor NMOS4 is connected to the input signal VBN2 and the gate of the fifth transistor NMOS5. The drain of the fourth transistor NMOS4 is connected to the drain of the sixth transistor PMOS1, the gate of the eighth transistor PMOS3, and the gate of the ninth transistor PMOS4. The drain of the fifth transistor NMOS5 is connected to the drain of the seventh transistor PMOS2 and the output signal OUT. The gate of the sixth transistor PMOS1 is connected to the input signal VBP and the gate of the seventh transistor PMOS2. The source of the sixth transistor PMOS1 is connected to the drain of the eighth transistor PMOS3. The source of the seventh transistor PMOS2 is connected to the drain of the ninth transistor PMOS4. The source of the eighth transistor PMOS3 is connected to the power supply VDD. The source of the ninth transistor PMOS4 is connected to the power supply VDD.

[0051] In one example, the fully differential gain boosting circuit FDGBST in the residual amplifier RA is as follows: Figure 10As shown, the gate of the first transistor NMOS1 is connected to the gate of the second transistor NMOS2, the gate of the sixth transistor NMOS6, the drain of the eighth transistor NMOS8, and the drain of the seventeenth transistor PMOS9. The drain of the first transistor NMOS1 is connected to the source of the third transistor NMOS3, and the source of the first transistor NMOS1 is connected to ground. The drain of the second transistor NMOS2 is connected to the source of the fourth transistor NMOS4, and the source of the second transistor NMOS2 is connected to ground. The gate of the third transistor NMOS3 is connected to the input signal VBN, the gate of the fourth transistor NMOS4, the gate of the seventh transistor NMOS7, and the gate of the eighth transistor NMOS9. The gates of transistors are connected to each other. The drain of the third transistor NMOS3 is connected to the output signal ON, the drain of the ninth transistor PMOS1, and the gate of the sixteenth transistor PMOS8. The drain of the fourth transistor NMOS4 is connected to the output signal OP, the drain of the tenth transistor PMOS2, and the gate of the fifteenth transistor PMOS7. The gate of the fifth transistor NMOS5 is connected to the drains of the seventh transistor NMOS7, the fifteenth transistor PMOS7, and the sixteenth transistor PMOS8. The drain of the fifth transistor NMOS5 is connected to the source of the seventh transistor NMOS7. The source of the fifth transistor NMOS5 is connected to ground. The drain of the sixth transistor NMOS6 is connected to the gate of the eighth transistor PMOS8. The source of transistor NMOS8 is connected to ground. The source of the sixth transistor NMOS6 is connected to ground. The gate of the ninth transistor PMOS1 is connected to the input signal VM, the gate of the tenth transistor PMOS2, and the gate of the seventeenth transistor PMOS9. The source of the ninth transistor PMOS1 is connected to the drain of the eleventh transistor PMOS3. The source of the tenth transistor PMOS2 is connected to the drain of the twelfth transistor PMOS4. The gate of the eleventh transistor PMOS3 is connected to the input signal VBP1 and the gate of the twelfth transistor PMOS4. The source of the eleventh transistor PMOS3 is connected to the drain of the thirteenth transistor PMOS5. The twelfth transistor PMOS6... The source of transistor 4 is connected to the drain of transistor 14 (PMOS 6). The gate of transistor 13 (PMOS 5) is connected to the input signal VP. The source of transistor 13 (PMOS 5) is connected to the power supply VDD. The gate of transistor 14 (PMOS 6) is connected to the input signal VN. The source of transistor 14 (PMOS 6) is connected to the power supply VDD. The source of transistor 15 (PMOS 7) is connected to the source of transistor 16 (PMOS 8), the source of transistor 17 (PMOS 9), and the drain of transistor 18 (PMOS 10). The gate of transistor 18 (PMOS 10) is connected to the input signal VBP2. The source of transistor 18 (PMOS 10) is connected to the power supply VDD.

[0052] Finally, it should be noted that the above-described embodiments are merely specific implementations of the present invention, used to illustrate the technical solutions of the present invention, and not to limit it. The scope of protection of the present invention is not limited thereto. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can still modify or easily conceive of changes to the technical solutions described in the foregoing embodiments within the technical scope disclosed in the present invention, or make equivalent substitutions for some of the technical features; and these modifications, changes, or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A method for improving the feedback coefficient of the residual amplifier in a dual-capacitor sampling margin gain unit, characterized in that... Including transistors NMOS1, NMOS2, NMOS3, NMOS4, NMOS5, NMOS6, NMOS7, NMOS8, NMOS9, NMOS10, NMOS11, NMOS12, NMOS13, NMOS14, NMOS15, NMOS16, PMOS17, PMOS2, C1, C2, C3, and C4; and a second sampling capacitor C1, a third sampling capacitor C2, a fourth feedback capacitor C3, and a fifth sampling capacitor C4. The circuit consists of a feedback capacitor C4, a first gate voltage bootstrap circuit BTSP1, a second gate voltage bootstrap circuit BTSP2, a bulk effect modulation circuit BEM, a DAC module, and a residual amplifier RA. The input terminal CLK of the first gate voltage bootstrap circuit BTSP1 is connected to the input signal VSAMPLE, the input terminal CLK of the second gate voltage bootstrap circuit BTSP2, the input terminal CLK of the bulk effect modulation circuit BEM, the DAC input terminal VSAMPLE, the gate of the twelfth transistor NMOS12, and the gate of the sixteenth transistor NMOS16. The input terminal VIN of the first gate voltage bootstrap circuit BTSP1 is connected to the input signal VIP, the input terminal VIP of the bulk effect modulation circuit BEM, and the source of the first transistor NMOS1. The output terminal VG of the first gate voltage bootstrap circuit BTSP1 is connected to the input terminal VG1 of the bulk effect modulation circuit BEM and the gate of the first transistor NMOS1. The input terminal VIN of the second gate voltage bootstrap circuit BTSP2 is connected to the input signal VIN, the input terminal VIN of the bulk effect modulation circuit BEM, and the source of the second transistor NMOS2. The output terminal VG of the second gate voltage bootstrap circuit BTSP2 is connected to the input terminal VG2 of the bulk effect modulation circuit BEM and the gate of the second transistor NMOS2. The output terminal OUTP of the bulk effect modulation circuit BEM is connected to the substrate of the first transistor NMOS1, and the output terminal OUTN of the bulk effect modulation circuit BEM is connected to the substrate of the second transistor NMOS2. The DAC input terminals VREFH, INP<7:0>, VSAMPLE_VDD, VCM, VSAMPLE_B, VSAMPLE_B_VDD, and INN<7:0> are connected to the input signal FLASH_OUTP<7:0>.The DAC input terminal VREFL is connected to the input signal VREFL. The RA input terminal VREF is connected to the input signal VREF. The RA input terminal VN is connected to the drain of the eighth transistor NMOS8, the drain of the tenth transistor NMOS10, and the drain of the eleventh transistor NMOS11. The RA input terminal VBP<4:0> is connected to the input signal VBP<4:0>. The RA input terminal VBN<2:0> is connected to the input signal VBN<2:0>. The RA input terminal VP is connected to the drain of the seventh transistor NMOS7, the drain of the ninth transistor NMOS9, and the source of the tenth transistor NMOS10. The RA input terminal CMFB1 is connected to the input signal CMFB1. The RA input terminal CMFB2 is connected to the input signal CMFB2. The RA input terminal CMFB3 is connected to the input signal CMFB3. The drain of the first transistor NMOS1 is connected to the lower plate of the first sampling capacitor C1 and the drain of the third transistor NMOS3. The drain of the second transistor NMOS2 is connected to the lower plate of the second sampling capacitor C2 and the source of the third transistor NMOS3. The gate of the third transistor NMOS3 is connected to the input signal VHOLD, the gate of the seventh transistor NMOS7, the gate of the eighth transistor NMOS8, the gate of the thirteenth transistor NMOS13, and the gate of the fifteenth transistor NMOS15. The gate of the fourth transistor NMOS4 is connected to the input signal VSAMPLE_A, the gate of the fifth transistor NMOS5, and the gate of the sixth transistor NMOS6. The drain of the fourth transistor NMOS4 is connected to the source of the fifth transistor NMOS5, the source of the seventh transistor NMOS7, the upper plate of the second sampling capacitor C2, the lower plate of the first feedback capacitor C3, and the DAC output terminal OUTN<7:0>. The source of the fourth transistor NMOS4 is connected to the input signal VCM2 and the source of the sixth transistor NMOS6. The drain of the sixth transistor NMOS6 is connected to the drain of the fifth transistor NMOS5, the source of the eighth transistor NMOS8, the upper plate of the first sampling capacitor C1, the lower plate of the second feedback capacitor C4, and the DAC output terminal OUTP<7:0>. The gate of the ninth transistor NMOS9 is connected to the input signal VSAMPLE_DELAY, the gate of the tenth transistor NMOS10, the gate of the eleventh transistor NMOS11, the gate of the fourteenth transistor NMOS14, the gate of the seventeenth transistor PMOS1, and the gate of the eighteenth transistor PMOS2. The source of the ninth transistor NMOS9 is connected to the input signal VCM3 and the source of the eleventh transistor NMOS11. The drain of the twelfth transistor NMOS12 is connected to the source of the thirteenth transistor NMOS13, the source of the seventeenth transistor PMOS1, and the upper plate of the first feedback capacitor C3.The source of the twelfth transistor NMOS12 is connected to the input signal VCM4 and the source of the sixteenth transistor NMOS16. The drain of the thirteenth transistor NMOS13 is connected to the source of the fourteenth transistor NMOS14, the drain of the seventeenth transistor PMOS1, the RA output terminal VON, and the output terminal OUTN. The drain of the fifteenth transistor NMOS15 is connected to the drain of the fourteenth transistor NMOS14, the drain of the eighteenth transistor PMOS2, the RA output terminal VOP, and the output terminal OUTP. The drain of the sixteenth transistor NMOS16 is connected to the source of the fifteenth transistor NMOS15 and the eighteenth transistor PMOS2. The source and upper plate of the second feedback capacitor C4 are connected. The first transistor NMOS1, the second transistor NMOS2, the first gate voltage bootstrap circuit BTSP1, the second gate voltage bootstrap circuit BTSP2, and the body effect modulation circuit BEM together constitute the sampling circuit. The first gate voltage bootstrap circuit BTSP1 and the second gate voltage bootstrap circuit BTSP2 provide constant gate-source voltage drops for the first transistor NMOS1 and the second transistor NMOS2, respectively. The body effect modulation circuit BEM provides bias voltages for the first transistor NMOS1 and the second transistor NMOS2 to mitigate their body effect. The DAC circuit samples the external FLASH memory. The ADC outputs a signal and converts it into an analog signal, which is then input to the first feedback capacitor C3 and the second feedback capacitor C4. The third transistor NMOS3, fourth transistor NMOS4, fifth transistor NMOS5, sixth transistor NMOS6, seventh transistor NMOS7, eighth transistor NMOS8, ninth transistor NMOS9, tenth transistor NMOS10, eleventh transistor NMOS11, twelfth transistor NMOS12, thirteenth transistor NMOS13, fourteenth transistor NMOS14, fifteenth transistor NMOS15, sixteenth transistor NMOS16, seventeenth transistor PMOS1, eighteenth transistor PMOS2, the first sampling capacitor C1, the second sampling capacitor C2, the first feedback capacitor C3, the second feedback capacitor C4, and the residual amplifier RA together constitute a switched-capacitor amplifier, which amplifies the difference between the input signal and the DAC output voltage.

2. The method for improving the feedback coefficient of the residual amplifier in a dual-capacitor sampling margin gain unit according to claim 1, characterized in that, The gate voltage bootstrap circuit includes: an inverter INV1, a first transistor NMOS1, a second transistor NMOS2, a third transistor NMOS3, a fourth transistor NMOS4, a fifth transistor NMOS5, a sixth transistor NMOS6, a seventh transistor PMOS1, an eighth transistor PMOS2, a ninth transistor PMOS3, a tenth transistor PMOS4, and a first capacitor C1. The gate of the first transistor NMOS1 is connected to the output signal VOUT, the gate of the second transistor NMOS2, the drain of the fifth transistor NMOS5, the gate of the eighth transistor PMOS2, and the drain of the ninth transistor PMOS3. The drain of the first transistor is connected to the source of the second transistor NMOS2, the source of the third transistor NMOS3, the drain of the fourth transistor NMOS4, and the lower plate of the first capacitor C1. The source of the first transistor NMOS1 is connected to the input signal VIN. The drain of the second transistor NMOS2 is connected to the drain of the third transistor NMOS3 and the drain of the seventh transistor PMOS1. The gate of the ninth transistor PMOS3 is connected to the power supply VDD. The gate of the third transistor NMOS3 is connected to the input signal PHI, the input of the first inverter INV1, and the gate of the seventh transistor PMOS1. The gate of the fourth transistor NMOS4 is connected to the output PHIB of the first inverter, the gate of the sixth transistor NMOS6, and the gate of the tenth transistor PMOS4. The source of the fourth transistor NMOS4 is connected to ground. The gate of the fifth transistor NMOS5 is connected to the power supply VDD. The source of the fifth transistor NMOS5 is connected to the drain of the sixth transistor NMOS6 and the drain of the tenth transistor PMOS4. The source of the sixth transistor is connected to ground. The source of the seventh transistor PMOS1 is connected to the power supply VDD. The drain of the eighth transistor PMOS2 is connected to its substrate, the source of the ninth transistor PMOS3, the substrate of the ninth transistor PMOS3, and the upper plate of the first capacitor C1. The source of the eighth transistor is connected to the power supply VDD. The source of the tenth transistor is connected to the power supply VDD.

3. The method for improving the feedback coefficient of the residual amplifier in a dual-capacitor sampling margin gain unit according to claim 1, characterized in that, The BEM module of the bulk effect modulation circuit includes: a first transistor NMOS1, a second transistor NMOS2, a third transistor NMOS3, and a fourth transistor NMOS4. The gate of the first transistor NMOS1 is connected to the input signal VSAMPLE and the gate of the third transistor NMOS3. The drain of the first transistor NMOS1 is connected to the output signal OUTP and the drain of the second transistor NMOS2. The source of the first transistor NMOS1 is connected to its substrate and ground. The gate of the second transistor NMOS2 is connected to the input signal VG1. The source of the second transistor NMOS2 is connected to the input signal VIP and its substrate. The drain of the third transistor NMOS3 is connected to the output signal OUTN and the drain of the fourth transistor NMOS4. The source of the third transistor NMOS3 is connected to its substrate and ground. The gate of the fourth transistor NMOS4 is connected to the input signal VG2. The source of the fourth transistor NMOS4 is connected to the input signal VIN and its substrate.

4. The method for improving the feedback coefficient of the residual amplifier in a dual-capacitor sampling margin gain unit according to claim 1 is characterized in that, The DAC circuit includes: a first output control module OUT_CTRL0, a second output control module OUT_CTRL1, a third output control module OUT_CTRL2, a fourth output control module OUT_CTRL3, a fifth output control module OUT_CTRL4, a sixth output control module OUT_CTRL5, a seventh output control module OUT_CTRL6, an eighth output control module OUT_CTRL7, a first level shift circuit LS1, a second level shift circuit LS2, a third level shift circuit LS3, a fourth level shift circuit LS4, a fifth level shift circuit LS5, a sixth level shift circuit LS6, a seventh level shift circuit LS7, an eighth level shift circuit LS8, and a ninth level shift circuit. The circuit consists of four level shifters: LS9 (10th level), LS10 (11th level), LS11 (12th level), LS13 (13th level), LS14 (14th level), LS15 (15th level), and LS16 (16th level). It also includes four output modules: OUT1 (1st level), OUT2 (2nd level), OUT3 (3rd level), OUT4 (4th level), OUT5 (5th level), OUT6 (6th level), OUT7 (7th level), and OUT8 (8th level). The first output control module OUT_CTRL0 has its input terminal INP connected to the input signal INP0, and its input terminal INN is connected to the input signal INN0.The first output control module OUT_CTRL0's input terminal VSAMPLE_B_VDD is connected to the input signal VSAMPLE_B_VDD; the second output control module OUT_CTRL1's input terminal VSAMPLE_B_VDD; the third output control module OUT_CTRL2's input terminal VSAMPLE_B_VDD; the fourth output control module OUT_CTRL3's input terminal VSAMPLE_B_VDD; the fifth output control module OUT_CTRL4's input terminal VSAMPLE_B_VDD; the sixth output control module OUT_CTRL5's input terminal VSAMPLE_B_VDD; and the seventh output control module OUT_CTRL6's input terminal... Input terminal VSAMPLE_B_VDD, input terminal VSAMPLE_B_VDD of the eighth output control module OUT_CTRL7, input terminal VSAMPLE_B_VDD of the first output module OUT1, input terminal VSAMPLE_B_VDD of the second output module OUT2, input terminal VSAMPLE_B_VDD of the third output module OUT3, input terminal VSAMPLE_B_VDD of the fourth output module OUT4, input terminal VSAMPLE_B_VDD of the fifth output module OUT5, input terminal VSAMPLE_B_VDD of the sixth output module OUT6, and input terminal VSAMPLE_B_VDD of the seventh output module OUT7. The input terminals VSAMPLE_B_VDD of the eighth output module OUT8 are connected. The output terminal L of the first output control module OUT_CTRL0 is connected to the input terminal VIN of the first level shift circuit LS1. The output terminal R of the first output control module OUT_CTRL0 is connected to the input terminal VIN of the second level shift circuit LS2. The input terminal INP of the second output control module OUT_CTRL1 is connected to the input signal INP1. The input terminal INN of the second output control module OUT_CTRL1 is connected to the input signal INN1. The output terminal L of the second output control module OUT_CTRL1 is connected to the input terminal VIN of the third level shift circuit LS3. The output terminal R of the second output control module OUT_CTRL1 is connected to the input terminal VIN of the fourth level shift circuit LS4. The input terminal INP of the third output control module OUT_CTRL2 is connected to the input signal INP2. The input terminal INN of the third output control module OUT_CTRL2 is connected to the input signal INN2. The output terminal L of the third output control module OUT_CTRL2 is connected to the input terminal VIN of the fifth level shift circuit LS5. The output terminal R of the third output control module OUT_CTRL2 is connected to the input terminal VIN of the sixth level shift circuit LS6. The input terminal INP of the fourth output control module OUT_CTRL3 is connected to the input signal INP3.The fourth output control module OUT_CTRL3 has its input terminal INN connected to the input signal INN3. Its output terminal L is connected to the input terminal VIN of the seventh level shift circuit LS7. Its output terminal R is connected to the input terminal VIN of the eighth level shift circuit LS8. The fifth output control module OUT_CTRL4 has its input terminal INP connected to the input signal INP4. Its input terminal INN is connected to the input signal INN4. Its output terminal L is connected to the input terminal VIN of the ninth level shift circuit LS9. The output terminal R of the fifth output control module OUT_CTRL4 is connected to the input terminal VIN of the tenth level shift circuit LS10. The input terminal INP of the sixth output control module OUT_CTRL5 is connected to the input signal INP5. The input terminal INN of the sixth output control module OUT_CTRL5 is connected to the input signal INN5. The output terminal L of the sixth output control module OUT_CTRL5 is connected to the input terminal VIN of the eleventh level shift circuit LS11. The output terminal R of the sixth output control module OUT_CTRL5 is connected to the input terminal VIN of the twelfth level shift circuit LS12. The input terminal INP of the seventh output control module OUT_CTRL6 is connected to the input signal... The seventh output control module OUT_CTRL6 has its input terminal INN connected to the input signal INN6. The output terminal L of the seventh output control module OUT_CTRL6 is connected to the input terminal VIN of the thirteenth level shift circuit LS13. The output terminal R of the seventh output control module OUT_CTRL6 is connected to the input terminal VIN of the fourteenth level shift circuit LS14. The eighth output control module OUT_CTRL7 has its input terminal INP connected to the input signal INP7. The input terminal INN of the eighth output control module OUT_CTRL7 is connected to the input signal INN7. The output terminal L of the eighth output control module OUT_CTRL7 is connected to the fifteenth level shift circuit LS14. The input terminal VIN of circuit 15 is connected. The output terminal R of the eighth output control module OUT_CTRL7 is connected to the input terminal VIN of the sixteenth level shift circuit LS16. The output terminal OUT of the first level shift circuit LS1 is connected to the input terminal INP of the first output module OUT1. The output terminal OUT of the second level shift circuit LS2 is connected to the input terminal INN of the first output module OUT1. The output terminal OUT of the third level shift circuit LS3 is connected to the input terminal INP of the second output module OUT2. The output terminal OUT of the fourth level shift circuit LS4 is connected to the input terminal INN of the second output module OUT2. The output terminal OUT of the fifth level shift circuit LS5 is connected to the input terminal INP of the third output module OUT3.The output terminal OUT of the sixth level shift circuit LS6 is connected to the input terminal INN of the third output module OUT3; the output terminal OUT of the seventh level shift circuit LS7 is connected to the input terminal INP of the fourth output module OUT4; the output terminal OUT of the eighth level shift circuit LS8 is connected to the input terminal INN of the fourth output module OUT4; the output terminal OUT of the ninth level shift circuit LS9 is connected to the input terminal INP of the fifth output module OUT5; the output terminal OUT of the tenth level shift circuit LS10 is connected to the input terminal INN of the fifth output module OUT5; the output terminal OUT of the eleventh level shift circuit LS11 is connected to the input terminal INP of the sixth output module OUT6; the output terminal OUT of the twelfth level shift circuit LS12 is connected to the input terminal INN of the sixth output module OUT6; the output terminal OUT of the thirteenth level shift circuit LS13 is connected to the input terminal INP of the seventh output module OUT7; the... The output terminal OUT of the fourteenth-level shift circuit LS14 is connected to the input terminal INN of the seventh output module OUT7. The output terminal OUT of the fifteenth-level shift circuit LS15 is connected to the input terminal INP of the eighth output module OUT8. The output terminal OUT of the sixteenth-level shift circuit LS16 is connected to the input terminal INN of the eighth output module OUT8. The input terminal VSAMPLE of the first output module OUT1 is connected to the input signal VSAMPLE, the input terminal VSAMPLE of the second output module OUT2, the input terminal VSAMPLE of the third output module OUT3, the input terminal VSAMPLE of the fourth output module OUT4, the input terminal VSAMPLE of the fifth output module OUT5, the input terminal VSAMPLE of the sixth output module OUT6, the input terminal VSAMPLE of the seventh output module OUT7, and the input terminal VSAMPLE of the eighth output module OUT8. The input terminal VSAMPLE_VDD of the first output module OUT1 is connected to the input signal VSAMPLE_VDD, the input terminal VSAMPLE_VDD of the second output module OUT2, the input terminal VSAMPLE_VDD of the third output module OUT3, the input terminal VSAMPLE_VDD of the fourth output module OUT4, the input terminal VSAMPLE_VDD of the fifth output module OUT5, the input terminal VSAMPLE_VDD of the sixth output module OUT6, the input terminal VSAMPLE_VDD of the seventh output module OUT7, and the input terminal VSAMPLE_VDD of the eighth output module OUT8.The input terminal VREFH of the first output module OUT1 is connected to the input signal VREFH, the input terminal VREFH of the second output module OUT2, the input terminal VREFH of the third output module OUT3, the input terminal VREFH of the fourth output module OUT4, the input terminal VREFH of the fifth output module OUT5, the input terminal VREFH of the sixth output module OUT6, the input terminal VREFH of the seventh output module OUT7, and the input terminal VREFH of the eighth output module OUT8. The input terminal VREFL of the first output module OUT1 is connected to the input signal VREFL, the input terminal VREFL of the second output module OUT2, and the input terminal VREFH of the third output module OUT3. The input terminal VREFL of the first output module OUT1, the input terminal VREFL of the fourth output module OUT4, the input terminal VREFL of the fifth output module OUT5, the input terminal VREFL of the sixth output module OUT6, the input terminal VREFL of the seventh output module OUT7, and the input terminal VREFL of the eighth output module OUT8 are connected. The input terminal VSAMPLE_B of the first output module OUT1 is connected to the input signal VSAMPLE_B, the input terminal VSAMPLE_B of the second output module OUT2, the input terminal VSAMPLE_B of the third output module OUT3, the input terminal VSAMPLE_B of the fourth output module OUT4, and the input terminal VSA of the fifth output module OUT5 are connected to the input terminal VREFL of the fifth output module OUT5. The input terminals VSAMPLE_B of the sixth output module OUT6, OUT7, and OUT8 are connected. The output terminal OUTP of the first output module OUT1 is connected to the output signal OUTP0. The output terminal OUTN of the first output module OUT1 is connected to the output signal OUTN0. The output terminal OUTP of the second output module OUT2 is connected to the output signal OUTP1. The output terminal OUTN of the second output module OUT2 is connected to the output signal OUTN1. The output terminal OUTP of the third output module OUT3 is connected to the output signal OUTN0. The output terminals of the third output module OUT3 (OUTN) and the fourth output module OUT4 (OUTP) and the fifth output module OUT5 (OUTN) are connected to the output signal OUTP4 and OUTP5, respectively. The output terminals of the sixth output module OUT6 (OUTP) and the seventh output module OUT7 (OUTP) are also connected to the output signal OUTP6.The output terminal OUTN of the seventh output module OUT7 is connected to the output signal OUTN6, the output terminal OUTP of the eighth output module OUT8 is connected to the output signal OUTP7, and the output terminal OUTN of the eighth output module OUT8 is connected to the output signal OUTN7.

5. The method for improving the feedback coefficient of the residual amplifier in a dual-capacitor sampling margin gain unit according to claim 1, characterized in that, The residual amplifier RA circuit includes: a first transistor NMOS1, a second transistor NMOS2, a third transistor NMOS3, a fourth transistor NMOS4, a fifth transistor NMOS5, a sixth transistor NMOS6, a seventh transistor NMOS7, an eighth transistor NMOS8, a ninth transistor NMOS9, a tenth transistor PMOS1, an eleventh transistor PMOS2, a twelfth transistor PMOS3, a thirteenth transistor PMOS4, a fourteenth transistor PMOS5, a fifteenth transistor PMOS6, a first Miller compensation capacitor C1, a second Miller compensation capacitor C2, a first zero-adjustment resistor R1, a second zero-adjustment resistor R2, a first gain boosting circuit GBST1, and a second... The gain boosting circuit GBST2 and the fully differential gain boosting circuit FDGBST are configured. The gate of the first transistor NMOS1 is connected to the input signal CMFB1. The drain of the first transistor NMOS1 is connected to the source of the second transistor NMOS2 and the source of the third transistor NMOS3. The source of the first transistor NMOS1 is connected to ground. The gate of the second transistor NMOS2 is connected to the input signal VP. The drain of the second transistor NMOS2 is connected to the source of the fourth transistor NMOS4 and the input terminal VN of the first gain boosting circuit GBST1. The gate of the third transistor NMOS3 is connected to the input signal VN. The drain of the third transistor NMOS3 is connected to the source of the fourth transistor NMOS4 and the input terminal VN of the first gain boosting circuit GBST1. The source of transistor NMOS5 is connected to the input terminal VN of the second gain boost circuit GBST2. The gate of transistor NMOS4 is connected to the output terminal OUT of the first gain boost circuit GBST1. The drain of transistor NMOS4 is connected to the gate of transistor NMOS9, the drain of transistor PMOS1, and the lower end of the second zero-adjustment resistor R2. The gate of transistor NMOS5 is connected to the output terminal OUT of the second gain boost circuit GBST2. The drain of transistor NMOS5 is connected to the gate of transistor NMOS8, the drain of transistor PMOS2, and the lower end of the first zero-adjustment resistor R1. The sixth transistor NMOS... The gate of transistor 6 is connected to the input signal CMFB2 and the gate of the seventh transistor NMOS7. The drain of the sixth transistor NMOS6 is connected to the drain of the seventh transistor NMOS7, the source of the eighth transistor NMOS8, and the source of the ninth transistor NMOS9. The source of the sixth transistor NMOS6 is connected to ground. The source of the seventh transistor NMOS7 is connected to ground. The drain of the eighth transistor NMOS8 is connected to the drain of the fourteenth transistor PMOS5, the upper plate of the first Miller compensation capacitor C1, and the output signal VON. The drain of the ninth transistor NMOS9 is connected to the drain of the fifteenth transistor PMOS6, the upper plate of the second Miller compensation capacitor C2, and the output signal VOP.The gate of the tenth transistor PMOS1 is connected to the output terminal ON of the fully differential gain boosting circuit FDGBST. The source of the tenth transistor PMOS1 is connected to the drain of the twelfth transistor PMOS3 and the input terminal VP of the fully differential gain boosting circuit FDGBST. The gate of the eleventh transistor PMOS2 is connected to the output terminal OP of the fully differential gain boosting circuit FDGBST. The source of the eleventh transistor PMOS11 is connected to the drain of the thirteenth transistor PMOS4 and the input terminal VN of the fully differential gain boosting circuit FDGBST. The twelfth transistor... The gate of PMOS3 is connected to the input signal VBP0 and the gate of the thirteenth transistor PMOS4. The source of the twelfth transistor PMOS3 is connected to the power supply VDD. The source of the thirteenth transistor PMOS4 is connected to the power supply VDD. The gate of the fourteenth transistor PMOS5 is connected to the input signal VBP1 and the gate of the fifteenth transistor PMOS6. The source of the fourteenth transistor PMOS5 is connected to the power supply. The source of the fifteenth transistor PMOS6 is connected to the power supply. The upper end of the first zero-adjustment resistor R1 is connected to the lower plate of the first Miller compensation capacitor C1. The upper end of the second zero-adjustment resistor R2 is connected to the lower plate of the second Miller compensation capacitor C2. The input terminal VP of the first gain boosting circuit GBST1 is connected to the input signal VREF and the input terminal VP of the second gain boosting circuit GBST2. The input terminal VBP of the first gain boosting circuit GBST1 is connected to the input signal VBP2 and the input terminal VBP of the second gain boosting circuit GBST2. The input terminal VBN2 of the first gain boosting circuit GBST1 is connected to the input signal VBN2 and the input terminal VBN2 of the second gain boosting circuit GBST2. The input terminal VBN1 of the first gain boosting circuit GBST1 is connected to the input signal VBN1, and the input terminal VBN1 of the second gain boosting circuit GBST2 is also connected. The input terminal VBN of the fully differential gain boosting circuit FDGBST is connected to the input signal VBN3. The input terminal VM of the fully differential gain boosting circuit FDGBST is connected to the input signal CMFB3. The input terminal VBP1 of the fully differential gain boosting circuit FDGBST is connected to the input signal VBP3. The input terminal VBP2 of the fully differential gain boosting circuit FDGBST is connected to the input signal VBP4.

6. A method for improving the feedback coefficient of the residual amplifier in a dual-capacitor sampling margin gain unit according to claim 4, characterized in that... The output control module OUT_CTRL includes a first inverter INV1, a second inverter INV2, a first AND gate AND1, and a second AND gate AND2. The input of the first inverter INV1 is connected to the input signal INN and the input C of the second AND gate AND2. The output of the first inverter INV1 is connected to the input C of the first AND gate AND1. The input of the second inverter INV2 is connected to the input signal INP and the input B of the first AND gate AND1. The output of the second inverter INV2 is connected to the input B of the second AND gate AND2. The input A of the first AND gate AND1 is connected to the input signal VSAMPLE_B_VDD and the input A of the second AND gate AND2.

7. A method for improving the feedback coefficient of the residual amplifier in a dual-capacitor sampling margin gain unit according to claim 4, characterized in that... The level shifting circuit LS includes a first inverter INV1, a second inverter INV2, an output buffer BUF, a first transistor NMOS1, a second transistor NMOS2, a third transistor NMOS3, a fourth transistor NMOS4, a fifth transistor PMOS1, and a sixth transistor PMOS2. The input terminal of the first inverter INV1 is connected to the input signal VIN. The output of the first inverter INV1 is connected to the input of the second inverter INV2 and the gate of the second transistor NMOS2. The output of the second inverter INV2 is connected to the gate of the first transistor NMOS1. The drain of the first transistor NMOS1 is the source of the third transistor NMOS3, the gate of the fourth transistor NMOS4, and the sixth transistor PMOS2 are connected to the gate of the second transistor NMOS1. The gate of MOS2 is connected to ground. The source of the first transistor NMOS1 is connected to ground. The drain of the second transistor NMOS2 is connected to the gate of the third transistor NMOS3, the source of the fourth transistor NMOS4, the gate of the fifth transistor PMOS1, and the input of the output buffer BUF. The source of the second transistor NMOS2 is connected to ground. The drain of the third transistor NMOS3 is connected to the drain of the fifth transistor PMOS1. The drain of the fourth transistor NMOS4 is connected to the drain of the sixth transistor PMOS2. The source of the fifth transistor PMOS1 is connected to the power supply VDD. The source of the sixth transistor PMOS2 is connected to the power supply VDD. The output of the input buffer is connected to the output signal OUT.

8. A method for improving the feedback coefficient of the residual amplifier in a dual-capacitor sampling margin gain unit according to claim 4, characterized in that... The output module includes a first transistor NMOS1, a second transistor NMOS2, a third transistor NMOS3, a fourth transistor NMOS4, a fifth transistor NMOS5, a sixth transistor NMOS6, a seventh transistor NMOS7, an eighth transistor NMOS8, a ninth transistor NMOS9, a tenth transistor NMOS10, a first capacitor C1, and a second capacitor C2. The gate of the first transistor NMOS1 is connected to the input signal VSAMPLE, the gate of the fifth transistor NMOS5, and the gate of the sixth transistor NMOS6. The drain of the first transistor NMOS1 is connected to the drain of the second transistor NMOS2. The lower plate of the first capacitor C1 is connected. The source of the first transistor NMOS1 is connected to the input signal VREFH and the source of the third transistor NMOS3. The gate of the second transistor NMOS2 is connected to the input signal VSAMPLE_B_VDD. The source of the second transistor NMOS2 is connected to the input signal VREFL and the source of the fourth transistor NMOS4. The gate of the third transistor NMOS3 is connected to the input signal VSAMPLE_B. The drain of the third transistor NMOS3 is connected to the drain of the fourth transistor NMOS4 and the lower plate of the second capacitor C2. The gate of the fourth transistor NMOS4 is connected to the input signal VSAMPLE_VDD. The drain of the fifth transistor NMOS5 is connected to the drain of the seventh transistor NMOS7, the drain of the eighth transistor NMOS8, and the upper plate of the first capacitor C1. The source of the fifth transistor NMOS5 is connected to the input signal VCM and the source of the sixth transistor NMOS6. The drain of the sixth transistor NMOS6 is connected to the drain of the ninth transistor NMOS9, the drain of the tenth transistor NMOS10, and the upper plate of the second capacitor C2. The gate of the seventh transistor NMOS7 is connected to the input signal L and the gate of the ninth transistor NMOS9. The source of the seventh transistor NMOS7 is connected to the output signal OUTN and the source of the tenth transistor NMOS10. The gate of the eighth transistor NMOS8 is connected to the input signal R and the gate of the tenth transistor NMOS10. The source of the eighth transistor NMOS8 is connected to the output signal OUTP and the source of the ninth transistor NMOS9.

9. A method for improving the feedback coefficient of the residual amplifier in a dual-capacitor sampling margin gain unit according to claim 5, characterized in that... The gain boosting circuit GBST includes a first transistor NMOS1, a second transistor NMOS2, a third transistor NMOS3, a fourth transistor NMOS4, a fifth transistor NMOS5, a sixth transistor PMOS1, a seventh transistor PMOS2, an eighth transistor PMOS3, and a ninth transistor PMOS4. The gate of the first transistor NMOS1 is connected to the input signal VBN1, and the drain of the first transistor NMOS1 is connected to the source of the second transistor NMOS2 and the source of the third transistor NMOS3. The source of the first transistor NMOS1 is connected to ground. The gate of the second transistor NMOS2 is connected to the input signal VP, and the drain of the second transistor NMOS2 is connected to the source of the fourth transistor NMOS4. The gate of the third transistor NMOS3 is connected to the input signal VN, and the drain of the third transistor NMOS3 is connected to the source of the fourth transistor NMOS4. The sources of five transistors, NMOS5 and NMOS4, are connected. The gate of the fourth transistor, NMOS4, is connected to the input signal VBN2 and the gate of the fifth transistor, NMOS5. The drain of the fourth transistor, NMOS4, is connected to the drain of the sixth transistor, PMOS1, the gate of the eighth transistor, PMOS3, and the gate of the ninth transistor, PMOS4. The drain of the fifth transistor, NMOS5, is connected to the drain of the seventh transistor, PMOS2, and the output signal OUT. The gate of the sixth transistor, PMOS1, is connected to the input signal VBP and the gate of the seventh transistor, PMOS2. The source of the sixth transistor, PMOS1, is connected to the drain of the eighth transistor, PMOS3. The source of the seventh transistor, PMOS2, is connected to the drain of the ninth transistor, PMOS4. The source of the eighth transistor, PMOS3, and the source of the ninth transistor, PMOS4, are connected to the power supply VDD.

10. A method for improving the feedback coefficient of the residual amplifier in a dual-capacitor sampling margin gain unit according to claim 5, characterized in that... The fully differential gain boosting circuit FDGBST includes a first transistor NMOS1, a second transistor NMOS2, a third transistor NMOS3, a fourth transistor NMOS4, a fifth transistor NMOS5, a sixth transistor NMOS6, a seventh transistor NMOS7, an eighth transistor NMOS8, a ninth transistor PMOS1, a tenth transistor PMOS2, an eleventh transistor PMOS3, a twelfth transistor PMOS4, a thirteenth transistor PMOS5, a fourteenth transistor PMOS6, a fifteenth transistor PMOS7, a sixteenth transistor PMOS8, a seventeenth transistor PMOS9, and an eighteenth transistor PMOS10. The gate of the first transistor NMOS1 is connected to... The gate of the second transistor NMOS2, the gate of the sixth transistor NMOS6, the drain of the eighth transistor NMOS8, and the drain of the seventeenth transistor PMOS9 are connected. The drain of the first transistor NMOS1 is connected to the source of the third transistor NMOS3, and the source of the first transistor NMOS1 is connected to ground. The drain of the second transistor NMOS2 is connected to the source of the fourth transistor NMOS4, and the source of the second transistor NMOS2 is connected to ground. The gate of the third transistor NMOS3 is connected to the input signal VBN, the gate of the fourth transistor NMOS4, the gate of the seventh transistor NMOS7, and the gate of the eighth transistor NMOS8. The drain of the fourth transistor NMOS4 is connected to the output signal ON, the drain of the tenth transistor PMOS2, and the gate of the fifteenth transistor PMOS7. The gate of the fifth transistor NMOS5 is connected to the drain of the seventh transistor NMOS7, the drain of the fifteenth transistor PMOS7, and the drain of the sixteenth transistor PMOS8. The drain of the fifth transistor NMOS5 is connected to the source of the seventh transistor NMOS7, and the source of the fifth transistor NMOS5 is connected to ground. The drain of the sixth transistor NMOS6 is connected to the source of the eighth transistor NMOS8. The source of NMOS6 is connected to ground. The gate of the ninth transistor PMOS1 is connected to the input signal VM, the gate of the tenth transistor PMOS2, and the gate of the seventeenth transistor PMOS9. The source of the ninth transistor PMOS1 is connected to the drain of the eleventh transistor PMOS3. The source of the tenth transistor PMOS2 is connected to the drain of the twelfth transistor PMOS4. The gate of the eleventh transistor PMOS3 is connected to the input signal VBP1 and the gate of the twelfth transistor PMOS4. The source of the eleventh transistor PMOS3 is connected to the drain of the thirteenth transistor PMOS5. The source of the twelfth transistor PMOS4 is connected to the drain of the fourteenth transistor PMOS6.The gate of the thirteenth transistor PMOS5 is connected to the input signal VP, and the source of the thirteenth transistor PMOS5 is connected to the power supply VDD. The gate of the fourteenth transistor PMOS6 is connected to the input signal VN, and the source of the fourteenth transistor PMOS6 is connected to the power supply VDD. The source of the fifteenth transistor PMOS7 is connected to the source of the sixteenth transistor PMOS8, the source of the seventeenth transistor PMOS9, and the drain of the eighteenth transistor PMOS10. The gate of the eighteenth transistor PMOS10 is connected to the input signal VBP2, and the source of the eighteenth transistor PMOS10 is connected to the power supply VDD.

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