Automatic closed loop control system and method for excitation amplitude of DLCP test

Abstract

This invention provides an automatic closed-loop control system and method for excitation amplitude in DLCP testing. The system includes: a multi-frequency AC excitation and DC bias application module for automatically applying AC excitation signals and DC bias signals according to a preset excitation amplitude sequence at multiple test frequencies; a PID closed-loop control module for performing closed-loop correction of the applied voltage based on the response of the test port of the semiconductor device under test, ensuring that the applied voltage condition at the test port meets preset requirements; a capacitance measurement module for acquiring the equivalent capacitance response signal of the semiconductor device under test; a capacitance test data caching module for associating, marking, and classifying capacitance test data according to test frequency, excitation level, and bias setpoint; and a main control module for coordinating the automatic test process under multiple test frequencies and different excitation amplitude conditions, and outputting the corresponding capacitance test data to improve the consistency, stability, and automation of DLCP testing.

Description

Technical Field

[0001] This invention relates to the field of semiconductor defect testing technology, and in particular to an automatic closed-loop control system and method for excitation amplitude in DLCP testing. Background Technology

[0002] Drive-Level Capacitance Profiling (DLCP) is an electrical testing method widely used for defect analysis and carrier distribution characterization in semiconductor devices. The core principle of this method lies in measuring the capacitance change of a semiconductor device under different AC excitation amplitudes and performing defect-related electrical characterization based on the capacitance response under different excitation conditions. Compared to traditional capacitance-voltage (CV) testing methods, DLCP testing can more effectively distinguish between free carrier and trapped state responses, thus having significant application value in defect characterization of thin-film solar cells, organic semiconductor devices, and compound semiconductor devices.

[0003] However, the following technical problems urgently need to be solved in the existing DLCP testing system:

[0004] First, in actual testing, due to the combined effects of factors such as parasitic impedance of the test connection, contact resistance, the impedance frequency characteristics of the semiconductor device under test (DUT), and the parasitic capacitance and inductance of the test fixture, there is often a significant deviation between the actual excitation amplitude applied at the test port of the DUT and the amplitude set at the output of the test instrument. Especially in multi-frequency testing scenarios, the impedance characteristics of the DUT change significantly with the test frequency, leading to inconsistencies in the actual excitation amplitude at the test port of the DUT at different frequencies. This results in DLCP tests at different frequencies not being performed under uniform applied voltage conditions, severely affecting the comparability of capacitance test data and the accuracy of test results.

[0005] Second, existing DLCP testing systems generally lack an automatic closed-loop correction mechanism for the voltage conditions applied at the test ports of the semiconductor device under test. Testers typically perform a one-time manual calibration before the test begins, which cannot compensate in real time for excitation amplitude deviations caused by factors such as temperature drift, changes in device operating point, and dynamic impedance changes caused by bias scanning. This makes it difficult to continuously ensure the consistency of the voltage conditions applied at the test ports of the semiconductor device under test throughout the entire bias scanning process.

[0006] Third, the existing testing system lacks a mechanism for systematically associating, marking, classifying, and caching capacitor test data according to test frequency, excitation level, and bias setpoint. This makes it difficult to accurately trace and reuse a large amount of capacitor test data acquired under multi-frequency and multi-excitation amplitude conditions in subsequent processing, reducing the automation level of the testing process and the standardization of data management. Summary of the Invention

[0007] This invention provides an automatic closed-loop control system and method for excitation amplitude in DLCP testing, which realizes automatic closed-loop correction of the voltage applied at the test port of the semiconductor device under test, so that the voltage applied at the test port of the semiconductor device under test meets the preset requirements, thereby improving the consistency, stability and automation of DLCP testing.

[0008] This invention provides an automatic closed-loop control system for excitation amplitude in DLCP testing, characterized in that the system comprises:

[0009] The multi-frequency AC excitation and DC bias application module is used to automatically apply AC excitation signals and DC bias signals according to a preset excitation amplitude sequence at multiple test frequencies.

[0010] The PID closed-loop control module is used to construct a feedback error signal based on the response measured at the test port of the semiconductor device under test at each bias set point of the preset bias scan sequence, and to perform closed-loop correction on the applied voltage based on the feedback error signal so that the applied voltage condition at the test port of the semiconductor device under test meets the preset requirements.

[0011] The capacitance measurement module is used to acquire the equivalent capacitance response signal of the semiconductor device under test.

[0012] The capacitor test data caching module is used to associate, mark, and classify capacitor test data according to test frequency, excitation level, and bias setpoint for caching.

[0013] The main control module is used to coordinate the automatic test process under multiple test frequencies and different excitation amplitude conditions, and output the corresponding capacitance test data.

[0014] Furthermore, the multi-frequency AC excitation and DC bias application module includes: a programmable AC signal source, a programmable DC bias source, and an application circuit connected in sequence;

[0015] The programmable AC signal source is used to output AC excitation signals with corresponding amplitudes according to a preset excitation amplitude sequence at each test frequency;

[0016] The programmable DC bias source is used to apply the DC bias signal to the semiconductor device under test according to the preset bias scan sequence;

[0017] The application circuit is used to apply the AC excitation signal and the DC bias signal to the test port of the semiconductor device under test.

[0018] Furthermore, the PID closed-loop control module includes an error calculation unit, a PID calculation unit, and an adjustment output unit;

[0019] The error calculation unit is used to generate a feedback error signal based on the response measured at the test port of the semiconductor device under test and a preset target value;

[0020] The PID calculation unit is used to perform proportional, integral, and derivative operations based on the feedback error signal to generate the adjustment amount;

[0021] The adjustment output unit is used to perform closed-loop correction of the applied voltage according to the adjustment amount.

[0022] Furthermore, the capacitance measurement module includes:

[0023] The detection circuit, with its input terminal electrically connected to the semiconductor device under test, is used to detect the current and voltage responses generated by the semiconductor device under test under the combined action of the AC excitation signal and the DC bias signal.

[0024] A measurement circuit is used to calculate the equivalent capacitance response signal based on the current response and the voltage response obtained after detection.

[0025] Furthermore, the capacitance test data caching module includes:

[0026] The condition marking unit is used to associate and mark the capacitance test data with the test frequency, excitation level and bias set point and record the timestamp;

[0027] A cache storage unit is used to classify and store the associated and tagged capacitance test data and provide a read interface to the main control module.

[0028] Furthermore, the main control module includes:

[0029] The test process control unit is used to control the test frequency switching, automatic excitation amplitude switching, and bias voltage application process;

[0030] The stability determination unit is used to determine whether the voltage conditions applied at the test port of the semiconductor device under test meet the preset stability requirements.

[0031] The result output unit is used to output capacitance test data under different test frequencies and different excitation amplitudes.

[0032] Furthermore, the stability determination unit is used to trigger the capacitance measurement module to perform capacitance measurement under the corresponding test frequency and excitation amplitude conditions when the feedback error signal falls within the preset threshold range.

[0033] Furthermore, the main control module is also used to perform automatic tests under multiple test frequencies and multiple excitation amplitude combinations in a preset test sequence, and send the obtained capacitance test data to the capacitance test data cache module for caching.

[0034] On the other hand, the present invention also discloses an automatic closed-loop control method for excitation amplitude in DLCP testing, the method comprising:

[0035] Automatically apply AC excitation signal and DC bias signal according to a preset excitation amplitude sequence at multiple test frequencies;

[0036] At each bias set point of the preset bias scan sequence, a feedback error signal is constructed based on the response measured at the test port of the semiconductor device under test. The applied voltage is then corrected in a closed loop based on the feedback error signal so that the applied voltage condition at the test port of the semiconductor device under test meets the preset requirements.

[0037] Obtain the equivalent capacitance response signal of the semiconductor device under test;

[0038] The capacitor test data is associated, marked, and categorized for buffering according to the test frequency, excitation level, and bias setpoint.

[0039] It coordinates the automatic testing process under multiple test frequencies and different excitation amplitudes, and outputs the corresponding capacitance test data.

[0040] Furthermore, before acquiring the equivalent capacitance response signal of the semiconductor device under test, the method further includes:

[0041] A feedback error signal is generated based on the response measured at the test port of the semiconductor device under test;

[0042] Determine whether the applied voltage condition meets the preset stability requirements;

[0043] If the judgment result is yes, perform capacitance measurement;

[0044] If the judgment result is negative, continue to perform closed-loop correction on the applied voltage.

[0045] Compared with the prior art, the present invention has at least the following technical effects:

[0046] The system supports automatic traversal application of multiple frequencies and excitation amplitudes through the multi-frequency AC excitation and DC bias application modules. Combined with the unified coordination and scheduling of the test process by the main control module, the test process under different test frequencies and different excitation amplitude combinations is fully automated, eliminating the operational differences introduced by manual intervention. The PID closed-loop control module performs closed-loop correction on the actual applied voltage at the test port of the semiconductor device under test based on the response feedback at the test port of the semiconductor device under test. This ensures that the applied voltage conditions at the test port of the semiconductor device under test meet the preset requirements during each test frequency switching and full bias scanning process. This overcomes the test condition deviation problems caused by factors such as parasitic impedance and changes in the impedance frequency characteristics of the device under test, and improves the consistency and stability of DLCP testing. The capacitance test data caching module performs multi-dimensional correlation marking and timestamp recording of each acquired capacitance test data point, including test frequency, excitation level, and bias setpoint. This decouples the mismatch between data acquisition rate and data processing rate, improving the continuity of the testing process. Furthermore, it enables standardized management and traceability of multi-condition, multi-dimensional test data, providing a reliable data foundation for subsequent data processing. In addition, the entire system comprises a modular architecture consisting of a multi-frequency AC excitation and DC bias application module, a PID closed-loop control module, a capacitance measurement module, a capacitance test data caching module, and a main control module. Each module is functionally independent, facilitating flexible expansion and integration for different types of devices under test, different test standards, or different application scenarios, demonstrating excellent engineering applicability and industrialization value. Attached Figure Description

[0047] Figure 1 This is a simplified structural diagram of the automatic closed-loop control system for excitation amplitude used in DLCP testing according to Embodiment 1 of the present invention;

[0048] Figure 2 This is a simplified flowchart illustrating the automatic closed-loop control method for excitation amplitude used in DLCP testing according to Embodiment 2 of the present invention. Detailed Implementation

[0049] The following description, with reference to schematic diagrams, illustrates an automatic closed-loop control system and method for excitation amplitude in DLCP testing according to the present invention. Preferred embodiments of the invention are shown. It should be understood that those skilled in the art can modify the invention described herein while still achieving its advantageous effects. Therefore, the following description should be understood as being of general knowledge to those skilled in the art and is not intended to limit the invention.

[0050] The invention is described more specifically by way of example in the following paragraphs with reference to the accompanying drawings. The advantages and features of the invention will become clearer from the following description. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the invention.

[0051] Example 1

[0052] Please refer to Figure 1 This embodiment discloses an automatic closed-loop control system for excitation amplitude used in DLCP testing, the system comprising:

[0053] The multi-frequency AC excitation and DC bias application module is used to automatically apply AC excitation signals and DC bias signals according to a preset excitation amplitude sequence at multiple test frequencies.

[0054] The PID closed-loop control module is used to construct a feedback error signal based on the response measured at the test port of the semiconductor device under test at each bias set point of the preset bias scan sequence, and to perform closed-loop correction on the applied voltage based on the feedback error signal, so that the applied voltage condition at the test port of the semiconductor device under test meets the preset requirements.

[0055] The capacitance measurement module is used to acquire the equivalent capacitance response signal of the semiconductor device under test.

[0056] The capacitor test data caching module is used to associate, mark, and classify capacitor test data according to test frequency, excitation level, and bias set point for caching.

[0057] The main control module is used to coordinate the automatic test process under multiple test frequencies and different excitation amplitude conditions, and output the corresponding capacitance test data.

[0058] In this embodiment, the multi-frequency AC excitation and DC bias application module supports automatic traversal application of multiple frequencies and excitation amplitudes at the system level. Combined with the unified coordination and scheduling of the test process by the main control module, the test process under different test frequencies and different excitation amplitude combinations is fully automated, eliminating operational differences introduced by manual intervention. The PID closed-loop control module performs closed-loop correction on the actual applied voltage at the test port of the semiconductor device under test based on the response feedback at the test port of the semiconductor device under test. This ensures that the applied voltage conditions at the test port of the semiconductor device under test meet the preset requirements during each test frequency switching and full bias scanning process. This overcomes the test condition deviation problems caused by factors such as parasitic impedance and changes in the impedance frequency characteristics of the device under test, and improves the consistency and stability of DLCP testing. Qualitatively, the capacitance test data caching module performs multi-dimensional correlation marking and timestamp recording of each acquired capacitance test data point, including test frequency, excitation level, and bias setpoint. This decouples the mismatch between data acquisition rate and data processing rate, improving the continuity of the testing process. Furthermore, it enables standardized management and traceability of multi-condition, multi-dimensional test data, providing a reliable data foundation for subsequent data processing. In addition, the entire system comprises a modular architecture consisting of a multi-frequency AC excitation and DC bias application module, a PID closed-loop control module, a capacitance measurement module, a capacitance test data caching module, and a main control module. Each module is functionally independent and can be flexibly expanded and integrated for different types of devices under test, different test standards, or different application scenarios, demonstrating good engineering applicability and industrialization value.

[0059] In this embodiment, the equivalent capacitance response signal refers to the signal used to characterize the capacitance characteristics of the semiconductor device under test (DUT) after signal processing of the current and voltage responses generated by the DUT under the combined action of an AC excitation signal and a DC bias signal. Specifically, when an AC excitation signal is applied to the DUT, the depletion region capacitance inside the device will generate a corresponding current response as the excitation signal changes. The amplitude and phase of this current response are directly related to the equivalent capacitance of the device. Using the capacitance measurement module designed in this embodiment, the component with the same frequency as the excitation signal can be accurately extracted from the current and voltage responses of the DUT, and then the equivalent capacitance value of the device can be calculated.

[0060] In this embodiment, the preset bias scanning sequence refers to a DC bias application sequence consisting of a pre-set start voltage, end voltage, step voltage, and scanning direction. By changing the DC bias applied to the device under test (DUT), the width of the depletion region inside the device can be modulated, thereby enabling capacitance measurement at different spatial depths. Those skilled in the art can select an appropriate bias scanning range and step accuracy based on the DUT's operating voltage range, structural parameters, and testing requirements.

[0061] In a specific example, the scanning method can be scanning from positive bias to negative bias (forward scanning), scanning from negative bias to positive bias (reverse scanning), or bidirectional reciprocating scanning. For typical PN junction devices, the bias scanning range can be set to -5V to +1V, and the step voltage can be set to 0.05V to 0.1V. For special devices such as thin-film solar cells, the bias scanning range can be appropriately adjusted according to the device's built-in potential and breakdown voltage.

[0062] In this embodiment, the applied voltage refers to a composite voltage signal applied to the test port of the semiconductor device under test, which includes an AC excitation signal and a DC bias signal.

[0063] In this embodiment, the system is applicable to semiconductor devices with depletion region structures whose capacitance characteristics are affected by defect states, including thin-film solar cells, organic semiconductor devices, compound semiconductor devices, and silicon-based semiconductor devices.

[0064] Furthermore, the multi-frequency AC excitation and DC bias application module includes: a programmable AC signal source, a programmable DC bias source, and an application circuit connected in sequence.

[0065] Specifically, the programmable AC signal source is used to output AC excitation signals with corresponding amplitudes according to a preset excitation amplitude sequence at each test frequency. The programmable DC bias source is used to apply the DC bias signal to the semiconductor device under test according to the preset bias scan sequence; the application circuit is used to apply the AC excitation signal and the DC bias signal to the test port of the semiconductor device under test.

[0066] The programmable AC signal source should have characteristics such as programmable frequency, adjustable output amplitude, low phase noise, and high frequency stability to meet the requirements of DLCP testing for excitation signal quality.

[0067] In a specific example, the programmable AC signal source may be a direct digital frequency synthesizer (DDS), a phase-locked loop frequency synthesizer (PLL), an arbitrary waveform generator (AWG), or a high-precision function signal generator, etc., without any specific limitations.

[0068] In another specific example, the frequency of the AC excitation signal can be any frequency in the range of 100Hz to 10MHz, with typical test frequencies including 1kHz, 10kHz, 100kHz, and 1MHz. Those skilled in the art can select different frequencies of AC excitation signals based on the type of semiconductor device under test, the depth of the trap energy level, and the required test accuracy.

[0069] In this embodiment, the programmable DC bias source should have characteristics such as wide output voltage range, high resolution, low ripple noise, and good long-term stability.

[0070] In a specific example, the programmable DC bias source may be a programmable voltage source composed of a high-precision digital-to-analog converter (DAC) and a low-noise operational amplifier, a precision programmable power supply, or a source measurement unit (SMU), etc., without specific limitations.

[0071] Furthermore, in this embodiment, the PID closed-loop control module includes an error calculation unit, a PID calculation unit, and an adjustment output unit.

[0072] The error calculation unit generates a feedback error signal based on the response measured at the test port of the semiconductor device under test and a preset target value. The PID calculation unit performs proportional, integral, and derivative operations based on the feedback error signal to generate an adjustment amount. The adjustment output unit performs closed-loop correction on the applied voltage based on the adjustment amount.

[0073] In this embodiment, the preset target value refers to the expected applied voltage value at the test port of the semiconductor device under test under the current test frequency, excitation amplitude, and bias setpoint. The preset target value is preset by the user according to the specifications of the device under test and is loaded into the error calculation unit before the test begins, serving as a reference value for closed-loop control.

[0074] In this embodiment, by introducing a PID closed-loop correction mechanism, the system can sense the deviation between the actual applied voltage condition at the test port of the semiconductor device under test and the preset target value in real time, and quickly and accurately eliminate the deviation through three adjustment links: proportional, integral, and derivative. This ensures that the applied voltage condition at the test port of the semiconductor device under test meets the preset requirements at each bias set point, each test frequency, and each excitation amplitude, thereby improving the consistency and stability of DLCP testing.

[0075] In a specific example, the specific adjustment process of the PID closed-loop control module is as follows:

[0076] At each bias setpoint, the error calculation unit first acquires the response at the test port of the semiconductor device under test through the detection circuit, and determines the deviation between the applied voltage condition at the test port of the semiconductor device under test and the preset target value based on the response, generating a feedback error signal e(t); subsequently, the PID calculation unit performs proportional (P), integral (I), and derivative (D) operations on the feedback error signal, calculating the proportional term respectively. ,in, The proportionality coefficient; the integral term ,in, For the integral coefficients; and for the differential terms. ,in, The three factors are used as differential coefficients; the sum of these three factors yields the total adjustment amount; finally, the adjustment output unit converts the adjustment amount into a correction command for the AC excitation signal output amplitude and / or DC bias output, so as to achieve closed-loop correction of the applied voltage condition at the test port of the semiconductor device under test through source-end adjustment.

[0077] Furthermore, in this embodiment, the capacitance measurement module includes:

[0078] The detection circuit, with its input terminal electrically connected to the semiconductor device under test, is used to detect the current and voltage responses generated by the semiconductor device under test under the combined action of the AC excitation signal and the DC bias signal. The measurement circuit is used to calculate the equivalent capacitance response signal based on the detected current and voltage responses.

[0079] In a specific example, the detection circuit may be a transimpedance amplifier (TIA) circuit, a current-to-voltage conversion circuit, a charge amplifier circuit, or a high-impedance voltage follower circuit, etc. Those skilled in the art can select an appropriate type of detection circuit based on the impedance characteristics of the semiconductor device under test and the test frequency range; no specific limitations are imposed here.

[0080] In another specific example, the measurement circuit can be a lock-in amplifier measurement circuit. The lock-in amplifier measurement circuit can accurately extract the weak capacitance response with the same frequency as the excitation signal in a wide-band noise background. It has the advantages of high signal-to-noise ratio and strong anti-interference ability, and is suitable for DLCP testing scenarios. Of course, those skilled in the art can choose different measurement circuits according to the actual situation, and no specific restrictions are made here.

[0081] Furthermore, in this embodiment, the capacitance test data caching module includes:

[0082] The condition marking unit is used to associate the capacitance test data with the test frequency, excitation level, and bias setpoint, and record the timestamp. The cache storage unit is used to classify and store the associated and marked capacitance test data and provide a read interface to the main control module.

[0083] In this embodiment, a condition marking unit precisely labels each capacitor test data point with its corresponding test frequency, excitation level, and bias setpoint, and adds a timestamp for data timing verification, thereby making the capacitor test data traceable and facilitating accurate classification and retrieval. Furthermore, by setting up a cache storage unit, the capacitor test data is pre-classified and temporarily stored. This decouples the mismatch between data acquisition rate and data processing rate, improving the continuity of the testing process. On the other hand, by providing a standardized reading interface to the main control module, the main control module can read the capacitor test data under various conditions on demand and in an orderly manner, improving the overall data throughput efficiency and stability of the system.

[0084] In this embodiment, the main control module includes: a test process control unit for controlling the test frequency switching, automatic excitation amplitude switching, and bias voltage application process; a stability determination unit for determining whether the voltage conditions applied at the test port of the semiconductor device under test meet preset stability requirements; and a result output unit for outputting capacitance test data corresponding to different test frequencies and different excitation amplitude conditions.

[0085] In a specific example, the main control module can be implemented using an industrial control computer (IPC), an embedded processor (such as an ARM Cortex series processor), a field-programmable gate array (FPGA), a digital signal processor (DSP), or a combination of the above devices. Of course, those skilled in the art can select a suitable processor platform and software architecture according to actual testing needs, cost constraints, and integration requirements, without making specific restrictions here.

[0086] Specifically, the stability determination unit is used to trigger the capacitance measurement module to perform capacitance measurement under the corresponding test frequency and excitation amplitude conditions when the feedback error signal falls within the preset threshold range.

[0087] The preset threshold range is used to characterize the allowable deviation range between the applied voltage condition at the test port of the semiconductor device under test and the preset target value.

[0088] In a specific example, the preset threshold range can be set by both the percentage of AC excitation amplitude deviation and / or the absolute value of DC bias deviation.

[0089] In another specific example, when the absolute value of the deviation between the actual AC excitation amplitude at the test port of the semiconductor device under test and the preset target amplitude is less than the preset amplitude threshold, for example, 1% to 5%, and the absolute value of the deviation between the actual DC bias value and the target bias value is less than the preset voltage threshold, it is determined that the applied voltage condition has reached a stable state.

[0090] In this embodiment, the main control module is also used to perform automatic tests under multiple test frequencies and multiple excitation amplitude combinations in a preset test order, and send the obtained capacitance test data to the capacitance test data cache module for caching.

[0091] In a specific example, the preset test sequence can be executed in a nested manner, with the outer loop traversing the test frequency, the inner loop traversing the excitation amplitude, and the innermost loop traversing the bias setpoint. The nested loop sequence can also be adjusted according to actual test requirements to balance test efficiency and data consistency requirements. No specific restrictions are imposed here.

[0092] Example 2

[0093] Please refer to Figure 2 Based on the same inventive concept, this embodiment discloses an automatic closed-loop control method for excitation amplitude in DLCP testing. The method is implemented using the automatic closed-loop control system for excitation amplitude in DLCP testing disclosed in Embodiment 1. The method includes:

[0094] S1. Automatically apply AC excitation signal and DC bias signal according to a preset excitation amplitude sequence at multiple test frequencies;

[0095] S2. At each bias set point of the preset bias scan sequence, a feedback error signal is constructed based on the response measured at the test port of the semiconductor device under test. The applied voltage is then corrected in a closed loop based on the feedback error signal so that the applied voltage condition at the test port of the semiconductor device under test meets the preset requirements.

[0096] S3. Obtain the equivalent capacitance response signal of the semiconductor device under test;

[0097] S4. Associate, mark, classify, and cache the capacitor test data according to the test frequency, excitation level, and bias setpoint;

[0098] S5. Coordinate the automatic test process under multiple test frequencies and different excitation amplitude conditions, and output the corresponding capacitance test data.

[0099] Specifically, in step S1, the main control module sends an initial test configuration command to the multi-frequency AC excitation and DC bias application module. The configuration command includes a test frequency list, an excitation amplitude sequence at each frequency, and bias scan parameters. The programmable AC signal source outputs the corresponding AC excitation signal according to the current test frequency and the current excitation amplitude level. The programmable DC bias source applies a DC bias signal starting from the initial bias according to a preset bias scan sequence. The application circuit synchronously applies the two signals to the test port of the semiconductor device under test.

[0100] In step S2, the PID closed-loop control module initiates a closed-loop correction process at each bias setpoint. Specifically, the error calculation unit acquires the response at the test port of the semiconductor device under test and compares it with a preset target value to generate a feedback error signal; the PID calculation unit performs proportional, integral, and derivative operations on the feedback error signal to generate an adjustment amount; the adjustment output unit adjusts the output amplitude of the AC excitation signal and / or the DC bias voltage based on the adjustment amount, thereby realizing closed-loop correction of the voltage condition applied at the test port of the semiconductor device under test.

[0101] Before executing step S3, the method further includes: generating a feedback error signal based on the response measured at the test port of the semiconductor device under test; determining whether the applied voltage condition meets the preset stability requirements; performing capacitance measurement when the determination result is yes; and continuing to perform closed-loop correction of the applied voltage when the determination result is no.

[0102] By using the above-mentioned decision sub-steps, each capacitance measurement can be performed under conditions where the applied voltage has reached stability and meets the preset accuracy requirements, thus avoiding measurement errors introduced by the non-convergence of the applied voltage conditions when performing capacitance test data acquisition.

[0103] In step S3, after the stability determination condition is met, the detection circuit of the capacitance measurement module collects the current response and voltage response generated by the semiconductor device under test under the current applied voltage condition. The measurement circuit processes the response signal and calculates the equivalent capacitance response signal under the current test frequency and excitation amplitude conditions.

[0104] In step S4, the condition marking unit of the capacitance test data caching module calculates and processes the equivalent capacitance response signal obtained in step S3 to obtain capacitance test data, and performs multi-dimensional condition marking on the capacitance test data, specifically including: recording the current test frequency, excitation level, bias setpoint value, and corresponding data acquisition timestamp, forming a complete condition-data association record. Subsequently, the cache storage unit stores the above association record into the corresponding cache area according to the classification index of test frequency, excitation level, and bias setpoint, and updates the data index of the read interface for the main control module to read as needed.

[0105] In step S5, after completing steps S2 to S4, the test process control unit of the main control module determines whether the current bias scan sequence has been traversed. If not, it sends the next bias step instruction to the programmable DC bias source and repeats steps S2 to S4. If all bias setpoints under the current excitation amplitude have been tested, it determines whether the excitation amplitude sequence has been traversed. If not, it switches to the next excitation amplitude, resets the bias scan start point, and re-executes steps S1 to S4. If all excitation amplitudes under the current frequency have been tested, it determines whether the test frequency list has been traversed. If not, it switches to the next test frequency and repeats the above process. When all combinations of test frequencies, all excitation amplitudes, and all bias setpoints have been tested, the result output unit reads all marked capacitor test data from the capacitor test data cache module, organizes it according to the multi-dimensional structure of test frequency, excitation amplitude, and bias setpoint, forms a complete capacitor test dataset, and outputs it for subsequent use.

[0106] It is understood that the automatic closed-loop control method for excitation amplitude for DLCP testing disclosed in this embodiment is based on the same technical design principle as the automatic closed-loop control system for excitation amplitude for DLCP testing disclosed in Embodiment 1. Both can achieve the same technical purpose. The effect that the automatic closed-loop control system for excitation amplitude for DLCP testing can achieve has been described in detail in Embodiment 1, so it will not be repeated here.

[0107] Those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. An automatic closed loop control system for excitation amplitude for DLCP testing, characterized in that, The system includes: The multi-frequency AC excitation and DC bias application module is used to apply a composite voltage signal consisting of AC excitation signal and DC bias signal to the test port of the same semiconductor device under test according to the test frequency list, excitation amplitude sequence and bias scan sequence. The capacitance measurement module is used to detect the actual response formed at the test port of the semiconductor device under test under the current test frequency, current excitation amplitude and current bias voltage setpoint. The PID closed-loop control module is used to compare the actual response with a preset target value to form a feedback error signal, and generate an adjustment amount based on the feedback error signal. The adjustment amount is used to perform closed-loop correction on the output amplitude of the AC excitation signal and the DC bias voltage respectively. The main control module includes a stability determination unit, which is used to determine that the composite voltage signal at the test port of the semiconductor device under test has reached a stable state when the AC amplitude error is less than a preset amplitude threshold and the bias error is less than a preset bias threshold. The capacitance measurement module is also used to acquire the equivalent capacitance response signal of the semiconductor device under test under the current test frequency, current excitation amplitude and current bias setpoint after the stability determination unit determines that the composite voltage signal has reached a stable state; The capacitance test data caching module processes the equivalent capacitance response signal to obtain capacitance test data and performs multi-dimensional condition labeling on the capacitance test data. Specifically, it records the current test frequency, excitation level, bias setpoint value and corresponding data acquisition timestamp to form a complete condition-data association record and cache, and updates the data index of the reading interface for the main control module to read as needed. The main control module also includes a test process control unit and a result output unit. The test process control unit is used to cyclically execute closed-loop stability determination and capacitance measurement processes under multiple test frequencies, multiple excitation amplitudes and multiple bias setpoints according to a preset test sequence. The result output unit outputs the capacitance test data for DLCP analysis.

2. The automatic closed loop control system for excitation amplitude of DLCP test according to claim 1, wherein, The multi-frequency AC excitation and DC bias application module includes: a programmable AC signal source, a programmable DC bias source, and an application circuit connected in sequence. The programmable AC signal source is used to output AC excitation signals with corresponding amplitudes according to the excitation amplitude sequence at each test frequency; The programmable DC bias source is used to output a corresponding DC bias signal according to the bias scan sequence; The application circuit is used to combine the AC excitation signal and the DC bias signal into the composite voltage signal and apply it to the test port of the semiconductor device under test.

3. The automatic closed loop control system for excitation amplitude of DLCP testing according to claim 1, wherein, The PID closed-loop control module includes an error calculation unit, a PID calculation unit, and an adjustment output unit. The error calculation unit is used to compare the actual voltage response with a preset target value to generate a feedback error signal; The PID calculation unit is used to perform proportional, integral, and derivative operations on the feedback error signal to generate the adjustment amount; The adjustment output unit is used to issue control commands to the multi-frequency AC excitation and DC bias application module according to the adjustment amount.

4. The automatic closed loop control system for excitation amplitude of DLCP testing according to claim 1, wherein, The capacitance measurement module includes a detection circuit and a measurement circuit; The input terminal of the detection circuit is electrically connected to the semiconductor device under test, and is used to detect the voltage response and current response generated by the semiconductor device under test under the action of the composite voltage signal; The measurement circuit is used to calculate the equivalent capacitance response signal based on the voltage response and current response.

5. The automatic closed loop control system for excitation amplitude of DLCP testing according to claim 1, wherein, The capacitance test data caching module includes a condition marking unit and a cache storage unit; The condition marking unit processes the equivalent capacitance response signal to obtain capacitance test data and performs multi-dimensional condition marking on the capacitance test data; specifically, it records the current test frequency, excitation level, bias setpoint value and corresponding data acquisition timestamp to form a complete condition-data association record and cache. The cache storage unit is used to classify and store the associated and tagged capacitance test data, and to provide a read interface to the main control module.

6. The automatic closed-loop control system for excitation amplitude for DLCP testing as described in claim 1, characterized in that, The test process control unit is used to execute closed-loop stability determination and capacitance measurement processes under multiple test frequencies, multiple excitation amplitudes, and multiple bias setpoints in a nested manner of outer loop traversing test frequencies, inner loop traversing excitation amplitudes, and innermost loop traversing bias setpoints.

7. A method for automatic closed loop control of the excitation amplitude for DLCP testing, characterized in that The method employs the automatic closed-loop control system for excitation amplitude used in DLCP testing as described in any one of claims 1-6, the method comprising: Automatically apply AC excitation signal and DC bias signal according to a preset excitation amplitude sequence at multiple test frequencies; At each bias set point of the preset bias scan sequence, a feedback error signal is constructed based on the response measured at the test port of the semiconductor device under test. The applied voltage is then corrected in a closed loop based on the feedback error signal so that the applied voltage condition at the test port of the semiconductor device under test meets the preset requirements. Obtain the equivalent capacitance response signal of the semiconductor device under test; The capacitor test data is associated, marked, and categorized for buffering according to the test frequency, excitation level, and bias setpoint. It coordinates the automatic testing process under multiple test frequencies and different excitation amplitudes, and outputs the corresponding capacitance test data.

8. The automatic closed-loop control method for excitation amplitude for DLCP testing as described in claim 7, characterized in that, Before acquiring the equivalent capacitance response signal of the semiconductor device under test, the method further includes: A feedback error signal is generated based on the response measured at the test port of the semiconductor device under test; Determine whether the applied voltage condition meets the preset stability requirements; If the judgment result is yes, perform capacitance measurement; If the judgment result is negative, continue to perform closed-loop correction on the applied voltage.

Images