Clock frequency detection system and method based on clock edge alignment detection

Abstract

The invention relates to the technical field of digital clock signal processing, in particular to a clock frequency detection system and method based on clock edge alignment detection, and the system comprises a working state monitoring module, a sampling period counting module, a clock sampling module, a state judgment and change module, and an index generation and output module. A signal of the system in a normal working state is released through the working state monitoring module, a high-frequency clock signal is input to the working state monitoring module, and the system controls a sampling period through a low-frequency clock, periodically samples the high-frequency clock, counts the number of high levels in the sampling period and judges the state change of the high-frequency clock. And judging that the rising edge of the low-frequency clock is aligned with the rising edge of the high-frequency clock, and outputting a corresponding phase index value. The device is realized by adopting pure digital logic, has anti-jitter capability, can accurately identify the phase of the high-frequency clock, and has the advantages of simple structure, high precision and strong transportability.

Description

Technical Field

[0001] This invention relates to the field of digital clock signal processing technology, and in particular to a clock frequency detection system and method based on clock edge alignment detection. Background Technology

[0002] In high-speed digital systems, clock signal synchronization and phase detection are key technologies for ensuring stable system operation, especially in scenarios such as 5G communication and high-speed storage. As system frequencies continue to increase, traditional clock detection methods struggle to accurately identify the phase relationship between high-frequency clocks and low-frequency reference clocks. Current high-frequency clock detection technologies suffer from significant drawbacks: analog phase-locked loops (PLLs) and delay-locked loops (DLLs) are weak in anti-interference, sensitive to high-frequency clock jitter, have poor stability, and poor portability; existing digital solutions can only perform coarse frequency measurement, failing to distinguish 32 or more fine phases, and are prone to alignment misjudgments due to incomplete logic loops; furthermore, most solutions have low functional integration, lack status monitoring, and suffer from significant resource waste. In summary, current technologies suffer from weak jitter resistance, low accuracy, poor portability, and insufficient integration, necessitating a pure digital logic, high-precision, and anti-interference high-frequency clock edge alignment and frequency detection solution. Summary of the Invention

[0003] In view of this, the purpose of this invention is to propose a clock frequency detection system and method based on clock edge alignment detection, so as to solve the problems of weak anti-jitter, low accuracy, poor portability and insufficient integration in the prior art.

[0004] To achieve the above objectives, the present invention provides a clock frequency detection system based on clock edge alignment detection, including a working state monitoring module, a sampling period counting module, a clock sampling module, a state determination and change module, and an index generation and output module. The output of the index generation and output module includes a phase index value and an index valid signal.

[0005] The working status monitoring module is used to detect the system working status and output the system normal working signal to the sampling period counting module, clock sampling module, status determination and change module and index generation and output module.

[0006] The sampling period counting module tracks the sampling period based on the input low-frequency clock signal and the system normal operation signal. When the count value in the current sampling period reaches the preset maximum value, it outputs a sampling period end signal.

[0007] The clock sampling module is used to sample the high-frequency clock signal in each sampling period, count the number of high-level signals in the high-frequency clock signal in the sampling period, and transmit the number of high-level signals as an input signal to the state determination and change module.

[0008] The state determination and change module determines the state of the high-frequency clock signal within the sampling period based on the number of high-level signals and detects state changes. When a valid state transition is detected, it outputs a state transition signal and triggers the working state monitoring module to adjust the normal working signal of the system.

[0009] The index generation and output module generates the final phase index value based on the number of high levels and the information of the state changes. After the rising edge of the low-frequency clock is aligned with the rising edge of the high-frequency clock, the index generation and output module continuously outputs the final phase index value.

[0010] Preferably, the sampling period counting module triggers a counting operation on each rising edge of the low-frequency clock. When the sampling count value reaches the preset maximum value, the sampling period end signal is generated, which indicates that the sampling of one sampling period has been completed.

[0011] Preferably, the sampling period end signal is generated by performing a bitwise AND operation on the sampling count value; when the sampling count value is a binary number of all 1s, the sampling period end signal is high.

[0012] Preferably, when the state determination and change module determines a valid transition, the process of outputting a state transition signal includes:

[0013] A first threshold and a second threshold are preset, with the first threshold being less than the second threshold; when the number of high-level signals is less than the first threshold, the high-frequency clock signal in the current sampling period is determined to be in an all-zero state; when the number of high-level signals is greater than the second threshold, the high-frequency clock signal in the current sampling period is determined to be in an all-one state; when the number of high-level signals is between the first threshold and the second threshold, the high-frequency clock signal in the current sampling period is determined to be in an edge state, where the edge state is a transitional state between 0 and 1.

[0014] By comparing the current state with the previous state in the previous sampling period, it is determined whether the effective transition has occurred, and the state transition signal is generated.

[0015] Preferably, when the state transition signal represents "transition from all 0 states to all 1 states" or "transition from edge states to all 1 states", the index generation and output module determines that the rising edge of the low-frequency clock is aligned with the rising edge of the high-frequency clock.

[0016] Preferably, the index generation and output module includes a current index register and a valid index register; the current index register is used to store the currently generated index value, and when the system is in normal working condition, the current index value is incremented by 1 after each sampling cycle.

[0017] When it is determined that the rising edge of the low-frequency clock is aligned with the rising edge of the high-frequency clock, the valid index register stores the value of the current index value minus 1 as the valid index value.

[0018] The index valid signal is used to indicate whether the output index value is valid, and the phase index value is the final output of the system.

[0019] Preferably, the output of the phase index value is controlled by the system normal operation signal: when the system normal operation signal is high, the phase index value is the lower five bits of the current index value; when the system normal operation signal is low, the phase index value is the lower five bits of the valid index value; the level of the system normal operation signal is controlled by the state transition signal: when the state transition signal indicates "transition from all 0 state to all 1 state" or "transition from edge state to all 1 state", the system normal operation signal is set to low; when the system normal operation signal is low, the current index value stops incrementing, and the valid index signal is set to high.

[0020] Preferably, the working status monitoring module controls the system's operating status through the system's normal operating signal: after the system is asynchronously reset, the system's normal operating signal is set to a high level, indicating that the system is in a working state; when the working status monitoring module detects that the state transition signal indicates "all 0 state to all 1 state" or "edge state to all 1 state", the system's normal operating signal is set to a low level, and the system stops index updating; when the system's normal operating signal is low, the index valid signal is set to a high level, and the phase index value outputs the lower five bits of the valid index value.

[0021] The present invention also provides a clock frequency detection method based on clock edge alignment detection, comprising the following steps:

[0022] S1. System Initialization: The system is reset by an asynchronous reset signal. The working status monitoring module generates and outputs a high-level system normal operation signal to indicate that the system has entered the working state. At the same time, the registers of the sampling period counting module, clock sampling module, status determination and change module and index generation and output module are all initialized to the preset initial state.

[0023] S2. Sampling Period Count: The sampling period counting module counts on each rising edge of the low-frequency clock signal and the high-level system normal operation signal. When the count value reaches the preset maximum value, it outputs a sampling period end signal, indicating that one sampling period has been completed.

[0024] S3. High-frequency clock sampling and statistics: During normal system operation, the clock sampling module continuously samples the high-frequency clock signal in each sampling cycle, counts the number of high-level signals in the high-frequency clock signal in that sampling cycle, and transmits the number of high-level signals to the status determination and change module.

[0025] S4. State Determination and Transition Detection: Based on the number of high-level signals, the state determination and change module determines the state of the high-frequency clock signal in the current sampling period, compares the current state with the state of the previous sampling period, and detects the state change during adjacent sampling periods; when a valid transition of "all 0 state to all 1 state" or "edge state to all 1 state" is detected, a state transition signal is output;

[0026] S5. System operating status adjustment: After receiving the status transition signal, the operating status monitoring module adjusts the level of the normal operating signal of the system to indicate that the system stops index updating;

[0027] S6. Index Generation and Output: The index generation and output module generates index values ​​based on the number of high-level signals and state change information, and outputs the corresponding index values ​​according to the level of the normal operating signal of the system. When the rising edge of the low-frequency clock is aligned with the rising edge of the high-frequency clock, the index generation and output module outputs the valid index value after subtracting 1 from the current index value as the final phase index value, and continues to output it. At the same time, the index valid signal is set to indicate that the phase index value is valid.

[0028] The beneficial effects of this invention are:

[0029] This invention employs a pure digital logic design, solving the problems of weak anti-jitter capability and poor portability of traditional analog schemes (PLL / DLL) by statistically analyzing the number of samplings in one cycle and determining the closed-loop state transition. It also solves the problem of coarse phase detection in existing digital schemes by accurately covering 32 high-frequency phases with a 5-bit index. It can meet the high-frequency clock synchronization requirements of scenarios such as 5G communication and high-speed storage, and is suitable for applications such as clock synchronization, data recovery, and phase calibration. It has the advantages of simple structure, high precision, and strong portability. Attached Figure Description

[0030] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only for this invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0031] Figure 1 This is a schematic diagram of the clock detection circuit module provided in an embodiment of the present invention;

[0032] Figure 2 This is a circuit diagram of the working status monitoring module provided in an embodiment of the present invention;

[0033] Figure 3 This is a circuit diagram of the sampling period counting module provided in an embodiment of the present invention;

[0034] Figure 4 This is a circuit diagram of the clock sampling module provided in an embodiment of the present invention;

[0035] Figure 5 This is a circuit diagram of the state determination and change module provided in an embodiment of the present invention;

[0036] Figure 6 This is a circuit diagram of the index generation and output module provided in an embodiment of the present invention;

[0037] Figure 7 This is a schematic diagram of the overall circuit architecture provided in an embodiment of the present invention. Detailed Implementation

[0038] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to specific embodiments.

[0039] It should be noted that, unless otherwise defined, the technical or scientific terms used in this invention should have the ordinary meaning understood by one of ordinary skill in the art to which this invention pertains. The terms "first," "second," and similar terms used in this invention do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are used only to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0040] Example 1:

[0041] This embodiment discloses a clock frequency detection system based on clock edge alignment detection. The core is used to accurately detect the phase of a high-frequency clock and output the corresponding valid index. It can be widely used in scenarios such as digital clock synchronization, phase detection, clock data recovery, on-chip clock management, or high-frequency clock phase calibration. The system is composed of a working status monitoring module, a sampling period counting module, a clock sampling module, a status determination and change module, and an index generation and output module. The input signals of the system include low-frequency clock, high-frequency clock, and asynchronous reset signal. The output signals are the phase index value and the index valid signal. The modules realize the complete functions of clock edge alignment detection and phase index output through signal interaction.

[0042] The operating status monitoring module, as the core of the system's operational status control, is primarily responsible for detecting the overall operating status of the system and generating a normal operating signal. This normal operating signal is synchronously output to the sampling period counting module, clock sampling module, status determination and change module, and index generation and output module, providing a unified status basis for the operation of each module and ensuring that each module coordinates the execution of the detection process. When the system is reset by an asynchronous reset signal, the operating status monitoring module sets the normal operating signal to a high level, indicating that the system has entered the normal operating state, at which time each functional module starts running. When it receives a status transition signal output by the status determination and change module (and the signal indicates "all 0 state transition to all 1 state" or "edge state transition to all 1 state"), the operating status monitoring module adjusts the normal operating signal to a low level, instructing the system to stop index updates and enter the result locking and output state.

[0043] The core function of the sampling period counting module is to track the sampling period based on the input low-frequency clock signal and the system's normal operating signal. Its counting operation is triggered by each rising edge of the low-frequency clock; that is, the sampling count value of the sampling period counting module increments accordingly each time a rising edge of the low-frequency clock is generated. This module has a preset maximum sampling count value (preferably 127 in this embodiment, corresponding to a 7-bit binary value of all 1s). When the sampling count value reaches this preset maximum value, the sampling period counting module generates a sampling period end signal to indicate the completion of a full sampling period. Specifically, the sampling period end signal is generated by performing a bitwise AND operation on the sampling count value. When the sampling count value is a binary number of all 1s, the sampling period end signal is high. This high-level signal is synchronously transmitted to the clock sampling module, the state determination and change module, and the index generation and output module, serving as the trigger for each module to perform cycle switching related operations.

[0044] During normal system operation (when the normal system signal is high), the clock sampling module responds to the periodic control of the sampling period counting module, continuously samples the high-frequency clock signal in each sampling period, and counts the number of high-level signals in the high-frequency clock signal in real time. The counted number of high-level signals is then transmitted to the status determination and change module as a key input signal to provide data support for subsequent status determination.

[0045] After receiving the number of high-level signals transmitted by the clock sampling module, the state determination and change module first determines the state of the high-frequency clock signal within the current sampling period based on a preset first threshold and a second threshold (where the first threshold is less than the second threshold): when the number of high-level signals is less than the first threshold, the current state is determined to be all 0s; when the number of high-level signals is greater than the second threshold, the current state is determined to be all 1s; when the number of high-level signals is between the first and second thresholds, the current state is determined to be an edge state, which is the transition state between 0 and 1 of the high-frequency clock signal (corresponding to the rising edge of the clock). Simultaneously, the state determination and change module stores the current state of the current sampling period and the previous state of the previous sampling period. By comparing the changes in the current state and the previous state, it determines whether a valid transition has occurred and generates a state transition signal. After an asynchronous reset, both the current state and the previous state are initialized to invalid states. Only after receiving the end-of-sampling signal for the first time are they updated to all 0s, all 1s, or an edge state based on the number of high-level signals. Invalid states only exist in the unsampled phase after reset. Specifically, a state transition signal is considered valid only when it represents a transition from an all-zero state to an all-one state or an edge state to an all-one state. At this time, the rising edge of the low-frequency clock happens to capture the end point of the rising edge of the high-frequency clock, satisfying the condition that the rising edges of the two are aligned. The state determination and change module will output the state transition signal to the working state monitoring module to trigger the adjustment of the system's working state.

[0046] The index generation and output module includes a current index register and a valid index register. Its core function is to generate the final phase index value based on the number of high-level clock samples and state change information. The current index register stores the currently generated index value. When the system is in normal operating condition (the normal operating signal is high), the current index value automatically increments by 1 after each sampling cycle (i.e., upon receiving a sampling cycle end signal). When the state determination and change module determines that the rising edge of the low-frequency clock aligns with the rising edge of the high-frequency clock (i.e., the state transition signal represents the aforementioned valid transition), the valid index register stores the value of the current index value minus 1; this value is the valid index value. The output of the phase index value is strictly controlled by the normal operating signal: when the normal operating signal is high, the phase index value outputs the lower five bits of the current index value; when the normal operating signal is low, the phase index value outputs the lower five bits of the valid index value. Meanwhile, the index valid signal is used to indicate whether the output phase index value is valid. When the normal operation signal of the system is set to low level by the state transition signal, the current index value stops incrementing and the index valid signal is set to high level. At this time, the lower five bits of the output valid index value are the final valid phase index value. After the rising edges of the low frequency clock and the high frequency clock are aligned, the index generation and output module will continue to output the final phase index value to ensure that the external device can stably obtain valid detection results.

[0047] Even when there is jitter in the high-frequency clock signal, this system can still maintain accurate detection. The maximum allowable jitter range of the high-frequency clock signal does not exceed 0.1% of half a cycle. Through the coordinated operation of various modules, reliable detection and effective index output of the high-frequency clock phase are achieved, meeting the application requirements of high-precision clock synchronization and phase calibration.

[0048] Example 2:

[0049] In one embodiment of this application, such as Figure 1 As shown, the input conditions are: the low-frequency clock is 10MHz second phase (start time 0+19.53125ps), the high-frequency clock is 3.2GHz second phase (with ±0.156ps jitter, period 312.5ps), and the asynchronous reset signal rst is first set to 1 and then set to 0;

[0050] In one embodiment of this application, such as Figure 2The working status monitoring module inputs an asynchronous reset signal rst. Asynchronous reset ensures that all modules are in the same initial state, improving system reliability. It is simple to implement and consumes few resources. During system reset, SystemWork is set to 1, indicating that the system is in normal working condition. When the state determination and change module outputs the signal index_case as 4'b1100 or 4'b1101, it indicates that the system transitions from an all-zero state to an all-one state or from an edge state to an all-one state, aligning the rising edge of the low-frequency signal with the rising edge of the high-frequency signal. The system stops working, and SystemWork is set to 0 after a 10MHz clock cycle delay, which also avoids false triggering caused by high-frequency clock jitter. When the asynchronous reset signal rst becomes valid again, SystemWork is set back to 1, and registers such as current_index and Valid_Index are synchronously cleared, supporting secondary system detection; that is, when rst=1, SystemWork=1, Sample_count=0, current_index=0, and index_state=index_state_last=2'b10.

[0051] In one embodiment of this application, such as Figure 3 As shown, in the sampling period counting module, when the system is reset, the sampling count Sample_count of the previous sampling period is cleared to zero. After the system is working normally, the value of Sample_count is incremented by 1 at each rising edge of 10MHz. After the count in the current sampling period reaches the maximum value of 127, Sample_count will be reset to start a new round of counting. The Sample_end signal is generated by bitwise AND of the 7-bit Sample_count signal. When Sample_count[6:0]=7'b111_1111, Sample_end=1, indicating that the sampling count has reached 128 times.

[0052] Furthermore, during system reset, such as Figure 4 As shown, all registers of the clock sampling module are cleared. When the system is working normally, the clock sampling module samples the high-frequency clock when each low-frequency clock rising edge arrives, counts the number of high levels in that cycle and updates the value of OnesNumber. When Sample_end is 0, OnesNumber is incremented by 1 when a high-frequency clock rising edge is detected; otherwise, OnesNumber remains unchanged. When Sample_end is 1, that is, when 128 sampling cycles are completed, the OnesNumber register is cleared and ready for the next sampling cycle.

[0053] Furthermore, the output of OnesNumber is passed to the status determination and change module, such as... Figure 5 As shown, the index_state and index_state_last registers are used to store the current state and the state of the previous sampling period, respectively.

[0054] Furthermore, index_state[1:0] and index_state_last[1:0] have only the following four states: 2'b00: represents all 0s, i.e., the value of OnesNumber is less than 10. 2'b11: represents all 1s, i.e., the value of OnesNumber is greater than 120. 2'b01: represents an edge state, i.e., the value of OnesNumber is between 10 and 120, which is considered to be a transition state between 0 and 1 (the rising edge of the clock). 2'b10: invalid state, which is the state during reset.

[0055] Furthermore, during system reset, both index_state and index_state_last are set to 2'b10. When the system is working normally and 128 samples have been collected, current_index_en is set to 1, the value of the index_state register is transferred to the index_state_last register, and the output of the clock sampling module is transferred to index_state. If the system is not working normally or 128 samples have not been collected, current_index_en is set to 0, and the values ​​of index_state and index_state_last remain unchanged.

[0056] Furthermore, index_case[3:0] is composed of index_state[1:0] and index_state_last[1:0] through bus operations, and its value represents the change between the current period's sampling result and the previous period's sampling result:

[0057] 4'b00_00: represents a transition from a state of all zeros to a state of all zeros;

[0058] 4'b00_11: represents a transition from an all-1 state to an all-0 state;

[0059] 4'b00_01: represents a transition from an edge state to a state of all zeros;

[0060] 4'b11_00: represents a transition from an all-zero state to an all-one state;

[0061] 4'b11_11: represents a transition from an all-1 state to an all-1 state;

[0062] 4'b11_01: Represents a transition from an edge state to an all-1 state;

[0063] 4'b01_00: represents the transition from a state with all edges at zero to a state with edges at zero;

[0064] 4'b01_11: represents a transition from an all-1 state to an edge state;

[0065] 4'b01_01: Represents a transition from an edge state to another edge state;

[0066] 4'b11_10, 4'b00_10, 4'b01_10, 4'b10_00, 4'b10_11, 4'b10_01, and 4'b10_10 are seven invalid transitions.

[0067] Furthermore, such as Figure 6 As shown, the current index register current_index[5:0] is used to store the currently generated index value. When the system is reset, current_index[5:0] is 6'b000000. When the system is working normally, when current_index_en is 1, that is, every 128 collections, current_index[5:0] will be incremented by 1; when current_index_en is 0, current_index[5:0] remains unchanged.

[0068] Furthermore, when the system is reset, the valid index register Valid_Index[5:0] is 6'b000000, and SystemWork is 1. When rst is 0 and SystemWork is 0, the system has completed the detection. Valid_Index[5:0] and SystemWork remain unchanged. When rst is 0 and SystemWork is 1, index_case[4:0] is 4'b1100 or 4'b1101, indicating that the system jumps from the all-zero state to the all-one state or from the edge state to the all-one state. At this time, Valid_Index[5:0] is the value of current_index[5:0] minus 1, and SystemWork is set to 0.

[0069] Furthermore, during system reset, the valid index value is set to 0, and the index valid signal index_valid is set to 0. Based on the value of SystemWork, it is determined whether the index output is current_index or Valid_Index. When the system is working normally, that is, when SystemWork is 1, the lower five bits of the current index register current_index[5:0] are assigned to the valid index value index[4:0], and the index valid signal index_valid is set to 0. When SystemWork is 0, it indicates that the system has completed the detection. At this time, the lower five bits of the valid index register Valid_Index[5:0] are assigned to the phase index value index[4:0], current_index stops counting, and index_valid is set to 1.

[0070] In one embodiment of this application, the index generation and output module, when rst=0, SystemWork=1, sample_count=127, sample_end=1, OnesNumber=1, is in an all-zero state, and outputs 2'b00. After a 10MHz rising edge delay, index_state_last[1:0]=index_state[1:0]=2'b11, index_state[1:0]=2'b00, index_case[3:0]=4'b1100, that is, it jumps from an all-zero state to an all-one state, current_index_en=1, and when current_index_en is 1, index_case will be updated; when the value of index_case[3:0] is 1101, the normal operating signal of the system becomes 0 after a 10MHz clock cycle delay; index_valid becomes 1 after a 10MHz clock cycle delay, and index[4:0] outputs the lower five bits of Valid_index[5:0]. At this time, in the 2-phase state, the high-frequency clock and the low-frequency clock are aligned. The final index=2, which is consistent with the second phase of the input 3.2GHz, proving that it can still detect accurately even with jitter.

[0071] Example 3:

[0072] This embodiment provides a clock frequency detection method based on clock edge alignment detection, including the following steps:

[0073] S1. System Initialization: The system is reset by an asynchronous reset signal. The working status monitoring module generates and outputs a high-level system normal operation signal to indicate that the system has entered the working state. At the same time, the registers of the sampling period counting module, clock sampling module, status determination and change module and index generation and output module are all initialized to the preset initial state.

[0074] S2. Sampling Period Count: The sampling period counting module counts on each rising edge of the low-frequency clock signal and the high-level system normal operation signal. When the count value reaches the preset maximum value, it outputs a sampling period end signal, indicating that one sampling period has been completed.

[0075] S3. High-frequency clock sampling and statistics: During normal system operation, the clock sampling module continuously samples the high-frequency clock signal in each sampling cycle, counts the number of high-level signals in the high-frequency clock signal in that sampling cycle, and transmits the number of high-level signals to the status determination and change module.

[0076] S4. State Determination and Transition Detection: Based on the number of high-level signals, the state determination and change module determines the state of the high-frequency clock signal in the current sampling period, compares the current state with the state of the previous sampling period, and detects the state change during adjacent sampling periods; when a valid transition of "all 0 state to all 1 state" or "edge state to all 1 state" is detected, a state transition signal is output;

[0077] S5. System operating status adjustment: After receiving the status transition signal, the operating status monitoring module adjusts the level of the normal operating signal of the system to indicate that the system stops index updating;

[0078] S6. Index Generation and Output: The index generation and output module generates index values ​​based on the number of high-level signals and state change information, and outputs the corresponding index values ​​according to the level of the normal operating signal of the system. When the rising edge of the low-frequency clock is aligned with the rising edge of the high-frequency clock, the index generation and output module outputs the valid index value after subtracting 1 from the current index value as the final phase index value, and continues to output it. At the same time, the index valid signal is set to indicate that the phase index value is valid.

[0079] Those skilled in the art should understand that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope of the invention is limited to these examples; within the framework of the invention, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of the different aspects of the invention as described above, which are not provided in detail for the sake of brevity. Any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the invention should be included within the scope of protection of the invention.

Claims

1. A clock frequency detection system based on clock edge alignment detection, characterized in that, It includes a working status monitoring module, a sampling period counting module, a clock sampling module, a status determination and change module, and an index generation and output module. The output of the index generation and output module includes a phase index value and an index valid signal. The working status monitoring module is used to detect the system working status and output the system normal working signal to the sampling period counting module, clock sampling module, status determination and change module and index generation and output module. The sampling period counting module tracks the sampling period based on the input low-frequency clock signal and the system normal operation signal. When the count value in the current sampling period reaches the preset maximum value, it outputs a sampling period end signal. The clock sampling module is used to sample the high-frequency clock signal in each sampling period, count the number of high-level signals in the high-frequency clock signal in the sampling period, and transmit the number of high-level signals as an input signal to the state determination and change module. The state determination and change module determines the state of the high-frequency clock signal within the sampling period based on the number of high-level signals and detects state changes. When a valid state transition is detected, it outputs a state transition signal and triggers the working state monitoring module to adjust the normal working signal of the system. The index generation and output module generates the final phase index value based on the number of high levels and the information of the state changes. After the rising edge of the low-frequency clock is aligned with the rising edge of the high-frequency clock, the index generation and output module continuously outputs the final phase index value.

2. The clock frequency detection system based on clock edge alignment detection according to claim 1, characterized in that, The sampling period counting module triggers a counting operation on each rising edge of the low-frequency clock. When the sampling count value reaches the preset maximum value, the sampling period end signal is generated. The sampling period end signal indicates that the sampling of one sampling period has been completed.

3. The clock frequency detection system based on clock edge alignment detection according to claim 2, characterized in that, The sampling period end signal is generated by performing a bitwise AND operation on the sampling count value; when the sampling count value is a binary number of all 1s, the sampling period end signal is high.

4. The clock frequency detection system based on clock edge alignment detection according to claim 1, characterized in that, When the state determination and change module determines a valid transition, the process of outputting a state transition signal includes: A first threshold and a second threshold are preset, with the first threshold being less than the second threshold; when the number of high-level signals is less than the first threshold, the high-frequency clock signal in the current sampling period is determined to be in an all-zero state; when the number of high-level signals is greater than the second threshold, the high-frequency clock signal in the current sampling period is determined to be in an all-one state; when the number of high-level signals is between the first threshold and the second threshold, the high-frequency clock signal in the current sampling period is determined to be in an edge state, where the edge state is a transitional state between 0 and 1. By comparing the current state with the previous state in the previous sampling period, it is determined whether the effective transition has occurred, and the state transition signal is generated.

5. The clock frequency detection system based on clock edge alignment detection according to claim 4, characterized in that, When the state transition signal represents "transition from all 0 states to all 1 states" or "transition from edge states to all 1 states", the index generation and output module determines that the rising edge of the low-frequency clock is aligned with the rising edge of the high-frequency clock.

6. The clock frequency detection system based on clock edge alignment detection according to claim 1, characterized in that, The index generation and output module includes a current index register and a valid index register; the current index register is used to store the currently generated index value, and when the system is in normal working condition, the current index value increments by 1 after each sampling cycle. When it is determined that the rising edge of the low-frequency clock is aligned with the rising edge of the high-frequency clock, the valid index register stores the value of the current index value minus 1 as the valid index value. The index valid signal is used to indicate whether the output index value is valid, and the phase index value is the final output of the system.

7. The clock frequency detection system based on clock edge alignment detection according to claim 6, characterized in that, The output of the phase index value is controlled by the system normal operation signal: when the system normal operation signal is high, the phase index value is the lower five bits of the current index value; When the normal operating signal of the system is low, the phase index value is the lower five bits of the effective index value; The level of the normal operating signal of the system is controlled by the state transition signal: when the state transition signal represents "transition from all 0 state to all 1 state" or "transition from edge state to all 1 state", the normal operating signal of the system is set to low level; when the normal operating signal of the system is low level, the current index value stops incrementing and the index valid signal is set to high level.

8. The clock frequency detection system based on clock edge alignment detection according to claim 1, characterized in that, The working status monitoring module controls the system's operating status through the system's normal operation signal: after the system is asynchronously reset, the system's normal operation signal is set to a high level, indicating that the system is in a working state; when the working status monitoring module detects that the state transition signal indicates "all 0 state to all 1 state" or "edge state to all 1 state", the system's normal operation signal is set to a low level, and the system stops index updating; when the system's normal operation signal is low, the index valid signal is set to a high level, and the phase index value outputs the lower five bits of the valid index value.

9. A clock frequency detection method based on clock edge alignment detection, characterized in that, The method includes the following steps: S1. System Initialization: The system is reset by an asynchronous reset signal. The working status monitoring module generates and outputs a high-level system normal operation signal to indicate that the system has entered the working state. At the same time, the registers of the sampling period counting module, clock sampling module, status determination and change module and index generation and output module are all initialized to the preset initial state. S2. Sampling Period Count: The sampling period counting module counts on each rising edge of the low-frequency clock signal and the high-level system normal operation signal. When the count value reaches the preset maximum value, it outputs a sampling period end signal, indicating that one sampling period has been completed. S3. High-frequency clock sampling and statistics: During normal system operation, the clock sampling module continuously samples the high-frequency clock signal in each sampling cycle, counts the number of high-level signals in the high-frequency clock signal in that sampling cycle, and transmits the number of high-level signals to the status determination and change module. S4. State Determination and Transition Detection: Based on the number of high-level signals, the state determination and change module determines the state of the high-frequency clock signal in the current sampling period, compares the current state with the state of the previous sampling period, and detects the state change during adjacent sampling periods; when a valid transition of "all 0 state to all 1 state" or "edge state to all 1 state" is detected, a state transition signal is output; S5. System operating status adjustment: After receiving the status transition signal, the operating status monitoring module adjusts the level of the normal operating signal of the system to indicate that the system stops index updating; S6. Index Generation and Output: The index generation and output module generates index values ​​based on the number of high-level signals and state change information, and outputs the corresponding index values ​​according to the level of the normal operating signal of the system. When the rising edge of the low-frequency clock is aligned with the rising edge of the high-frequency clock, the index generation and output module outputs the valid index value after subtracting 1 from the current index value as the final phase index value, and continues to output it. At the same time, the index valid signal is set to indicate that the phase index value is valid.

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