Sample rate converter with clock multiplier

Abstract

A rate estimator circuit is provided for adjusting the sampling rate filter of a sampling rate converter circuit. The rate estimator circuit includes a first integrator clocked by a first clock signal having a first sampling frequency and a second integrator clocked by a second clock signal having a second sampling frequency; a resolution upscaling circuit including a third integrator clocked by a system clock signal; a digital clock multiplier circuit including the second integrator and a multiplier loop circuit having a fourth integrator; a multiplier output stage connected to the output of the fourth integrator; and a rate estimator circuit including the first integrator and an estimator loop circuit having a fifth integrator.

Description

Technical Field

[0001] This invention relates to a rate estimator circuit for adjusting the sampling rate filter of a sampling rate converter circuit, and also to a method for estimating the ratio of a first clock signal to a second clock signal. Background Technology

[0002] This type of sample rate converter requires asynchronous data processing to convert digital signals between different sample rates in audio and speech systems. In audio and speech systems, there is often more than one sample rate used for different standards, such as 44.1kHz and 48kHz audio, and 8kHz and 16kHz speech. Typically, signals from speech and audio need to be mixed, meaning the sample rate needs to be the same. It is common practice to convert signals from different audio sources to a common rate (e.g., 96kHz) so that they can be processed by a digital signal processor operating at a constant clock rate. The data sources are often asynchronous, meaning they come from uncorrelated clock domains. For example, data might be received from a Bluetooth receiver at a rate dependent on the remote Bluetooth transmitter, and this data might need to be converted to a sample rate associated with a local master clock, derived by a crystal oscillator.

[0003] This invention specifically relates to sampling rate estimation, a component in a sampling rate converter, used to estimate the sampling rate ratio R between input and output data. This sampling rate estimation is required to adjust the sampling rate filter to provide an efficient conversion between the input sampling rate FSI and the output sampling rate FSO. Figure 1 A block diagram of a sample rate converter 1 with a sample rate estimator 2 and a sample rate filter 3, according to the prior art, is shown. The sample rate estimator 2 provides an estimate of the ratio R between the input sample rate FSI and the output sample rate FSO, where R = FSI / FSO. This estimated ratio R is passed to the sample rate filter 3, which resamples the input data signal DATA_IN at the output sample rate FSO and provides necessary anti-aliasing or anti-imaging filters. One of the main design considerations for the sample rate estimator 2 is lock-in time. This is the time it takes for the sample rate estimator 2 to provide an estimate of the sample rate ratio R within a defined error range. If the lock-in time is too long, the sample rate converter 1 takes too long to start up, which can affect the responsiveness of the audio / speech system containing the sample rate converter 1. High-performance sample rate converters (e.g., THD+N < 120 dB) require small estimation errors (within the same order of magnitude as the THD+N specification) but also low lock-in times, typically < 50 ms. Designing a sample rate converter with high performance and low lock-in time is very challenging.

[0004] “A Stereo Asynchronous Digital Sample-Rate Converter for DigitalAudio”, Robert Adams and Tom Kwan, IEEE Journal of Solid-state Circuits, Vol 29, No 4, April 1994, teaches a method for estimating the ratio R between the input sampling rate FSI and the output sampling rate FSO. Figure 2 This sampling rate converter 4 is illustrated, where a first integrator 5 is clocked at the input sampling rate FSI, and a second integrator 6 is clocked at the output sampling rate FSO. The loop tracks the difference between the slopes of the outputs of the first integrator 5 and the second integrator 6, and adjusts the slope of the second integrator 6 in the FSO domain to match. The input to the second integrator 6 is a ratio R = FSI / FSO. This ratio R is passed to... Figure 1 The sampling rate filter 3 performs the sampling rate conversion of the data signal DATA_IN to DATA_OUT.

[0005] In designing the rate estimator 2, there is a trade-off between locking speed and accuracy. For fast convergence, the time constant of the sampling rate filter 3 must be fast. For accuracy, the time constant must be slow. Typically, the time constant is adjusted so that the rate estimator 2 tracks quickly at startup and then improves accuracy over time. However, adjusting the time constant can introduce glitch into the sampling rate estimation, which can lead to a degrade in audio quality and may mean that the loop must be re-stabilized, increasing the lock-in time.

[0006] For example, in Figure 2 In this circuit, since the estimated sampling rate ratio R is at the output of coefficient K, adjusting coefficient K immediately adjusts the value of ratio R, resulting in glitches, after which the loop must re-stabilize. The prior art sampling rate converter disclosed in US7948405 addresses the glitches problem with a second loop that biases the first loop to minimize them, but because this loop is first-order, the convergence time is slow.

[0007] A system solution to reduce lock-in time is to use higher frequency clocks, such as N×FSI and M×FSO clocks, where N and M are integers. These are typically generated by phase-locked loops (PLLs), but this has the disadvantages of larger silicon area, higher power consumption, and reduced flexibility, because each sample rate converter in a system using different input and output clock rates requires two PLLs. Summary of the Invention

[0008] The object of this invention is to provide a rate estimator circuit and a rate estimation method with fast lock-in time, low error rate, and low system cost. This object is achieved by the rate estimator circuit according to claim 1 and the method according to claim 10.

[0009] This invention is based on the understanding that in systems using a sample-rate converter with a rate estimator circuit to asynchronously process data, a high-frequency master clock is often already present. Digital techniques can be used to multiply the input and output clock signals of the rate estimator circuit relative to this high-frequency master clock to produce a finer clock resolution. These multipliers must track each other, which is achieved by using the same resolution coefficient value in these multipliers, thereby ensuring that the ratio of the input clock to the output clock remains substantially the same as the ratio of the multiplied clock, and this significantly improves the lock-in time of the sample-rate converter.

[0010] These and other aspects of the invention will become apparent and elucidated with reference to the embodiments described below. Those skilled in the art will understand that various embodiments can be combined. Attached Figure Description

[0011] Figure 1 A block diagram of a sampling rate converter circuit according to the prior art is shown. Figure 2 Another sampling rate converter circuit according to the prior art is shown, wherein a first integrator clocks at the input sampling rate and a second integrator clocks at the output sampling rate. Figure 3 A block diagram of a first embodiment of the rate estimator circuit according to the present invention is shown. Figure 4 This shows the increase in resolution of the output signal of the first integrator compared to... Figure 3 The relationship between the output of the rate estimator circuit and the resolution enhancer circuit is shown in the graph. Figure 5 Show Figure 3 The diagram shows the rate estimator circuit's frequency multiplier output stage generating a ratio clock signal. Figure 6 Showing according to Figure 1 The existing rate estimator circuit and Figure 3 A performance simulation comparison of the rate estimator circuit of the present invention. Detailed Implementation

[0012] Figure 3 A block diagram of sampling rate converter circuit 7 is shown, which has the following characteristics: Figure 1The sample rate converter circuit 1 shown is configured as follows, but also includes a rate estimator circuit 8 according to the invention. The sample rate converter circuit 7 is configured to receive a first signal DATA_IN at a first sampling frequency and to output a second signal DATA_OUT having a second sampling frequency, the second signal representing the first signal DATA_IN.

[0013] The rate estimator circuit 8 is configured to receive a first clock signal having an input sampling rate FSI with the first sampling frequency and a second clock signal having an output sampling rate FSO with the second sampling frequency. Furthermore, the rate estimator circuit 8 is configured to generate an estimate of the ratio R = FSI / FSO of the input sampling rate FSI to the output sampling rate FSO, used to adjust the sampling rate filter 3.

[0014] The rate estimator circuit 8 includes a first integrator I1 and a second integrator I2. The first integrator I1 is clocked by a first clock signal operating at the input sampling rate FSI, and the second integrator I2 is clocked by a second clock signal operating at the output sampling rate FSO. Figure 3 As shown, the first integrator I1 and the second integrator I2 are incremented by a value of 1 for each clock pulse.

[0015] The rate estimator circuit 8 also includes a resolution upscaling circuit Res Loop, which includes a third integrator I3 clocked by a system clock signal FSH, which is a clock signal available in the system using the sampling rate converter circuit 7. The system clock signal FSH includes a frequency higher than the first and second sampling frequencies, and in one embodiment of the invention, the system clock signal FSH is the clock of the system's digital circuitry. In other embodiments, the system clock signal FSH is the clock of the system's microprocessor or digital signal processor, which is on the same chip as the sampling rate converter circuit 7. The advantage of using such a system-available clock signal is that no additional silicon area and power consumption are required to generate the system clock signal FSH.

[0016] The resolution upscaling circuit Res Loop is connected to the output of the first integrator I1 and is configured to subtract the output signal 9 of the third integrator I3 from the output signal 10 of the first integrator I1 to provide the resulting resolution loop signal 11, which is weighted by the resolution coefficient K2 and provided to the input of the third integrator I3. Figure 4 As can be seen, the output signal 9 of the third integrator I3 tracks the slope of the output signal 10 of the first integrator I1. However, since the third integrator I3 of the resolution enhancer circuit Res Loop is clocked at a frequency much higher than the input sampling rate FSI, the stepped slope has a finer resolution, making the error of the ratio R estimated by the rate estimator circuit 8 very small, which will be explained further below.

[0017] The rate estimator circuit 8 also includes a digital clock multiplier circuit 12, which includes a second integrator I2, a multiplier loop circuit Mult Loop, and a multiplier output stage Mult Out. The multiplier loop circuit Mult Loop includes a fourth integrator I4 clocked by the system clock signal FSH. The multiplier loop circuit Mult Loop is connected to the output of the second integrator I2 and is configured to subtract the output signal 13 of the fourth integrator I4 from the output signal 14 of the second integrator I2 to provide the resulting multiplier loop signal 15, which is weighted by the multiplier coefficient K1 and provided to the input of the fourth integrator I4.

[0018] The fourth integrator I4 in the frequency multiplier loop circuit Mult Loop operates in the same way as the third integrator I3 in the resolution enhancer circuit ResLoop. The output signal I3 of the fourth integrator I4 is a ramp with a slope equal to y / x=FSO, but it is retied to the system clock FSH.

[0019] The multiplier output stage Mult Out includes a multiplier K3 connected to the output of the fourth integrator I4 and the input of the comparator circuit 16. The multiplier K3 is configured to increase the slope of the output signal 13 of the fourth integrator I4 to obtain a ramp signal 17 of y / x = K3 × FSO. Figure 5 The ramp signal 17 is shown in the image.

[0020] If the output of frequency multiplier K3 has wrapping arithmetic, then its output ramp signal 17 will have a sawtooth waveform 18 with a frequency of K3 × FSO. Comparator circuit 16 converts the sawtooth waveform 18 into a ratio clock signal FSR.

[0021] The rate estimator circuit 8 also includes a rate estimator circuit 19, which includes a first integrator I1 and an estimator loop circuit Est Loop with a fifth integrator I5, which is clocked by the ratio clock signal FSR.

[0022] The estimator loop circuit Est Loop is connected to the output of the resolution upscaling circuit Res Loop and is configured to subtract the output signal 20 of the fifth integrator I5 from the output signal 9 of the third integrator I3 to provide the estimator loop signal 21. This estimator loop signal 21 is weighted by the estimator coefficients K4 and is provided at the output 22 of the estimator loop circuit Est Loop as an estimate of the ratio R. Furthermore, the fifth integrator I5 is configured to increment by the ratio R with each clock pulse of the ratio clock signal FSR. Thus, the sampling rate of the estimator loop circuit Est Loop is increased by a factor K3, therefore:

[0023] FSR = K3 × FSO; and

[0024] R = FSI / (K3 × FSO).

[0025] Since the multiplier K3 is a constant, the output rate R can be easily amplified by the factor K3 to produce the ratio R = FSI / FSO.

[0026] As described above, the first integrator I1 produces an output signal I0 with a slope proportional to the input sampling rate FSI. The estimator loop circuit Est Loop also produces a slope with the same slope as the first integrator I1. This is because the feedback of the loop circuits Res Loop and Est Loop minimizes the error between the slopes of their input and output.

[0027] The equation can be derived as follows:

[0028] Each input sampling rate FSI clock (with period T) FSI The first integrator I1 increments by 1, therefore it has a slope y / x = 1 / T. FSI =FSI;

[0029] For each clock cycle of the ratio clock signal FSR, the fifth integrator I5 increments by R, thus having a slope y / x = R × FSR;

[0030] Since the slopes at the outputs of I1 and I5 are matched, FSI = R × FSR, therefore R = FSI / FSR.

[0031] The frequency multiplier loop (Mult Loop) and the resolution enhancer loop (Res Loop) do not stabilize immediately; the time required to reach steady-state values ​​depends on their time constants, which are determined by the frequency multiplier coefficient K1 and the resolution enhancer coefficient K2. However, since the required output ratio R is the ratio of the ramp slopes of the third integrator I3 to the fourth integrator I4, the startup error caused by the settling time will be roughly offset as long as the frequency multiplier loop (Mult Loop) and the resolution enhancer loop (Res Loop) stabilize at the same rate. Because both the frequency multiplier loop (Mult Loop) and the resolution enhancer loop (Res Loop) are clocked by the same system clock signal FSH, error cancellation will occur if K1 = K2.

[0032] Figure 6 Show Figure 1 Simulation results 23 of the performance of the existing rate estimator 2 and the present invention Figure 3 Simulation results 24 show the performance of the rate estimator circuit 8. The rate estimator circuit 8 of the present invention converges faster and has lower error.

[0033] Typical values ​​for the constant and clock rate are as follows:

[0034] The input sampling rate (FSI) is in the range of 8-192kHz;

[0035] The output sampling rate FSO is in the range of 8-192kHz;

[0036] The system clock signal FSH is typically 8MHz;

[0037] Frequency multiplier coefficient K1 = resolution coefficient K2 = 2 -11 ;

[0038] Frequency multiplier K3=16;

[0039] Estimator coefficient K4=2 -10 ;

[0040] Integrators I3 through I5 require a delay.

[0041] In further preferred embodiments, various enhancements are possible, such as:

[0042] Use a higher-order estimator loop circuit to reduce ripple in the ratio R.

[0043] Adjust the loop coefficients K1 to K4 to reduce convergence time.

[0044] The frequency multiplier coefficient K1 and the resolution coefficient K2 are defined as similar but not identical values. Compared to K1=K2, the loop converges more slowly, but still converges well enough to allow the sampling rate converter circuit to work as expected.

[0045] As described above, the rate estimator circuit 8 performs a method having the following steps:

[0046] • Generate an estimate of the ratio R between the first sampling frequency and the second sampling frequency, which is used to adjust the sampling rate filter;

[0047] • The resolution of the output signal of the first integrator I1, which is clocked by the first clock signal and has an input sampling rate FSI, is increased by the resolution increaser circuit Res Loop. The Res Loop has a third integrator I3, which is clocked by the system clock signal FSH, and has a frequency higher than the first and second sampling frequencies.

[0048] • The resolution of the output signal of the second integrator I2, which is clocked by the second clock signal with the output sampling rate FSO, is increased by the frequency multiplier loop circuit Mult Loop. Mult Loop has a fourth integrator I4, which is clocked by the system clock signal FSH.

[0049] • Ensure that the resolution increaser circuit Res Loop and the frequency multiplier loop circuit Mult Loop are processed with similar or preferably the same values ​​of the frequency multiplier coefficient K1 and resolution coefficient K2 to weight the resolution loop signal 11, which is the input to the third integrator I3, and the frequency multiplier loop signal 15, which is the input to the fourth integrator I4.

[0050] It is advantageous if the rate estimator circuit 8 performs the following further steps:

[0051] • The second integrator I2 and the frequency multiplier loop circuit Mult Loop and the frequency multiplier output stage Mult Out are used as a digital clock multiplier to provide a ratio clock signal FSR, which is used to clock the fifth integrator I5 in the estimator loop circuit Est Loop of the rate estimator circuit 19 to generate an estimate of the ratio R of the first sampling frequency to the second sampling frequency.

[0052] In another preferred embodiment, the following steps may be performed:

[0053] • An estimate of the ratio R between the first sampling frequency and the second sampling frequency is generated and used to adjust the sampling rate filter 3 of the sampling rate converter circuit 7;

[0054] • Process a first clock signal having an input sampling rate FSI (corresponding to the first sampling frequency) and a second clock signal having an output sampling rate FSO (corresponding to the second sampling frequency) to provide a noise ratio R between the first sampling frequency and the second sampling frequency;

[0055] • Low-pass filtering is performed on the noise ratio R between the first sampling frequency and the second sampling frequency based on the adjustable filter coefficients K to provide the estimated ratio R between the first sampling frequency and the second sampling rate, which is used to adjust the sampling rate filter 3.

Claims

1. A rate estimator circuit for adjusting the sampling rate filter of a sampling rate converter circuit, the rate estimator circuit comprising: A first integrator clocked by a first clock signal having a first sampling frequency and a second integrator clocked by a second clock signal having a second sampling frequency, wherein the rate estimator circuit is configured to generate an estimate of the ratio of the first sampling frequency to the second sampling frequency; A resolution upscaling circuit includes a third integrator clocked by a system clock signal with a frequency higher than the first sampling frequency and the second sampling frequency, wherein the resolution upscaling circuit is connected to the output of the first integrator; A digital clock multiplier circuit includes: The second integrator, and A frequency multiplier loop circuit having a fourth integrator clocked by the system clock signal, the frequency multiplier loop circuit being connected to the output of the second integrator; A frequency multiplier output stage, connected to the output of the fourth integrator, wherein the frequency multiplier output stage includes a comparator circuit for providing a ratio clock signal; and Rate estimator circuit, comprising: The first integrator, and An estimator loop circuit having a fifth integrator clocked by the ratio clock signal, the estimator loop circuit being connected to the output of the resolution increaser circuit and configured to generate an estimate of the ratio of the first sampling frequency to the second sampling frequency.

2. The rate estimator circuit of claim 1, wherein the resolution enhancer circuit is configured to subtract the output signal of the third integrator from the output signal of the first integrator to provide a resulting resolution loop signal, the resolution loop signal being weighted by resolution coefficients and provided to the input of the third integrator.

3. The rate estimator circuit of claim 1, wherein the multiplier loop circuit of the digital clock multiplier circuit is configured to subtract the output signal of the fourth integrator from the output signal of the second integrator to provide a resulting multiplier loop signal, the multiplier loop signal being weighted by multiplier coefficients and provided to the input of the fourth integrator.

4. The rate estimator circuit of claim 1, wherein the estimator loop circuit is configured to subtract the output signal of the fifth integrator from the output signal of the third integrator to provide an estimator loop signal, the estimator loop signal being weighted by estimator coefficients and provided at the output of the estimator loop circuit as an estimate of the rate.

5. The rate estimator circuit of claim 1, wherein the frequency multiplier output stage includes a frequency multiplier connected to the output of the fourth integrator and the input of the comparator circuit, the frequency multiplier being configured to increase the slope of the output signal of the fourth integrator.

6. The rate estimator circuit of claim 1, wherein the system clock generated outside the rate estimator circuit is configured to be received at the input of the rate estimator circuit.

7. The rate estimator circuit of claim 1, wherein the first integrator is configured to increment by an integer 1 with each clock pulse of the first clock signal, and wherein the fifth integrator is configured to increment by the ratio with each clock pulse of the ratio clock signal.

8. The rate estimator circuit of claim 1, wherein the resolution factor used by the resolution increaser circuit and the frequency multiplier factor used by the frequency multiplier loop circuit have the same value.

9. A sampling rate converter circuit for receiving an input signal at a first sampling frequency and outputting an output signal representing the input signal and having a second sampling frequency, the sampling rate converter circuit comprising the rate estimator circuit according to claim 1.

10. A method for estimating the ratio of a first clock signal having a first sampling frequency of an input signal having a sampling rate converter circuit to a second clock signal having a second sampling frequency of an output signal having the sampling rate converter circuit, for adjusting a sampling rate filter of the sampling rate converter circuit, wherein the following steps are performed by a rate estimator circuit of the sampling rate converter circuit: An estimate of the ratio of the first sampling frequency to the second sampling frequency is generated for adjusting the sampling rate filter; The resolution of the output signal of the first integrator, which is clocked by the first clock signal, is increased by a resolution increaser circuit. The resolution increaser circuit has a third integrator, which is clocked by the system clock signal, and its frequency is higher than the first sampling frequency and the second sampling frequency. The resolution of the output signal of the second integrator, which is clocked by the second clock signal, is increased by a frequency multiplier loop circuit having a fourth integrator clocked by the system clock signal.

11. The method for estimating a ratio according to claim 10, wherein the rate estimator circuit performs the following further steps: Ensure that the resolution increaser circuit and the frequency multiplier loop circuit are processed with the same coefficient values ​​to weight the input signal of their integrator.

12. The method for estimating a ratio according to claim 10, wherein the rate estimator circuit performs the following further steps: The second integrator, the frequency multiplier loop circuit, and the frequency multiplier output stage are used as a digital clock multiplier to provide a ratio clock signal, which is used to clock the fifth integrator in the estimator loop circuit of the rate estimator circuit, thereby generating an estimate of the ratio of the first sampling frequency to the second sampling frequency.

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