Sample rate converter with fast tracking function

Abstract

A sample rate converter circuit for receiving a first signal at a first sample frequency and outputting a second signal having a second sample frequency. The sample rate converter circuit includes a rate estimator circuit structured to receive a first clock signal having the first sample frequency and a second clock signal having the second sample frequency and structured to generate an estimate of a ratio of the first sample frequency to the second sample frequency. The rate estimator circuit includes an instantaneous rate estimator circuit structured to process the first clock signal and the second clock signal to provide a noisy ratio of the first sample frequency to the second sample frequency and a low pass filter structured to filter the noisy ratio of the first sample frequency to the second sample frequency based on filter coefficients adjustable by a time constant controller of the rate estimator circuit.

Description

Technical Field

[0001] The present invention relates to a sampling rate converter circuit for receiving a first signal at a first sampling frequency and outputting a second signal having a second sampling frequency representing the first signal. Background Technology

[0002] This type of sample rate converter requires asynchronous data processing to convert digital signals between different sample rates in audio and speech systems. In audio and speech systems, there is often more than one sample rate used for different standards, such as 44.1kHz and 48kHz audio, and 8kHz and 16kHz speech. Typically, signals from speech and audio need to be mixed, meaning the sample rate needs to be the same. It is common practice to convert signals from different audio sources to a common rate (e.g., 96kHz) so that they can be processed by a digital signal processor operating at a constant clock rate. The data sources are often asynchronous, meaning they come from uncorrelated clock domains. For example, data might be received from a Bluetooth receiver at a rate dependent on the remote Bluetooth transmitter, and this data might need to be converted to a sample rate associated with a local master clock, derived by a crystal oscillator.

[0003] This invention specifically relates to sampling rate estimation, a component in a sampling rate converter, used to estimate the sampling rate ratio R between input and output data. This sampling rate estimation is required to adjust the sampling rate filter to provide an efficient conversion between the input sampling rate FSI and the output sampling rate FSO. Figure 1 A block diagram of a sample rate converter 1 with a sample rate estimator 2 and a sample rate filter 3, according to the prior art, is shown. The sample rate estimator 2 provides an estimate of the ratio R between the input sample rate FSI and the output sample rate FSO, where R = FSI / FSO. This estimated ratio R is passed to the sample rate filter 3, which resamples the input data signal DATA_IN at the output sample rate FSO and provides necessary anti-aliasing or anti-imaging filters. One of the main design considerations for the sample rate estimator 2 is lock-in time. This is the time it takes for the sample rate estimator 2 to provide an estimate of the sample rate ratio R within a defined error range. If the lock-in time is too long, the sample rate converter 1 takes too long to start up, which can affect the responsiveness of the audio / speech system containing the sample rate converter 1. High-performance sample rate converters (e.g., THD+N < 120 dB) require small estimation errors (within the same order of magnitude as the THD+N specification) but also low lock-in times, typically < 50 ms. Designing a sample rate converter with high performance and low lock-in time is very challenging.

[0004] “A Stereo Asynchronous Digital Sample-Rate Converter for DigitalAudio”, Robert Adams and Tom Kwan, IEEE Journal of Solid-state Circuits, Vol 29, No 4, April 1994, teaches a method for estimating the ratio R between the input sampling rate FSI and the output sampling rate FSO. Figure 2 This sampling rate converter 4 is illustrated, where a first integrator 5 is clocked at the input sampling rate FSI, and a second integrator 6 is clocked at the output sampling rate FSO. The loop tracks the difference between the slopes of the outputs of the first integrator 5 and the second integrator 6, and adjusts the slope of the second integrator 6 in the FSO domain to match. The input to the second integrator 6 is a ratio R = FSI / FSO. This ratio R is passed to... Figure 1 The sampling rate filter 3 performs the sampling rate conversion of the data signal DATA_IN to DATA_OUT.

[0005] In designing the rate estimator 2, there is a trade-off between locking speed and accuracy. For fast convergence, the time constant of the sampling rate filter 3 must be fast. For accuracy, the time constant must be slow. Typically, the time constant is adjusted so that the rate estimator 2 tracks quickly at startup and then improves accuracy over time. In the method disclosed in the aforementioned IEEE Journal, since the estimated sampling rate ratio R is at the output of coefficient K, adjusting coefficient K immediately adjusts the value of ratio R, resulting in glitch, after which the loop must re-stabilize.

[0006] Another prior art sampling rate converter disclosed in US7948405 addresses the glitches problem by biasing the first loop with the second loop to minimize glitches, but since the loop is first-order, the convergence time is slow, which is a real drawback of this sampling rate converter.

[0007] Another issue affecting lockout time that needs to be addressed is the effective management of data buffers, especially in the presence of clock jitter. Jitter is a transient variation in clock edges caused by timing errors in clock generation or transmission. Jitter causes the arrival time of input data to vary over time, and this variation needs to be absorbed. A common existing technique for absorbing jitter is to use a circular buffer, such as... Figure 3As shown in the diagram. Circular buffer 7 is controlled by two pointers: an input write pointer 8 and an output read pointer 9. Write pointer 8 points to the location in circular buffer 7 where DATA_IN is written, and read pointer 9 points to the location in circular buffer 7 where DATA_OUT is read. Once data is written or read, the corresponding pointers 8 and 9 move cyclically around circular buffer 7. To absorb jitter, read pointer 9 moves at a constant rate, while write pointer 8 moves back and forth relative to read pointer 9 in a timed manner. To avoid collisions between pointers 8 and 9 that could lead to data loss, a method must be used to control the bias between pointers 8 and 9. To maximize jitter tolerance, the average bias should be maintained at half the length of circular buffer 7. Circular buffer 7 is installed in a sample rate converter on the input sample rate FSI domain, as shown in the diagram. Figure 4 As shown in the diagram. The cyclic buffer 7 can also be installed between the input sampling rate FSI domain and the output sampling rate FSO domain within the sampling rate filter block.

[0008] based on Figure 2 The method for estimating the sampling rate ratio between the input sampling rate FSI and the output sampling rate FSO, as disclosed in the aforementioned IEEE Journal, is explained in which two integrators 5 and 6 are clocked using the input sampling rate FSI and the output sampling rate FSO. The loop tracks the error between the output slopes of integrators 5 and 6 and adjusts the slope of integrator 6 in the output sampling rate FSO domain to minimize this error. The input to integrator 6 is the ratio R = FSI / FSO, which is an estimate of the sampling rate ratio. The modulus (lower integer bits) of integrators 5 and 6 can be used to drive pointers 8 and 9 of the circular buffer 7, as they track each other and are based on... Figure 5 The increment of the defined quantity is followed by a newline (wrap). However, Figure 5 The architecture shown has two problems:

[0009] The first problem is that while the loop minimizes the frequency error between the two integrators 5 and 6, causing pointers 8 and 9 to increment at the same rate, the phase error is not minimized. Therefore, the bias between the two pointers 8 and 9 depends on the sampling rate. This is obvious because the output of the subtractor, i.e., the difference between the two integrators 5 and 6 driving the pointers, has a value R / K. Therefore, with the circular buffer 7 having a storage space of length 8, the difference between the read pointer 9 and the write pointer 8 is: Bias = R / K mod 8.

[0010] Figure 5 The second problem with the existing technical architecture is that, in order to reduce lock-up time, the time constant of the rate estimator 2 is typically set to enable fast initial tracking, and then gradually increase accuracy. Figure 5In the setup shown, this can be achieved by modifying the coefficient K. However, this results in noticeable glitches because the R value derived from the coefficient K changes as the coefficient K changes.

[0011] A known method for making pointers 8 and 9 track is to introduce another integrator in the loop. This loop then tracks the phase and frequency, which eliminates the bias between the slopes of integrators 5 and 6, thus ensuring that the bias between the two pointers 8 and 9 is also zero. The pointer bias amount, which is half the length of the buffer, can then be added. Examples of this idea using a second-order filter are disclosed in the prior art. Figure 6 An exemplary filter architecture 10 is shown in the figure.

[0012] However, this loop exhibits overshoot, which significantly increases settling and locking times. Each time the coefficient K is adjusted, the loop must re-stabilize, exacerbating the overshoot problem. Therefore, this existing technique is difficult to use in designs requiring rapid locking.

[0013] Another prior art method disclosed in US7948405 uses a second loop that biases the first loop to minimize the error between integrators. However, since this loop is first-order, a very low cutoff frequency must be used to achieve sufficient jitter attenuation. This requires a long time constant, which means a slow lock-in time. Summary of the Invention

[0014] The object of this invention is to provide a sampling rate converter circuit with a rate estimation circuit and a rate estimation method with low error and fast convergence. This object is achieved by the sampling rate converter circuit according to claim 1 and the method according to claim 9.

[0015] The present invention is based on dividing the rate estimator circuit into two parts. The first part is an instantaneous rate estimator circuit that generates a noisy estimate of the ratio R = FSI / FSO. The second part is an adjustable low-pass filter that filters out noise from the output signal of the instantaneous rate estimator circuit. The second part can be implemented using a low-pass filter with a conventional architecture, but in a way that allows for adjustment of the time constant without glitches.

[0016] A preferred embodiment of the present invention is a sampling rate converter circuit that converges quickly to low error, maintains a well-defined phase relationship between the input and output pointers, and has a good jitter attenuation level.

[0017] These and other aspects of the invention will become apparent and elucidated with reference to the embodiments described below. Those skilled in the art will understand that various embodiments can be combined. Attached Figure Description

[0018] Figure 1 A block diagram of a sampling rate converter circuit according to the prior art is shown. Figure 2 It is another sampling rate converter circuit based on the prior art, wherein the first integrator clocks the clock at the input sampling rate and the second integrator clocks the clock at the output sampling rate. Figure 3 A circular buffer according to the prior art is shown. Figure 4 A sample rate converter circuit with a cyclic buffer according to the prior art is shown. Figure 5 Showing according to the prior art Figure 4 The rate estimator circuit of the sampling rate converter circuit. Figure 6 The filter architecture based on the prior art is shown. Figure 7 A block diagram of a first embodiment of the rate estimator circuit according to the present invention is shown. Figure 8 Show Figure 7 Detailed block diagram of the instantaneous rate estimator circuit. Figure 9 Show Figure 7 A schematic diagram of the output value V of the integrator of the rate estimator circuit. Figure 10 Show Figure 7 A schematic diagram of the stepped output of the integrator in the rate estimator circuit. Figure 11 Show Figure 7 Detailed block diagram of the low-pass filter of the rate estimator circuit. Figure 12 Show Figure 7 Detailed block diagram of the time constant controller of the rate estimator circuit. Figure 13 A block diagram of another embodiment of the sampling rate converter circuit according to the present invention is shown. Figure 14 Show Figure 13 Detailed block diagram of the controlled low-pass filter of the sampling rate converter circuit. Figure 15 Show Figure 6 Simulation results of existing rate estimator circuits in China. Figure 16 Show Figure 7 The simulation results of the rate estimator circuit of the present invention. Detailed Implementation

[0019] Figure 7 A block diagram of a rate estimator circuit 11 according to the present invention is shown, the circuit being located as follows: Figure 1 The main setup of the sample rate converter circuit shown is as follows. This sample rate converter line is configured to receive a first signal DATA_IN at a first sampling frequency and is configured to output a second signal DATA_OUT, which represents the first signal DATA_IN and has a second sampling frequency.

[0020] Rate estimator circuit 11 is constructed to adjust Figure 1 The sampling rate filter 3 of the sampling rate converter circuit shown is further configured to receive a first clock signal with an input sampling rate FSI having the first sampling frequency and a second clock signal with an output sampling rate FSO having the second sampling frequency. The rate estimator circuit 11 is also configured to generate an estimate of the ratio R of the input sampling rate FSI to the output sampling rate FSO.

[0021] The rate estimator circuit 11 includes an instantaneous rate estimator circuit 12 configured to process the first clock signal and the second clock signal to provide an instantaneous, noisy estimate of the ratio R = FSI / FSO of the first sampling frequency to the second sampling frequency. The rate estimator circuit 11 also includes a low-pass filter 13 configured to filter the noise ratio R based on filter coefficients K required to adjust the time constant, which are provided by a time constant controller 14 in the rate estimator circuit 11. In this preferred embodiment of the invention, the addition of the time constant controller 14 to adjust the time constant accelerates convergence.

[0022] Figure 8 A detailed block diagram of the instantaneous rate estimator circuit 12 is shown. This uses an integrator 15 operating at the input sampling rate FSI, which adds an increment of 1 to the integrator output signal 19 with each clock pulse, and then uses a differentiator 16 operating at the output sampling rate FSO. Between the two domains, a dual buffer 17 is arranged to connect to the output pin of the integrator 15 and the input pin of the differentiator 16 to prevent clock problems across the asynchronous clock domain, as explained above with the circular buffer 7. The differentiator 16 is constructed to subtract the integrator output signal received at the input pin of the differentiator 16 and delayed by one clock pulse of the output sampling rate FSO for each clock pulse of the output sampling rate FSO from the actual integrator output signal 19 received at the input pin of the differentiator 16 to provide the output signal 20.

[0023] Figure 9The diagram shows the output value V of the integrator output signal 19 of integrator 15 as a function of time t. Integrator 15 is configured to produce a triangle with a height increment of 1 for each clock cycle of the input sampling rate FSI, T1 = 1 / FSI. Through a similar triangle, after time T2 = 1 / FSO, the height increment is T2 / T1. This increment is calculated by differentiator 16, which is clocked at the output sampling rate FSO. Therefore, the output signal 20 of instantaneous rate estimator circuit 12 is an estimate of R = T2 / T1 = FSI / FSO.

[0024] The integrator 15 and differentiator 16 of the instantaneous rate estimator circuit 12 are both implemented with integers. For example... Figure 10 As disclosed, integrator 15 increments by 1 for each clock pulse of the input sampling rate FSI, producing a stepped output of integrator 15, which is resampled at the input of differentiator 16 at the output sampling rate FSO. In this example, T2 = (2 / 3) × T1, meaning that 3 / 2 output samples are produced for each input sample. After differentiation by differentiator 16, the output signal 20 has a repetitive pattern {0,1,1,0,1,1,…} with an average value of 2 / 3 = FSI / FSO. Therefore, the output signal 20 of the instantaneous rate estimator circuit 12 oscillates between two values, corresponding to the long-term value R = FSI / FSO.

[0025] Low-pass filter 13 employs the noisy estimate of R=FSI / FSO and produces a clean estimate of R. There are many implementations of low-pass filters, but they are broadly classified into finite impulse response (FIR) filters and infinite impulse response (IIR) filters. In a preferred embodiment, an IIR filter is used because it offers the best trade-off between attenuation and implementation complexity, and can be easily parameterized to adjust the time constant. Figure 11 An exemplary low-pass filter 13 is shown. This is a cascade of two first-order filters 21 and 22. It was chosen because cascading provides better attenuation than first-order filters and can be easily adjusted with coefficient K. The feedback loop of the IIR filter helps to produce glitch-free coefficient adjustment. The average output of the first adder is zero (unlike R / K in the prior art), meaning that the loop does not need to re-stabilize when coefficient K changes. This means that fast convergence can be achieved using this sample rate converter circuit with fast tracking capability.

[0026] Figure 12 It was made public. Figure 7This is one embodiment of the time constant controller 14 of the rate estimator circuit 11 shown. To adjust the coefficient K, the time constant controller 14 uses a counter 23, which outputs a "hit" when a predetermined value is reached. This hit increments another counter 24, which indexes a lookup table 25 storing the values ​​of the coefficient K. The coefficient initially has a large value (e.g., 2). -3 This produces a fast time constant, allowing the loop to stabilize quickly. The value of the coefficient K is gradually decreased (e.g., 2). -7 2 -11 2 -15 This allows for a gradual reduction of the time constant and a more accurate estimate of the ratio R.

[0027] The output of low-pass filter 13 is an accurate estimate of the ratio R = FSI / FSO. It is passed to sampling rate filter 3, which, as is known in the art, adjusts its filtering characteristics and resamples the first signal DATA_IN at the FSO output rate to provide the second signal DATA_OUT.

[0028] Figure 13 A block diagram illustrating another embodiment of the invention is shown, wherein the sampling rate converter circuit 26 includes the aforementioned rate estimator circuit 11 and extends the cyclic buffer 27. As described above, the rate estimator circuit 11 generates an instantaneous but noisy estimate of R = FSI / FSO, which is then filtered by a low-pass filter 28 controlled by an adjustable time constant.

[0029] When the rate estimator circuit 11 is followed by a read pointer integrator 29 that generates the read pointer, as the controlled low-pass filter 28 stabilizes, an error E will be generated compared to the final value of R: E = R - F1out.

[0030] The error E is integrated by the read pointer integrator 29, resulting in a pointer bias that depends on the transient characteristics of the controlled low-pass filter 28.

[0031] The low-pass filter 13 of the rate estimator circuit 11 described above can be used Figure 13 and Figure 14 The controlled low-pass filter 28 with an error feedforward architecture shown in the diagram is used instead. This architecture eliminates pointer bias while minimizing overshoot, thus allowing for higher performance. Figure 6 The conventional low-pass filter 11 disclosed in the paper stabilizes faster.

[0032] Figure 14This embodiment of the controlled low-pass filter 28 is shown in more detail. The input to the controlled low-pass filter 28 is a noisy estimate of R from the instantaneous rate estimator 12. The first low-pass filter 30 produces a clean estimate of R, but has a transient error E at its output F1out, which affects the pointer bias.

[0033] To compensate for this transient error, an error E is derived, which is obtained by subtracting its input from the output of the first low-pass filter 30. This error is then filtered using a second low-pass filter 31 to reduce noise, and the output of the second low-pass filter 31 is subtracted from the output of the first low-pass filter 30 to eliminate the transient error of the first low-pass filter 30. Figure 5 Unlike other implementations, the pointers will track each other with a zero-phase bias.

[0034] The first low-pass filter 30 does not need to be phase accurate, so a simple low-overshoot filter can be used. A key characteristic of the first low-pass filter 30 is that it should be adjustable without introducing glitches.

[0035] The key feature of the second low-pass filter 31 is that any errors introduced by the second low-pass filter 31, such as quantization or coefficient adjustment, are tracked and taken into account by the feedback loop of the second low-pass filter 31.

[0036] Figure 13 The generation of read and write pointers for circular buffer 27 is also disclosed. These include two modular integrators that generate read and write pointers for the input buffer of circular buffer 27, which has a length of L bits. Write pointer integrator 32 increments by 1 per clock pulse of the input sampling rate FSI and performs a line feed when it reaches the value of length L. Read pointer integrator 29 increments by a value R per clock pulse of the output sampling rate FSO and performs a line feed when it reaches the value of L. The rate of change of the output of read pointer integrator 29 is R. Since R = FSI / FSO, the rate of change of the output of read pointer integrator 29 is equal to the clock pulse of the input sampling rate FSI.

[0037] This means that the input and output pointers will track each other. However, since the read pointer is driven by the output of the controlled low-pass filter 28, jitter is attenuated and absorbed by the circular buffer 27.

[0038] In another preferred embodiment of the controlled low-pass filter 28, the first low-pass filter 30 and the second low-pass filter 31 are replaced by a second-order low-pass filter to improve jitter attenuation.

[0039] Figure 15 Showing the use Figure 6 Simulation results of convergence 33 of the prior art rate estimator of the filter architecture 10. Figure 16 Showing the invention Figure 7 Simulation results show improved convergence 34 of the rate estimator 11 disclosed in the paper. The output signal of the rate estimator 11 converges to a lower error more quickly while maintaining the correct bias between the pointers.

[0040] Furthermore, the sampling rate converter circuit 26 described above is configured to perform the following method steps:

[0041] • Generate an estimate of the ratio R between the first sampling frequency and the second sampling frequency, which is used to adjust the sampling rate filter 3 of the sampling rate converter circuit 26;

[0042] • Process the first clock signal FSI corresponding to the first sampling frequency and the second clock signal FSO corresponding to the second sampling frequency to provide a noisy ratio R of the first sampling frequency to the second sampling frequency;

[0043] • Low-pass filtering is performed on the noisy ratio R of the first sampling frequency to the second sampling frequency based on the adjustable filter coefficients K to provide the estimated ratio R of the first sampling frequency to the second sampling frequency for adjusting the sampling rate filter 3.

Claims

1. A sampling rate converter circuit for receiving a first signal at a first sampling frequency and outputting a second signal having a second sampling frequency representing the first signal, the sampling rate converter comprising: A rate estimator circuit is included for adjusting the sampling rate filter of the sampling rate converter circuit. The rate estimator circuit is configured to receive a first clock signal having a first sampling frequency and a second clock signal having a second sampling frequency, and is configured to generate an estimate of the ratio of the first sampling frequency to the second sampling rate. The rate estimator circuit mentioned above includes: An instantaneous rate estimator circuit is configured to process the first clock signal and the second clock signal to provide a noisy ratio of the first sampling frequency to the second sampling frequency; and A low-pass filter is constructed to filter the noisy ratio of the first sampling frequency to the second sampling frequency based on filter coefficients that can be adjusted by a time constant controller of the rate estimator circuit.

2. The sampling rate converter circuit according to claim 1, wherein the instantaneous rate estimator circuit comprises: An integrator is configured to add an increment to each clock pulse of the first clock signal and to provide an integrator output signal at the output pin of the integrator; A differentiator is constructed to subtract from the actual integrator output signal received at the input pin of the differentiator the integrator output signal received at the input pin of the differentiator, which is delayed by one clock pulse of the second clock signal for each clock pulse of the second clock signal; and A dual buffer is arranged between the output pin of the integrator and the input pin of the differentiator to prevent clock problems between asynchronous clock domains.

3. The sampling rate converter circuit of claim 2, wherein the integrator is configured to increment by an integer 1.

4. The sampling rate converter circuit according to claim 1, wherein the low-pass filter is implemented as an infinite impulse response filter having two first-order filters cascaded together.

5. The sampling rate converter circuit of claim 1, wherein the time constant controller includes at least one counter and a lookup table, the lookup table being constructed to store counter values ​​of the at least one counter, and these counter values ​​being used for filter coefficients.

6. The sampling rate converter circuit of claim 5, wherein the time constant controller is configured to provide a decrease in the filter coefficients as the counter value increases, to generate a more accurate estimate of the ratio of the first sampling frequency to the second sampling frequency over time.

7. The sampling rate converter circuit of claim 1, wherein the low-pass filter is implemented by another error tracking low-pass filter with feedforward error control.

8. The sampling rate converter circuit of claim 7, wherein the buffer is configured to store data samples received from the first signal at a write pointer position in the buffer provided by the write pointer generation stage, and these data samples can be read from the buffer at a read pointer position in the buffer provided by the read pointer generation stage for generating the second signal.

9. A method for converting a first signal received at a first sampling frequency into a second signal having a second sampling frequency representing the first signal, wherein the following steps are performed by a sampling rate converter circuit: An estimate of the ratio of the first sampling frequency to the second sampling frequency is generated to adjust the sampling rate filter of the sampling rate converter circuit; Process a first clock signal corresponding to the first sampling frequency and a second clock signal corresponding to the second sampling frequency to provide a noisy ratio of the first sampling frequency to the second sampling frequency; and Low-pass filtering is performed on the noisy ratio of the first sampling frequency to the second sampling frequency based on adjustable filter coefficients to provide an estimate of the ratio of the first sampling frequency to the second sampling rate, which is used to adjust the sampling rate filter.

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