Automatic switching of working modes control circuit

Abstract

This disclosure provides a control circuit for automatically switching operating modes, including a current generation circuit, a first current difference circuit, a second current difference circuit, a valley control circuit, a PFM detection circuit, and an oscillator. The current generation circuit converts the control voltage into a first control current and generates a second control current of the same magnitude as the first control current through a first mirror. The first current difference circuit generates a fixed bias current. When the first control current is greater than the fixed bias current, the control circuit operates in a fixed-frequency PWM mode. The second current difference circuit generates a third control current of the same magnitude as the first control current through the first mirror. The valley control circuit adjusts the valley current when the lower transistor is turned on, and controls the frequency of the switching node to decrease by reducing the valley current. When the third control current is less than the fixed bias current, the overcurrent signal of the lower transistor is high, and the control circuit reduces the frequency by decreasing the valley current.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit technology, and specifically to a control circuit for automatically switching operating modes. Background Technology

[0002] Among the different modulation modes of BUCK DC-DC converters, Pulse Width Modulation (PWM) uses a fixed switching frequency to control the switch conduction and modulates the output voltage by changing the switch conduction time. PWM mode has high conversion efficiency under heavy load, but as the load decreases, if switching is performed in every cycle, the switching losses of the power switch will greatly reduce the conversion efficiency. Pulse Frequency Modulation (PFM), also known as frequency conversion modulation mode, modulates the duty cycle by changing the operating frequency of the switch. The switching frequency decreases as the load decreases, thereby improving the conversion efficiency under light load.

[0003] Currently, BUCK-type DC-DC converters often employ a dual operating mode of PWM+PFM to achieve high efficiency under full load. They operate in PWM mode when the load is high and switch to PFM mode when the load decreases to a lower value to improve efficiency. However, when a BUCK-type DC-DC converter is at the critical PFM level, it will switch back and forth between PFM and PWM operating modes, resulting in unstable output voltage and increased ripple. Summary of the Invention

[0004] The main objective of this disclosure is to provide a control circuit that automatically switches operating modes.

[0005] To achieve the above objectives, the first aspect of this disclosure provides a control circuit for automatically switching operating modes, applicable to BUCK type DC-DC converters, including a current generation circuit, a first current difference circuit, a second current difference circuit, a valley control circuit, a PFM detection circuit, and an oscillator.

[0006] The current generation circuit is configured to convert the control voltage into a first control current and generate a second control current of the same magnitude as the first control current through a first mirror.

[0007] The first current difference circuit is configured to generate a fixed bias current, obtain a first difference current based on the difference between the fixed bias current and the second control current, generate a difference voltage based on the first difference current, and convert the difference voltage into a second difference current. When the first control current is greater than the fixed bias current, the control circuit operates in a fixed frequency PWM mode.

[0008] The second current difference circuit is configured to generate a third difference current with the same magnitude as the second difference current through the second mirror, generate a third control current with the same magnitude as the first control current through the first mirror, generate a first difference current with the same magnitude as the third difference current through the third mirror, and obtain the second difference current through the third difference current and the first difference current.

[0009] The valley control circuit is configured to generate a third differential current with the same magnitude as the second differential current through the fourth mirror, and adjust the valley current through the third differential current when the lower tube is turned on. By reducing the valley current, the frequency of the control switching node is reduced, and the lower tube overcurrent signal is output to the oscillator. When the third control current is less than the fixed bias current, the lower tube overcurrent signal is high level, and the control circuit reduces the frequency by reducing the valley current.

[0010] The PFM detection circuit is configured to compare the magnitude of the control voltage and the PFM threshold voltage and output a PFM signal to the oscillator. When the control voltage is less than the PFM threshold voltage, the PFM signal is high and the control circuit operates in a down-frequency PFM mode.

[0011] The oscillator is configured to perform a logical OR operation on the lower transistor overcurrent signal and the PFM signal, and output a clock signal to the logic control circuit.

[0012] Optionally, the current generation circuit includes a first operational amplifier, a first transistor, a first resistor, the on-resistance of the upper sampling transistor, a second transistor, and a second resistor;

[0013] The non-inverting input of the first operational amplifier is coupled to the PFM detection circuit and connected to the control voltage. The inverting input is coupled to the second terminal of the first transistor and the first terminal of the first resistor, respectively. The output is coupled to the control terminal of the first transistor and the control terminal of the second transistor, respectively.

[0014] The first end of the on-resistance of the upper sampling transistor is connected to the input voltage, and the second end is coupled to the first pole of the first transistor and the first current difference circuit respectively. The on-resistance of the upper sampling transistor is configured to generate a set current according to the input voltage.

[0015] The first terminal of the second transistor is coupled to the first current difference circuit, and the second terminal is coupled to the first terminal of the second resistor;

[0016] The second terminal of the first resistor and the second terminal of the second resistor are respectively grounded;

[0017] The first operational amplifier, the first transistor, and the first resistor constitute a first voltage-to-current circuit, which is configured to convert the control voltage into a first control current flowing through the first transistor.

[0018] Furthermore, the first current difference circuit includes a current source, a third resistor, and a second voltage-to-current circuit, wherein the second voltage-to-current circuit includes a second operational amplifier, a third transistor, and a fourth resistor, and the second voltage-to-current circuit is configured to convert the difference voltage into a second difference current flowing through the third transistor.

[0019] The first end of the current source is connected to the power supply voltage, and the second end is coupled to the first pole of the second transistor, the non-inverting input terminal of the second operational amplifier and the first end of the third resistor respectively. The current source is configured to provide a fixed bias current. When the first control current is greater than the fixed bias current, the first differential current flowing to the first end of the third resistor is 0. The current is set to be equal to the first control current, and the control circuit operates in a fixed frequency PWM mode.

[0020] The second terminal of the third resistor is grounded, and the third resistor is configured to generate a differential voltage based on the first differential current;

[0021] The non-inverting input of the second operational amplifier is connected to a differential voltage, the inverting input is coupled to the second terminal of the third transistor and the first terminal of the fourth resistor, and the output is coupled to the control terminal of the third transistor and the second current difference circuit.

[0022] The first terminal of the third transistor is coupled to the second terminal of the on-resistance of the sampling transistor.

[0023] The second terminal of the fourth resistor is grounded.

[0024] Furthermore, the second current differential circuit includes a fourth transistor, a fifth resistor, a sixth resistor, a sixth transistor, a seventh transistor, and an eighth transistor;

[0025] The control electrode of the fourth transistor is coupled to the control electrode of the third transistor and the output terminal of the second operational amplifier, the first electrode is coupled to the control electrode of the sixth transistor, the first electrode of the sixth transistor and the control electrode of the seventh transistor, and the second electrode is coupled to the first terminal of the fifth resistor. The fourth transistor is configured to generate a third differential current with the same magnitude as the second differential current through the second mirror. The third transistor and the fourth transistor constitute the second current mirror circuit.

[0026] The control electrode of the fifth transistor is coupled to the control electrode of the second transistor, the control electrode of the first transistor, and the output terminal of the first operational amplifier. The first electrode is coupled to the first electrode of the seventh transistor, the control electrode of the eighth transistor, and the first electrode of the eighth transistor. The second electrode is coupled to the first terminal of the sixth resistor. The fifth transistor is configured to generate a third control current with the same magnitude as the first control current through the first mirror. The first transistor, the second transistor, and the fifth transistor constitute the first current mirror circuit.

[0027] The second terminal of the sixth transistor is coupled to the second terminals of the seventh transistor, the second terminal of the eighth transistor, and the valley control circuit, and is connected to the power supply voltage.

[0028] The seventh transistor is configured to generate a first differential current with the same magnitude as the third differential current through the third mirror; the sixth and seventh transistors constitute the third current mirror circuit.

[0029] The control electrode and the second electrode of the eighth transistor are both coupled to the valley control circuit. The eighth transistor is configured to generate a second differential current when the third control current is less than the fixed bias current.

[0030] Furthermore, the valley control circuit includes a ninth transistor, a lower sampling transistor, a lower transistor, and a comparator;

[0031] The control electrode of the ninth transistor is coupled to the control electrode of the eighth transistor and the first electrode of the eighth transistor. The first electrode is coupled to the second electrode of the lower sampling transistor and the non-inverting input of the comparator. The second electrode is coupled to the second electrode of the eighth transistor, the second electrode of the seventh transistor and the second electrode of the sixth transistor. The ninth transistor is configured to generate a third differential current with the same magnitude as the second differential current through the fourth mirror. The eighth transistor and the ninth transistor constitute the fourth current mirror circuit.

[0032] The control electrode of the lower sampling tube is coupled to the control electrode of the lower tube and connected to the lower tube drive signal. The first electrode of the lower sampling tube is coupled to the first electrode of the lower tube through a switching node, and the second electrode of the lower tube is grounded.

[0033] The inverting input of the comparator is grounded, and the output terminal outputs the lower tube overcurrent signal to the oscillator.

[0034] Furthermore, in the valley control circuit, the valley current is detected by detecting the voltage of the switching node. When the valley current drops to a preset value, the overcurrent signal of the lower tube output to the oscillator is high level.

[0035] Furthermore, when the third control current is less than the fixed bias current, the valley control circuit controls the switching frequency to decrease by reducing the valley current, and the control circuit operates in the valley frequency reduction mode.

[0036] Optionally, the PFM detection circuit includes a hysteresis comparator;

[0037] The non-inverting input of the hysteresis comparator is connected to the PFM threshold voltage, and the inverting input is coupled to the non-inverting input of the first operational amplifier and connected to the control voltage. The hysteresis comparator is configured to compare the magnitude of the control voltage and the PFM threshold voltage and output a PFM signal to the oscillator. When the control voltage changes from large to small, the PFM threshold voltage is the falling PFM threshold voltage, and when the control voltage changes from small to large, the PFM threshold voltage is the rising PFM threshold voltage.

[0038] The second aspect of this disclosure provides a BUCK-type DC-DC converter, including the control circuitry for automatically switching operating modes provided in the first aspect.

[0039] A third aspect of this disclosure provides a chip characterized in that it includes the BUCK-type DC-DC converter provided in the second aspect.

[0040] A fourth aspect of this disclosure provides an electronic device including the chip provided in the third aspect. Attached Figure Description

[0041] To more clearly illustrate the technical solutions in the specific embodiments or related technologies of this disclosure, the accompanying drawings used in the description of the specific embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0042] Figure 1 A typical circuit diagram for a BUCK-type DC-DC converter with PWM+PFM dual operating modes;

[0043] Figure 2 A diagram illustrating the switching process for an ideal dual-working mode;

[0044] Figure 3 Waveforms of key signals during the ideal dual-mode switching process;

[0045] Figure 4 This is a diagram illustrating the actual switching process between dual working modes in related technologies.

[0046] Figure 5 A schematic diagram of a control circuit for automatically switching operating modes provided in an embodiment of this disclosure;

[0047] Figure 6 Key signal diagrams during the switching process of the three operating modes provided in the embodiments of this disclosure;

[0048] Figure 7 Waveform diagram of key signals after entering peak current control, provided in an embodiment of this disclosure;

[0049] Figure 8 The waveform diagram of the key signal during the valley down-frequency reduction process provided in the embodiments of this disclosure. Detailed Implementation

[0050] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are also within the scope of protection of this disclosure.

[0051] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this subject matter pertains. It will be further understood that terms such as those defined in commonly used dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the specification and in the relevant art, and shall not be interpreted in an idealized or overly formal form unless otherwise explicitly defined herein. As used herein, the statement of “connecting” or “coupling” two or more parts together shall mean that these parts are directly joined together or joined through one or more intermediate components.

[0052] In all embodiments of this disclosure, since the source and drain of a metal-oxide-semiconductor (MOS) transistor are symmetrical, and the conduction current directions between the source and drain of an N-type transistor and a P-type transistor are opposite, the gate of the MOS transistor is referred to as the control electrode, and the remaining two terminals of the MOS transistor are referred to as the first electrode and the second electrode, respectively. The transistors used in the embodiments of this disclosure are primarily switching transistors. Furthermore, for the sake of consistency, in this context, the base of a bipolar junction transistor (BJT) is referred to as the control electrode, the emitter of the BJT as the first electrode, and the collector of the BJT as the second electrode. Additionally, terms such as "first" and "second" are used only to distinguish one component (or part of a component) from another component (or another part of a component).

[0053] For BUCK DC-DC converters, different modulation modes can be used, such as pulse width modulation (PWM) and frequency conversion modulation (PFM).

[0054] Pulse Width Modulation (PWM) uses a constant switching frequency fs to control the conduction of the switch and modulates the output voltage by changing the on-time Ton, or duty cycle D. It has high conversion efficiency under heavy load, but as the load decreases, if switching continues every cycle, the switching losses of the power switch will greatly reduce the system's conversion efficiency.

[0055] Light-load frequency conversion modulation (PFM) modulates the duty cycle by changing the operating frequency of the switch. The frequency of the switch decreases as the load decreases, thereby improving the conversion efficiency under light load.

[0056] Most switching power supplies currently use a dual operating mode of PWM+PFM to achieve high efficiency under full load. When the load is large, it operates in PWM mode, and when the load decreases to a smaller value, the chip automatically switches to PFM mode to improve efficiency.

[0057] like Figure 1 The diagram shown is a typical circuit diagram of a PWM+PFM dual-mode BUCK DC-DC converter, including the error amplifier OTA, the comp clamping circuit, and the resistor R. C Capacitor C C The circuit consists of a PFM detection circuit (PFM_DET), an operational amplifier (AMP), a first N-type transistor (NM1), a resistor (R), and a current source (I). bpeak Current clamping circuit, second N-type transistor NM2, third N-type transistor NM3, first P-type transistor PM1, second P-type transistor PM2, on-resistance Rsense of upper sampling transistor, PWM comparator PWMCOMP, oscillator, logic control circuit, upper transistor driver HSDRV, lower transistor driver LSDRV, upper transistor HS, lower transistor LS, inductor L, output resistor R OUT Output capacitor C OUT First feedback resistor R F1 Second feedback resistor R F2 Load R L Where Rdson is the on-resistance of the upper transistor, Ksense is the scaling factor between the upper transistor and the upper transistor sampling transistor, and V PEAK VDD is the peak voltage, VIN is the power supply voltage, and V is the input voltage. SW It is the switching node voltage, V FB It is the feedback voltage, V REF It is the reference voltage, V comp It is the control voltage, I comp1 It is the first control current, I comp2 It is the second control current, I set It sets the current.

[0058] Figure 1 The basic principle can be summarized as follows: the error amplifier OTA detects the feedback voltage V. FB The size generates a comp control voltage V comp The comp control voltage V is controlled by a V2I circuit. comp Converted to the first control current I comp1Furthermore, the setting current I is generated through mirroring. set Adjust the peak current I peak The magnitude controls the on-time of the upper transistor. The oscillator (OSC module) generates the clock signal, controlling the off-time of the lower transistor and the on-time of the upper transistor. The functions of the other modules are described below.

[0059] The PFM_DET module (i.e., the PFM detection circuit) is used to detect the comp control voltage V. comp This allows for switching of the operating mode when the control voltage V... comp Less than the drop threshold voltage V PFM_f When V is in PFM mode, the PFM signal controls the clock signal CLK output by the OSC module, thereby achieving frequency modulation; when V comp Voltage higher than the rise threshold voltage V PFM_r When the time is right, exit PFM mode and enter fixed-frequency PWM mode.

[0060] The current clamping circuit is used to set the current I set The size is used for low-clamping, limiting the minimum peak current to I. peak_min Size, to achieve a fixed peak current I under light load. peak Work. When I comp bpeak V comp bpeak When R, set the current I set It will be clamped at N I bpeak Thus controlling the minimum peak current I peak_min The size; where N represents the size ratio of transistors NM2 and NM3 in the current mirror circuit. To achieve more stable light-load operation, I bpeak R must be greater than the threshold voltage V of the PFM detection circuit. PFM Large, when the control voltage V comp When the threshold voltage V decreases, PFM For the falling threshold voltage V PFM_f When the control voltage V comp When rising, the threshold voltage V PFM Rising threshold voltage V PFM_r .

[0061] The comp clamping circuit ensures that the output voltage of the error amplifier OTA is within the normal range, allowing the OTA to operate correctly. Additionally, high clamping also limits peak current for overcurrent protection, while low clamping voltage is typically higher than the threshold voltage V. PFM Smaller. ​​

[0062] Figure 2 This diagram illustrates the switching process of an ideal dual-mode PWM+PFM BUCK converter. As the load decreases, the operating mode switches from PWM to PFM, where Iload represents the load current. In a BUCK-type DC-DC converter, the load current gradually decreases. peak_min Inductor current I L The minimum peak current; Figure 3 This is a schematic diagram illustrating the switching of key signals according to the operating mode in an ideal dual-mode operation. The load (Load) decreases from large to small, and the control voltage (V)... comp From the highest control voltage V comp_high The voltage is gradually reduced to a fixed bias voltage V. bpeak PFM threshold voltage V PFM Minimum control voltage V comp_low Set the current I set Reduce to minimum set current I set_min When the operating mode is switched from PWM to PFM, the switching frequency Fsw gradually decreases from a fixed value in PWM mode to a value that is gradually reduced in PFM mode.

[0063] Figure 4 This diagram illustrates the actual dual-mode switching process of a BUCK-type DC-DC converter in related technologies. Under heavy load, the chip operates under fixed-frequency PWM control, with the peak current controlled by the comp control voltage V. comp1 As shown in Figure T1, the load current is Iload1.

[0064] As the load decreases, the comp control voltage V comp Reduced to exactly equal to the internal fixed bias voltage V bpeak At that time, the chip enters a fixed peak current I. peak Control, at this time the chip is just in a stable state, as shown in stage T2, the load current is Iload2;

[0065] As the load continues to decrease, the comp control voltage V comp Initially less than the internal fixed bias voltage V bpeak The chip uses a fixed peak current I peak After operating at a fixed frequency for several cycles, the comp control voltage V comp Reduce to the drop threshold voltage V PFM_f The chip will only enter light-load PFM operation when the comp control voltage V is reached; therefore, when the comp control voltage V is reached... comp Internal fixed bias voltage V bpeak and the drop threshold voltage V PFM_f At the intermediate voltage, the chip has no loop control and is controlled only by a fixed period and a fixed peak current I. peakDuring control, the chip switches back and forth between PFM and PWM modes, as shown in stage T3, with a load current of Iload3. The chip fully enters PFM mode as the load continues to decrease, at which point it can operate stably, i.e., stage T4, with a load current of Iload4.

[0066] Since the chip in stage T3 lacks loop control, it only has a fixed period and a fixed peak current I. peak This control mechanism causes the chip to switch back and forth between PFM and PWM operating modes when it is operating at the critical PFM level, resulting in an output voltage V... OUT It is unstable and the output voltage ripple increases significantly, especially at higher switching frequencies, which can cause more serious problems.

[0067] To address the aforementioned problems, this disclosure provides a control circuit for automatically switching operating modes, applicable to BUCK-type DC-DC converters. The circuit diagram is shown below. Figure 5 As shown, it includes a current generation circuit, a first current difference circuit, a second current difference circuit, a valley control circuit, a PFM detection circuit, and an oscillator.

[0068] The current generation circuit is configured to control voltage V comp Converted to the first control current I comp1 The first mirror image generates the first control current I. comp1 Second control current I of the same size comp2 ;

[0069] The first current differential circuit is configured to generate a fixed bias current I. bpeak According to the fixed bias current I bpeak Second control current I comp2 The difference value is used to obtain the first difference current I. X1 Based on the first differential current I X1 Generate differential voltage V X1 and the difference voltage V X1 Converted to second differential current I X2 Wherein, when the first control current I comp1 Greater than the fixed bias current I bpeak At this time, the control circuit operates in a fixed-frequency PWM mode;

[0070] The second current difference circuit is configured to generate a second difference current I through the second mirror. X2 The third differential current I of the same magnitude X3 The first mirror image generates the first control current I. comp1 The same third control current I comp3 The third differential current I is generated through the third mirror image.X3 First differential current I of the same magnitude P1 And through the third differential current I X3 Find the difference current I in the first step. P1 The second differential current I is obtained P2 ;

[0071] The valley control circuit is configured to generate a differential current I with the second mirror via the fourth mirror. P2 Find the third differential current I of the same magnitude P3 And when the lower power FET is turned on, it uses the third differential current I P3 Adjusting the valley current I valley By reducing the valley current I valley The frequency of the control switch node SW is reduced, and an overcurrent signal for the lower power FET is output to the oscillator oscillator. This occurs when the third control current I... comp3 Less than the fixed bias current I bpeak At this time, the overcurrent signal of the lower power FET is high, and the control circuit reduces the valley current I. valley To reduce the frequency;

[0072] The PFM detection circuit is configured to compare the control voltage V. comp The PFM signal is output to the oscillator based on the magnitude of the PFM threshold voltage, where the control voltage V... comp When the voltage is less than the PFM threshold voltage, the PFM signal is high and the control circuit operates in the reduced-frequency PFM mode.

[0073] The oscillator is configured to perform a logical OR operation on the lower transistor overcurrent signal LSOC and the PFM signal, and output a clock signal CLK to the logic control circuit.

[0074] The automatic switching control circuit provided in this embodiment enables the chip to achieve stable automatic switching between three operating modes, solving the problems of unstable output voltage and increased output voltage ripple in related technologies with dual operating modes. When the load decreases to the point where a fixed peak current I is reached... peak When the chip is under control but not in PFM mode, it will automatically switch to valley frequency reduction. During this stage, the inductor current and output voltage are adjusted by valley current control until the load decreases and the valley current drops to 0, which is when the intermittent conduction mode (DCM) is reached, and then the chip is allowed to enter PFM mode. Through the valley control circuit, the chip can automatically switch from heavy load PWM mode to valley frequency reduction mode and then smoothly switch to light load PFM mode.

[0075] Figure 5In the circuit, the current generation circuit includes a first operational amplifier AMP1, a first transistor M1, a first resistor R1, the on-resistance Rsense of the upper sampling transistor, a second transistor M2, and a second resistor R2; the first transistor M1 and the second transistor M2 can be N-type MOS transistors, and the resistance value of the first resistor R1 and the second resistor R2 can be equal.

[0076] The non-inverting input of the first operational amplifier AMP1 is coupled to the PFM detection circuit and connected to the control voltage V. comp The inverting input terminal is coupled to the second terminal of the first transistor M1 and the first terminal of the first resistor R1, respectively, and the output terminal is coupled to the control terminal of the first transistor M1 and the control terminal of the second transistor M2, respectively.

[0077] The first terminal of the on-resistance Rsense of the upper sampling transistor is connected to the input voltage, and the second terminal is coupled to the first terminal of the first transistor M1 and the first current difference circuit, respectively. The on-resistance Rsense of the upper sampling transistor is configured to generate a setting current I based on the input voltage. set ;

[0078] The first terminal of the second transistor M2 is coupled to the first current difference circuit, and the second terminal is coupled to the first terminal of the second resistor R2.

[0079] The second terminal of the first resistor R1 and the second terminal of the second resistor R2 are respectively grounded;

[0080] The first operational amplifier AMP1, the first transistor M1, and the first resistor R1 constitute a first voltage-to-current circuit, which is configured to convert the control voltage V... comp Converted into the first control current I flowing through the first transistor M1 comp1 The first voltage-to-current circuit is the first V2I circuit.

[0081] Figure 5 In the first current difference circuit, there is a current source, a third resistor R3, and a second voltage-to-current conversion circuit. The second voltage-to-current conversion circuit includes a second operational amplifier AMP2, a third transistor M3, and a fourth resistor R4. The second voltage-to-current conversion circuit is configured to convert the difference voltage V... X1 Converted into a second differential current I flowing through the third transistor M3 X2 The second voltage-to-current circuit is the second V2I circuit. The third transistor M3 can be an N-type MOS transistor. The resistance value of the third resistor R3 and the fourth resistor R4 can be equal.

[0082] The first terminal of the current source is connected to the power supply voltage, and the second terminal is coupled to the first terminal of the second transistor M2, the non-inverting input terminal of the second operational amplifier AMP2, and the first terminal of the third resistor R3. The current source is configured to provide a fixed bias current I. bpeak Wherein, when the first control current I comp1 Greater than the fixed bias current I bpeak At that time, the first differential current I flowing to the first terminal of the third resistor R3 X1 Set the current I to 0. set Equal to the first control current I comp1 The control circuit operates in a fixed-frequency PWM mode;

[0083] The second terminal of the third resistor R3 is grounded, and the third resistor R3 is configured based on the first differential current I. X1 Generate differential voltage V X1 ;

[0084] The differential voltage V is connected to the non-inverting input of the second operational amplifier AMP2. X1 The inverting input terminal is coupled to the second terminal of the third transistor M3 and the first terminal of the fourth resistor R4, respectively, and the output terminal is coupled to the control terminal of the third transistor M3 and the second current difference circuit, respectively.

[0085] The first terminal of the third transistor M3 is coupled to the second terminal of the on-resistance Rsense of the sampling transistor.

[0086] The second terminal of the fourth resistor R4 is grounded.

[0087] Figure 5 In the second current difference circuit, there are a fourth transistor M4, a fifth resistor R5, a sixth resistor R6, a seventh transistor M7, and an eighth transistor M8; the fourth transistor M4 and the fifth transistor M5 can be N-type MOSFETs, the sixth transistor M6, the seventh transistor M7, and the eighth transistor M8 can be P-type MOSFETs, and the resistance value of the fifth resistor R5 and the sixth resistor R6 can be equal.

[0088] The control terminal of the fourth transistor M4 is coupled to the control terminal of the third transistor M3 and the output terminal of the second operational amplifier AMP2. Its first terminal is coupled to the control terminal of the sixth transistor M6, the first terminal of the sixth transistor M6, and the control terminal of the seventh transistor M7. Its second terminal is coupled to the first terminal of the fifth resistor R5. The fourth transistor M4 is configured to generate a second differential current I through the second mirror. X2 The third differential current I of the same magnitude X3 The third transistor M3 and the fourth transistor M4 constitute the second current mirror circuit; the mirror ratio of the second current mirror circuit can be 1:1.

[0089] The control terminal of the fifth transistor M5 is coupled to the control terminals of the second transistor M2, the first transistor M1, and the output terminal of the first operational amplifier AMP1. Its first terminal is coupled to the first terminal of the seventh transistor M7, the control terminal of the eighth transistor M8, and the first terminal of the eighth transistor M8. Its second terminal is coupled to the first terminal of the sixth resistor R6. The fifth transistor M5 is configured to generate a first control current I through the first mirror. comp1 The same third control current I comp3 The first transistor M1, the second transistor M2, and the fifth transistor M5 constitute the first current mirror circuit; the mirror ratio of the first current mirror circuit can be 1:1:1.

[0090] The second terminal of the sixth transistor M6 is coupled to the second terminals of the seventh transistor M7, the eighth transistor M8, and the valley control circuit, respectively, and connected to the power supply voltage.

[0091] The seventh transistor M7 is configured to generate a third differential current I via the third mirror. X3 First differential current I of the same magnitude P1 The sixth transistor M6 and the seventh transistor M7 constitute the third current mirror circuit; the mirror ratio of the third current mirror circuit can be 1:1.

[0092] The control electrode and the second electrode of the eighth transistor M8 are both coupled to the valley control circuit. The eighth transistor M8 is configured to respond to the third control current I. comp3 Less than the fixed bias current I bpeak At that time, the second differential current I is generated. P2 .

[0093] Figure 5 In the middle, the valley control circuit includes the ninth transistor M9, the lower sampling transistor Sense FET, the lower power FET, and a comparator; the ninth transistor M9 can be a P-type MOSFET;

[0094] The control electrode of the ninth transistor M9 is coupled to the control electrode and the first electrode of the eighth transistor M8, respectively. The first electrode is coupled to the second electrode of the lower sampling transistor Sense FET and the non-inverting input of the comparator, respectively. The second electrode is coupled to the second electrode of the eighth transistor M8, the second electrode of the seventh transistor M7, and the second electrode of the sixth transistor M6, respectively. The ninth transistor M9 is configured to generate a third differential current IP3 with the same magnitude as the second differential current IP2 through the fourth mirror. The eighth transistor M8 and the ninth transistor M9 constitute the fourth current mirror circuit. The mirror ratio of the fourth current mirror circuit can be 1:1.

[0095] The control terminal of the lower sampling transistor Sense FET is coupled to the control terminal of the lower power FET and is connected to the lower drive signal. The first terminal of the lower sampling transistor Sense FET is coupled to the first terminal of the lower power FET via the switching node SW, and the second terminal of the lower power FET is grounded.

[0096] The inverting input of the comparator is grounded, and the output terminal outputs the lower tube overcurrent signal LSOC to the oscillator.

[0097] This disclosure provides an optional implementation where, in the valley control circuit, the valley current I is controlled by detecting the voltage at the switching node SW. valley When the valley current I is detected, the detection is performed. valley When the current drops to the preset value, the lower tube overcurrent signal LSOC output to the oscillator Oscillator is at a high level.

[0098] In one optional embodiment of this disclosure, when the third control current I... comp3 Less than the fixed bias current I bpeak At that time, the valley control circuit reduces the valley current I. valley The control switching frequency is reduced, and the control circuit operates in valley frequency reduction mode.

[0099] Figure 5 In this circuit, the PFM detection circuit includes a hysteresis comparator;

[0100] The non-inverting input of the hysteresis comparator is connected to the PFM threshold voltage, and the inverting input is coupled to the non-inverting input of the first operational amplifier AMP1, and connected to the control voltage V. comp The hysteresis comparator is configured to compare the control voltage V. comp The PFM signal is output to the oscillator based on the magnitude of the PFM threshold voltage, where the control voltage V... comp When the PFM threshold voltage changes from large to small, it is the decreasing PFM threshold voltage, when the control voltage V comp When the voltage changes from small to large, the PFM threshold voltage is the rising PFM threshold voltage.

[0101] This embodiment of the invention adds valley control to the light load operation based on the control method in the related art, which can effectively solve the problem of unstable operation under critical PFM load and achieve a smoother transition to light load PFM operation.

[0102] Figure 6 The key signal diagram during the switching process of the three operating modes provided in this embodiment shows that as the load gradually decreases, from heavy load to light load, the control voltage V... comp From the highest control voltage V comp_high Reduce to the lowest control voltage Vcomp_low When the control voltage V comp Reduced to a fixed bias voltage V bpeak When, set the current I set Reduce to minimum set current I set_min The frequency is initially reduced by decreasing the valley current, automatically switching from a fixed-frequency PWM to a valley-based frequency reduction. When the control voltage V... comp Reduced to PFM threshold voltage V PFM At that time, the frequency reduction smoothly transitions from the valley value to PFM frequency reduction; Figure 7 This is a waveform diagram of the key signal after entering peak current control according to an embodiment of this disclosure, including the inductor current I. L The peak value is fixed at the minimum peak current I. peak_min By reducing the inductor current I L The frequency reduction is controlled by the valley value. When the valley current decreases to 0, the frequency reduction enters PFM when the clock signal CLK is high. Figure 8 The waveform diagram of the key signal during the valley frequency reduction process provided in the embodiments of this disclosure, with the first control current I comp1 The decrease in valley current I valley Gradually decrease to 0.

[0103] The following is combined Figures 5 to 8 The specific circuit principle of the control circuit for automatically switching working modes provided in the embodiments of this disclosure is described.

[0104] Figure 5 In the circuit, the resistance values ​​of resistors one through six are equal, R1=R2=R3=R4=R5=R6. Transistors M1 through M5 have the same size and width-to-length ratio (W / L). Transistor M6 and transistors M7 are mirror images of each other in a 1:1 ratio. Transistors M8 and M9 are mirror images of each other in a 1:1 ratio. The working principle of each circuit module in the control circuit is as follows:

[0105] (1) The first control current I in the current generation circuit comp1 :

[0106] Control voltage V comp The first V2I circuit converts it into the first control current I. comp1 First control current I comp1 Then, by mirroring M1, M2, and M5 in a 1:1:1 ratio, a second control current I of the same magnitude is generated. comp2 Third control current I comp3 ;

[0107] (2) First current difference circuit:

[0108] First control current Icomp1 and fixed bias current I bpeak Difference circuit: First, only when I comp1 bpeak At that time, the first control current I comp1 and fixed bias current I bpeak Generate current difference I X1 First differential current I X1 =I bpeak -I comp1 Otherwise I X1 =0; then I X1 Voltage V is generated when the resistor flows through it. X1 After passing through the second V2I circuit, it is converted back into the second differential current I. X2 Output, since R3=R4, therefore I X2 =I X1 Second differential current I X2 Then, a third differential current I of the same magnitude is generated by mirroring M3 and M4 at a 1:1 ratio. X3 The third differential current I X3 The first differential current I is then generated by mirroring M6 and M7 at a 1:1 ratio. P1 ;

[0109] (3) Setting current I in the current generation circuit set :

[0110] I set =I comp1 +I X1 ; when I comp1 bpeak At that time, I set = I comp1 +I bpeak -I comp1 =I bpeak I bpeak It is an internal fixed bias current; when I comp1 >I bpeak At that time, I set = I comp1 The first control current I comp1 The peak current is determined by the first control current I. comp1 Confirmed, currently operating in PWM mode;

[0111] (4) Second current difference circuit:

[0112] Only when I comp3 bpeak At that time, the first differential current I is calculated. P1 With the third control current I comp3 The second step is to calculate the difference current I by generating the current difference. P2 =2​​​ I comp3 -I bpeak Then, after being mirrored by PM3 and PM4 at a 1:1 ratio, a third differential current I of the same magnitude is output. P3 =I P2 =2 I comp3 -I bpeak ;

[0113] (5) Basic principle of valley value control circuit:

[0114] When the lower power FET is turned on, the switching node voltage V SW =-I L Ron is the on-resistance of the lower transistor, therefore, by detecting the switching node voltage V... SW It can achieve valley current I valley The detection, when the inductor current I is detected L The cycle is only allowed to begin when the current drops to the set value. Valley current I valley The calculation is as follows:

[0115] When the current sampling transistor Sense FET source voltage V SW_LSON =V SW +(2 I comp3 -I bpeak ) When Rsns=0, the comparator output of the lower transistor overcurrent signal LSOC flips to a high level, and the control output clock signal CLK is high. Here, Rsns is the on-resistance of the lower transistor sampling transistor Sense FET, and Rsns / Ron=K, where K is the scaling factor between the lower transistor Power FET and the lower transistor sampling transistor Sense FET.

[0116] When the inductor current I L =I valley =(2 I comp3 -I bpeak ) At time K, i.e., the valley current I valley Decrease to (2) I comp3 -I bpeak ) When K is reached, the output clock signal CLK enters the next cycle.

[0117] The following is an overall principle analysis of the control circuit:

[0118] When V comp >V bpeak At that time, I comp1 >Ibpeak Therefore I X1 =0, which is I set =I comp1 The peak current is controlled by the voltage V. comp The chip operates in a normal fixed-frequency PWM mode, where the fixed bias voltage V... bpeak =I bpeak R3;

[0119] When V comp <V bpeak At that time, I comp1 bpeak At this time, the differential current I X1 =I bpeak -I comp1 Then, the valley current I is reduced through the second current difference circuit and the valley control circuit. valley This achieves the frequency reduction function.

[0120] Until the control voltage V comp Reduced to PFM threshold voltage V PFM Time (V) PFM ≤0.5 V bpeak At this point, it enters the intermittent conduction mode, and at the same time, it can also enter the PFM frequency reduction mode.

[0121] This disclosure also provides a BUCK-type DC-DC converter, including the aforementioned control circuit for automatically switching operating modes. The BUCK-type DC-DC converter further includes an error amplifier, a comp clamping circuit, resistors, capacitors, a logic control circuit, an upper-side driver, a lower-side driver, an upper-side MOSFET, and an inductor.

[0122] This disclosure also provides a chip including the above-described BUCK-type DC-DC converter.

[0123] This disclosure also provides an electronic device including the aforementioned chip.

[0124] As can be seen from the above description, this disclosure achieves the following technical effects:

[0125] The control circuit for automatic switching of operating modes provided in this disclosure incorporates valley current control as a transitional operating mode when switching between PWM and PFM before entering light-load PFM operation, so as to achieve smooth switching of operating modes. This enables the chip to achieve stable automatic switching between three operating modes, solving the problems of unstable output voltage and increased output voltage ripple in dual operating modes in related technologies.

[0126] ​The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of apparatuses and methods according to various embodiments of the present disclosure. In this regard, each block in a flowchart or block diagram may represent a portion of a circuit, program segment, or instruction, which includes one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0127] Unless otherwise expressly indicated by the context, the singular form of words used herein and in the appended claims includes the plural form, and vice versa. Thus, when referring to the singular, the plural form of the corresponding term is generally included. Similarly, the terms “comprising” and “including” shall be interpreted as including rather than exclusive. Likewise, the terms “including” and “or” shall be interpreted as including unless such interpretation is expressly prohibited herein. Where the term “example” is used herein, particularly when it follows a set of terms, “example” is merely exemplary and illustrative and should not be considered exclusive or extensive.

[0128] Further aspects and scope will become apparent from the description provided herein. It should be understood that various aspects of this disclosure may be implemented individually or in combination with one or more other aspects. It should also be understood that the descriptions and specific embodiments herein are intended for illustrative purposes only and are not intended to limit the scope of this disclosure.

[0129] Although embodiments of the present disclosure have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the present disclosure, and such modifications and variations all fall within the scope defined by the appended claims.

Claims

1. A control circuit for automatically switching between operating modes, characterized in that Suitable for BUCK type DC-DC converters, including current generation circuit, first current difference circuit, second current difference circuit, valley control circuit, PFM detection circuit and oscillator; The current generation circuit is configured to convert the control voltage into a first control current and generate a second control current of the same magnitude as the first control current through a first mirror. The first current difference circuit is configured to generate a fixed bias current, obtain a first difference current based on the difference between the fixed bias current and the second control current, generate a difference voltage based on the first difference current, and convert the difference voltage into a second difference current. When the first control current is greater than the fixed bias current, the control circuit operates in a fixed frequency PWM mode. The second current difference circuit is configured to generate a third difference current with the same magnitude as the second difference current through a second mirror, generate a third control current with the same magnitude as the first control current through a first mirror, generate a first difference current with the same magnitude as the third difference current through a third mirror, and obtain a second difference current through the third difference current and the first difference current. The valley control circuit is configured to generate a third differential current with the same magnitude as the second differential current through a fourth mirror, and adjust the valley current through the third differential current when the lower transistor is turned on. The frequency of the control switching node is reduced by decreasing the valley current, and a lower transistor overcurrent signal is output to the oscillator. When the third control current is less than the fixed bias current, the lower transistor overcurrent signal is high level, and the control circuit reduces the frequency by decreasing the valley current. The PFM detection circuit is configured to compare the magnitude of the control voltage and the PFM threshold voltage and output a PFM signal to the oscillator. When the control voltage is less than the PFM threshold voltage, the PFM signal is high and the control circuit operates in a reduced-frequency PFM mode. The oscillator is configured to perform a logical OR operation on the lower tube overcurrent signal and the PFM signal, and output a clock signal to the logic control circuit.

2. The control circuit for automatically switching the operation mode according to claim 1, wherein, The current generation circuit includes a first operational amplifier, a first transistor, a first resistor, the on-resistance of the upper sampling transistor, a second transistor, and a second resistor. The non-inverting input of the first operational amplifier is coupled to the PFM detection circuit and connected to the control voltage. The inverting input is coupled to the second terminal of the first transistor and the first terminal of the first resistor, respectively. The output is coupled to the control terminal of the first transistor and the control terminal of the second transistor, respectively. The first end of the on-resistance of the upper sampling transistor is connected to the input voltage, and the second end is coupled to the first pole of the first transistor and the first current difference circuit respectively. The on-resistance of the upper sampling transistor is configured to generate a set current according to the input voltage. The first terminal of the second transistor is coupled to the first current difference circuit, and the second terminal is coupled to the first terminal of the second resistor; The second terminal of the first resistor and the second terminal of the second resistor are respectively grounded; The first operational amplifier, the first transistor, and the first resistor constitute a first voltage-to-current circuit, which is configured to convert the control voltage into a first control current flowing through the first transistor.

3. The control circuit for automatically switching the operating mode according to claim 2, wherein The first current difference circuit includes a current source, a third resistor, and a second voltage-to-current circuit. The second voltage-to-current circuit includes a second operational amplifier, a third transistor, and a fourth resistor. The second voltage-to-current circuit is configured to convert the difference voltage into a second difference current flowing through the third transistor. The first end of the current source is connected to the power supply voltage, and the second end is coupled to the first terminal of the second transistor, the non-inverting input terminal of the second operational amplifier, and the first end of the third resistor. The current source is configured to provide the fixed bias current. When the first control current is greater than the fixed bias current, the first differential current flowing to the first end of the third resistor is 0. The set current is equal to the first control current, and the control circuit operates in a fixed frequency PWM mode. The second terminal of the third resistor is grounded, and the third resistor is configured to generate a differential voltage based on the first differential current; The non-inverting input of the second operational amplifier is connected to the differential voltage, the inverting input is coupled to the second terminal of the third transistor and the first terminal of the fourth resistor, and the output is coupled to the control terminal of the third transistor and the second current difference circuit. The first terminal of the third transistor is coupled to the second terminal of the on-resistance of the upper sampling transistor; The second terminal of the fourth resistor is grounded.

4. The control circuit for automatically switching the operating mode according to claim 3, wherein The second current differential circuit includes a fourth transistor, a fifth resistor, a sixth resistor, a sixth transistor, a seventh transistor, and an eighth transistor; The control electrode of the fourth transistor is coupled to the control electrode of the third transistor and the output terminal of the second operational amplifier, the first electrode is coupled to the control electrode of the sixth transistor, the first electrode of the sixth transistor and the control electrode of the seventh transistor, and the second electrode is coupled to the first terminal of the fifth resistor. The fourth transistor is configured to generate a third differential current with the same magnitude as the second differential current through the second mirror. The third transistor and the fourth transistor constitute a second current mirror circuit. The control electrode of the fifth transistor is coupled to the control electrode of the second transistor, the control electrode of the first transistor, and the output terminal of the first operational amplifier. The first electrode is coupled to the first electrode of the seventh transistor, the control electrode of the eighth transistor, and the first electrode of the eighth transistor. The second electrode is coupled to the first terminal of the sixth resistor. The fifth transistor is configured to generate a third control current with the same magnitude as the first control current through the first mirror. The first transistor, the second transistor, and the fifth transistor constitute a first current mirror circuit. The second terminal of the sixth transistor is coupled to the second terminals of the seventh transistor, the second terminal of the eighth transistor, and the valley control circuit, and is connected to the power supply voltage. The seventh transistor is configured to generate a first difference current with the same magnitude as the third difference current through the third mirror, and the sixth transistor and the seventh transistor constitute a third current mirror circuit; The control electrode and the second electrode of the eighth transistor are both coupled to the valley control circuit. The eighth transistor is configured to generate the second differential current when the third control current is less than the fixed bias current.

5. The control circuit for automatically switching the operating mode according to claim 4, wherein, The valley control circuit includes a ninth transistor, a lower sampling transistor, a lower transistor, and a comparator; The control electrode of the ninth transistor is coupled to the control electrode of the eighth transistor and the first electrode of the eighth transistor. The first electrode is coupled to the second electrode of the lower sampling transistor and the non-inverting input of the comparator. The second electrode is coupled to the second electrode of the eighth transistor, the second electrode of the seventh transistor and the second electrode of the sixth transistor. The ninth transistor is configured to generate a third differential current with the same magnitude as the second differential current through the fourth mirror. The eighth transistor and the ninth transistor constitute a fourth current mirror circuit. The control electrode of the lower sampling tube is coupled to the control electrode of the lower tube and connected to the lower tube drive signal. The first electrode of the lower sampling tube is coupled to the first electrode of the lower tube via a switching node, and the second electrode of the lower tube is grounded. The inverting input of the comparator is grounded, and the lower tube overcurrent signal is output from the output to the oscillator.

6. The control circuit for automatically switching the operating mode according to claim 5, wherein In the valley control circuit, the valley current is detected by detecting the voltage of the switching node. When the valley current drops to a preset value, the overcurrent signal of the lower tube output to the oscillator is high.

7. The control circuit for automatically switching the operating mode according to claim 6, wherein When the third control current is less than the fixed bias current, the valley control circuit controls the switching frequency to decrease by reducing the valley current, and the control circuit operates in the valley frequency reduction mode.

8. The control circuit of claim 2, wherein, The PFM detection circuit includes a hysteresis comparator; The non-inverting input of the hysteresis comparator is connected to the PFM threshold voltage, and the inverting input is coupled to the non-inverting input of the first operational amplifier and connected to the control voltage. The hysteresis comparator is configured to compare the magnitude of the control voltage and the PFM threshold voltage and output a PFM signal to the oscillator. When the control voltage changes from large to small, the PFM threshold voltage is a falling PFM threshold voltage, and when the control voltage changes from small to large, the PFM threshold voltage is a rising PFM threshold voltage.

9. A BUCK-type DC-DC converter, characterized in that, The control circuit includes the automatic switching operating mode as described in any one of claims 1 to 8.

10. A chip, characterized in that, Includes the BUCK-type DC-DC converter as described in claim 9.

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