Manufacturing method of super-junction SGT MOSFET

Abstract

The invention provides a super junction SGT MOSFET manufacturing method comprising the following steps: providing a substrate and forming an epitaxial layer, the epitaxial layer is doped with first and second conductive type impurities, and the concentration of the second type is higher than that of the first type; etching a groove; the method comprises the following steps: thermally growing a dielectric layer on the inner wall of a groove, and utilizing the difference of segregation coefficients of two impurities in the dielectric layer and an epitaxial layer to enable first type impurities to be gathered on an interface and second type impurities to be consumed, so that conduction type inversion occurs in a region adjacent to the inner wall of the groove, a first type doped region surrounding the groove is formed, and a super junction structure is formed; and then manufacturing a shield gate, a control gate and a source-drain electrode. The super junction is naturally formed by using the impurity segregation effect, high-energy injection or multi-time epitaxy is not needed, the method is compatible with the existing SGT process, the cost is remarkably reduced, and the device performance is improved.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit manufacturing, and in particular to a method for fabricating a superjunction SGT MOSFET. Background Technology

[0002] Metal-oxide-semiconductor field-effect transistors (MOSFETs) are core components of power semiconductor devices. Among them, shielded gate trench (SGT) MOSFETs, due to the integration of shielding electrodes in the lower part of the trench, can significantly reduce the gate-drain capacitance (Cgd), thereby reducing switching losses and improving device performance, and are widely used in power management and low-to-medium voltage applications. On the other hand, super junction (SJ) technology, by introducing alternating P-type and N-type regions into the device drift region, utilizes the charge balance principle to break the limiting relationship between specific on-resistance and breakdown voltage of traditional silicon devices.

[0003] However, due to the extreme cost sensitivity of low- and medium-voltage MOSFET products, traditional superjunction shielded gate (SGT) fabrication processes face significant challenges. Existing superjunction fabrication processes, such as multiple epitaxial growths combined with multiple ion implantations, or deep trench high-energy ion implantation, are not only cumbersome in their process steps and have long production cycles, but also place extremely high demands on equipment, resulting in high manufacturing costs. Furthermore, the epitaxial layer of conventional SGT MOSFETs is relatively thin. If non-epitaxy methods such as trench sidewall tilting implantation are used to fabricate superjunctions, precise doping control within the narrow trenches is extremely difficult, and doping inhomogeneity is easily caused by the shadowing effect.

[0004] Therefore, the industry urgently needs a low-cost, highly compatible method for fabricating superjunction SGT MOSFETs. Summary of the Invention

[0005] The technical problem this invention aims to solve is that existing superjunction MOSFET fabrication processes typically employ multiple epitaxial growth processes combined with multiple ion implantations, or deep trench high-energy ion implantation. These methods are complex, require expensive equipment, and have long production cycles, making them difficult to apply to cost-sensitive low- and medium-voltage products. While conventional SGT MOSFETs have relatively mature processes, it is difficult to introduce a superjunction structure to overcome the resistance-voltage limit of silicon material without adding expensive equipment. Therefore, this invention provides a low-cost fabrication method that utilizes the impurity segregation effect to naturally form a superjunction structure and is compatible with existing SGT processes.

[0006] This invention provides a method for fabricating a superjunction SGT MOSFET, the method comprising the following steps:

[0007] Step 1: Provide a substrate and form an epitaxial layer on the substrate; the epitaxial layer is simultaneously doped with impurity ions of a first conductivity type and impurity ions of a second conductivity type; wherein the concentration of the impurity ions of the second conductivity type is higher than the concentration of the impurity ions of the first conductivity type, so that the epitaxial layer as a whole exhibits the polarity of the second conductivity type;

[0008] Step 2: Forming trenches on the epitaxial layer, the trenches extending along the thickness direction of the epitaxial layer;

[0009] Step 3: Form a dielectric layer on the inner wall of the trench; utilizing the difference in segregation coefficients between the first conductivity type impurity ions and the second conductivity type impurity ions in the dielectric layer and the epitaxial layer material, the first conductivity type impurity ions accumulate on the epitaxial layer side at the interface between the dielectric layer and the epitaxial layer, while the second conductivity type impurity ions enter the dielectric layer and are consumed, thereby causing conductivity type reversal in the region adjacent to the inner wall of the trench, forming a first conductivity type doped region surrounding the trench, while the epitaxial layer remains a second conductivity type doped region in the region away from the trench. The first conductivity type doped region and the second conductivity type doped region constitute a superjunction structure.

[0010] Preferably, in step one, the epitaxial layer material is silicon.

[0011] Preferably, in step one, the first conductivity type impurity ion is an N-type impurity.

[0012] Preferably, in step one, the first conductivity type of impurity ion includes arsenic or phosphorus.

[0013] Preferably, in step one, the second conductivity type impurity ion is a P-type impurity.

[0014] Preferably, in step one, the second type of conductivity impurity ion includes boron.

[0015] Preferably, in step one, the epitaxial layer is a multilayer gradient concentration structure or a gradually changing concentration structure.

[0016] Preferably, in step two, the aspect ratio of the trench is greater than 5.

[0017] Preferably, in step three, the process for forming the dielectric layer is a thermal oxidation process.

[0018] Preferably, in step three, the dielectric layer is a silicon oxide layer.

[0019] Preferably, in step three, the solubility of the first conductivity type impurity ion in silicon is greater than its solubility in silicon oxide.

[0020] Preferably, in step three, the solubility of the second type of conductivity impurity ion in silicon oxide is greater than its solubility in silicon.

[0021] Preferably, in step three, the thickness of the dielectric layer is 5000 Å to 10000 Å.

[0022] Preferably, in step three, at the interface between the dielectric layer and the epitaxial layer, the concentration of the first conductivity type impurity ions is increased to 2.0 to 3.0 times the initial concentration.

[0023] Preferably, in step three, at the interface between the dielectric layer and the epitaxial layer, the concentration of the second conductivity type impurity ions is reduced to 0.4 to 0.8 times the initial concentration.

[0024] Preferably, the manufacturing method further includes step four: after step three, filling the trench in which the dielectric layer is formed with conductive material to form a shielding grid.

[0025] Preferably, in step four, the conductive material of the shielding gate is polycrystalline silicon.

[0026] Preferably, in step four, the specific operation of forming the shielding gate includes: using a dry etching process to etch back the conductive material of the shielding gate to flatten its top surface.

[0027] Preferably, the manufacturing method further includes step five: after step four, removing part of the dielectric layer and part of the shielding gate conductive material, forming a gate dielectric layer on the upper part of the trench, and filling the gate dielectric layer with control gate conductive material to form a control gate.

[0028] Preferably, in step five, the conductive material of the control gate is polycrystalline silicon.

[0029] Preferably, in step five, the specific operation of forming the control gate includes: using wet etching to remove a portion of the shielding gate conductive material and a portion of the dielectric layer above the trench.

[0030] Preferably, the fabrication method further includes step six: after step five, body region implantation, source region implantation and contact hole processes are performed on the upper surface of the epitaxial layer to form source metal and drain metal.

[0031] As described above, the method for fabricating the superjunction SGT MOSFET of the present invention has the following beneficial effects:

[0032] This invention utilizes an epitaxial layer containing two types of impurities combined with a thermal oxidation process. By leveraging the segregation characteristics of different impurities during dielectric layer growth (such as the accumulation effect of arsenic and the adsorption effect of boron), it achieves the natural inversion formation of N-pillars (or P-pillars) of superjunctions on the trench sidewalls. This eliminates the need for additional high-energy ion implantation equipment or complex and expensive multiple epitaxial processes, significantly reducing the manufacturing cost of superjunction SGT MOSFETs. Furthermore, this method is highly compatible with existing standard SGT processes. The resulting superjunction structure incorporates the field shielding effect of SGT, not only reducing the on-resistance of the device but also decreasing the sensitivity of the device's breakdown voltage to charge balance, thereby improving the process window and product yield. Attached Figure Description

[0033] Figure 1 The diagram shows a process flow diagram of a method for fabricating a superjunction SGT MOSFET according to the present invention.

[0034] Figure 2 The diagram shows a structural schematic after trenching is formed in a method for fabricating a superjunction SGT MOSFET according to the present invention.

[0035] Figure 3 The diagram shows a structural schematic after the formation of a dielectric layer and a first conductivity type doped region in a method for fabricating a superjunction SGT MOSFET according to the present invention.

[0036] Figure 4 The diagram shows the structure after the shielding gate is formed in a method for fabricating a superjunction SGT MOSFET according to the present invention.

[0037] Figure 5 The diagram shows the structure after the control gate is formed in a method for fabricating a superjunction SGT MOSFET according to the present invention.

[0038] Figure 6 The diagram shows a schematic of the structure of a superjunction SGT MOSFET formed in a method for fabricating a superjunction SGT MOSFET according to the present invention. Detailed Implementation

[0039] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0040] like Figure 1 As shown, this application provides a method for fabricating a superjunction SGT MOSFET, the method comprising the following steps:

[0041] Step 1: Provide a substrate 100 and form an epitaxial layer 101 on the substrate 100; the epitaxial layer 101 is simultaneously doped with impurity ions of a first conductivity type and impurity ions of a second conductivity type; wherein, the concentration of the impurity ions of the second conductivity type is higher than the concentration of the impurity ions of the first conductivity type, so that the epitaxial layer 101 as a whole exhibits the polarity of the second conductivity type.

[0042] In some embodiments, in step one, the epitaxial layer 101 is made of silicon. In addition, to cover a wider range of semiconductor applications, the specific materials of the substrate 100 and the epitaxial layer 101 can be selected from elemental semiconductors, including but not limited to single-crystal silicon, polycrystalline silicon, amorphous silicon, germanium (Ge), or diamond; they can also be selected from compound semiconductors, including but not limited to silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), indium antimonide (InSb), zinc selenide (ZnSe), zinc sulfide (ZnS), or cadmium telluride (CdTe); and they can also be selected from alloy semiconductors, including but not limited to silicon germanium (SiGe), silicon germanium carbide (SiGeC), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), or gallium arsenide phosphide (GaInAsP). Furthermore, substrate 100 can also be a semiconductor-on-insulator (SOI) structure, a germanium-on-insulator (GOI) structure, a silicon-on-sapphire (SOS) structure, or a combination thereof. Substrate 100 can contain various doping configurations depending on design requirements. For example... Figure 6 As shown, substrate 100 is typically a heavily doped silicon substrate of the first conductivity type (e.g., N+ type), and its lattice orientation can be... <100> , <111> or <110> Crystal orientation. The epitaxial layer 101 is a double-doped layer grown on the heavily doped substrate 100. Its formation process can employ vapor phase epitaxy (VPE), liquid phase epitaxy (LPE), molecular beam epitaxy (MBE), ambient pressure chemical vapor deposition (APCVD), low pressure chemical vapor deposition (LPCVD), or ultra-high vacuum chemical vapor deposition (UHVCVD). This special double-doped epitaxial layer replaces the single-doped epitaxial layer in traditional SGT MOSFETs, providing a foundation for subsequent formation of superjunction structures using thermal processes.

[0043] In some embodiments, in step one, the first conductivity type of impurity ion is an N-type impurity. N-type impurities are used to provide free electrons to the semiconductor energy band.

[0044] In some embodiments, in step one, the first conductivity type impurity ion includes arsenic or phosphorus. Besides arsenic (As) and phosphorus (P), the first conductivity type impurity ion may also include other Group V elements, such as antimony (Sb), bismuth (Bi), or nitrogen (N), or may include Group I elements such as lithium (Li), and combinations thereof. In specific applications, because arsenic, phosphorus, and antimony have specific properties in their diffusion and segregation coefficients during thermal oxidation—that is, their solubility in silicon is greater than their solubility in the oxide layer—they tend to be repelled from the oxide layer and accumulate on the silicon side. Therefore, they are very suitable for the impurity redistribution process of this scheme to form a localized N-type inversion layer.

[0045] In some embodiments, in step one, the second conductivity type of impurity ion is a P-type impurity. P-type impurities are used to provide holes to the semiconductor energy band.

[0046] In some embodiments, in step one, the second conductivity type impurity ion includes boron. Besides boron (B), the second conductivity type impurity ion may also include boron difluoride (BF2), other Group III elements such as aluminum (Al), gallium (Ga), indium (In), and combinations thereof. Boron, as a typical p-type impurity, has significantly higher solubility in silicon oxide than in silicon. This characteristic allows it to easily enter the oxide layer from silicon during thermal oxidation, which is the opposite of the accumulation effect of the first conductivity type impurities and is a key mechanism for the subsequent formation of the inversion layer.

[0047] In some embodiments, in step one, the epitaxial layer 101 is a multilayer gradient concentration structure or a gradually varying concentration structure. By dynamically adjusting the flow rate of the gas source containing impurity ions of the first and second conductivity types using a mass flow controller (MFC) during epitaxial growth, an epitaxial structure with gradually varying or stepped concentrations along the growth direction can be formed. For example, the concentration can be higher near the substrate 100 and lower near the surface, or a multi-segmented distribution can be designed according to electric field distribution requirements. This helps optimize the electric field distribution inside the device, further improving the device's breakdown voltage and reliability.

[0048] In specific experimental data, for example, the arsenic doping concentration in epitaxial layer 101 can be 3e16 atoms / cm³, and the boron doping concentration can be 4e16 atoms / cm³. In another set of experimental data, the arsenic doping concentration in epitaxial layer 101 is 6e16 atoms / cm³, and the boron doping concentration is 8e16 atoms / cm³. These concentration settings ensure that epitaxial layer 101 exhibits a second conductivity type (e.g., P-type) in the initial state, and that the concentrations of both impurities are at a high level (e.g., greater than 1e16 atoms / cm³), which is beneficial for producing a significant segregation effect in subsequent steps. At this time, the thickness of epitaxial layer 101 is approximately 6 μm.

[0049] like Figure 2 As shown, step two involves forming trenches on the epitaxial layer 101, with the trenches extending along the thickness direction of the epitaxial layer 101. The formation of these trenches is typically accomplished through photolithography and etching processes. For example... Figure 2 As shown, a hard mask layer 102 is first deposited on the surface of the epitaxial layer 101. The material of the hard mask layer 102 includes, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof. The deposition method includes chemical vapor deposition (CVD) or thermal oxidation. Photoresist is then coated, and the trench pattern is defined by exposure and development. Using the patterned photoresist or hard mask 102 as a barrier layer, a dry etching process is employed to form the trenches. Dry etching can use deep reactive ion etching (DRIE) or inductively coupled plasma (ICP) etching. The etching gas can include one or more of sulfur hexafluoride, octafluorocyclobutane, hydrogen bromide, chlorine, oxygen, or argon.

[0050] In some embodiments, in step two, the aspect ratio of the trench is greater than 5. A higher aspect ratio (e.g., a depth of 7.0 μm, a width of 2.0 μm, and a device pitch of 4 μm) helps to increase the vertical length of the drift region, thereby improving the device's breakdown voltage without increasing the device footprint. Simultaneously, the deep trench structure can accommodate deeper and larger shielding gates, enhancing charge balancing.

[0051] like Figure 3 As shown, in step three, a dielectric layer 103 is formed on the inner wall of the trench. Utilizing the difference in segregation coefficients between the first conductivity type impurity ions and the second conductivity type impurity ions in the dielectric layer 103 and the epitaxial layer 101, the first conductivity type impurity ions accumulate on the epitaxial layer 101 side at the interface between the dielectric layer 103 and the epitaxial layer 101, while the second conductivity type impurity ions enter the dielectric layer 103 and are consumed. This causes a conductivity type reversal in the region adjacent to the inner wall of the trench, forming a first conductivity type doped region 104 surrounding the trench. The epitaxial layer 101 remains a second conductivity type doped region in the region away from the trench. The first conductivity type doped region 104 and the second conductivity type doped region constitute a superjunction structure.

[0052] In some embodiments, step three, the process of forming the dielectric layer 103, is a thermal oxidation process. The thermal oxidation process can be carried out in a vertical or horizontal furnace tube, and the oxidation atmosphere includes dry oxygen (pure oxygen), wet oxygen (hydrogen-oxygen mixture combustion producing water vapor), or water vapor oxidation. The process temperature range is typically controlled between 800°C and 1200°C; higher temperatures help accelerate the oxidation rate and impurity diffusion. At high temperatures, silicon reacts with oxygen to form silicon oxide, simultaneously driving impurity ions to redistribute at the interface according to thermodynamic equilibrium. Figure 2 compared to, Figure 3The medium-hard mask layer 102 has been removed, and this removal step can be completed by wet etching before thermal oxidation.

[0053] In some embodiments, in step three, the dielectric layer 103 is a silicon oxide layer. Alternatively, the dielectric layer 103 can also be a silicon oxynitride (SiON) layer, a doped silicon oxide layer (such as fluorine-containing silicon oxide, boron-containing silicon oxide, or phosphorus-containing silicon oxide), or other oxygen-containing dielectric composites. Any material capable of consuming the substrate material (such as silicon) of the epitaxial layer 101 and inducing the accumulation of impurities of the first conductivity type and the precipitation of impurities of the second conductivity type during its formation can be used as the dielectric layer 103 in this embodiment.

[0054] In some embodiments, in step three, the solubility of the first conductivity type of impurity ions in silicon is greater than their solubility in silicon oxide. Taking arsenic (As) as an example, because its solubility in silicon is much greater than its solubility in silicon oxide, as the oxide layer advances into the silicon, arsenic cannot enter the oxide layer in large quantities and is forced to accumulate on the silicon side at the oxide / silicon interface, resulting in a significant increase in the arsenic concentration at the interface.

[0055] In some embodiments, in step three, the solubility of the second conductivity type impurity ions in silicon oxide is greater than their solubility in silicon. Taking boron (B) as an example, its segregation coefficient m (concentration in silicon / concentration in oxide layer) is less than 1, meaning that boron tends to dissolve in the oxide layer. As the oxide layer grows, a large amount of boron in the silicon near the interface diffuses into the oxide layer, resulting in a significant decrease in the boron concentration on the silicon side at the interface.

[0056] In some embodiments, in step three, the thickness of the dielectric layer 103 is 5000 Å to 10000 Å. In a specific experiment, the temperature of the thermal oxidation process was 1050 °C, and the thickness of the grown dielectric layer 103 was approximately 7500 Å. The sufficiently thick dielectric layer 103 requires a long growth time, ensuring sufficient time for impurity segregation and redistribution, so that changes in impurity concentration at the interface are sufficient to cause a reversal of the conductivity type. Figure 3 As shown, the dielectric layer 103 (e.g., field oxide layer FOX) is mainly used to isolate the subsequently formed shielding gate from the bulk silicon.

[0057] In some embodiments, in step three, at the interface between the dielectric layer 103 and the epitaxial layer 101, the concentration of impurity ions of the first conductivity type is increased to 2.0 to 3.0 times the initial concentration. For example, in simulation tests, the As concentration at the interface is increased to approximately 2.3 to 2.5 times the initial concentration.

[0058] In some embodiments, in step three, at the interface between the dielectric layer 103 and the epitaxial layer 101, the concentration of the second conductivity type impurity ions is reduced to 0.4 to 0.8 times the initial concentration. For example, in simulation tests, the Boron concentration at the interface is reduced to approximately 0.6 times the initial concentration. This concentration change, with one increasing and the other decreasing, causes the previously lower concentration of N-type impurities (arsenic) to surpass the previously higher concentration of P-type impurities (boron) in the region immediately adjacent to the trench sidewall, thereby locally inverting the P-type epitaxial layer to N-type, forming a structure such as... Figure 3 The first conductivity type doped region 104 is shown in the diagram. This structure, together with the internally retained second conductivity type doped region (i.e., the remaining portion of the original epitaxial layer 101), forms a lateral PN junction, i.e., a superjunction structure. Since the N-region charge can be depleted with the help of the P-region and the subsequently formed shielding gate, this superjunction structure does not require extremely precise charge balance, reducing the difficulty of process control while maintaining low on-resistance and high breakdown voltage characteristics.

[0059] like Figure 4 As shown, the manufacturing method also includes step four: after step three, the trench in which the dielectric layer 103 is formed is filled with conductive material of the shielding grid to form the shielding grid 105.

[0060] In some embodiments, in step four, the conductive material of the shielding gate is polycrystalline silicon. Alternatively, the conductive material of the shielding gate can be selected from one or a combination of conductive materials such as amorphous silicon, metals (e.g., tungsten, aluminum, copper), metal alloys (e.g., titanium nitride, tantalum nitride), metal silicides (e.g., tungsten silicide, titanium silicide, cobalt silicide, nickel silicide), or carbon materials (e.g., graphene, carbon nanotubes). The filling process can employ low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), or physical vapor deposition (PVD). If polycrystalline silicon is used, in-situ doping can be performed to introduce phosphorus, arsenic, or boron ions, or ion implantation and annealing can be performed after deposition to reduce resistivity.

[0061] In some embodiments, step four, the specific operation of forming the shielding gate 105, includes: using a dry etching process to etch back the conductive material of the shielding gate to planarize its top surface. The etch-back process is used to remove excess conductive material outside the trench and to precisely control the height of the shielding gate 105 inside the trench. Figure 4 As shown, the shielding gate 105 fills the lower part of the trench and is surrounded by the dielectric layer 103. Planarization can also be achieved using a chemical mechanical polishing (CMP) process. This treatment helps reduce surface topography undulations and improves the alignment accuracy of subsequent photolithography processes.

[0062] like Figure 5As shown, the manufacturing method also includes step five: after step four, a portion of the dielectric layer 103 and a portion of the shielding gate conductive material are removed, a gate dielectric layer 107 is formed on the upper part of the trench, and a control gate conductive material is filled on the gate dielectric layer 107 to form a control gate 108.

[0063] In some embodiments, in step five, the control gate conductive material is polysilicon. The control gate 108 can also use doped polysilicon, a metal gate, a stacked structure of polysilicon and metal silicides, or a combination of metals and metal nitrides to obtain the desired work function and low gate resistance. Figure 5 As shown, the control gate 108 is located above the shielding gate 105.

[0064] In some embodiments, step five, specifically the operation of forming the control gate 108, includes: using wet etching to remove a portion of the shielding gate conductive material and a portion of the dielectric layer 103 above the trench. For example... Figure 5 As shown, an inter-electrode dielectric layer 106 (IPD) is also formed between the shielding gate 105 and the control gate 108 to isolate the two gates. Wet etching typically uses hydrofluoric acid (HF) or buffered oxide etchant (BOE) to remove silicon oxide, and potassium hydroxide (KOH), tetramethylammonium hydroxide (TMAH), or a mixture of nitric acid and hydrofluoric acid to remove part of the polysilicon. This step not only defines the vertical position of the control gate 108, but also retains the previously grown thicker dielectric layer 103 (field oxide layer) in the lower part of the trench as the shielding gate dielectric, while a higher quality and thinner gate dielectric layer 107 is regrown in the upper part of the trench through thermal oxidation or CVD to meet the precise control requirements of threshold voltage and transconductance. The material of the gate dielectric layer 107 can be silicon oxide, silicon oxynitride, or high dielectric constant materials such as hafnium oxide (HfO2), aluminum oxide (Al2O3), zirconium oxide (ZrO2), etc.

[0065] like Figure 6 As shown, the fabrication method also includes step six: after step five, body region implantation, source region implantation and contact hole processes are performed on the upper surface of epitaxial layer 101 to form source metal 112 and drain metal 113.

[0066] On the lower surface of the epitaxial layer 101 (i.e., the back side of the initially provided substrate 100), a heavily doped region of the first conductivity type (e.g., an N+ substrate) typically already exists, or a drain contact region can be formed by back-side grinding and back-side ion implantation, upon which drain metal 113 is deposited. Body implantation typically utilizes photoresist as a mask to implant a second conductivity type impurity (e.g., boron or boron difluoride) from the front side, forming a body region 109, followed by push-pull annealing. Source implantation typically implants a high concentration of the first conductivity type impurity (e.g., arsenic or phosphorus) to form a source region 110, and combines this with rapid thermal annealing (RTA) to activate the impurity. Figure 6As shown, an insulating cap layer 111 is formed above the control gate 108 to isolate the gate from the metal above it. An interlayer dielectric (ILD) layer, such as borosilicate glass (BPSG) or undoped silicon glass (USG), is then deposited, and contact holes are formed by photolithography and etching. A metal silicide (such as titanium silicide) can be formed at the bottom of the contact holes to reduce contact resistance. The formation of the source metal 112 and drain metal 113 may include depositing a barrier layer (such as Ti / TiN), depositing a metal plug (such as tungsten), and depositing a main metal layer (such as Al, Cu, or an AlCu alloy). The resulting device utilizes a first conductivity type doped region 104 (as a drift region, i.e., an N-type pillar) formed on the trench sidewalls and a shielding gate 105 structure, combined with a heavily doped drain substrate 100 (N+ region) at the bottom, to achieve excellent breakdown voltage characteristics (e.g., a measured device BV of approximately 137V) and low specific on-resistance (e.g., Rsp of approximately 74mΩ·cm). Furthermore, by adjusting the area ratio of SJ and SGT or refining the epitaxial layer structure, the device performance can be further optimized.

[0067] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0068] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for fabricating a superjunction SGT MOSFET, characterized in that, At least including: Step 1: Provide a substrate and form an epitaxial layer on the substrate; the epitaxial layer is simultaneously doped with impurity ions of a first conductivity type and impurity ions of a second conductivity type; wherein the concentration of the impurity ions of the second conductivity type is higher than the concentration of the impurity ions of the first conductivity type, so that the epitaxial layer as a whole exhibits the polarity of the second conductivity type; Step 2: Forming trenches on the epitaxial layer, the trenches extending along the thickness direction of the epitaxial layer; Step 3: Form a dielectric layer on the inner wall of the trench; utilizing the difference in segregation coefficients between the first conductivity type impurity ions and the second conductivity type impurity ions in the dielectric layer and the epitaxial layer material, the first conductivity type impurity ions accumulate on the epitaxial layer side at the interface between the dielectric layer and the epitaxial layer, while the second conductivity type impurity ions enter the dielectric layer and are consumed, thereby causing conductivity type reversal in the region adjacent to the inner wall of the trench, forming a first conductivity type doped region surrounding the trench, while the epitaxial layer remains a second conductivity type doped region in the region away from the trench. The first conductivity type doped region and the second conductivity type doped region constitute a superjunction structure.

2. The method for fabricating a superjunction SGT MOSFET according to claim 1, characterized in that: In step one, the epitaxial layer material is silicon.

3. The method for fabricating a superjunction SGT MOSFET according to claim 1, characterized in that: In step one, the first conductivity type of impurity ion is an N-type impurity.

4. The method for fabricating a superjunction SGT MOSFET according to claim 3, characterized in that: In step one, the first type of conductivity impurity ion includes arsenic or phosphorus.

5. The method for fabricating a superjunction SGT MOSFET according to claim 1, characterized in that: In step one, the second conductivity type impurity ion is a P-type impurity.

6. The method for fabricating a superjunction SGT MOSFET according to claim 5, characterized in that: In step one, the second type of conductivity impurity ion includes boron.

7. The method for fabricating a superjunction SGT MOSFET according to claim 1, characterized in that: In step one, the epitaxial layer is a multilayer gradient concentration structure or a gradually changing concentration structure.

8. The method for fabricating a superjunction SGT MOSFET according to claim 1, characterized in that: In step two, the aspect ratio of the trench is greater than 5.

9. The method for fabricating a superjunction SGT MOSFET according to claim 1, characterized in that: In step three, the process for forming the dielectric layer is a thermal oxidation process.

10. The method for fabricating a superjunction SGT MOSFET according to claim 1, characterized in that: In step three, the dielectric layer is a silicon oxide layer.

11. The method for fabricating a superjunction SGT MOSFET according to claim 10, characterized in that: In step three, the solubility of the first type of conductivity impurity ion in silicon is greater than its solubility in silicon oxide.

12. The method for fabricating a superjunction SGT MOSFET according to claim 10, characterized in that: In step three, the solubility of the second type of conductivity impurity ion in silicon oxide is greater than its solubility in silicon.

13. The method for fabricating a superjunction SGT MOSFET according to claim 1, characterized in that: In step three, the thickness of the dielectric layer is 5000 Å to 10000 Å.

14. The method for fabricating a superjunction SGT MOSFET according to claim 1, characterized in that: In step three, at the interface between the dielectric layer and the epitaxial layer, the concentration of the first type of conductivity impurity ions is increased to 2.0 to 3.0 times the initial concentration.

15. The method for fabricating a superjunction SGT MOSFET according to claim 1, characterized in that: In step three, at the interface between the dielectric layer and the epitaxial layer, the concentration of the second conductivity type impurity ions is reduced to 0.4 to 0.8 times the initial concentration.

16. The method for fabricating a superjunction SGT MOSFET according to claim 1, characterized in that: The manufacturing method further includes step four: after step three, the trench in which the dielectric layer is formed is filled with conductive material of the shielding grid to form a shielding grid.

17. The method for fabricating a superjunction SGT MOSFET according to claim 16, characterized in that: In step four, the conductive material of the shielding gate is polycrystalline silicon.

18. The method for fabricating a superjunction SGT MOSFET according to claim 16, characterized in that: In step four, the specific operations for forming the shielding gate include: using a dry etching process to etch back the conductive material of the shielding gate to flatten its top surface.

19. The method for fabricating a superjunction SGT MOSFET according to claim 16, characterized in that: The manufacturing method further includes step five: after step four, a portion of the dielectric layer and a portion of the shielding gate conductive material are removed, a gate dielectric layer is formed on the upper part of the trench, and a control gate conductive material is filled on the gate dielectric layer to form a control gate.

20. The method for fabricating a superjunction SGT MOSFET according to claim 19, characterized in that: In step five, the conductive material of the control gate is polycrystalline silicon.

21. The method for fabricating a superjunction SGT MOSFET according to claim 19, characterized in that: In step five, the specific operations for forming the control gate include: using wet etching to remove a portion of the shielding gate conductive material and a portion of the dielectric layer above the trench.

22. The method for fabricating a superjunction SGT MOSFET according to claim 19, characterized in that: The fabrication method further includes step six: after step five, body region implantation, source region implantation and contact hole processes are performed on the upper surface of the epitaxial layer to form source metal and drain metal.

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