Bayesian network-based auxiliary pattern generation method and system for mask pattern and terminal
Patent Information
- Application Number
- CN202610517960.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2026-04-20
- Publication Date
- 2026-09-11
- Estimated Expiration
- 2046-04-20
AI Technical Summary
[0007]鉴于以上所述现有技术的缺点,本发明的目的在于提供一种基于贝叶斯网络的掩模板图形的辅助图形生成方法、系统及终端,用于解决在现有先进制程节点下,亚分辨率辅助图形的生成方法存在效率低下、精度不足的技术问题
[0018] As described above, the auxiliary image generation method, system, and terminal based on a Bayesian network for mask images of this application have the following beneficial effects: This invention constructs an auxiliary image discrete parameter space for the target mask image to obtain multiple sets of candidate auxiliary image discrete parameters; it obtains at least one set of optimal auxiliary image discrete parameters by generating a Bayesian fully connected network based on pre-trained auxiliary images and combining it with an optimization algorithm; it obtains an auxiliary mask image containing the auxiliary images by performing auxiliary image processing on the optimal auxiliary image discrete parameters; and it obtains a final auxiliary mask image containing the final auxiliary images by performing photolithography process simulation verification on the auxiliary mask image. Compared with traditional auxiliary image generation methods, this application significantly improves the auxiliary image generation efficiency and imaging accuracy by integrating the above-mentioned technical means.
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Figure CN122043853B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuit lithography, and in particular to an auxiliary pattern generation method, system, and terminal for mask patterns based on Bayesian networks. Background Technology
[0002] With the continuous iteration of semiconductor technology, the scale and complexity of chip design are growing exponentially. When the feature size is close to or even smaller than the photolithography exposure wavelength, the optical proximity effect occurs, causing the actual pattern on the wafer to deviate from the designed pattern. This not only reduces the exposure quality and process fault tolerance, but also becomes a key bottleneck restricting the development and advancement of advanced process nodes.
[0003] Sub-Resolution Assist Feature (SRAF) is a key Optical Proximity Correction (OPC) technique in chip lithography, primarily used to improve lithography resolution and process window. Its principle is to add auxiliary features smaller than the lithography machine's resolution around the main pattern, using optical interference effects to optimize the imaging quality of the main pattern. SRAF itself does not form an actual pattern on the wafer, but it significantly enhances the imaging contrast and edge steepness of the main pattern, and has become an indispensable key method in advanced lithography processes, crucial for ensuring chip performance and mass production yield.
[0004] As process nodes advance to 3nm and below, the placement rules for photomask patterns (SRAFs) become extremely complex. Different graphic environments require different SRAF configurations, directly leading to a surge in the number of Design Rule Files (DRCs), significantly increasing chip design cycles and verification difficulty. Furthermore, SRAF optimization relies on high-precision lithography models, requiring comprehensive consideration of multiple physical effects such as optics, photoresist, and etching. Insufficient model accuracy directly impacts SRAF optimization performance. Therefore, providing a feasible and efficient SRAF generation method to ensure the effectiveness of SRAF placement, the convergence of iterative optimization, and the manufacturability of process conditions has become one of the core issues that must be addressed in modern high-end integrated circuit R&D. Simultaneously, SRAFs interact with photomask patterns, and this coupling further increases the overall optimization difficulty, easily leading to suboptimal solutions or even non-convergence, resulting in a serious waste of computational resources and production costs. Therefore, developing a novel SRAF generation method is urgently needed to ensure the mass production yield of advanced process chips.
[0005] Currently, the mainstream SRAF generation methods are mainly divided into two categories: one is the placement method based on predefined design rules (DRC rules). This method builds a rule base by accumulating engineering experience, clarifies key parameters such as the spacing, width, and length of the SRAF and the main graphic, and then automatically adds auxiliary features around the main graphic on the layout based on the rules. This method is fast and efficient, but lacks flexibility and is difficult to adapt to complex and ever-changing graphic environments. The other category is the optimization method based on lithography simulation models, such as inverse lithography (ILT). This method solves the optimal SRAF configuration through multiple rounds of iterative calculations, which can more accurately compensate for optical proximity effects and is suitable for complex graphics and advanced process scenarios. However, it suffers from huge computational loads, requires powerful computing resources, and has a long running time.
[0006] To balance efficiency and accuracy, current mainstream applications employ a hybrid strategy combining rules and models: first, an initial SRAF layout is quickly generated using rule-based methods, and then local optimization is performed using model-based methods. However, this approach is still limited by the completeness and applicability of the rule base. In scenarios with extremely small feature sizes, the process window (exposure dose and focal length tolerance) of SRAF shrinks drastically, and even minor process fluctuations can cause SRAF failure or graphic defects, leading to rule base failure and significantly increasing the difficulty of process integration. Although artificial intelligence / machine learning (AI / ML) methods can effectively alleviate this problem, the acquisition and annotation of massive training samples limit their large-scale application in practical engineering. Summary of the Invention
[0007] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide an auxiliary graphic generation method, system and terminal based on Bayesian network mask graphic, to solve the technical problems of low efficiency and insufficient accuracy in the sub-resolution auxiliary graphic generation method under the current advanced process nodes.
[0008] To achieve the above and other related objectives, this application provides an auxiliary pattern generation method for a mask pattern based on a Bayesian network, comprising: constructing an auxiliary pattern discrete parameter space for a target mask pattern; wherein the auxiliary pattern discrete parameter space includes multiple sets of candidate auxiliary pattern discrete parameters; generating a Bayesian fully connected network based on pre-trained auxiliary patterns to obtain intermediate feature data corresponding to the multiple sets of candidate auxiliary pattern discrete parameters respectively; determining at least one set of optimal auxiliary pattern discrete parameters from the multiple sets of candidate auxiliary pattern discrete parameters based on each intermediate feature data using an optimization algorithm; performing auxiliary pattern processing on the optimal auxiliary pattern discrete parameters to obtain an auxiliary mask pattern containing the auxiliary pattern; performing photolithography process simulation verification on the auxiliary mask pattern, and outputting a final auxiliary mask pattern containing the final auxiliary pattern based on the verification results.
[0009] In some embodiments of the first aspect of this application, the training process of the pre-trained auxiliary graph generation Bayesian fully connected network includes: obtaining an initial Bayesian fully connected network and constructing a training auxiliary graph discrete parameter space for training mask graphs; wherein the initial Bayesian fully connected network includes a preset prior distribution of trainable parameters; and based on the training auxiliary graph discrete parameter space, performing at least one round of auxiliary graph generation fully connected network training on the initial Bayesian fully connected network to obtain the pre-trained auxiliary graph generation Bayesian fully connected network.
[0010] In some embodiments of the first aspect of this application, the training process of the fully connected network for each round of auxiliary image generation training includes: determining the Bayesian fully connected network to be trained in this round; obtaining the discrete parameters of the batch of training auxiliary images required in this round from the discrete parameter space of the training auxiliary images, inputting them into the Bayesian fully connected network to be trained in this round, and obtaining the corresponding intermediate training feature data; converting the intermediate training feature data into a training auxiliary mask image containing the training auxiliary images, performing photolithography process simulation calculations on the training auxiliary mask image to obtain the photolithography simulation image outline; and obtaining the imaging quality based on the photolithography simulation image outline and the training design layout corresponding to the training mask image. The image quality loss cost is calculated; based on the log-likelihood estimate transformed from the image quality loss cost, and the KL divergence between the posterior and prior distributions of the trainable parameters of the Bayesian fully connected network to be trained in this round, the negative evidence lower bound loss value of the Bayesian fully connected network to be trained in this round is obtained; based on the image quality loss cost and the negative evidence lower bound loss value, the overall training loss value is obtained; it is determined whether the overall training loss value meets the preset convergence condition; if it does, the Bayesian fully connected network trained in this round is used as an auxiliary image to generate a Bayesian fully connected network; if it does not meet the condition, the Bayesian fully connected network trained in this round is used as the Bayesian fully connected network for the next round of training.
[0011] In some embodiments of the first aspect of this application, obtaining the imaging quality loss cost based on the lithographic simulation pattern outline and the training design layout corresponding to the training mask pattern includes: presetting multiple detection points on the training design layout, calculating the positional deviation between the lithographic simulation pattern outline and the training design layout at the corresponding detection points; and obtaining the imaging quality loss cost based on the statistical value of the positional deviation.
[0012] In some embodiments of the first aspect of this application, the overall training loss value is calculated using the following formula: ;in, This is the overall training loss value; The cost of the aforementioned imaging quality loss; The lower bound loss value for the negative evidence is given.
[0013] In some embodiments of the first aspect of this application, the negative evidence lower bound loss value is calculated using the following formula: ;in, This is the lower bound loss value for the negative evidence; This is the log-likelihood estimate; The KL divergence value is given; the log-likelihood estimate is negatively correlated with the cost of the imaging quality loss.
[0014] In some embodiments of the first aspect of this application, determining at least one set of optimal auxiliary graphic discrete parameters from the plurality of candidate auxiliary graphic discrete parameters based on each intermediate feature data using the optimization algorithm includes: selecting the optimal intermediate feature data based on the intermediate feature data using the optimization algorithm; and converting the optimal intermediate feature data into the corresponding optimal auxiliary graphic discrete parameters using an auxiliary graphic processing tool.
[0015] In some embodiments of the first aspect of this application, the step of performing photolithography process simulation verification on the auxiliary mask pattern containing the auxiliary pattern, and outputting a final auxiliary mask pattern containing the final auxiliary pattern based on the verification result includes: performing photolithography process simulation on the auxiliary mask pattern containing the auxiliary pattern, and performing photolithography process simulation verification based on the photolithography process simulation result; if the verification result meets the preset accuracy requirement, then performing process rule detection on the photolithography process simulation result, and outputting a final auxiliary mask pattern containing the final auxiliary pattern based on the detection result; if the verification result does not meet the preset accuracy requirement, then performing transfer training on the pre-trained auxiliary pattern generation Bayesian fully connected network based on the target mask pattern and the photolithography process simulation result, and obtaining a final auxiliary mask pattern containing the final auxiliary pattern based on the transferred trained auxiliary pattern generation Bayesian fully connected network.
[0016] To achieve the above and other related objectives, a second aspect of this application provides an auxiliary pattern generation system for a mask pattern based on a Bayesian network, comprising: an auxiliary pattern discrete parameter space construction module for constructing an auxiliary pattern discrete parameter space for a target mask pattern; wherein the auxiliary pattern discrete parameter space includes multiple sets of candidate auxiliary pattern discrete parameters; an optimal auxiliary pattern discrete parameter acquisition module for generating a Bayesian fully connected network based on a pre-trained auxiliary pattern to obtain intermediate feature data corresponding to the multiple sets of candidate auxiliary pattern discrete parameters; and, in conjunction with an optimization algorithm, determining at least one set of optimal auxiliary pattern discrete parameters from the multiple sets of candidate auxiliary pattern discrete parameters based on each intermediate feature data; an auxiliary mask pattern acquisition module for performing auxiliary pattern processing on the optimal auxiliary pattern discrete parameters to obtain an auxiliary mask pattern containing the auxiliary pattern; and a final auxiliary mask pattern acquisition module for performing photolithography process simulation verification on the auxiliary mask pattern and outputting a final auxiliary mask pattern containing the final auxiliary pattern based on the verification results.
[0017] To achieve the above and other related objectives, a third aspect of the present invention provides an electronic terminal, including a memory, a processor, and a computer program stored in the memory; the processor executes the computer program to implement the auxiliary graphic generation method for Bayesian network-based mask graphic.
[0018] As described above, the auxiliary image generation method, system, and terminal based on a Bayesian network for mask images of this application have the following beneficial effects: This invention constructs an auxiliary image discrete parameter space for the target mask image to obtain multiple sets of candidate auxiliary image discrete parameters; it obtains at least one set of optimal auxiliary image discrete parameters by generating a Bayesian fully connected network based on pre-trained auxiliary images and combining it with an optimization algorithm; it obtains an auxiliary mask image containing the auxiliary images by performing auxiliary image processing on the optimal auxiliary image discrete parameters; and it obtains a final auxiliary mask image containing the final auxiliary images by performing photolithography process simulation verification on the auxiliary mask image. Compared with traditional auxiliary image generation methods, this application significantly improves the auxiliary image generation efficiency and imaging accuracy by integrating the above-mentioned technical means. Attached Figure Description
[0019] Figure 1 The diagram shown is a flowchart illustrating an auxiliary graphic generation method for a mask graphic based on a Bayesian network according to an embodiment of the present invention.
[0020] Figure 2 The diagram shown is a schematic representation of the training process of a pre-trained auxiliary graph generation Bayesian fully connected network according to an embodiment of the present invention.
[0021] Figure 3The diagram shown is a schematic representation of the structure of an initial Bayesian fully connected network in one embodiment of the present invention.
[0022] Figure 4 The diagram shows a flowchart illustrating the training process of a fully connected network for each round of auxiliary graph generation in an embodiment of the present invention.
[0023] Figure 5 The diagram shows a flowchart of verifying an auxiliary mask pattern containing auxiliary graphics, according to an embodiment of the present invention.
[0024] Figure 6 The diagram shown is a schematic representation of an auxiliary graphic generation system for a mask graphic based on a Bayesian network, according to an embodiment of the present invention.
[0025] Figure 7 The diagram shown is an electronic terminal according to an embodiment of the present invention. Detailed Implementation
[0026] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. This application can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application. It should be noted that, unless otherwise specified, the following embodiments and features in the embodiments can be combined with each other.
[0027] It should be noted that in the following description, reference is made to the accompanying drawings, which illustrate several embodiments of the present invention. It should be understood that other embodiments may also be used. In the embodiments of the present invention, the terms "first," "second," etc., are used to distinguish identical or similar items with substantially the same function and effect, without limiting their order. Those skilled in the art will understand that the terms "first," "second," etc., do not limit the quantity or execution order, and that "first," "second," etc., are not necessarily different.
[0028] Furthermore, in the embodiments of the present invention, the words "exemplary" or "for example" indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in the present invention should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of the words "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.
[0029] Furthermore, in this embodiment of the invention, "at least one" refers to one or more, and "more than one" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can represent: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or multiple.
[0030] Before providing a further detailed description of the present invention, the nouns and terms used in the embodiments of the present invention are explained, and the nouns and terms used in the embodiments of the present invention are subject to the following interpretations:
[0031] <1> Optical Proximity Correction (OPC): Optical proximity correction is a key resolution enhancement technology in integrated circuit manufacturing. Its main purpose is to counteract the pattern distortion caused by the diffraction and interference effects of light in the photolithography system by fine-tuning and compensating the pattern shape on the mask in advance (such as adding auxiliary patterns or correcting corners). This ensures that the actual exposed pattern on the wafer is as consistent as possible with the design layout, thereby improving the reliability of the process and the accuracy of feature dimensions.
[0032] <2> Sub-Resolution Assist Features (SRAF): SRAF is an important resolution enhancement technique in integrated circuit lithography. It involves adding tiny auxiliary patterns, smaller than the resolution limit of the lithography machine's optical system, around the main pattern on the photomask. Without affecting the final wafer exposure pattern, it utilizes the optical proximity effect to improve the imaging quality of the main pattern and the process window, thereby enhancing the consistency of critical dimensions and pattern fidelity. It is a key means to achieve precise pattern transfer in deep submicron and below technology nodes.
[0033] <3> Mentor Calibre SRAF (Siemens EDA Calibre SRAF): Mentor Calibre SRAF is a core module in the industry-leading electronic design automation (EDA) tool suite, specifically designed for the automated generation and optimization of sub-resolution auxiliary features. Integrated into the Calibre physical verification and design for manufacturability platform, it uses advanced algorithms to analyze the graphic distribution and density of the design layout, and intelligently inserts, adjusts, and verifies the size, shape, and position of SRAFs according to the optical models and rules specific to the process, maximizing lithography window performance and chip manufacturing yield.
[0034] <4> Synopsys IC Compiler II (ICC II): Synopsys IC Compiler II is Synopsys' next-generation flagship physical implementation platform, a core tool in the digital integrated circuit design flow. At advanced process nodes, this tool automates the entire process from the gate-level netlist after logic synthesis to the final deliverable layout (GDSII). Its key features include an innovative multi-engine, memory-efficient architecture that enables parallel processing of critical steps such as placement, clock tree synthesis, routing, timing optimization, and design for manufacturability, significantly improving design convergence speed and optimizing chip power consumption, performance, and area targets.
[0035] <5> Kullback-Leibler Divergence (KLD): KL divergence is an asymmetric measure of the difference between two probability distributions. In integrated circuit design and manufacturing, especially in scenarios such as statistical static timing analysis and yield modeling at advanced process nodes, it is used to quantify the degree of information loss or difference between the actual distribution and the target distribution (or the distribution under different process corners) of circuit performance parameters (such as delay and power consumption). It is a key mathematical tool for assessing the impact of process variations and performing probabilistic design optimization.
[0036] <6> Mentor Calibre DRC (Siemens EDA Calibre Design Rule Checking): Mentor Calibre DRC is an industry-standard tool in the field of electronic design automation (EDA) for physical verification of integrated circuits. It automatically and thoroughly checks whether all geometries in the chip design layout (GDSII / OASIS format) and the design rule files provided by the specific semiconductor manufacturing process fully comply with the physical, electrical, and manufacturability constraints (such as linewidth, spacing, and coverage) set by the process. This ensures that the design does not violate any rules before delivery for manufacturing, and is a crucial step in guaranteeing the correctness of chip functionality and manufacturing yield.
[0037] The present invention provides a method, system, and terminal for generating auxiliary patterns based on Bayesian networks for mask patterns. This involves constructing an auxiliary pattern discrete parameter space for a target mask pattern to obtain multiple sets of candidate auxiliary pattern discrete parameters; generating a Bayesian fully connected network based on pre-trained auxiliary patterns and combining it with an optimization algorithm to obtain at least one set of optimal auxiliary pattern discrete parameters; performing auxiliary pattern processing on the optimal auxiliary pattern discrete parameters to obtain an auxiliary mask pattern containing the auxiliary patterns; and performing photolithography process simulation verification on the auxiliary mask pattern to obtain a final auxiliary mask pattern containing the final auxiliary patterns. The technical solutions in the embodiments of the present invention will be further described in detail below with reference to the embodiments and accompanying drawings. It should be understood that the specific embodiments described herein are only for explaining the present invention and are not intended to limit the invention.
[0038] like Figure 1 The diagram illustrates a flowchart of an auxiliary graphic generation method based on a Bayesian network mask pattern according to an embodiment of the present invention. The auxiliary graphic generation method based on a Bayesian network mask pattern in this embodiment includes the following steps:
[0039] Step S11: Construct an auxiliary graphic discrete parameter space for the target mask graphic; wherein the auxiliary graphic discrete parameter space includes multiple sets of candidate auxiliary graphic discrete parameters.
[0040] It should be understood that this step is the data preparation stage of the entire auxiliary pattern generation method. Its purpose is to construct an auxiliary pattern discrete parameter space that adapts to the target mask pattern and the requirements of the photolithography process, and to select an optimal set of auxiliary pattern discrete parameters from multiple sets of candidate auxiliary pattern discrete parameters in this auxiliary pattern discrete parameter space.
[0041] In one embodiment of this application, the construction of the auxiliary pattern discrete parameter space of the target mask pattern requires first combining the inherent characteristics of the target mask pattern, the photolithography process requirements, and the design requirements of the corresponding chip layout to complete the parameter attribute definition and parameter discretization processing of the auxiliary pattern (i.e., sub-resolution auxiliary feature pattern, hereinafter referred to as auxiliary pattern), ensuring that any combination of auxiliary pattern discrete parameters in the constructed auxiliary pattern discrete parameter space can meet the process feasibility requirements. The specific operation process of the parameter attribute definition and parameter discretization processing is as follows:
[0042] First, based on the functional requirements of the design chip corresponding to the target mask pattern, the pattern pitch, preset process error parameters (including exposure error, focal length error, mask manufacturing error, etc.), and the geometry of the target mask pattern, the type and basic parameters of the auxiliary pattern to be added are defined. The auxiliary pattern type includes edge type, vertex type, symmetry mode, etc., which can adapt to the structural requirements of different regions of the target mask pattern. The basic parameters include key process parameters such as the minimum size, maximum size, spacing from the main pattern, and center positioning coordinates of the auxiliary pattern. The values of all basic parameters follow the lithography process rules of advanced process nodes, and any combination of some or all of the basic parameters also meets the requirements of process feasibility.
[0043] Secondly, the aforementioned basic parameters are discretized. For different basic parameters, reasonable discretization steps and value ranges are set. For example, for continuous basic parameters such as size and spacing, uniform or gradient discretization can be used to generate discrete values (e.g., dividing the value range into steps of 0.1nm to 0.5nm based on the precision requirements of the photolithography process). For basic parameters strongly correlated with the target mask pattern, such as center positioning coordinates, discretization can be adapted to the coordinate system of the target mask pattern to ensure that the values of these basic parameters correspond to the position of the target mask pattern. Through the above discretization process, the continuous value range of each basic parameter is transformed into a finite set of discrete values. By combining the discrete values of each basic parameter, multiple sets of discrete parameters containing the basic parameters are formed. This set of discrete parameters is the auxiliary pattern discrete parameter space of the target mask pattern. The multiple combinations of basic parameters determined from this auxiliary pattern discrete parameter space are multiple sets of candidate auxiliary pattern discrete parameters. It should be noted that the dimension of this auxiliary pattern discrete parameter space must match the dimension of the input layer of the pre-trained Bayesian fully connected network for generating auxiliary patterns.
[0044] Step S12: Generate a Bayesian fully connected network based on the pre-trained auxiliary graphs to obtain intermediate feature data corresponding to the discrete parameters of the multiple sets of candidate auxiliary graphs; combine the optimization algorithm to determine at least one set of optimal auxiliary graph discrete parameters from the multiple sets of candidate auxiliary graph discrete parameters based on each intermediate feature data.
[0045] It should be understood that this step is the core reasoning and screening step of the auxiliary pattern generation method. The purpose is to rely on the pre-trained Bayesian fully connected network and the selection algorithm for auxiliary pattern generation to select at least one set of optimal auxiliary pattern discrete parameters that are suitable for the photolithography process from multiple sets of candidate auxiliary pattern discrete parameters in the auxiliary pattern discrete parameter space of step S11, so as to provide parameter support for the subsequent generation of auxiliary mask pattern containing auxiliary patterns.
[0046] In some optional implementations, relying on a pre-trained Bayesian fully connected network for auxiliary pattern generation and an optimization algorithm, the specific implementation process of selecting at least one set of optimal auxiliary pattern discrete parameters that are suitable for the lithography process from multiple sets of candidate auxiliary pattern discrete parameters in the auxiliary pattern discrete parameter space of step S11 is as follows:
[0047] Input of multiple sets of candidate auxiliary graphic discrete parameters and generation of intermediate feature data: The multiple sets of candidate auxiliary graphic discrete parameters in the auxiliary graphic discrete parameter space constructed in step S11 are input into a pre-trained Bayesian fully connected network for auxiliary graphic generation. After passing through the Bayesian fully connected network for auxiliary graphic generation, the intermediate feature data corresponding to each set of candidate auxiliary graphic discrete parameters is output. The input method can be batch input or sequential input, depending on the needs of the scenario.
[0048] It should be noted that the pre-trained Bayesian fully connected network for auxiliary image generation has established a mapping relationship from discrete parameters of auxiliary images to intermediate feature data and then to lithographic imaging quality. The intermediate feature data corresponding to each set of candidate discrete parameters of auxiliary images are high-dimensional feature vectors. Although they have no direct physical meaning, they have a one-to-one mapping relationship with the probabilistic evaluation results of the corresponding candidate discrete parameters of auxiliary images (i.e., the probability of good or bad lithographic imaging quality corresponding to the candidate discrete parameters of auxiliary images), and are an important basis for subsequent selection of optimal discrete parameters of auxiliary images.
[0049] Optimal selection based on intermediate feature data: An optimization algorithm uses the intermediate feature data corresponding to the discrete parameters of each group of candidate auxiliary graphics as the selection object. Combined with the mapping relationship established during the training of the Bayesian fully connected network for generating auxiliary graphics, the probabilistic evaluation results corresponding to each intermediate feature data are indirectly derived, and then all intermediate feature data are sorted and selected. The optimization algorithm can employ a full-traversal scoring and sorting algorithm or an equivalent global extremum selection algorithm, which can be flexibly chosen based on the size of the discrete parameters of multiple groups of candidate auxiliary graphics. The full-traversal scoring and sorting algorithm includes weighted scoring methods, distance sorting methods, etc., which traverse all intermediate feature data corresponding to the discrete parameters of all candidate auxiliary graphics, calculate the comprehensive score or feature distance of each intermediate feature data based on the mapping relationship between the intermediate feature data and its implicit probabilistic evaluation results, and then sort and evaluate them according to the score from high to low (or the distance from near to far), selecting the intermediate feature data with the best evaluation. The equivalent global extremum selection algorithm includes Bayesian optimization algorithms, evolutionary algorithms (including genetic algorithms), particle swarm optimization algorithms, etc., which do not require traversing all intermediate feature data and quickly locate the optimal intermediate feature data through a global search strategy. After screening using the above-mentioned optimization algorithm, one or more sets of intermediate feature data are finally determined as the optimal intermediate feature data.
[0050] Inverse determination of optimal auxiliary graphic discrete parameters: Since there is a one-to-one correspondence between intermediate feature data and candidate auxiliary graphic discrete parameters, after determining the optimal intermediate feature data, the candidate auxiliary graphic discrete parameters corresponding to the optimal intermediate feature data are located through inverse mapping, which is at least one set of optimal auxiliary graphic discrete parameters.
[0051] In one embodiment of this application, after determining the optimal intermediate feature data, the optimal intermediate feature data can be converted into corresponding optimal auxiliary graphical discrete parameters using an auxiliary graphical processing tool. The auxiliary graphical processing tool can be Mentor Calibre SRAF, Synopsys IC Compiler II, etc.
[0052] In some optional implementations, the specific method by which the aforementioned auxiliary image processing tool performs the conversion includes: while inputting multiple sets of candidate auxiliary image discrete parameters into a pre-trained auxiliary image generation Bayesian fully connected network to generate corresponding intermediate feature data, the auxiliary image processing tool simultaneously establishes a unique index association table between the candidate auxiliary image discrete parameters and the intermediate feature data. Subsequently, the auxiliary image processing tool can quickly match the corresponding candidate auxiliary image discrete parameters based on the optimal intermediate feature data by retrieving this unique index association table. It should also be noted that this auxiliary image processing tool can also be directly used for subsequent auxiliary image processing of the optimal auxiliary image discrete parameters, thus realizing the conversion from the optimal auxiliary image discrete parameters to an auxiliary mask image containing the auxiliary image.
[0053] In one embodiment of this application, the pre-trained auxiliary graph generation Bayesian fully connected network is obtained through at least one round of iterative training and optimization, such as... Figure 2 As shown, the training process of the pre-trained auxiliary graph generation Bayesian fully connected network includes:
[0054] Step S21: Obtain the initial Bayesian fully connected network and construct the training auxiliary graph discrete parameter space of the training mask graph; wherein, the initial Bayesian fully connected network includes a preset prior distribution of trainable parameters.
[0055] Specifically, firstly, an initial Bayesian fully connected network is constructed. This initial Bayesian fully connected network has a pre-defined prior distribution of trainable parameters (such as a normal distribution, Laplace distribution, etc.). This prior distribution is a fixed distribution set before training begins, based on the characteristics of the lithography process and the structure of the initial Bayesian fully connected network. It is used to constrain the initial distribution range of the trainable parameters of the initial Bayesian fully connected network, ensuring that the values of the trainable parameters conform to the logic of advanced lithography processes. This lays the foundation for the trainable parameters to converge to the posterior distribution adapted to the lithography process during subsequent training. Secondly, a training auxiliary graphic discrete parameter space corresponding to the training mask pattern is constructed. This training auxiliary graphic discrete parameter space is used to provide the input data required for the subsequent training of the initial Bayesian fully connected network. Its construction logic (including parameter type definition method, parameter discretization processing method, etc.) is completely consistent with the construction logic of the auxiliary graphic discrete parameter space of the target mask pattern in step S11, and will not be repeated here.
[0056] Step S22: Based on the training auxiliary graph discrete parameter space, train the initial Bayesian fully connected network for at least one round of auxiliary graph generation fully connected network training to obtain a pre-trained auxiliary graph generation Bayesian fully connected network.
[0057] It should be understood that the training of the auxiliary graph generation fully connected network is an iterative optimization process. The initial Bayesian fully connected network serves as the training starting point, and its initial values for trainable parameters are sampled from the preset prior distribution to ensure that the initial settings of the trainable parameters meet the process requirements. In each round of training, a batch of training auxiliary graph discrete parameters required for that round is randomly selected from the training auxiliary graph discrete parameter space as training data, and a complete auxiliary graph generation fully connected network training process is executed. After each round of training, an overall training loss value reflecting the convergence state is obtained.
[0058] Training terminates based on whether the overall training loss value meets a preset convergence condition: if the preset convergence condition is met, the Bayesian fully connected network completed in the current training round is used as a pre-trained auxiliary graph to generate the Bayesian fully connected network output; if the preset convergence condition is not met, the Bayesian fully connected network completed in the current training round with updated trainable parameters is used as the training object for the next round of training to continue iterative optimization. Through iterative training, the posterior distribution of the trainable parameters of the Bayesian fully connected network, under the constraint of a preset prior distribution, gradually converges to the optimal state that adapts to the imaging quality requirements and conforms to the lithography process logic.
[0059] In one embodiment of this application, as Figure 3The constructed initial Bayesian fully connected network includes an input layer, an output layer, and two hidden layers. Its specific structure can be referenced from existing Bayesian fully connected neural network constructions. The input layer receives discrete parameter data of the training auxiliary graph in the discrete parameter space, and the output layer outputs the corresponding output data (i.e., the intermediate training feature data mentioned later in the training process). The two hidden layers contain trainable parameters, and the purpose of training is primarily to optimize and update the trainable parameters of these two hidden layers.
[0060] In one embodiment of this application, as Figure 4 As shown, the training process for each round of auxiliary graph generation fully connected network training includes:
[0061] Step S41: Determine the Bayesian fully connected network to be trained in this round.
[0062] It should be noted that the Bayesian fully connected network to be trained in this round is determined according to the training round: if this round of training is the first training, then the Bayesian fully connected network to be trained in this round is the initial Bayesian fully connected network; if this round of training is not the first training, then the Bayesian fully connected network to be trained in this round is the Bayesian fully connected network after the previous training was completed and the trainable parameters were updated.
[0063] Step S42: Obtain the discrete parameters of the training auxiliary graphics required for this round from the discrete parameter space of the training auxiliary graphics, input them into the Bayesian fully connected network to be trained in this round, and obtain the corresponding intermediate training feature data; convert the intermediate training feature data into a training auxiliary mask graphic containing the training auxiliary graphics, perform photolithography process simulation calculation on the training auxiliary mask graphic, and obtain the photolithography simulation graphic outline.
[0064] Specifically, from the training auxiliary graphic discrete parameter space constructed in step S21, the discrete parameters of the training auxiliary graphics required for this round of training (one batch includes multiple sets of training auxiliary graphic discrete parameters) are selected and input into the Bayesian fully connected network to be trained in this round as determined in step S31. After inference by the Bayesian fully connected network to be trained in this round, the intermediate training feature data corresponding one-to-one with each set of training auxiliary graphic discrete parameters are output. Next, using the auxiliary graphic processing tools mentioned above (such as Mentor Calibre SRAF, Synopsys IC Compiler II, etc.), each training intermediate feature data is converted into training auxiliary mask template graphics containing training auxiliary graphics. Then, based on the preset lithography process parameters (including exposure dose, focal length, photoresist performance, etc.), lithography process simulation calculations are performed on each training auxiliary mask template graphic to simulate the actual lithography imaging process, and finally, multiple sets of lithography simulation graphic contours that can reflect the lithography effect are obtained.
[0065] In some alternative implementations, the exposure intensity of the training auxiliary mask pattern is characterized by photolithography process simulation calculations, and can be represented by the following formula to simulate the light intensity distribution during the photolithography imaging process:
[0066] ;(Formula 1)
[0067] In formula 1, For exposure intensity; ( () represents the imaging position coordinates; It is the optical cross-transfer function, used to characterize the transmission characteristics of an optical system for signals of different frequencies; This refers to the spatial sampling frequency; To train the spectral distribution of the transmission coefficient of the auxiliary mask pattern; It is its conjugate.
[0068] Among them, optical cross transfer function This can be further characterized by the following formula:
[0069] ;(Formula 2)
[0070] In formula 2, This is the cross-correlation function of the light source, used to reflect the degree of correlation between different spectra; The pupil frequency response is used to characterize the filtering characteristics of the pupil of an optical system for frequency signals. It is its conjugate.
[0071] For coherent imaging systems, the optical cross-transfer function This can be further expanded into the following form:
[0072] ;(Formula 3)
[0073] In formula 3, For the imaging kernel of the optical system; Its conjugate; For the first The weighting coefficients corresponding to each imaging kernel; This represents the total number of equivalent convolution kernels. According to the unfolded form of Equation 3, the lithographic imaging intensity can be transformed into a more computationally efficient convolutional form:
[0074] ;(Formula 4)
[0075] In Formula 4, ⊗ represents the convolution operation; M is the spatial domain distribution of the training auxiliary mask pattern. This convolution formula can quickly solve for the exposure intensity at different locations, improving the efficiency of simulation calculations.
[0076] To obtain the lithographic simulation pattern contour from the exposure intensity, the exposure intensity result calculated by formula (4) is binarized using a threshold truncation method. The specific processing method is as follows:
[0077] ;(Formula 5)
[0078] In Formula 5, counter is the result of binarization, used to characterize the outline of the photolithography simulation pattern; thres is the preset exposure intensity threshold, the value of which is determined according to the photoresist photosensitive characteristics and actual process requirements.
[0079] It should be understood that, after binarization, the exposure intensity area with a value of 1 corresponds to the effective contour of the lithographic simulation pattern, and the exposure intensity area with a value of 0 corresponds to the ineffective contour of the lithographic simulation pattern; the final output binarization result is the contour of the lithographic simulation pattern.
[0080] Step S43: Obtain the imaging quality loss cost based on the lithographic simulation pattern outline and the training design layout corresponding to the training mask pattern.
[0081] In some optional implementations, the imaging quality loss cost value can be obtained through positional deviation statistics of the lithographic simulation graphic contour and the training design layout corresponding to the training mask graphic. The specific process includes: First, multiple detection points are preset on the training design layout. The distribution of the detection points should include the core graphic area, edge contour, and key feature positions of the training design layout. The density of the detection points is determined according to the complexity of the training design layout and the precision requirements of the lithography process to ensure that the subsequent deviation statistics are accurate and comprehensive. Second, based on the preset positional information (e.g., coordinate information) of the detection points, the actual positional information of the lithographic simulation graphic contour at each corresponding detection point is obtained. Then, it is compared with the preset positional information of the detection points on the training design layout to obtain the positional deviation corresponding to each detection point (which can be expressed by Euclidean distance, Manhattan distance, etc.). Finally, the positional deviations of all detection points are statistically analyzed, and the statistical values of all positional deviations (e.g., mean deviation, variance, maximum deviation, etc.) are calculated. The statistical values are substituted into a preset imaging quality loss cost function to be converted into the corresponding imaging quality loss cost value. Among them, the cost of imaging quality loss is positively correlated with the positional deviation: the higher the cost of imaging quality loss, the greater the positional deviation between the lithographic simulation pattern outline and the training design layout, and the worse the imaging quality; conversely, the lower the cost of imaging quality loss, the smaller the positional deviation between the lithographic simulation pattern outline and the training design layout, and the better the imaging quality.
[0082] In one embodiment of this application, positional deviation is calculated using coordinate comparison. Specifically, this includes: setting coordinate axes based on the training design layout, obtaining the coordinate information of preset detection points and the actual coordinate information of the lithographic simulation pattern contour at the corresponding detection points, and obtaining the positional deviation of each detection point by comparing the coordinate information of the two.
[0083] In one embodiment of this application, the preset imaging quality loss cost function is characterized by the following formula:
[0084] ;(Formula 6)
[0085] In Formula 6, cost is the cost of image quality loss; The actual coordinates of the lithographic simulation pattern outline at the corresponding i-th detection point; To train the coordinates of the i-th detection point on the design layout; This represents the preset total number of detection points; For the first The weight coefficient of each detection point is determined based on factors such as the importance of the detection point (e.g., the weight of detection points in the core graphic area is higher than that in the edge area) and the sensitivity of the photolithography process, and is used to highlight the impact of key position deviations on imaging quality.
[0086] Step S44: Based on the log-likelihood estimate of the image quality loss cost transformation and the KL divergence values of the posterior and prior distributions of the trainable parameters of the Bayesian fully connected network to be trained in this round, obtain the negative evidence lower bound loss value of the Bayesian fully connected network to be trained in this round.
[0087] Specifically, firstly, the imaging quality loss values obtained in step S43, which correspond one-to-one with the intermediate training feature data, are converted into log-likelihood estimates. These log-likelihood estimates characterize the degree of fit between the lithographic imaging quality corresponding to the intermediate training feature data and the training design layout in this round of training. A higher log-likelihood estimate indicates a better fit between the lithographic simulation graphic contour corresponding to the intermediate feature data output by the Bayesian fully connected network to be trained in this round and the training design layout, resulting in better imaging quality. Secondly, the value of the Bayesian fully connected network to be trained in this round is calculated... The KL divergence value between the posterior distribution of the trainable parameters of the network and the prior distribution preset in step S21 is used to characterize the degree of difference between the posterior and prior distributions. The smaller the KL divergence value, the closer the posterior distribution of the trainable parameters is to the reasonable range of the process defined by the prior distribution. Finally, the log-likelihood estimate and the KL divergence value are substituted into the preset negative evidence lower bound loss function to calculate the negative evidence lower bound loss value for this round of training.
[0088] In some optional implementations, the preset negative evidence lower bound loss function is characterized by the following formula:
[0089] ;(Formula 7)
[0090] In formula 7, This is the lower bound loss value for the negative evidence; This is the log-likelihood estimate; The KL divergence value is given. It should be noted that the log-likelihood estimate is negatively correlated with the imaging quality loss cost; that is, the lower the imaging quality loss cost (the better the lithographic imaging quality), the higher the converted log-likelihood estimate.
[0091] Step S45: Obtain the overall training loss value based on the image quality loss cost and the negative evidence lower bound loss value.
[0092] Specifically, the imaging quality loss value obtained in step S43 and the negative evidence lower bound loss value obtained in step S44 are substituted into the preset overall training loss function to calculate the overall training loss value for this round of training, and the preset convergence condition is determined based on the overall training loss value.
[0093] In some optional implementations, the preset overall training loss function is characterized by the following formula:
[0094] ;(Formula 8)
[0095] In formula 8, This is the overall training loss value; The cost of the aforementioned imaging quality loss; The lower bound loss value for the negative evidence is given.
[0096] Step S46: Determine whether the overall training loss value meets the preset convergence condition; if it does, use the Bayesian fully connected network completed in this round of training as an auxiliary graph to generate a Bayesian fully connected network; if it does not meet the condition, use the Bayesian fully connected network completed in this round of training as the Bayesian fully connected network for the next round of training.
[0097] Specifically, if the overall training loss value meets the preset convergence condition (e.g., the overall training loss value is less than the preset convergence threshold), then the training terminates, and the Bayesian fully connected network completed in this round of training is used as a pre-trained auxiliary graph to generate a Bayesian fully connected network; if the overall training loss value does not meet the preset convergence condition, then the trainable parameters of the Bayesian fully connected network completed in this round of training are optimized and updated, and the updated Bayesian fully connected network is used as the Bayesian fully connected network to be trained in the next round of training, and the iterative training continues.
[0098] In one embodiment of this application, the optimization and updating of trainable parameters can be achieved through an optimization tool, such as the Adam optimizer. Specifically, the optimization and updating of trainable parameters mainly targets the trainable parameters of the two hidden layers in the Bayesian fully connected network structure. By adjusting the trainable parameters of the two hidden layers, the overall training loss value is gradually optimized, making the posterior distribution of the trainable parameters of the Bayesian fully connected network closer to the optimal distribution.
[0099] Step S13: Perform auxiliary graphic processing on the optimal auxiliary graphic discrete parameters to obtain an auxiliary mask graphic containing the auxiliary graphic.
[0100] In some optional implementations, the auxiliary graphics processing tools mentioned above (such as MentorCalibre SRAF, Synopsys IC Compiler II, etc.) are used to perform auxiliary graphics transformation processing on the optimal auxiliary graphics discrete parameters to generate an auxiliary mask graphic containing the auxiliary graphics.
[0101] Step S14: Perform photolithography process simulation verification on the auxiliary mask pattern containing the auxiliary pattern, and output the final auxiliary mask pattern containing the final auxiliary pattern according to the verification results.
[0102] It should be noted that this step mainly verifies the auxiliary mask pattern containing the auxiliary pattern to ensure that it meets the imaging accuracy requirements and process compliance requirements, such as... Figure 5 As shown, the specific verification process includes:
[0103] 1. Preliminary verification of photolithography process simulation: Perform photolithography process simulation on the auxiliary mask pattern containing the auxiliary pattern (e.g., use formulas 1 to 5 for photolithography process simulation calculation), and verify the photolithography process simulation results to determine whether the photolithography process simulation results meet the preset imaging accuracy requirements. The photolithography process simulation results include imaging quality indicators (e.g., the imaging quality loss cost calculated using formula 6).
[0104] If the simulation results of the photolithography process meet the preset imaging accuracy requirements, then proceed to the subsequent comprehensive testing and verification stage;
[0105] If the simulation results of the photolithography process do not meet the preset imaging accuracy requirements, the process will proceed to the retraining and optimization stage of the auxiliary image generation Bayesian fully connected network.
[0106] 2. Network Retraining Optimization: If the lithography process simulation results in the preliminary verification stage do not meet the preset imaging accuracy requirements, the auxiliary pattern generation Bayesian fully connected network is retrained. Since the trainable parameters of the auxiliary pattern generation Bayesian fully connected network have formed a mapping relationship between the candidate auxiliary pattern discrete parameters in the auxiliary pattern discrete parameter space of the target mask pattern and the lithography process imaging quality, under the same process conditions, only a small amount of retraining is required for the auxiliary pattern generation Bayesian fully connected network to achieve rapid iterative optimization of the network.
[0107] In some optional implementations, a transfer learning process is employed to achieve rapid optimization of the Bayesian fully connected network for auxiliary graph generation, specifically including:
[0108] Prepare fine-tuning data: Take the discrete parameter set of the auxiliary pattern of the current target auxiliary mask pattern that has not been preliminarily verified by the photolithography process simulation, and its corresponding photolithography process simulation results (such as the cost of imaging quality loss) as new training samples.
[0109] Transfer training is performed: a pre-trained Bayesian fully connected network for auxiliary image generation is used as the initial network. A small learning rate is adopted, and a few iterations of retraining are conducted using newly added training samples (which can be combined with some of the original training data). Thanks to the fact that the trainable parameters of this Bayesian fully connected network for auxiliary image generation have formed a mapping relationship between the candidate discrete parameters of auxiliary images in the discrete parameter space of the target mask image and the imaging quality of the lithography process, this transfer training process can converge quickly, and usually only a few iterations are needed to adapt the network to the new image scene.
[0110] A Bayesian fully connected network is generated using the auxiliary graphics trained by transfer learning. Steps S12 and S13 are re-executed based on the discrete parameter space of the auxiliary graphics of the target mask graphic to generate a new auxiliary mask graphic containing the auxiliary graphics. The photolithography process simulation is then performed again on the new auxiliary mask graphic containing the auxiliary graphics for preliminary verification until the verification is passed and the final auxiliary mask graphic containing the final auxiliary graphics is output.
[0111] In one embodiment of this application, when constructing the auxiliary graphic discrete parameter space of the target mask graphic, if some of the auxiliary graphic discrete parameters (such as graphic spacing and maximum width) have been determined to be fixed values due to process constraints, the mapping relationship between the remaining free auxiliary graphic discrete parameters and the lithographic simulation imaging quality can still be optimized through transfer training to achieve the effective addition of auxiliary graphics to meet the preset imaging accuracy requirements.
[0112] 3. Comprehensive Testing and Verification: If the lithography process simulation results in the initial verification stage meet the preset imaging accuracy requirements, then the auxiliary mask pattern containing auxiliary patterns will undergo subsequent dual process compliance testing (i.e., process rule testing) to ensure its suitability for actual lithography production needs.
[0113] Process geometry rule detection: Using a process rule detection tool (such as Mentor Calibre DRC), the auxiliary mask pattern containing auxiliary graphics is checked to see if it conforms to preset geometric rules. The preset geometric rules include minimum spacing between graphics, minimum width between graphics, and geometric topological relationships of graphics.
[0114] High-fidelity lithography simulation inspection: Using higher precision lithography process simulation calculations, stricter process window parameters, and simulation conditions that are closer to the extreme conditions of mass production, the auxiliary mask pattern is simulated again to verify whether the lithography process simulation results meet the preset higher imaging accuracy requirements.
[0115] 4. Final auxiliary mask graphic output:
[0116] If the lithography process simulation results in the preliminary verification stage meet the preset imaging accuracy requirements, and the auxiliary mask image containing the auxiliary image passes all the detection items in the comprehensive verification of process geometry rules and high-fidelity lithography simulation, then the auxiliary mask image containing the auxiliary image is output as the final auxiliary mask image containing the final auxiliary image. If the lithography process simulation results in the preliminary verification stage meet the preset imaging accuracy requirements, but the auxiliary mask image containing the auxiliary image fails to pass any of the detection items in the comprehensive verification of process geometry rules and high-fidelity lithography simulation, then the Bayesian fully connected network generated by the auxiliary image is subjected to the above-mentioned network retraining optimization operation according to the reason for failure.
[0117] like Figure 6 The diagram illustrates the structure of an auxiliary image generation system 600 based on a Bayesian network mask pattern according to an embodiment of the present invention. The Bayesian network-based auxiliary image generation system 600 in this embodiment includes: an auxiliary image discrete parameter space construction module 601, an optimal auxiliary image discrete parameter acquisition module 602, an auxiliary mask pattern acquisition module 603, and a final auxiliary mask pattern acquisition module 604.
[0118] The auxiliary graphic discrete parameter space construction module 601 is used to construct the auxiliary graphic discrete parameter space of the target mask graphic; wherein, the auxiliary graphic discrete parameter space includes multiple sets of candidate auxiliary graphic discrete parameters;
[0119] The optimal auxiliary graph discrete parameter acquisition module 602 is used to generate a Bayesian fully connected network based on a pre-trained auxiliary graph to obtain intermediate feature data corresponding to the discrete parameters of the multiple sets of candidate auxiliary graphs respectively; and, in combination with the selection algorithm, to determine at least one set of optimal auxiliary graph discrete parameters from the multiple sets of candidate auxiliary graph discrete parameters based on each intermediate feature data.
[0120] The auxiliary mask pattern acquisition module 603 is used to perform auxiliary pattern processing on the discrete parameters of the optimal auxiliary pattern to obtain an auxiliary mask pattern containing the auxiliary pattern.
[0121] The final auxiliary mask pattern acquisition module 604 is used to perform photolithography process simulation verification on the auxiliary mask pattern, and output the final auxiliary mask pattern containing the final auxiliary pattern according to the verification result.
[0122] It should be noted that the implementation principle and process of the Bayesian network-based mask template auxiliary graphic generation system provided in this embodiment are similar to the Bayesian network-based mask template auxiliary graphic generation method described above, and will not be repeated here. The specific process of each module performing the above-mentioned corresponding steps has been described in detail in the above method embodiments, and will not be repeated here for the sake of brevity.
[0123] It should also be understood that the module division in the embodiments of the present invention is illustrative and only represents one logical functional division; in actual implementation, there may be other division methods. Furthermore, the functional modules in the various embodiments of the present invention can be integrated into a single processor, exist as separate physical entities, or two or more modules can be integrated into a single module. The integrated modules described above can be implemented in hardware or as software functional modules.
[0124] like Figure 7 The diagram shown is a schematic of an electronic terminal provided in an embodiment of this application. The electronic terminal includes at least one processor 701, a memory 702, at least one network interface 703, and a user interface 705. The various components in the device are coupled together via a bus system 704. It is understood that the bus system 704 is used to implement communication between these components. In addition to a data bus, the bus system 704 also includes a power bus, a control bus, and a status signal bus. However, for clarity, ... Figure 7 The general will label all buses as bus systems.
[0125] The user interface 705 may include a monitor, keyboard, mouse, trackball, clicker, button, touchpad, or touch screen.
[0126] It is understood that memory 702 can be volatile memory or non-volatile memory, or both. Non-volatile memory can be read-only memory (ROM) or programmable read-only memory (PROM), which serves as an external cache. By way of example, but not limitation, many forms of RAM are available, such as static random access memory (SRAM) and synchronous static random access memory (SSRAM). The memories described in the embodiments of this invention are intended to include, but are not limited to, these and any other suitable categories of memory.
[0127] In this embodiment of the invention, the memory 702 is used to store various types of data to support the operation of the electronic terminal 700. Examples of this data include: any executable program for operation on the electronic terminal 700, such as the operating system 7021 and application program 7022; the operating system 7021 contains various system programs, such as the framework layer, core library layer, driver layer, etc., for implementing various basic services and handling hardware-based tasks. The application program 7022 may contain various applications, such as a media player, browser, etc., for implementing various application services. The method for testing the lateral positioning accuracy of agricultural machinery provided in this embodiment of the invention can be included in the application program 7022.
[0128] The methods disclosed in the above embodiments of the present invention can be applied to processor 701, or implemented by processor 701. Processor 701 may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method can be completed by the integrated logic circuit of the hardware in processor 701 or by instructions in software form. The processor 701 may be a general-purpose processor, a digital signal processor (DSP), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. Processor 701 can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of the present invention. General-purpose processor 701 may be a microprocessor or any conventional processor, etc. The steps of the accessory optimization method provided in the embodiments of the present invention can be directly reflected as being executed by a hardware decoding processor, or being executed by a combination of hardware and software modules in the decoding processor. The software module may be located in a storage medium, which is located in memory. The processor reads the information in the memory and combines it with its hardware to complete the steps of the aforementioned method.
[0129] In an exemplary embodiment, the electronic terminal 700 may be used to execute the aforementioned method by one or more application-specific integrated circuits (ASICs), DSPs, programmable logic devices (PLDs), or complex programmable logic devices (CPLDs).
[0130] As used in this specification, the terms "component," "module," "system," etc., are used to refer to computer-related entities, hardware, firmware, combinations of hardware and software, software, or software in execution. For example, a component can be, but is not limited to, a process running on a processor, a processor, an object, an executable file, an execution thread, a program, and / or a computer. As illustrated, applications running on computing devices and computing devices can both be components. One or more components may reside in a process and / or an execution thread, and components may be located on a single computer and / or distributed among two or more computers. Furthermore, these components can be executed from various computer-readable media on which various data structures are stored. Components can communicate, for example, via local and / or remote processes based on signals having one or more data packets (e.g., data from two components interacting with another component between a local system, a distributed system, and / or a network, such as the Internet interacting with other systems via signals).
[0131] Those skilled in the art will recognize that the various illustrative logical blocks and steps described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this application.
[0132] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.
[0133] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.
[0134] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.
[0135] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.
[0136] In the above embodiments, the functions of each functional unit can be implemented entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially in the form of a computer program product. A computer program product includes one or more computer instructions (programs). When the computer program instructions (programs) are loaded and executed on a computer, all or part of the flow or function according to the embodiments of this application is generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. Computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available media can be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., high-density digital video discs, DVDs), or semiconductor media (e.g., solid-state disks, SSDs, etc.).
[0137] If a function is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.
[0138] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.
[0139] In summary, the auxiliary image generation method, system, and terminal based on Bayesian networks provided by this invention construct an auxiliary image discrete parameter space for the target mask image to obtain multiple sets of candidate auxiliary image discrete parameters; obtain at least one set of optimal auxiliary image discrete parameters by generating a Bayesian fully connected network based on pre-trained auxiliary images and combining it with an optimization algorithm; obtain an auxiliary mask image containing the auxiliary images by performing auxiliary image processing on the optimal auxiliary image discrete parameters; and obtain a final auxiliary mask image containing the final auxiliary images by performing photolithography process simulation verification on the auxiliary mask image. Compared with traditional auxiliary image generation methods, this application significantly improves the auxiliary image generation efficiency and imaging accuracy by integrating the above-mentioned technical means.
[0140] Therefore, this application effectively overcomes the various shortcomings of the prior art and has high industrial application value.
[0141] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this application. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this application should still be covered by the claims of this application.
Claims
1. A method for generating an auxiliary pattern based on a mask pattern using a Bayesian network, the method comprising: obtaining a mask pattern; obtaining a Bayesian network; and generating an auxiliary pattern based on the mask pattern and the Bayesian network. include: Construct an auxiliary graphic discrete parameter space for the target mask graphic; wherein, the auxiliary graphic discrete parameter space includes multiple sets of candidate auxiliary graphic discrete parameters; Based on a pre-trained Bayesian fully connected network for generating auxiliary graphs, intermediate feature data corresponding to the discrete parameters of the multiple sets of candidate auxiliary graphs are obtained. The intermediate feature data are high-dimensional feature vectors and have a one-to-one mapping relationship with the probabilistic evaluation results of the corresponding candidate auxiliary graph discrete parameters. Combined with the optimization algorithm, based on the probabilistic evaluation results corresponding to each intermediate feature data, at least one set of optimal auxiliary graph discrete parameters is determined from the multiple sets of candidate auxiliary graph discrete parameters. The training process of the pre-trained auxiliary graph generation Bayesian fully connected network includes: An initial Bayesian fully connected network is obtained, and a training auxiliary graph discrete parameter space for training mask graphs is constructed; wherein, the initial Bayesian fully connected network includes a preset prior distribution of trainable parameters; based on the training auxiliary graph discrete parameter space, the initial Bayesian fully connected network is trained with an auxiliary graph generation fully connected network for at least one round to obtain a pre-trained auxiliary graph generation Bayesian fully connected network. The training process for each round of training the fully connected network for auxiliary graph generation includes: Determine the Bayesian fully connected network to be trained in this round; obtain the discrete parameters of the training auxiliary graphics required for this round from the discrete parameter space of the training auxiliary graphics, input them into the Bayesian fully connected network to be trained in this round, and obtain the corresponding intermediate training feature data; convert the intermediate training feature data into a training auxiliary mask graphic containing the training auxiliary graphics, and perform photolithography process simulation calculation on the training auxiliary mask graphic to obtain the photolithography simulation graphic outline; Multiple detection points are preset on the training design layout corresponding to the training mask pattern. The positional deviation between the contour of the lithographic simulation pattern and the training design layout at the corresponding detection points is calculated. Based on the statistical value of the positional deviation, the imaging quality loss cost is obtained. Based on the log-likelihood estimate of the cost transformation of the imaging quality loss, and the KL divergence between the posterior and prior distributions of the trainable parameters of the Bayesian fully connected network to be trained in this round, the negative evidence lower bound loss value of the Bayesian fully connected network to be trained in this round is obtained. Based on the image quality loss cost and the negative evidence lower bound loss value, the overall training loss value is obtained; it is determined whether the overall training loss value meets the preset convergence condition; if it does, the Bayesian fully connected network completed in this round of training is used as an auxiliary graph to generate a Bayesian fully connected network; if it does not meet the condition, the Bayesian fully connected network completed in this round of training is used as the Bayesian fully connected network for the next round of training. The optimal auxiliary graphic discrete parameters are subjected to auxiliary graphic processing to obtain an auxiliary mask graphic containing the auxiliary graphic. The auxiliary mask pattern is subjected to photolithography process simulation verification, and the final auxiliary mask pattern containing the final auxiliary pattern is output based on the verification results; The process of performing photolithography process simulation verification on the auxiliary mask pattern and outputting the final auxiliary mask pattern containing the final auxiliary pattern based on the verification results includes: The auxiliary mask pattern is subjected to photolithography process simulation, and the photolithography process simulation is verified based on the simulation results. If the verification result meets the preset imaging accuracy requirements, then the process rule detection is performed on the lithography process simulation result, and the final auxiliary mask pattern containing the final auxiliary pattern is output according to the detection result; If the verification result does not meet the preset imaging accuracy requirements, the auxiliary pattern discrete parameter group that failed the photolithography process simulation verification and its corresponding photolithography process simulation results are used as new training samples. The pre-trained auxiliary pattern generation Bayesian fully connected network is then transferred and trained to obtain the transferred-trained auxiliary pattern generation Bayesian fully connected network. Based on the transferred-trained auxiliary pattern generation Bayesian fully connected network, the optimal auxiliary pattern discrete parameters are re-determined, and an auxiliary mask pattern containing the auxiliary pattern is regenerated. The regenerated auxiliary mask pattern is then subjected to photolithography process simulation verification again until the photolithography process simulation verification result meets the preset imaging accuracy requirements. Finally, the final auxiliary mask pattern containing the final auxiliary pattern is output.
2. The method according to claim 1, wherein, The overall training loss value is calculated using the following formula: ; wherein, is the overall training loss value; is the imaging quality loss value; is the negative evidence lower bound loss value.
3. The auxiliary pattern generation method of a mask pattern based on a Bayesian network according to claim 1 or 2, characterized in that, The lower bound loss value for negative evidence is calculated using the following formula: ; in, This is the lower bound loss value for the negative evidence; This is the log-likelihood estimate; The KL divergence value is given; the log-likelihood estimate is negatively correlated with the cost of the imaging quality loss.
4. The method for generating auxiliary graphics based on Bayesian network template graphics according to claim 1, characterized in that, Combining the selection algorithm, at least one set of optimal auxiliary graphic discrete parameters is determined from the multiple sets of candidate auxiliary graphic discrete parameters based on each intermediate feature data, including: Based on the intermediate feature data, the optimal intermediate feature data is selected by the selection algorithm; The optimal intermediate feature data is converted into corresponding optimal auxiliary graphical discrete parameters using an auxiliary graphical processing tool.
5. An auxiliary graphic generation system based on Bayesian network template graphics, characterized in that, include: An auxiliary graphic discrete parameter space construction module is used to construct an auxiliary graphic discrete parameter space for a target mask graphic; wherein, the auxiliary graphic discrete parameter space includes multiple sets of candidate auxiliary graphic discrete parameters; The optimal auxiliary graph discrete parameter acquisition module is used to generate a Bayesian fully connected network based on a pre-trained auxiliary graph to obtain intermediate feature data corresponding to the multiple sets of candidate auxiliary graph discrete parameters. The intermediate feature data is a high-dimensional feature vector and has a one-to-one mapping relationship with the probabilistic evaluation results of the corresponding candidate auxiliary graph discrete parameters. Combined with the optimization algorithm, based on the probabilistic evaluation results corresponding to each intermediate feature data, at least one set of optimal auxiliary graph discrete parameters is determined from the multiple sets of candidate auxiliary graph discrete parameters. The training process of the pre-trained auxiliary graph generation Bayesian fully connected network includes: An initial Bayesian fully connected network is obtained, and a training auxiliary graph discrete parameter space for training mask graphs is constructed; wherein, the initial Bayesian fully connected network includes a preset prior distribution of trainable parameters; based on the training auxiliary graph discrete parameter space, the initial Bayesian fully connected network is trained with an auxiliary graph generation fully connected network for at least one round to obtain a pre-trained auxiliary graph generation Bayesian fully connected network. The training process for each round of training the fully connected network for auxiliary graph generation includes: Determine the Bayesian fully connected network to be trained in this round; obtain the discrete parameters of the training auxiliary graphics required for this round from the discrete parameter space of the training auxiliary graphics, input them into the Bayesian fully connected network to be trained in this round, and obtain the corresponding intermediate training feature data; convert the intermediate training feature data into a training auxiliary mask graphic containing the training auxiliary graphics, and perform photolithography process simulation calculation on the training auxiliary mask graphic to obtain the photolithography simulation graphic outline; Multiple detection points are preset on the training design layout corresponding to the training mask pattern. The positional deviation between the contour of the lithographic simulation pattern and the training design layout at the corresponding detection points is calculated. Based on the statistical value of the positional deviation, the imaging quality loss cost is obtained. Based on the log-likelihood estimate of the cost transformation of the imaging quality loss, and the KL divergence between the posterior and prior distributions of the trainable parameters of the Bayesian fully connected network to be trained in this round, the negative evidence lower bound loss value of the Bayesian fully connected network to be trained in this round is obtained. Based on the image quality loss cost and the negative evidence lower bound loss value, the overall training loss value is obtained; it is determined whether the overall training loss value meets the preset convergence condition; if it does, the Bayesian fully connected network completed in this round of training is used as an auxiliary graph to generate a Bayesian fully connected network; if it does not meet the condition, the Bayesian fully connected network completed in this round of training is used as the Bayesian fully connected network for the next round of training. The auxiliary mask pattern acquisition module is used to perform auxiliary pattern processing on the discrete parameters of the optimal auxiliary pattern to obtain an auxiliary mask pattern containing the auxiliary pattern. The final auxiliary mask pattern acquisition module is used to perform photolithography process simulation verification on the auxiliary mask pattern, and output the final auxiliary mask pattern containing the final auxiliary pattern according to the verification result; The process of performing photolithography process simulation verification on the auxiliary mask pattern and outputting the final auxiliary mask pattern containing the final auxiliary pattern based on the verification results includes: The auxiliary mask pattern is subjected to photolithography process simulation, and the photolithography process simulation is verified based on the simulation results. If the verification result meets the preset imaging accuracy requirements, then the process rule detection is performed on the lithography process simulation result, and the final auxiliary mask pattern containing the final auxiliary pattern is output according to the detection result; If the verification result does not meet the preset imaging accuracy requirements, the auxiliary pattern discrete parameter group that failed the photolithography process simulation verification and its corresponding photolithography process simulation results are used as new training samples. The pre-trained auxiliary pattern generation Bayesian fully connected network is then transferred and trained to obtain the transferred-trained auxiliary pattern generation Bayesian fully connected network. Based on the transferred-trained auxiliary pattern generation Bayesian fully connected network, the optimal auxiliary pattern discrete parameters are re-determined, and an auxiliary mask pattern containing the auxiliary pattern is regenerated. The regenerated auxiliary mask pattern is then subjected to photolithography process simulation verification again until the photolithography process simulation verification result meets the preset imaging accuracy requirements. Finally, the final auxiliary mask pattern containing the final auxiliary pattern is output.
6. An electronic terminal, comprising a memory, a processor, and a computer program stored in the memory, characterized in that, The processor executes the computer program to implement the auxiliary graphic generation method for Bayesian network-based mask graphics as described in any one of claims 1 to 4.
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