System-on-chip design method and device, deadlock detection method and device, electronic equipment and storage medium

Abstract

The embodiment of the invention provides a system-on-chip design method and device, a deadlock detection method and device, electronic equipment and a storage medium. The system-on-chip design method comprises the steps that a network-on-chip included in a system-on-chip in design is mapped into a first directed connected graph; determining a first directed connectivity dependency graph according to the first directed connectivity graph and a routing algorithm of the network-on-chip; mapping subsystems included in the system-on-chip in the design into a second directed connected graph; determining a second directed connectivity dependency graph according to the second directed connectivity graph and a logic routing algorithm of the subsystem; determining a third directed connected graph according to the first directed connected graph and the second directed connected graph; determining a third directed connectivity dependency graph according to the first directed connectivity dependency graph and the second directed connectivity dependency graph; and performing deadlock detection on the system-on-chip in design according to the third directed connectivity graph and the third directed connectivity dependency graph, and optimizing the system-on-chip in design according to a deadlock detection result. According to the scheme, the design cost of the system-on-chip can be reduced.

Description

Technical Field

[0001] This disclosure relates to the field of chip testing technology, and in particular to a system-on-a-chip design method, a deadlock detection method apparatus, an electronic device, and a storage medium. Background Technology

[0002] Deadlock is a common concurrency problem in the design phase of large-scale chips, and its presence can severely impact the performance and reliability of the entire system. When designing complex multi-core processors or on-chip network systems, it is quite challenging to fully verify all deadlock scenarios in the hardware.

[0003] Currently, deadlock is detected through methods such as Electronic Design Automation (EDA) functional simulation and hardware prototype verification.

[0004] However, deadlock is usually a structural problem. Detecting deadlock through methods such as EDA functional simulation and hardware prototype verification can only be done after the chip has entered the code development stage. Modifying the chip structure after deadlock is discovered will lead to higher chip design costs. Summary of the Invention

[0005] In view of this, embodiments of the present disclosure provide a system-on-a-chip design method, a deadlock detection method, an apparatus, an electronic device, and a storage medium to at least solve or alleviate the above-mentioned problems.

[0006] According to a first aspect of the present disclosure, a system-on-a-chip (SoC) design method is provided, comprising: mapping an on-chip network included in the SoC design to a first directed connectivity graph, the first directed connectivity graph indicating access devices connected to the on-chip network and routing buses of the on-chip network; determining a first directed connectivity dependency graph based on the first directed connectivity graph and a routing algorithm of the on-chip network, the first directed connectivity dependency graph indicating dependencies between routing buses included in the on-chip network; mapping a subsystem for transaction processing included in the SoC design to a second directed connectivity graph, the second directed connectivity graph indicating message passing paths between functional modules in the subsystem; and mapping according to... The second directed connected graph and the logical routing algorithm corresponding to the subsystem are used to determine a second directed connected dependency graph, which is used to indicate the dependencies between the message passing paths. Based on the first and second directed connected graphs, a third directed connected graph corresponding to the on-chip system in the design is determined. Based on the first and second directed connected dependency graphs, a third directed connected dependency graph corresponding to the on-chip system in the design is determined. Based on the third directed connected graph and the third directed connected dependency graph, deadlock detection is performed on the on-chip system in the design to obtain deadlock detection results. Based on the deadlock detection results, the on-chip system in the design is optimized.

[0007] According to a second aspect of the present disclosure, a deadlock detection method is provided, comprising: mapping an on-chip network included in a system-on-a-chip (SoC) to a first directed connected graph, the first directed connected graph indicating access devices connected to the SoC and routing buses of the SoC; determining a first directed connected dependency graph based on the first directed connected graph and a routing algorithm of the SoC, the first directed connected dependency graph indicating dependencies between routing buses included in the SoC; and mapping a subsystem for transaction processing included in the SoC to a second directed connected graph, the second directed connected graph indicating dependencies between the subsystems. The system identifies message passing paths between functional modules; determines a second directed connected dependency graph based on the second directed connected graph and the logical routing algorithm corresponding to the subsystem, the second directed connected dependency graph indicating the dependencies between the message passing paths; determines a third directed connected graph corresponding to the on-chip system based on the first and second directed connected graphs; determines a third directed connected dependency graph corresponding to the on-chip system based on the first and second directed connected dependency graphs; and performs deadlock detection on the on-chip system based on the third directed connected graph and the third directed connected dependency graph.

[0008] According to a third aspect of the present disclosure, a deadlock detection apparatus is provided, comprising: a first mapping unit, configured to map an on-chip network included in a system-on-a-chip (SoC) to a first directed connectivity graph, the first directed connectivity graph indicating access devices connected to the SoC and routing buses of the SoC; a first processing unit, configured to determine a first directed connectivity dependency graph based on the first directed connectivity graph and a routing algorithm of the SoC, the first directed connectivity dependency graph indicating dependencies between routing buses included in the SoC; and a second mapping unit, configured to map a subsystem for transaction processing included in the SoC to a second directed connectivity graph, the second directed connectivity graph indicating functions in the subsystem. The system comprises: a message passing path between modules; a second processing unit, configured to determine a second directed connected dependency graph based on the second directed connected graph and the logical routing algorithm corresponding to the subsystem, wherein the second directed connected dependency graph indicates the dependency relationship between the message passing paths; a first integration unit, configured to determine a third directed connected graph corresponding to the on-chip system based on the first directed connected graph and the second directed connected graph; a second integration unit, configured to determine a third directed connected dependency graph corresponding to the on-chip system based on the first directed connected dependency graph and the second directed connected dependency graph; and a detection unit, configured to perform deadlock detection on the on-chip system based on the third directed connected graph and the third directed connected dependency graph.

[0009] According to a fourth aspect of the present disclosure, an electronic device is provided, including: a processor, a memory, a communication interface, and a communication bus, wherein the processor, the memory, and the communication interface communicate with each other through the communication bus; the memory is used to store at least one executable instruction, which causes the processor to perform the operation corresponding to the method described in the first or second aspect above.

[0010] According to a fifth aspect of the present disclosure, a computer storage medium is provided that stores a computer program thereon, which, when executed by a processor, implements the method described in the first or second aspect above.

[0011] According to a sixth aspect of the present disclosure, a computer program product is provided, including computer instructions that instruct a computing device to perform the method described in the first or second aspect above.

[0012] According to the system-on-a-chip (SoC) design scheme provided in this disclosure, the on-chip network is abstracted as a first directed connected graph, and the subsystem for transaction processing is abstracted as a second directed connected graph. A first directed connected dependency graph is constructed based on the routing algorithm of the on-chip network in the first directed connected graph. A second directed connected dependency graph is constructed based on the logical routing algorithm corresponding to the subsystem in the second directed connected graph. The first and second directed connected graphs are merged and interconnected to form a third directed connected graph. After merging and interconnecting the first and second directed connected dependency graphs to form the third directed connected dependency graph, deadlock detection is performed on the SoC based on the third directed connected graph and the third directed connected dependency graph. Based on the theoretical foundation of mathematical graph theory, deadlock detection is achieved by abstractly modeling the on-chip network and transaction processing in the SoC. This allows for deadlock detection in the early stages of SoC architecture and microarchitecture design, reducing the cost of modifying the SoC design compared to discovering deadlocks after the SoC has entered the code development stage and then making modifications. This reduces the overall design cost of the SoC. Attached Figure Description

[0013] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings.

[0014] Figure 1 This is a schematic diagram of an exemplary system to which this disclosure is applied, according to one embodiment.

[0015] Figure 2 This is a flowchart of a deadlock detection method according to an embodiment of this disclosure;

[0016] Figure 3 This is a schematic diagram of a transaction abstraction and connection subgraph according to an embodiment of this disclosure;

[0017] Figure 4 This is a schematic diagram of a SoC architecture according to an embodiment of this disclosure;

[0018] Figure 5 This is a schematic diagram of a first directed connected graph according to an embodiment of this disclosure;

[0019] Figure 6 This is a schematic diagram of a second directed connected graph according to an embodiment of this disclosure;

[0020] Figure 7 This is a schematic diagram of a third directed connected graph according to an embodiment of this disclosure;

[0021] Figure 8This is a schematic diagram of a pseudo-deadlock ring according to an embodiment of this disclosure;

[0022] Figure 9 This is a schematic diagram of a subgraph of a third directed connected dependency graph according to an embodiment of this disclosure;

[0023] Figure 10 This is a schematic diagram of a transaction flow according to an embodiment of this disclosure;

[0024] Figure 11 This is a schematic diagram of a third directed connectivity dependency graph according to an embodiment of this disclosure;

[0025] Figure 12 This is a schematic diagram of a directed dependency subgraph according to an embodiment of this disclosure;

[0026] Figure 13 This is a schematic diagram of a deadlock configuration loop according to an embodiment of this disclosure;

[0027] Figure 14 This is a flowchart of a system-on-a-chip design method according to an embodiment of this disclosure;

[0028] Figure 15 This is a schematic diagram of a deadlock detection device according to an embodiment of the present disclosure;

[0029] Figure 16 This is a schematic diagram of an electronic device according to an embodiment of the present disclosure. Detailed Implementation

[0030] The present disclosure is described below based on embodiments, but it is not limited to these embodiments. In the detailed description of the present disclosure below, certain specific details are described in detail. Those skilled in the art will fully understand the present disclosure even without these details. To avoid obscuring the substance of the present disclosure, well-known methods, processes, and procedures are not described in detail. Furthermore, the accompanying drawings are not necessarily drawn to scale.

[0031] First, some of the nouns or terms that appear in the description of the embodiments of this disclosure are to be interpreted as follows.

[0032] System-on-a-Chip (SoC): A system-on-a-chip (SoC) is a technology that integrates key components of a traditional computer or other electronic system onto a single integrated circuit (chip). This integration includes a processor core, memory, input / output ports, analog input / output, and additional circuit modules for specific applications. The goal of SoC design is to reduce the overall system size, lower power consumption, improve performance, and simplify the design and manufacturing process.

[0033] Network on Chip (NoC) is a technology that enables communication between subsystems in digital circuits, particularly within a System-on-a-Chip (SoC). NoC is a hardware-level circuit structure similar to a computer network, facilitating data exchange between its components. NoC can be viewed as a simplified network within a digital circuit, with the components connecting the network abstracted as terminals, and the interconnecting network responsible for transmitting data between these terminals via channels.

[0034] Deadlock: Deadlock refers to a blocking phenomenon caused by two or more processes competing for resources or communicating with each other. Without external intervention, they cannot proceed. At this time, the system is said to be in a deadlock state or the system has deadlocked. These processes that are forever waiting for each other are called deadlocked processes.

[0035] Directed Connected Graph: A directed connected graph, also known as a digit graph, is a graph theory structure in which edges (or arcs) are directed. That is, an edge from one vertex to another is directed, meaning you cannot traverse from one vertex to another. Nodes in a directed connected graph are called vertices, and the directed lines connecting the vertices are called edges or arcs. Each edge has a starting point and an ending point.

[0036] Routing algorithms: Routing algorithms are a series of algorithms that select the transmission path and determine the transmission path of data packets from the source node to the destination node in the network.

[0037] Application Environment of This Disclosure

[0038] This disclosure presents a deadlock detection scheme in the chip design process. The scheme is relatively general and can be used to detect deadlocks in SoC design processes, including NoC (System-on-a-Chip) architectures. The SoC may include one or more general-purpose or special-purpose processors such as a Central Processing Unit (CPU), Graphics Processing Unit (GPU), Neural Network Processing Unit (NPU), Tensor Processing Unit (TPU), Data Processing Unit (DPU), and Infrastructure Processing Unit (IPU). The deadlock detection scheme provided in this disclosure is independent of the hardware deployed on the computing device executing the scheme.

[0039] Exemplary System

[0040] Figure 1 An exemplary system for a deadlock detection method applicable to embodiments of this disclosure is shown. For example... Figure 1 As shown, the system may include a cloud server 102, a communication network 104, and at least one user device 106. Figure 1 The example shown is multiple user devices 106. It should be noted that the solution in this embodiment can be applied to both the cloud server 102 and the user devices 106.

[0041] The cloud server 102 can be any suitable device for storing information, data, programs, and / or any other suitable type of content, including but not limited to distributed storage system devices, server clusters, computing cloud server clusters, etc. In some embodiments, the cloud server 102 can perform any suitable function. For example, in some embodiments, the cloud server 102 can be used for deadlock detection. As an optional example, the cloud server 102 can receive operation instructions sent by the user equipment 106 and perform deadlock detection on the SoC based on the operation instructions.

[0042] Communication network 104 can be any suitable combination of one or more wired and / or wireless networks. For example, communication network 104 can include any one or more of the following: the Internet, intranet, wide area network (WAN), local area network (LAN), wireless network, digital subscriber line (DSL) network, frame relay network, asynchronous transfer mode (ATM) network, virtual private network (VPN), and / or any other suitable communication network. User equipment 106 can be connected to communication network 104 via one or more communication links (e.g., communication link 112), which can be linked to cloud server 102 via one or more communication links (e.g., communication link 114). Communication links can be any communication link suitable for transmitting data between cloud server 102 and user equipment 106, such as network links, dial-up links, wireless links, hardwired links, any other suitable communication links, or any suitable combination of such links.

[0043] User equipment 106 may include any one or more user devices suitable for interaction. In some embodiments, when deadlock detection is performed by cloud server 102, user equipment 106 may send an operation command to cloud server 102 in response to a user's operation. Upon receiving the operation command, cloud server 102 performs deadlock detection on the SoC based on the operation command. In other embodiments, user equipment 106 may perform deadlock detection on the SoC locally.

[0044] User equipment 106 may include any suitable type of device. For example, user equipment 106 may include mobile devices, tablet computers, laptop computers, desktop computers, and any other suitable type of user equipment. User equipment may include standard interactive screens and / or input / output devices such as mice and keyboards.

[0045] This application embodiment mainly focuses on the deadlock detection process performed by the cloud server 102 or the user equipment 106. The deadlock detection process will be described in detail later.

[0046] Deadlock detection methods

[0047] Based on the above system, this disclosure provides a deadlock detection method, which can be executed by the cloud server 102 or the user equipment 106. The deadlock detection method will be described in detail below through multiple embodiments.

[0048] Figure 2 This is a flowchart of a deadlock detection method according to an embodiment of this disclosure. Figure 2 As shown, the deadlock detection method includes the following steps:

[0049] Step 201: Map the NoCs included in the SoC to a first directed connected graph.

[0050] In the SoC design process, the SoC can be divided into NoC (No-System-on-Channel) and multiple subsystems for transaction processing. By abstracting the NoC, it can be mapped to a first directed connected graph, which can indicate the access devices connected to the NoC and the routing bus of the NoC. In one example, the vertices of the first directed connected graph can indicate the access devices connected to the NoC, and the edges of the first directed connected graph can indicate the routing bus of the NoC.

[0051] Access devices connected to the NoC can be CPU cores, accelerators, cache coherency controllers (home nodes), etc.

[0052] Step 202: Determine the first directed connected dependency graph based on the first directed connected graph and the NoC routing algorithm.

[0053] After abstracting NoC as a first directed connected graph, a first directed connected dependency graph can be constructed based on the routing algorithm of NoC, so that the first directed connected dependency graph can indicate the dependencies between the routing buses included in NoC. In one example, the vertices included in the first directed connected dependency graph can be at least some of the edges in the first directed connected graph, so that the edges included in the first directed connected dependency graph can indicate the dependencies between the routing buses included in NoC.

[0054] It should be noted that the routing algorithm of NoC includes not only the message routing algorithm of NoC, but also the routing of transaction logic.

[0055] Step 203: Map the transaction processing subsystems included in the SoC to a second directed connected graph.

[0056] Based on the transaction processing flow and specific implementation architecture / microarchitecture of the NoC access devices in the SoC, the NoC access devices can be divided into subsystems. Specifically, one access device can be divided into one subsystem, one access device into multiple subsystems, or multiple access devices into one subsystem. After dividing the NoC access devices into subsystems for transaction processing, each subsystem can be abstracted and mapped to a corresponding second directed connected graph. This second directed connected graph can indicate the message passing paths between functional modules within the subsystem.

[0057] In one example, the vertices of the second directed connected graph can indicate the functional modules included in the corresponding subsystem, and the edges of the second directed connected graph can indicate the message transmission path between the functional modules.

[0058] Step 204: Determine the second directed connected dependency graph based on the logical routing algorithm corresponding to the second directed connected graph and the subsystem.

[0059] After mapping the transaction processing subsystem in the SoC to a second directed connected graph, a second directed connected dependency graph can be constructed based on the logical routing algorithm of the subsystem. This second directed connected dependency graph can indicate the dependencies between message passing paths. In one example, the vertices of the second directed connected dependency graph can be at least some of the edges in the second directed connected graph, so that the edges in the second directed connected dependency graph can indicate the dependencies between different message passing paths.

[0060] The logical routing algorithm corresponding to a subsystem is logically derived from the subsystem's transaction processing flow and specific implementation architecture / microarchitecture. This algorithm can indicate the logical flow and data stream of the subsystem in handling transactions.

[0061] Step 205: Determine the third directed connected graph corresponding to the SoC based on the first directed connected graph and the second directed connected graph.

[0062] After obtaining the first directed connected graph corresponding to the NoC and the second directed connected graph corresponding to the subsystem, the first directed connected graph and multiple second directed connected graphs can be merged and interconnected to obtain the third directed connected graph corresponding to the SoC.

[0063] Step 206: Based on the first and second directed connected dependency graphs, determine the third directed connected dependency graph corresponding to the SoC.

[0064] After obtaining the first directed connected dependency graph corresponding to the NoC, i.e. the second directed connected dependency graph corresponding to the subsystem, the first directed connected dependency graph and multiple second directed connected dependency graphs can be merged and interconnected to obtain the third directed connected dependency graph corresponding to the SoC.

[0065] Step 207: Perform deadlock detection on the SoC based on the third directed connected graph and the third directed connected dependency graph.

[0066] The third directed connectivity graph can indicate the connection relationship between the access devices of the NoC and the functional modules inside the access devices. The third directed connectivity graph can also indicate the data transmission dependency relationship between access devices and between the functional modules inside the access devices. Therefore, based on the third directed connectivity graph and the third directed connectivity dependency graph, and based on the necessary and sufficient conditions for deadlock caused by the transaction processing microarchitecture of the NoC and subsystem in the SoC design, deadlock detection can be performed on the SoC.

[0067] In this embodiment, the NoC (No Connectivity) is abstracted as a first directed connected graph, and the subsystem for transaction processing is abstracted as a second directed connected graph. A first directed connected dependency graph is constructed based on the first directed connected graph according to the routing algorithm of the NoC. A second directed connected dependency graph is constructed based on the second directed connected graph according to the logical routing algorithm corresponding to the subsystem. The first and second directed connected graphs are merged and interconnected to form a third directed connected graph. After merging and interconnecting the first and second directed connected dependency graphs to form the third directed connected dependency graph, deadlock detection is performed on the SoC based on the third directed connected graph and the third directed connected dependency graph. Based on the theoretical foundation of mathematical graph theory, deadlock detection of the SoC is achieved by abstractly modeling the NoC and transaction processing in the SoC. This allows for deadlock detection of the SoC in the early stages of SoC architecture and microarchitecture design. Compared to discovering deadlocks after the SoC has entered the code development stage and then making modifications, this reduces the cost of modifying the SoC design, thereby reducing the overall design cost of the SoC.

[0068] In one possible implementation, when the SoC includes multiple subsystems for transaction processing, each subsystem can be mapped to a corresponding second directed connected graph, and the second directed connected dependency graph corresponding to each subsystem can be determined based on the second directed connected graph corresponding to each subsystem and the logical routing algorithm corresponding to that subsystem.

[0069] Based on the transaction processing flow and specific implementation architecture / microarchitecture of the access devices connected to the NoC in the SoC, a second directed connected graph can be constructed for each subsystem. Then, based on the logical routing algorithm corresponding to each subsystem, a second directed connected dependency graph can be constructed on top of this second directed connected graph. Different subsystems correspond to different second directed connected graphs, and the size and mathematical properties of these different second directed connected graphs can vary.

[0070] Based on the transaction processing flow and specific implementation architecture / microarchitecture design of the subsystem, the corresponding logical routing algorithm can be abstracted. The logical routing algorithm is logical and can indicate the logical flow and data flow of the subsystem in processing transactions.

[0071] In one example, based on the main logical processing flow, data flow, and architecture / microarchitecture of a subsystem's transaction handling, we can deduce that the subsystem receives transaction messages routed from the NoC. These messages, according to the architecture / microarchitecture design, enter a specific functional module within the subsystem. Based on transaction processing requirements, this functional module then sends another transaction message to other subsystems. Furthermore, transaction messages initiated by this subsystem itself enter its sending and processing module. Based on the message propagation path within the subsystem, we can abstract the message routing algorithm for that subsystem and thus determine it as the corresponding logical routing algorithm for that subsystem.

[0072] In this embodiment, based on the transaction processing flow and specific implementation architecture / microarchitecture of the NoC access device in the SoC, the access device linked to the NoC is divided into multiple subsystems. By abstractly modeling the subsystems, a corresponding second directed connectivity graph can be obtained. Based on the subsystem's transaction processing flow, data flow, and architecture / microarchitecture, a logical routing algorithm for the subsystem can be abstracted. Then, based on the corresponding second directed connectivity graph and logical routing algorithm, a second directed connectivity dependency graph for that subsystem can be constructed. This ensures that the second directed connectivity graph and second directed connectivity dependency graph for the subsystem accurately indicate the message passing paths and dependencies within the subsystem, thereby guaranteeing the accuracy of subsequent deadlock detection results.

[0073] In one possible implementation, when mapping the NoC to a first directed connected graph, the first directed connected graph G can be determined based on the access devices connected to the SoC and the routing bus included in the NoC.N =(V N E N ), G N Mid-vertex set V N The included elements represent the access devices connected to the NoC, G N In the directed edge set E N The included elements constitute the routing bus of NoC.

[0074] Vertex set V N =v1,v2,…,v n Where v1, v2, ..., v n For all access devices connected to the NoC, including routing devices and transaction processing node devices, there is a directed edge set E. N It is the actual routing bus of the SoC. E N ={e i = i ,d i >|s i ,d i ∈V N}, directed edge e i The source vertex is s i Directed edge e i The destination node is d i For any directed edge e i It has a weight value cap(e) i ) and size(e i ), cap(e i ) represents the directed edge e i Maximum communication capacity, size(e) i ) represents the directed edge e i Current communication traffic value. Each directed edge e i Corresponding to a queue q i Then cap(e) i The depth of the queue can be represented by size(e). i The number of communication messages currently stored in the queue can be represented.

[0075] In this embodiment of the disclosure, a first directed connectivity graph G is constructed based on the access devices connected to the NoC and the routing bus included in the NoC. N =(V N E N Vertex set V N Including all access devices connected to the NoC, directed edge set E N Including the actual NoC routing bus, making the first directed connected graph G N =(V j E N ​) can indicate all access devices connected to the NoC and the routing bus of the NoC, and the access devices connected to the NoC and the routing bus of the NoC can determine whether there is a deadlock situation in the SoC, thereby ensuring the accuracy of subsequent deadlock detection of the SoC based on the first directed connected graph G N =(V N , E N ).

[0076] In a possible implementation, when constructing the first directed connected dependency graph, the vertex set E N =(V N , E N ) and the routing algorithm of the NoC can be used to determine the first directed connected dependency graph The first directed connected dependency graph The vertex set E N in is the directed edge set E N in the first directed connected graph G N , and the directed edge set I in the first directed connected dependency graph N The element <e i , e j > satisfies: in the queue q N =(V N , E N ) of the edge e i in the first directed connected graph G i , there exists a next hop of the message m i going to the destination access device v i , and the next hop of the message m i is going to the queue q N of the edge e j in the first directed connected graph G j .

[0077] For the convenience of the description of subsequent embodiments, the following definitions are made for the time scale sequence, messages, and transactions in the SoC.

[0078] (1) Define the implementation scale sequence: Define the order < in the set T = {t0, t1,..., t n}: for i < j, then t i < t j , under the action of this strict order <, the set T = {t0, t1,..., t n} is a time scale sequence. Define the clock function c:

[0079]

[0080] is the set of non-negative integers, satisfying t i <t j Then c(t) i ) <c(t j ).

[0081] (2) Define a finite set of messages in the SoC M = {m1, m2, ..., m} l Define a function set Φ = {φ | φ is a function: M → M}. Define a partial order in set M. For any message m i ,m j ∈M, if there exists φ∈Φ such that φ(m i ) = m j ,but Define this partially ordered set These are transmission messages within the SoC. It represents the transmission and communication relationship, denoted as (m) i ,φ,m j )∈Γ is

[0082] Under the action of relation Γ, establish a function g: M→T, satisfying: for any (m i ,φ,m j )∈Γ, we have g(m) i ) <g(m j Therefore, a function exists. Satisfy: For any (m) i ,φ,m j )∈Γ,τ(m i )≤τ(m j The function τ is called the message passing timing function.

[0083] (3) Order Under the action of Γ, the following condition is satisfied:

[0084] (TR1) It must exist. Or Or

[0085] (TR2) exists Make the There always (1≤j <I, It may contain ), making φ0,φ k ∈Γ,k=1,2,…,j, Called M tr The source message.

[0086] (TR3) exists Make the unless Otherwise, none of them exist. say The news has been lost.

[0087] make Let M be the power set of all subsets satisfying (TR1), (TR2), and (TR3), and M be called M. tr For SoC transport transactions, Tr represents the SoC transport transaction set. Specifically, the above three properties are still satisfied even when I=1.

[0088] definition The function to:

[0089]

[0090] to(tr) is called the token for the transmission transaction tr∈Tr.

[0091] (4) For any tr i ∈Tr, construct an ordered set The following conditions must be met:

[0092] (D1) for any They formed in D tri A partial order within. Where a and b can be equal to i and j, respectively.

[0093] (D2) for any There exists a finite sequence {i1,i2,…,i... t} makes it possible for any 1≤s≤t-1,t≥2, satisfying when have It should be understood that when At that time, D2 still holds true.

[0094] say For transactions in SoC i Transaction dependencies are called tr i Transactions are initiated based on dependencies. (Definition) for tr i The potential. When the potential is zero, tr i It does not depend on any other transaction. (Definition) This is a set of transaction dependencies in the SoC.

[0095] Based on the above definitions of time-scale sequences, messages, and transactions in a SoC, the following definition is defined: This refers to the message routing relationship on a NoC, i.e., the routing algorithm of a NoC, denoted as r = <(m i ,v i ),(e i ,e j )>∈R NOC for Indicates in G N =(V N E N edge e in ) i queue q i In the middle, there is a destination node device v i message m i The next jump, and the next jump should go to the side e. j queue q j .

[0096] In one example, define a Boolean function.

[0097] In another example, the Boolean function could be a ternary function b(v) with time t. i ,e i The expression (t) represents a network that is a connected directed graph that changes over time. That is:

[0098]

[0099] Based on the above, R NOC And the definition of Boolean functions in R NOC Under the influence of this, the first directed connected dependency graph is established. The included vertices are G N The edge, Included edge c = <e i ,e j >∈I means: There exists v∈V such that b noc (v i ,e i (ej) = 1 or b noc (v i ,e i ,e j ,t)=1.

[0100] In R NOC Under the influence of any given tr i ∈T r Each message In the first directed connected graph G N =(V N E N There is one final node device in ) First directed connected dependency graph There is a path. Definition For the message A routing path containing a directed edge e i+b The endpoint is definition

[0101] It should be noted that in constructing the first directed connected dependency graph... In this context, the SoC's virtual channels, reserved space, pre-allocated space, and other mechanisms will be abstracted into different directed edges. The abstraction of graphs and routing algorithms is extensive, encompassing routing at the transaction logic level, not just the actual message routing algorithm of the NoC.

[0102] In this embodiment of the disclosure, the routing algorithm of NoC is abstracted as R. NOC According to the first directed connected graph G N and R NOC Construct the first directed connected dependency graph Make the first directed connected dependency graph The vertices in the graph are the first directed connected graph G. N The directed edges in the graph, the first directed connected dependency graph The edge e i Satisfy: Edge e i queue q i In the middle, there exists a destination access device v i message m i The next hop, and message m i The next hop is to go to the first directed connected graph G. N edge e in j queue q j This results in the first directed connected dependency graph. It can accurately characterize the dependencies between routing buses in NoC, thereby ensuring the reliability of the first directed connectivity dependency graph. The accuracy of deadlock detection for SoC.

[0103] In one possible implementation, when constructing the second directed connected graph corresponding to the subsystem, the second directed connected graph corresponding to the subsystem can be determined based on the functional modules included in the access device corresponding to the subsystem. Second directed connected graph Mid-vertex set The included elements represent the access devices V corresponding to the subsystem. i Included functional modules, second directed connected graph In-directed edge set The included elements represent the access device V. i The message passing path between functional modules.

[0104] Based on the transaction processing flow and specific implementation architecture / microarchitecture of the NoC's access devices (such as CPU cores, accelerators, cache coherency controllers, etc.), each subsystem can be abstractly modeled to obtain a second directed connected graph corresponding to each subsystem. This represents the second directed connected graph corresponding to the i-th subsystem included in the SoC. There can be multiple second directed connected graphs, and the size and mathematical properties of these multiple second directed connected graphs can be different.

[0105] In a SoC system, for a certain access device V connected to a NoC i ∈V N By this access device V i The set of vertices say For access device V i Functional module set, For access device V i It includes multiple functional modules.

[0106] In a SoC system, node devices include functional modules that can receive certain messages from message set M routed from the NoC, while access devices are modules designed to handle certain transactions. Therefore, a set of device modules can be defined for the SoC. And define the first directed connected graph G. N =(V N E N The vertices of ) represent the device locations of the SoC, and its vertex set V N This is the set of device locations for the SoC.

[0107] definition It is about V i The device data flow relationship. Definition For functional modules Send message m z , For access device V i In the middle, message m y Will be sent Go to the middle.

[0108] Define the second directed connected graph It is access device V i The extended directed connected subgraph has a set of directed edges. Define the weight of each edge and queue depth Therefore, by definition It is the access device V i The corresponding second directed connected graph The message routing relationship on the above, record for It should be understood that routing algorithms It is logical and can represent the logical flow and data flow of the corresponding subsystem in handling transactions.

[0109] In the vertex set There exists a special subset of functional modules. Correspondingly, the set of directed edges There exists a directed edge subset in the middle. remember x0≤x i For any One of the following two conditions must be met:

[0110] (1) In Figure G N =(V N E N In ), there exists e i ∈E N ,m∈M, such that

[0111] (2) In Figure G N =(V N E N In ), there exists e i ∈E N m∈M Make

[0112] Right now The point in the middle is the access device v i The set of directed edges that directly connect to NoC is called the vertex device v. i The input and output directed edge set.

[0113] For any One of the following two conditions must be met:

[0114] (1) Existence And exist in v j ∈V N ;

[0115] (2) Existence And exist in v j ∈V N ;

[0116] Right now The functional module in it is the access device v i The functional modules that are directly connected to NoC are called vertex devices. i The set of input / output module nodes.

[0117] In this embodiment of the disclosure, a second directed connected graph is constructed based on the functional modules included in the access device corresponding to the subsystem. Vertex set Including the access device V corresponding to the subsystem i Includes functional modules, edge sets Includes access devices V i The message passing paths between the functional modules make the second directed connected graph... It can indicate the message passing path between functional modules within a subsystem, and the message passing path between functional modules can determine whether there is a deadlock in the SoC, thereby ensuring that subsequent operations based on the second directed connectivity graph are successful. The accuracy of deadlock detection for SoC.

[0118] In one possible implementation, when constructing the second directed connected dependency graph, it can be based on the second directed connected graph. The logical routing algorithm corresponding to the subsystem determines the second directed connectivity dependency graph corresponding to that subsystem. Second directed connected dependency graph Mid-vertex set For the second directed connected graph directed edge set in Second directed connected dependency graph In-directed edge set Included elements Satisfy: Access device V i Included functional modules The sent message contains message m s Message m s It will be sent to the access device V i Included functional modules

[0119] Based on the subsystem transaction processing flow and the specific implementation architecture / microarchitecture, abstract the logical routing algorithm for each subsystem. Logical routing algorithm It is logical; specifically, the logical routing algorithm can be abstracted in the following ways.

[0120] Based on the main logical processing flow, data flow, and architecture / microarchitecture of the subsystem's transaction processing, we can deduce that the subsystem receives transaction messages from the NoC route. These messages, according to the architecture / microarchitecture design, enter a specific functional module within the subsystem. Based on transaction processing requirements, this functional module then sends another transaction message to other subsystems. Furthermore, transaction messages initiated by this subsystem itself enter its sending and processing module. Based on this, we can abstract the logical routing algorithm corresponding to this subsystem.

[0121] Based on the logical routing algorithm corresponding to the subsystem Second directed connected graph The second directed connected dependency graph corresponding to this subsystem can be constructed as follows:

[0122] Based on the transaction processing flow, directly list the functional modules belonging to the subsystem that need to be processed to handle this transaction. This needs to be determined in the early stages of the subsystem's architecture design. When a transaction processing moves from functional module A to the next functional module B, it is considered that the corresponding subsystem has a second directed connected graph. This includes the abstract vertices a and b corresponding to functional modules A and B, i.e., A→B=<a,b> This is a directed edge.

[0123] Based on the architecture / microarchitecture design, list the relevant resource queues (such as cache, queue and other resource structures), and then define the capacity (cap(e)) of the corresponding edge e as the size of the corresponding resource.

[0124] Logical processing dependencies within transactions, such as transaction A depending on transaction B for processing, can be addressed by merging the subgraphs abstracted from transactions A and B into a new connected subgraph. The edges connecting these two subgraphs can be abstracted. For example, if the processing of transaction A ultimately requires reporting an interrupt to the software, and the software, through the Application Processor (AP), completes its operation before processing transaction A again, this transaction can be abstracted as transaction B. The connecting edge between the two subgraphs corresponding to transactions A and B represents the interrupt. Figure 3 As shown, the red edges are the edges after the interruption abstraction. Transaction A and Transaction B have a connection subgraph due to the interruption and the behavior of the AP core, and a corresponding connection dependency subgraph is also generated.

[0125] In one example, the algorithm tool can guide the subsystem's architect / microarchitecture designer to output the corresponding transaction dependency table in the manner described above. This transaction dependency table is straightforward and clear, eliminating the need for the designer to consider the long process of transaction processing and reducing human-introduced omissions.

[0126] The algorithm tool abstracts the required SoC and subsystem architecture / microarchitecture design schemes and transaction processing flows. It can abstractly model the architecture / microarchitecture and transaction processing flows of different subsystems individually. Under the guidance of the algorithm tool, abstract modeling can be performed directly without the need for user-defined analysis. For example, taking the transaction type, dependencies, transaction description, component modules in the architecture, queues within the microarchitecture of the module, distribution, and other resource logic functional modules as input, the algorithm tool performs abstract modeling and outputs the graph data structure and information such as the corresponding dependency graph and edge weights.

[0127] In one example, define a Boolean function.

[0128] In another example, the Boolean function could be a ternary function b(v) with time t. i ,e i The expression (t) represents a network that is a connected directed graph that changes over time. That is:

[0129]

[0130] Based on the above logical routing algorithm corresponding to the subsystem exist Under its influence, establish relevant access devices V i Second directed connected dependency graph vertex set for The directed edge set, directed edge set

[0131] In this embodiment of the disclosure, the logical routing algorithm of the abstract subsystem According to the second directed connected graph corresponding to this system and Construct the second directed connected dependency graph corresponding to this subsystem. Make the second directed connected dependency graph vertex set For the second directed connected graph directed edge set in And the second directed connected dependency graph directed edge set in Included elements Satisfy: Access device V i Included functional modules The sent message contains message m s Message m s It will be sent to the access device V i Included functional modules Thus, the second directed connected dependency graph It can accurately indicate the dependencies between message passing paths in the subsystem, thereby ensuring the reliability of the second directed connected dependency graph. The accuracy of deadlock detection for SoC.

[0132] In one possible implementation, after obtaining the first and second directed connected graphs, the third directed connected graph corresponding to the SoC is obtained by calculating the union of the first directed connected graph and the second directed connected graph corresponding to each subsystem.

[0133] After obtaining the first directed connected graph G N =(V N E N (and multiple second directed connected graphs corresponding to multiple subsystems) Then, the first directed connected graph G N =(V N E N ) and each of the second directed connected graphs Combining these, we obtain the third directed connected graph of the SoC, such that the third directed connected graph...

[0134] In this embodiment of the disclosure, the first directed connected graph G is calculated. N =(V N E N ) and each of the second directed connected graphs The union of the three directives is used to obtain a third directed connected graph G, which can indicate the message passing path between the routing bus included in the NoC and the functional modules in the access device. Since the message passing path between the routing bus included in the NoC and the functional modules can all lead to deadlock, deadlock detection of the SoC based on the third directed connected graph G can ensure the accuracy of the deadlock detection results and the comprehensiveness of the deadlock detection.

[0135] In one possible implementation, after obtaining the first and second directed connected dependency graphs, the third directed connected dependency graph corresponding to the SoC is obtained by calculating the union of the first directed connected dependency graph and the second directed connected dependency graph corresponding to each subsystem.

[0136] After obtaining the first directed connected dependency graph Multiple second directed connected dependency graphs corresponding to multiple subsystems Then, the first directed connected dependency graph and each second directed connected dependency graph By combining these elements, we obtain the third directed connected dependency graph of the SoC, such that the third directed connected dependency graph...

[0137] In this embodiment of the disclosure, a first directed connected dependency graph is computed. and each second directed connected dependency graph The union of the sets yields the third directed connected dependency graph G. D This makes the third directed connected dependency graph G D The NoC can indicate the dependencies between routing buses and the dependencies between message passing paths of functional modules. Both dependencies between routing buses and dependencies between message passing paths can lead to deadlock. Therefore, a third directed connectivity dependency graph G is used. D Performing deadlock detection can ensure the accuracy and comprehensiveness of the deadlock detection results.

[0138] In one possible implementation, in the third directed connected dependency graph G D In, combined with NoC's b noc (v i ,e a ,e b ) functions and subsystems Functions, defined in the SoC

[0139] This disclosure embodiment can automatically merge and interconnect the second directed connected graph and second directed connected dependency graph of each independently output subsystem, and the first directed connected graph and first directed connected dependency graph of NoC. Finally, according to the SoC architecture design, the above-mentioned directed graphs are structurally merged together to form a large third directed connected graph G and third directed connected dependency graph G. D These merging operations are all graph operations, which can be directly performed on the mathematical model, providing a theoretical basis and ensuring the model's accuracy. It's important to note that different edges may not be connected in the directed connected dependency graph under the routing function, or they may be connected due to transaction dependencies. For example, the sending of a transaction's request depends on its response being routed back from the NoC. In the NoC, the request channel and response channel are two different edges, independent and not interdependent (in message transmission), thus corresponding to the first directed connected dependency graph. These two different paths are not connected. However, in the second directed connected dependency graph of the subsystem modeled in this embodiment, the vertices corresponding to these two edges are connected by directed edges, thus connecting them in the third directed connected dependency graph G. D These two different paths will also be connected due to transaction dependencies. It should be understood that the directed connected graph in this disclosure embodiment may contain edges with infinite weights (cap(e) = +∞).

[0140] The following example illustrates the third directed connected graph G and the third directed connected dependency graph G. D The process of obtaining it will be explained.

[0141] Figure 4 A schematic diagram of a SoC architecture according to an embodiment of this disclosure is shown. (As follows) Figure 4 As shown, the internal architecture / microarchitecture of the green HN-F subsystem can be abstracted into functional modules PQ, PIPE, TRACK, and RSP. The architecture / microarchitecture of the two HN-F subsystems is identical. The circles in the diagram represent the routing subsystem, and "port" represents a port. The route mapping is defined as follows:

[0142] Port2 connects to the HN-F subsystem, and port4 connects to the SN-F subsystem; Figure 4 The SN-F subsystem is connected to ports 2 and 4 of intermediate routing device 03 and routing device 60;

[0143] Port0 can be routed to port1 and port2; port4 can be routed to port2 and port1.

[0144] Requests to port2 can be routed to port1; requests to port3 can be routed to port2.

[0145] The response from Port1 can be routed to Port2; the response from Port4 can be routed to Port2.

[0146] Routing devices can be rotated at any angle (port connections) to enable NoC to request XY routes (e.g., Figure 4 (As shown by the green arrow in the middle). A port without a connected device indicates that no requests / responses have come from or been sent to this port.

[0147] based on Figure 4 The first directed connected graph G of the NoC established by the architecture shown. N The first directed connected graph G of NoC N like Figure 5 As shown.

[0148] Based on the functional modules PQ, PIPE, TRACK, and RSP included in the HN-F subsystem, a second directed connected graph is constructed. Figure 4 Two HN-F subsystems are shown, and these two HN-F subsystems have the same architecture / microarchitecture. Therefore, a second directed connected graph corresponding to these two HN-F subsystems is constructed. and Second directed connected graph and All Figure 6 As shown.

[0149] Let the first directed connected graph G N and each of the second directed connected graphs ( and Merging and connecting to a larger directed connected graph yields a third directed connected graph G, as shown below. Figure 7 As shown.

[0150] Based on the generated third directed connected graph G and the above definition, an automatic third directed connected dependency graph G is generated. D Based on the third directed connected graph G obtained from the abstraction of SoC, the following definitions apply to message consumption and message flow in SoC:

[0151] (1) In any given transaction tr i In ∈Tr, for each message There is a target access device v i ∈V N As this news The final device, and in this access device v i Related second directed connected dependency graph In the middle, news There is a path There is a directed edge in this path. It's a message. Second directed connected dependency graph The last edge that the middle element passes through. Define this directed edge. For the message The landing direction is denoted as . And it is called a directed edge The endpoint is the landing node. At this point, for any...

[0152] definition For directed edges The source message set, This is the directed edge set for SoC deployment.

[0153] (2) Based on the first directed connected graph G N Second directed connected graph First directed connected dependency graph Second directed connected dependency graph The definition of information flow in SoC, for any given transaction tr i and messages definition For the message In transaction tri One of the routing paths in [the context]. It's a message. The directed edge of the landing. Definition It is a transaction (tr) i Information flow. Using P(tr) i )∩ p P(tr j ) indicates that the condition is satisfied. A set of.

[0154] (3) For a set of transaction dependencies definition For transactions tr i Transaction dependency message flow.

[0155] In this embodiment of the disclosure, the data stream is defined as follows:

[0156] Definition 1: For any source message A message can be disposed of and consumed along a directed edge if and only if it can be routed to its associated disposal edge. For any message other than the source message... The message is routed to the relevant destination directed edge if and only if the message can be routed to the destination edge, and for any other existence News of Relationship And the message When the message can be delivered and consumed, it can be delivered and consumed within the directed edge.

[0157] Definition 2: For any transaction tr i ∈T r :

[0158] (C1) When transaction tr i When the potential is zero, it is true if and only if it belongs to tr i All messages can be stored and consumed, tr i It can be accomplished.

[0159] (C2) When transaction tr i The potential is greater than zero if and only if for any tr j Both can be completed, tr i It can be completed. (The tr part is missing from the original text.) j with tr i They can be equal.

[0160] In the third directed connected graph G = (V, E), for any given edge e ∈ E, the number of messages pushed into the queue of edge e should not exceed cap(e). Let In(e) be the number of messages routed to edge e, and Out(e) be the number of messages routed out of edge e. When edge... For the landing of certain messages, a directed edge is formed. This includes the number of messages that have been consumed. At this moment, all messages in the queue routed to this edge should have been consumed. in and

[0161] Define when and At that time, the landing direction is oriented. There is a deadlock configuration.

[0162] Definition 3: In a third directed connected graph G = (V, E), if there exists a message Makes existence And cap(e) i ) = size(e i ), then in e i There is a message routing blocking configuration. Specifically, when e i When it is a directed edge that lands, in e i There is a deadlock configuration.

[0163] Definition 4: In a third directed connected graph G = (V, E), if there exists a transaction tr i This makes a message exist. Make any edge If there is a message routing blocking configuration, then there is a routing blocking configuration in the third directed connected graph G=(V,E).

[0164] Definition 5: In a SoC, for a given transaction dependency If a transaction exists And tr j If it cannot be completed, then There exists a deadlock chain.

[0165] Definition 6: In a third directed connected graph G = (V, E), for any e i ∈E, if there exists a message satisfy Furthermore, if the message has a message routing blocking configuration on this edge, then there is a deadlock configuration in the third directed connected graph G=(V,E).

[0166] In this embodiment of the disclosure, deadlock detection can be performed using the following theorem:

[0167] Theorem 1: In the third directed connected graph G = (V, E), if for any transaction tr i ∈T r , has to(tr iIf ) = 1, then the third directed connected graph G is related to the third directed connected dependent graph G. D There is a ring in the middle And for each In the finite case, a route-blocking configuration exists in the third directed connected graph G. Specifically, when there exists to(tr i When )>1, this is a sufficient condition for the existence of a route blocking configuration in the third directed connected graph G.

[0168] Corollary 1: In the third directed connected graph G = (V, E), if for any transaction tr i ∈T r , has to(tr i If )>1, then there are two different messages. satisfy and At that time, there exists a route blocking configuration in graph G=(V,E).

[0169] Theorem 2: If there is a route blocking configuration in a third directed connected graph G = (V, E), then there exists a tr i ∈T r It cannot be completed.

[0170] Corollary 2: If there is a route blocking configuration in the third directed connected graph G=(V,E), then there exists a transaction dependency containing a deadlock chain.

[0171] Theorem 3: If there exists a deadlock configuration in a third directed connected graph G = (V, E), then for any given There is a deadlock chain in both.

[0172] Theorem 4: In the third directed connected graph G = (V, E), for any given D tri If there are two transactions satisfy Then in There is a deadlock chain in it.

[0173] In one possible implementation, after obtaining the third directed connected graph and the third directed connected dependency graph, a target connected path forming a cycle can be found from the connected paths included in the third directed connected graph. If the target connected path is a true deadlock cycle under the condition of having an escape mechanism, then the path in the third directed connected dependency graph corresponding to the target connected path is determined as the deadlock path.

[0174] In one example, based on the third directed connected graph G = (V, E) and the third directed connected dependency graph G D Deadlock detection algorithms may include the following steps:

[0175] S1. Determine the set

[0176] S2, Search for the third directed connected dependency graph G D The ring r in i Based on the above verification algorithm, the searched ring r is verified. i Is it still a true deadlock cycle even with an escape mechanism (e.g., message retransmission)? If it is a true deadlock cycle, then let RingP = RingP∪{r} i}

[0177] S3, according to ring r i Given a third directed connected graph G, output the corresponding path p in the third directed connected graph G, and let D = D∪{p}.

[0178] S4. Repeat steps S2-3. When the third directed connected dependency graph G... D The program exits after all connected paths have been searched. Set D is the set of deadlock paths in the SoC.

[0179] In this embodiment of the disclosure, if the third directed connected dependency graph G D The ring r in i If a deadlock loop still exists even with an escape mechanism, then the third directed connected graph G containing the loop r is considered as follows: i The corresponding path p is identified as a deadlock path. By searching for deadlock paths that meet the above conditions, all deadlock paths included in the SoC can be detected, ensuring the accuracy and comprehensiveness of deadlock detection for the SoC.

[0180] In one possible implementation, NoC's routing algorithm R NOC The tool can define an input interface, which chip developers (such as architects) can use to define the routing algorithm R. NOC Therefore, the aforementioned third directed connected graph G and third directed connected dependent graph G D These are all tools based on the input routing algorithm R NOC It is automatically generated and does not require much human intervention to avoid human error.

[0181] The tool defines a verification algorithm input interface, which users can customize. This disclosure provides a verification algorithm to verify the searched cycles. The following is an example of one such verification algorithm from this disclosure:

[0182] In ARM's CHI protocol, a link-layer retransmission mechanism is used to resolve some routing congestion. Figure 8A pseudo-deadlock loop is shown in a 4x6 mesh on-chip network (e.g., ARM's CMN) implemented using the ARM CHI protocol. Figure 8 As shown, because network access devices 48 and 768 (yellow in the diagram above) issue read requests, they will both go to HN-F58 and HN-F778, with routing paths as indicated by the black and red dashed arrows in the diagram, respectively. After receiving the request transactions, HN-F58 and HN-F778 generate further requests due to transaction and microarchitecture dependencies, which are then routed to devices 55 and 775 (blue devices in the diagram above) according to the black and red dashed arrows, respectively. Because the queue depth of each node is finite, the entire transaction processing generates a third directed connectivity dependency graph G obtained from the abstract model. D Therefore, a cycle r is detected in step S2 of the deadlock detection algorithm. i However, in reality, both device HN-F778(58) and device SN-F775(55) utilize the retransmission mechanism to retransmit the blocked messages in the queue of this ring, thereby releasing the queue and allowing the messages in the entire ring to move forward. Therefore, this ring may be a false ring. Therefore, the algorithm tool of this disclosure embodiment can automatically use the verification algorithm to verify whether the ring is true or false.

[0183] Figure 9 This is a subgraph of a third directed connected dependency graph according to an embodiment of this disclosure. For example... Figure 9 As shown, e_{02,03} represents the directed edge from vertex 02 to vertex 03, and so on.

[0184] (1) Based on transaction abstraction, mark the device nodes that can receive messages that can be retransmitted, process message transactions, and send messages. Let the set of these device nodes be V. D ={v1,v2,…,n m}, Figure 9 The green and yellow nodes are both V. D The element in V D It is a subset of the vertex set E of the third directed connected graph G = (V, E). Let these device nodes v be... i The transaction dependency subgraph generated after abstract modeling is H. Di (i = 1, 2, ..., m), these device nodes and the directed connectivity dependency graph generated after NoC modeling. The set of connected nodes is It is the third directed connected dependency graph G D A subset of nodes.

[0185] (2)V D device node v i ∈V D Its transactions depend on the request-receiving edge e of the directed subgraph.i ∈I D The message in the middle must come from set V. D A node v in i To do this:

[0186] (i) In the third directed connected graph G=(V,E), from node v i Starting from the request channel, a reverse search is performed to eventually obtain the corresponding node.

[0187] (ii) Based on the routing function, find the corresponding third directed connected dependency graph G. D = A subset of nodes in (E,I) (which is also a subset of edges in the third directed connected graph G) The edges all correspond to the node v. i of The request (transaction) exit edge of the middle node (e.g.) Figure 9 The yellow nodes in the middle, e_{768,60} and e_{48,03}, belong to the set. ).

[0188] (iii) For the deadlock detection algorithm, the cycle found If there are two device nodes' request entry edges e j ,e k ∈I D It is also in this ring, namely e j ,e k ∈r i Then at this point: if it exists Then ring r i It's a true cycle; otherwise, it's because of retransmissions, degenerating into a false cycle. For example... Figure 9 The subgraph in the image is a cycle that the deadlock detection algorithm finds, but the verification algorithm finds that the node marked in yellow is not in this cycle, so it is verified as a false cycle.

[0189] Deadlock detection algorithms may find a cycle, such as Figure 9 As shown, this pure routing loop solves the deadlock problem through retransmission, and more importantly, the transactions that can be retransmitted are in the third directed connected dependency graph G. D Does a deadlock configuration cycle exist within the transaction? Therefore, the deadlock configuration cycle detection algorithm essentially checks whether a deadlock configuration cycle also exists within the transaction after finding a physical connection cycle.

[0190] Figure 10 This disclosure includes a schematic diagram of a transaction process according to an embodiment, comprising: Figure 4 A schematic diagram of the transaction flow of subsystem HN-F(778) and subsystem HN-F(58). Figure 10 As shown, in the third directed connected dependency graph GD In the diagram, the red and green edges do not form a cycle, nor do the blue and black edges. That is, in the transaction dependency subgraphs HN-F(778) and HN-F(58), the subgraphs H... Di Subgraph H Dj Merge into the third directed connected dependency graph G D In the middle and later stages, the transactions of nodes HN-F(778) and HN-F(58) in the above figure do not form a dependency cycle between them.

[0191] Figure 11 A schematic diagram of a third directed connectivity dependency graph according to an embodiment of the present disclosure is shown. Figure 12 It shows Figure 11 The directed dependent subgraph corresponding to the third directed connected dependent graph G in the graph. Figure 13 This demonstrates how to detect deadlock from... Figure 12 The directed dependency subgraph SubG is shown. D A schematic diagram of the deadlock configuration loop detected in the system.

[0192] like Figure 13 As shown, the path formed by the red edge and vertices constitutes a deadlock configuration cycle. The directed edge connecting vertices e_{70_71} and e_{71_72} in the corresponding dependency subgraph inside the accelerator is because the accelerator needs to report an interrupt to the core after receiving an operation; this edge is logical. The specific transactional meaning behind the deadlock is:

[0193] (1) The core initiates a write to the accelerator to control the configuration of the accelerator;

[0194] (2) When the accelerator receives a specific configuration from the core, it will report an interrupt to the core, expecting the software to intervene and configure some things. The accelerator will complete the specific configuration of the core only when the software configuration is completed.

[0195] (3) This interrupt happens to be routed to the core that was previously configured;

[0196] (4) The necessary condition for this core to handle this interruption is that all previous configuration operations must be completed;

[0197] (5) When the queue for receiving read and write configurations of the accelerator is full, a deadlock in transactions is formed.

[0198] In summary, the deadlock detection method provided in this disclosure, based on mathematical graph theory, achieves automatic deadlock detection through abstract modeling of the chip's on-chip network and transaction processing. This allows for verification of deadlock issues in the entire chip system during the early stages of chip architecture and microarchitecture design. The deadlock detection method provided in this embodiment does not require Register Transfer Level (RTL) functional code and provides 100% accurate deadlock detection. Compared to related technologies that rely on EDA functional simulation and hardware prototype verification to discover deadlocks, this solution can detect problems earlier, more accurately, and more comprehensively. The deadlock detection algorithm provided in this disclosure has a high degree of automation, requiring minimal human intervention, greatly reducing human error, and significantly improving efficiency.

[0199] On-chip system design method

[0200] Figure 14 This is a flowchart of a system-on-a-chip design method according to an embodiment of this disclosure. Figure 14 As shown, the on-chip system design method includes the following steps:

[0201] Step 1401: Map the on-chip network included in the system-on-chip design to a first directed connectivity graph. The first directed connectivity graph is used to indicate the access devices connected to the on-chip network and the routing bus of the on-chip network.

[0202] In the design, the system-on-a-chip (SoC) is a system-on-a-chip that is in the design process. It can be the initial design of the SoC or the intermediate design of the SoC.

[0203] Step 1402: Determine the first directed connectivity dependency graph based on the first directed connectivity graph and the routing algorithm of the on-chip network. The first directed connectivity dependency graph is used to indicate the dependencies between the routing buses included in the on-chip network.

[0204] Step 1403: Map the subsystems for transaction processing included in the system-on-a-chip design into a second directed connected graph. The second directed connected graph is used to indicate the message passing paths between functional modules in the subsystems.

[0205] Step 1404: Determine the second directed connected dependency graph based on the second directed connected graph and the logical routing algorithm corresponding to the subsystem. The second directed connected dependency graph is used to indicate the dependency relationship between message passing paths.

[0206] Step 1405: Based on the first and second directed connected graphs, determine the third directed connected graph corresponding to the on-chip system in the design.

[0207] Step 1406: Based on the first and second directed connected dependency graphs, determine the third directed connected dependency graph corresponding to the on-chip system in the design.

[0208] Step 1407: Based on the third directed connected graph and the third directed connected dependency graph, perform deadlock detection on the on-chip system in the design and obtain the deadlock detection results.

[0209] Deadlock detection results can indicate whether deadlock exists in the on-chip system of the design, and indicate the deadlock path when deadlock exists in the on-chip system of the design.

[0210] Step 1408: Optimize the on-chip system in the design based on the deadlock detection results.

[0211] Deadlock detection results can determine whether deadlock exists in the on-chip system design. If deadlock exists, the design can be optimized based on the deadlock path indicated by the deadlock detection results to eliminate the deadlock. If no deadlock exists, subsequent verification and implementation phases in the on-chip system design process can continue.

[0212] In this embodiment, the NoC is abstracted as a first directed connected graph, and the subsystem for transaction processing is abstracted as a second directed connected graph. A first directed connected dependency graph is constructed based on the first directed connected graph according to the routing algorithm of the NoC. A second directed connected dependency graph is constructed based on the second directed connected graph according to the logical routing algorithm corresponding to the subsystem. The first and second directed connected graphs are merged and interconnected to form a third directed connected graph. After merging and interconnecting the first and second directed connected dependency graphs to form the third directed connected dependency graph, deadlock detection is performed on the SoC in the design based on the third directed connected graph and the third directed connected dependency graph to obtain the deadlock detection result. Then, when deadlock exists in the SoC in the design, the SoC in the design is optimized based on the deadlock detection result to eliminate the deadlock in the SoC in the design. Based on mathematical graph theory, this paper achieves deadlock detection of SoC by abstracting and modeling NoC and transaction processing in SoC design. This allows for deadlock detection and modification of SoC in the early stages of SoC architecture and microarchitecture design. Compared to discovering deadlocks after SoC has entered the code development stage, this reduces the cost of modifying SoC design and thus lowers the overall design cost of SoC.

[0213] It should be noted that the on-chip system design method in this embodiment is based on the deadlock detection method in the foregoing embodiments. Therefore, the on-chip system design method in this embodiment is a specific application of the foregoing deadlock detection method embodiments. The on-chip system design method is applicable to the architectural and microarchitecture design of various types of on-chip systems. The specific process of deadlock detection in the on-chip system design method in this embodiment can be found in the description of the foregoing deadlock detection method embodiments, and will not be repeated here.

[0214] Deadlock detection device

[0215] Figure 15 A schematic diagram of a deadlock detection device 150 according to an embodiment of this disclosure is shown. Figure 15 As shown, the deadlock detection device 150 includes:

[0216] The first mapping unit 151 is used to map the on-chip network included in the system-on-chip to a first directed connectivity graph, the first directed connectivity graph being used to indicate access devices connected to the on-chip network and routing buses of the on-chip network.

[0217] The first processing unit 152 is used to determine a first directed connectivity dependency graph based on a first directed connectivity graph and a routing algorithm of the on-chip network. The first directed connectivity dependency graph is used to indicate the dependency relationships between the routing buses included in the on-chip network.

[0218] The second mapping unit 153 is used to map the subsystems for transaction processing included in the on-chip system into a second directed connected graph, the second directed connected graph being used to indicate the message passing paths between functional modules in the subsystems;

[0219] The second processing unit 154 is used to determine the second directed connected dependency graph based on the second directed connected graph and the logical routing algorithm corresponding to the subsystem. The second directed connected dependency graph is used to indicate the dependency relationship between message passing paths.

[0220] The first integration unit 155 is used to determine a third directed connected graph corresponding to the on-chip system based on the first directed connected graph and the second directed connected graph.

[0221] The second integration unit 156 is used to determine a third directed connected dependency graph corresponding to the on-chip system based on the first directed connected dependency graph and the second directed connected dependency graph.

[0222] The detection unit 157 is used to perform deadlock detection on the on-chip system based on the third directed connected graph and the third directed connected dependency graph.

[0223] In this embodiment of the disclosure, the first mapping unit 151 abstracts the NoC into a first directed connected graph, the first processing unit 152 abstracts the subsystem used for transaction processing into a second directed connected graph, the second mapping unit 153 constructs a first directed connected dependency graph based on the first directed connected graph according to the routing algorithm of the NoC, the second processing unit 154 constructs a second directed connected dependency graph based on the second directed connected graph according to the logical routing algorithm corresponding to the subsystem, the first integration unit 155 merges and interconnects the first and second directed connected graphs into a third directed connected graph, the second integration unit 156 merges and interconnects the first and second directed connected dependency graphs into a third directed connected dependency graph, and the detection unit 157 performs deadlock detection on the SoC based on the third directed connected graph and the third directed connected dependency graph. Based on mathematical graph theory, deadlock detection of SoC is achieved by abstracting and modeling NoC and transaction processing in SoC. This allows deadlock detection to be performed in the early stages of SoC architecture and microarchitecture design. Compared to discovering deadlocks after the SoC has entered the code development stage and then making modifications, this reduces the cost of modifying the SoC design and thus reduces the overall design cost of the SoC.

[0224] It should be noted that the deadlock detection device in this embodiment is used to implement the deadlock detection method in the aforementioned method embodiment and has the beneficial effects of the corresponding method embodiment, which will not be repeated here.

[0225] electronic devices

[0226] Figure 16 This is a schematic block diagram of an electronic device provided in an embodiment of this disclosure. Specific embodiments of this disclosure do not limit the specific implementation of the electronic device. Figure 16 As shown, the electronic device may include: a processor 1602, a communications interface 1604, a memory 1606, and a communication bus 1608. Wherein:

[0227] The processor 1602, communication interface 1604, and memory 1606 communicate with each other via communication bus 1608.

[0228] Communication interface 1604 is used to communicate with other electronic devices or servers.

[0229] The processor 1602 is used to execute program 1610, which can specifically execute the relevant steps in any of the aforementioned deadlock detection method embodiments or on-chip system design method embodiments.

[0230] Specifically, program 1610 may include program code that includes computer operation instructions.

[0231] The processor 1602 may be a CPU, an application-specific integrated circuit (ASIC), or one or more integrated circuits configured to implement embodiments of this disclosure. The smart device may include one or more processors of the same type, such as one or more CPUs; or it may include processors of different types, such as one or more CPUs and one or more ASICs.

[0232] Memory 1606 is used to store program 1610. Memory 1606 may include high-speed RAM memory, and may also include non-volatile memory, such as at least one disk storage device. Specifically, program 1610 can be used to cause processor 1602 to execute the deadlock detection method or on-chip system design method in any of the foregoing embodiments.

[0233] The specific implementation of each step in program 1610 can be found in the corresponding steps and units described in any of the aforementioned deadlock detection method embodiments or on-chip system design method embodiments, and will not be repeated here. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working process of the devices and modules described above can be referred to the corresponding process descriptions in the aforementioned method embodiments, and will not be repeated here.

[0234] In the electronic device of this disclosure, the NoC (No Connectivity) is abstracted as a first directed connected graph, and the subsystem for transaction processing is abstracted as a second directed connected graph. A first directed connected dependency graph is constructed based on the first directed connected graph according to the routing algorithm of the NoC. A second directed connected dependency graph is constructed based on the second directed connected graph according to the logical routing algorithm corresponding to the subsystem. The first and second directed connected graphs are merged and interconnected to form a third directed connected graph. After merging and interconnecting the first and second directed connected dependency graphs to form the third directed connected dependency graph, deadlock detection is performed on the SoC based on the third directed connected graph and the third directed connected dependency graph. Based on the theoretical foundation of mathematical graph theory, deadlock detection of the SoC is achieved by abstractly modeling the NoC and transaction processing in the SoC. This allows for deadlock detection of the SoC in the early stages of SoC architecture and microarchitecture design. Compared to discovering deadlocks after the SoC has entered the code development stage and then making modifications, this reduces the cost of modifying the SoC design, thereby reducing the overall design cost of the SoC.

[0235] Computer storage media

[0236] This disclosure also provides a computer-readable storage medium storing instructions for causing a machine to perform the deadlock detection method or system-on-a-chip design method as described herein. Specifically, a system or apparatus equipped with a storage medium storing software program code that implements the functions of any of the embodiments described above, and enabling a computer (or CPU or MPU) of the system or apparatus to read and execute the program code stored in the storage medium.

[0237] In this case, the program code read from the storage medium can itself implement the function of any of the above embodiments, and therefore the program code and the storage medium storing the program code constitute a part of this disclosure.

[0238] Examples of storage media used to provide program code include floppy disks, hard disks, magneto-optical disks, optical disks (such as CD-ROM, CD-R, CD-RW, DVD-ROM, DVD-RAM, DVD-RW, DVD+RW), magnetic tapes, non-volatile memory cards, and ROMs. Alternatively, program code can be downloaded from a server computer via a communication network.

[0239] Computer program products

[0240] This disclosure also provides a computer program product, including computer instructions that instruct a computing device to perform any corresponding operation in the above-described plurality of method embodiments.

[0241] It should be noted that the user-related information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to sample data used for training the model, data used for analysis, stored data, displayed data, etc.) involved in the embodiments of this disclosure are all information and data authorized by the user or fully authorized by all parties. Furthermore, the collection, use and processing of related data must comply with the relevant laws, regulations and standards of the relevant countries and regions, and corresponding operation entry points are provided for users to choose to authorize or refuse.

[0242] It should be noted that, depending on the implementation needs, the various components / steps described in the embodiments of this disclosure can be broken down into more components / steps, or two or more components / steps or parts of the operation of components / steps can be combined into new components / steps to achieve the purpose of the embodiments of this disclosure.

[0243] The methods described above according to embodiments of this disclosure can be implemented in hardware, firmware, or as software or computer code that can be stored in a recording medium (such as a CD-ROM, RAM, floppy disk, hard disk, or magneto-optical disk), or as computer code originally stored on a remote recording medium or a non-transitory machine-readable medium and subsequently stored on a local recording medium, downloaded over a network. Thus, the methods described herein can be processed by software stored on a recording medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware (such as an ASIC or FPGA). It is understood that the computer, processor, microprocessor controller, or programmable hardware includes storage components (e.g., RAM, ROM, flash memory, etc.) capable of storing or receiving software or computer code that, when accessed and executed by the computer, processor, or hardware, implements the methods described herein. Furthermore, when a general-purpose computer accesses code used to implement the methods shown herein, the execution of the code transforms the general-purpose computer into a dedicated computer for executing the methods shown herein.

[0244] It should be noted that the user-related information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to sample data used for training the model, data used for analysis, stored data, displayed data, etc.) involved in the embodiments of this disclosure are all information and data authorized by the user or fully authorized by all parties. Furthermore, the collection, use and processing of related data must comply with the relevant laws, regulations and standards of the relevant countries and regions, and corresponding operation entry points are provided for users to choose to authorize or refuse.

[0245] Those skilled in the art will recognize that the units and method steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for specific applications, but such implementations should not be considered beyond the scope of the embodiments disclosed herein.

[0246] The above embodiments are only used to illustrate the embodiments of this disclosure, and are not intended to limit the embodiments of this disclosure. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the embodiments of this disclosure. Therefore, all equivalent technical solutions also fall within the scope of the embodiments of this disclosure, and the patent protection scope of the embodiments of this disclosure should be defined by the claims.

Claims

1. A system-on-a-chip design method, comprising: The on-chip network included in the system-on-chip design is mapped to a first directed connectivity graph, which is used to indicate the access devices connected to the on-chip network and the routing bus of the on-chip network. Based on the first directed connectivity graph and the routing algorithm of the on-chip network, a first directed connectivity dependency graph is determined, which is used to indicate the dependency relationship between the routing buses included in the on-chip network. The system-on-chip in the design includes a subsystem for transaction processing, which is mapped to a second directed connected graph. The second directed connected graph is used to indicate the message passing path between functional modules in the subsystem. Based on the second directed connected graph and the logical routing algorithm corresponding to the subsystem, a second directed connected dependency graph is determined. The second directed connected dependency graph is used to indicate the dependency relationship between the message passing paths. Based on the first directed connected graph and the second directed connected graph, a third directed connected graph corresponding to the on-chip system in the design is determined; Based on the first directed connected dependency graph and the second directed connected dependency graph, a third directed connected dependency graph corresponding to the on-chip system in the design is determined; Based on the third directed connected graph and the third directed connected dependency graph, deadlock detection is performed on the on-chip system in the design to obtain the deadlock detection result; Based on the deadlock detection results, the on-chip system in the design is optimized.

2. A deadlock detection method, comprising: The on-chip network included in the system-on-chip is mapped to a first directed connectivity graph, which is used to indicate access devices connected to the on-chip network and the routing bus of the on-chip network. Based on the first directed connectivity graph and the routing algorithm of the on-chip network, a first directed connectivity dependency graph is determined, which is used to indicate the dependency relationship between the routing buses included in the on-chip network. The on-chip system includes a subsystem for transaction processing, which is mapped to a second directed connected graph. The second directed connected graph is used to indicate the message passing path between functional modules in the subsystem. Based on the second directed connected graph and the logical routing algorithm corresponding to the subsystem, a second directed connected dependency graph is determined. The second directed connected dependency graph is used to indicate the dependency relationship between the message passing paths. Based on the first directed connected graph and the second directed connected graph, a third directed connected graph corresponding to the on-chip system is determined; Based on the first directed connected dependency graph and the second directed connected dependency graph, a third directed connected dependency graph corresponding to the on-chip system is determined; Deadlock detection is performed on the on-chip system based on the third directed connected graph and the third directed connected dependency graph.

3. The method according to claim 2, wherein, The step of mapping the transaction processing subsystems included in the system-on-a-chip to a second directed connected graph includes: mapping at least two transaction processing subsystems included in the system-on-a-chip to corresponding second directed connected graphs respectively; The step of determining the second directed connected dependency graph based on the second directed connected graph and the logical routing algorithm corresponding to the subsystem includes: determining the second directed connected dependency graph corresponding to the subsystem based on the second directed connected graph corresponding to the subsystem and the logical routing algorithm.

4. The method according to claim 2, wherein, The step of mapping the on-chip network included in the on-chip system to a first directed connected graph includes: Based on the access devices connected to the on-chip network and the routing bus included in the on-chip network, the first directed connectivity graph G is determined. N =(V N E N The first directed connected graph G N Mid-vertex set V N The included elements represent access devices connected to the on-chip network, and the first directed connected graph G N In the directed edge set E N The included elements constitute the routing bus of the on-chip network.

5. The method according to claim 4, wherein, The step of determining the first directed connectivity dependency graph based on the first directed connectivity graph and the routing algorithm of the on-chip network includes: According to the first directed connected graph G N =(V N E N The routing algorithm of the on-chip network is used to determine the first directed connectivity dependency graph. The first directed connected dependency graph Vertex set E in N Let G be the first directed connected graph. N The directed edge set E in N The first directed connected dependency graph Directed edge set I N Included elements <e i ,e j >Satisfies: In the first directed connected graph G N edge e in i queue q i In the middle, there exists a destination access device v i message m i The next hop, and message m i The next hop is to go to the first directed connected graph G. N edge e in j queue q j .

6. The method according to claim 2, wherein, The step of mapping the subsystems for transaction processing included in the on-chip system to a second directed connected graph includes: Based on the functional modules included in the access devices corresponding to the subsystem, determine the second directed connectivity graph corresponding to the subsystem. The second directed connected graph Mid-vertex set The included elements represent the access device V corresponding to the subsystem. i Included functional modules, the second directed connected graph In-directed edge set The included elements represent the access device V. i The message passing path between functional modules.

7. The method according to claim 6, wherein, The step of determining the second directed connected dependency graph based on the second directed connected graph and the logical routing algorithm corresponding to the subsystem includes: According to the second directed connected graph The logical routing algorithm corresponding to the subsystem determines the second directed connectivity dependency graph corresponding to the subsystem. The second directed connected dependency graph Mid-vertex set The second directed connected graph directed edge set in The second directed connected dependency graph In-directed edge set Included elements Satisfy: Access device V i Included functional modules The sent message contains message m s Message m s It will be sent to the access device V i Included functional modules 8. The method according to claim 3, wherein, The step of determining a third directed connected graph corresponding to the on-chip system based on the first directed connected graph and the second directed connected graph includes: Calculate the union of the first directed connected graph and the second directed connected graph corresponding to each subsystem included in the on-chip system to obtain the third directed connected graph corresponding to the on-chip system.

9. The method according to claim 3, wherein, The step of determining a third directed connected dependency graph corresponding to the on-chip system based on the first directed connected dependency graph and the second directed connected dependency graph includes: Calculate the first directed connected dependency graph and the second directed connected dependency graph corresponding to each subsystem included in the on-chip system to obtain the third directed connected dependency graph corresponding to the on-chip system.

10. The method according to any one of claims 1-9, wherein, The step of performing deadlock detection on the on-chip system based on the third directed connected graph and the third directed connected dependency graph includes: Find the target connected path that forms a loop from the connected paths included in the third directed connected graph; If the target connected path is a real deadlock loop under the condition of having an escape mechanism, then the path corresponding to the target connected path in the third directed connected dependency graph is determined as a deadlock path.

11. A deadlock detection device, comprising: The first mapping unit is used to map the on-chip network included in the system-on-chip to a first directed connectivity graph, wherein the first directed connectivity graph is used to indicate the access devices connected to the on-chip network and the routing bus of the on-chip network. The first processing unit is configured to determine a first directed connectivity dependency graph based on the first directed connectivity graph and the routing algorithm of the on-chip network. The first directed connectivity dependency graph is used to indicate the dependency relationships between the routing buses included in the on-chip network. The second mapping unit is used to map the subsystems for transaction processing included in the on-chip system into a second directed connected graph, wherein the second directed connected graph is used to indicate the message passing paths between functional modules in the subsystems; The second processing unit is used to determine a second directed connectivity dependency graph based on the second directed connectivity graph and the logical routing algorithm corresponding to the subsystem. The second directed connectivity dependency graph is used to indicate the dependency relationship between the message passing paths. The first integration unit is configured to determine a third directed connected graph corresponding to the on-chip system based on the first directed connected graph and the second directed connected graph. The second integration unit is used to determine a third directed connected dependency graph corresponding to the on-chip system based on the first directed connected dependency graph and the second directed connected dependency graph. The detection unit is used to perform deadlock detection on the on-chip system based on the third directed connected graph and the third directed connected dependency graph.

12. An electronic device, comprising: The processor, memory, communication interface, and communication bus communicate with each other through the communication bus. The memory is used to store at least one executable instruction that causes the processor to perform the operation corresponding to any one of the methods in claims 1-10.

13. A computer storage medium having a computer program stored thereon, which, when executed by a processor, implements the method of any one of claims 1-10.

14. A computer program product comprising computer instructions that instruct a computing device to perform the method as claimed in any one of claims 1-10.

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