Transmitting device based on DSP-DAC architecture and high-speed serial communication system

Abstract

The invention discloses a transmitting device based on a DSP-DAC framework and a high-speed serial communication system, and relates to the field of serial communication, in the device, a digital processing unit processes a signal to be transmitted based on multi-tap FIR feedforward equalization to obtain B paths of parallel A-bit data signals; the low-speed data processing module obtains C paths of parallel A-bit data signals; the differential-pulse generation module under the ith group of DAC slices receives C paths of parallel ith-bit data signals so as to obtain C paths of parallel pulse signals, the merging and serializing driving module performs merging and serializing according to the C paths of parallel pulse signals, driving corresponding to the ith group of slice weight is performed through an SST driving structure so as to output a serialized differential signal corresponding to the ith bit, and the serial differential signal corresponds to the ith bit. And a target serialized differential signal is obtained through superposition. According to the scheme, parallel-to-serial processing and output driving are combined to set the merging-serializing driving module, and a full-rate signal node is only limited at a final output stage, so that the front-end circuit design is simplified, and high speed and completeness of an output signal are ensured.

Description

Technical Field

[0001] This invention relates to the field of serial communication technology, and in particular to a transmitter and a high-speed serial communication system based on a DSP-DAC architecture. Background Technology

[0002] With the rapid development of communication technology, the demand for data transmission bandwidth between chips in data centers, artificial intelligence, and high-performance computing has exploded. Limited by the number of chip package pins, synchronization timing, and channel crosstalk, traditional parallel interfaces have become the main bottleneck for improving system bandwidth. Against this backdrop, serializer / deserializer technology has become a core solution in the field of high-speed interconnection because it can significantly reduce the number of wires and overcome the timing problems of parallel transmission.

[0003] Currently, the transmitter circuits used as high-speed serial interfaces mainly rely on two architectures: analog mixed-signal architecture and DSP-DAC architecture (Digital Signal Processing - Digital to Analog Converter). As the interface data rate increases to 56Gbps and above, the channel loss effect becomes increasingly significant. The timing of the configuration based on the analog mixed-signal architecture is very tight when implementing multi-tap equalization, making it difficult to cope with the non-ideal factors such as large attenuation, strong reflection, and high crosstalk faced by medium and long-distance transmission. It cannot solve the communication signal quality degradation caused by medium and long-distance channel transmission loss. Therefore, the configuration based on the DSP-DAC architecture has become dominant. However, in order to utilize high-order PAM (Pulse Amplitude Modulation) and DSP equalization technology, there are multiple full-rate nodes on the high-speed data path of the voltage-mode logic drive section in the current configuration. This requires additional pre-drivers, resulting in a complex circuit structure, high power consumption, and a large footprint on the layout, which is not conducive to practical applications.

[0004] Therefore, how to provide a more effective transmitter based on the DSP-DAC architecture is an urgent problem to be solved. Summary of the Invention

[0005] In view of this, the present invention provides a transmitting device and a high-speed serial communication system based on a DSP-DAC architecture. It combines the final stage of parallel data to serial data processing with output driving to set up a merging and serialization driving module. This can limit the full-rate signal nodes to the final output stage, which is beneficial to simplify the front-end circuit design. It eliminates the need for a pre-driver, which helps to reduce overall power consumption and area, while ensuring the high speed and integrity of the output target serialized differential signal.

[0006] To address the aforementioned technical problems, this application provides a transmitting device based on a DSP-DAC architecture, comprising a digital processing unit and a data path unit connected in sequence. The data path unit includes a low-speed data processing module and a high-speed data processing module. The high-speed data processing module includes A groups of DAC slices, and each group of DAC slices includes a differential-pulse generation module and a merging-serialization driving module. The digital processing unit is used to convert and process the signal to be transmitted based on multi-tap FIR feedforward equalization to obtain B parallel A-bit data signals; in the A-bit data signal, A1 bit adopts binary code and A2 bit adopts thermometer code, A1+A2=A, A1 and A2 are both integers and the number of bits of A2 is higher than A1; The low-speed data processing module is used to serialize the B-channel parallel A-bit data signals to obtain C-channel parallel A-bit data signals, where A is an integer greater than 1, B and C are even numbers greater than 1 and B > C. The differential-pulse generation module of the i-th DAC slice is used to receive the i-th bit data signal of C parallel channels, and to perform differential and pulse generation processing on it based on a preset non-full rate clock to obtain the corresponding i-th bit, C parallel pulse signal. The pulse width of the pulse signal under any channel is one symbol period, and each pulse signal corresponding to the i-th bit data signal of a group of C parallel channels is delayed by one symbol period in sequence, 1≤i≤A and i is an integer. The outputs of the merging and serialization driving modules of the A-group DAC slices are connected in parallel. The merging and serialization driving module in the i-th DAC slice is used to receive the C-channel parallel pulse signal corresponding to the i-th bit, perform merging and serialization processing on it, and drive it according to the weight corresponding to the i-th DAC slice through the SST driving structure to output the serialized differential signal corresponding to the i-th bit. Then, the A-bit serialized differential signals are superimposed to obtain the target serialized differential signal.

[0007] Furthermore, the digital processing unit includes a pseudo-random binary sequence generator and a DSP module connected in sequence; The pseudo-random binary sequence generator is used to generate B parallel data signals based on the signal to be transmitted. The DSP module is used to perform multi-tap FIR feedforward equalization and binary-to-thermometer code processing on the B-channel parallel signals to obtain the A-bit data signal in the B-channel parallel signals.

[0008] Furthermore, the low-speed data processing module includes K parallel circuits connected in sequence, where K is an integer greater than 1; Each of the parallel circuits includes multiple 2:1 MUX modules connected in parallel, and the number of 2:1 MUX modules connected in parallel varies in different parallel circuits, so as to realize the conversion of B-channel parallel A-bit data signals to C-channel parallel A-bit data signals.

[0009] Furthermore, A=9 and A1=6, A2=3; The weights of DAC slices from group 1 to group 6 are 1, 2, 4, 8, 16, and 32 respectively, to achieve weighted drive control of the lower 6 bits of binary code; the weights of DAC slices from group 7 to group 9 are 64, 64, and 64 respectively, to achieve weighted drive control of the higher 3 bits of thermometer code.

[0010] Furthermore, C=4, the differential-pulse generation module under the i-th DAC slice includes a single-ended to differential module, a retiming module and a 1UI pulse generation module connected in sequence; The single-ended to differential module is used to receive the i-th bit data signal from four parallel channels and perform single-ended to differential processing on it using a differential clock signal to obtain the first intermediate differential signal from four parallel channels corresponding to the i-th bit. The retiming module is used to receive the first intermediate differential signal corresponding to the i-th bit, which is 4 parallel channels, and to use a 1 / 4 rate four-phase clock signal to synchronize and delay it with 1UI, so as to obtain the second intermediate differential signal corresponding to the i-th bit, which is 4 parallel channels and is delayed by one symbol period in sequence. The 1UI pulse generation module is used to receive the second intermediate differential signal corresponding to the i-th bit, which is 4 parallel channels and sequentially delayed by one symbol period, and to perform narrow pulse generation processing using the 1 / 4 rate four-phase clock signal to obtain a pulse signal group corresponding to the i-th bit, which is 4 parallel channels; the pulse signal group under any channel includes a first pulse signal corresponding to the positive output terminal and a second pulse signal corresponding to the negative output terminal, and the pulse width of the first pulse signal and the second pulse signal is one symbol period, and the two adjacent pulse signal groups under any channel are separated by 3 symbol periods.

[0011] Furthermore, the 1UI pulse generation module includes 4 sets of processing circuits. The j-th set of processing circuits corresponding to the j-th channel includes two logic gate circuits. The input of the first logic gate circuit is used to receive the positive differential signal of the j-th channel second intermediate differential signal and the output is used to output the first pulse signal corresponding to the positive output terminal. The input of the second logic gate circuit is used to receive the negative differential signal of the j-th channel second intermediate differential signal and the output is used to output the second pulse signal corresponding to the negative output terminal. 1≤j≤4 and j is an integer. The logic gate circuit includes two NOT gates, two AND gates, and two OR gates; the 1 / 4 rate four-phase clock signal includes a first clock signal, a second clock signal, a third clock signal, and a fourth clock signal with phases differing by 90 degrees in sequence; The inputs of the first NOT gate and the second NOT gate are connected, and the common terminal of the connection is used as the input of the logic gate circuit. The first input terminal of the second AND gate is connected to the output terminal of the first NOT gate, the second input terminal is connected to the output terminal of the first AND gate, and the output terminal serves as the first output terminal among the output terminals of the logic gate circuit. The first input terminal of the second OR gate is connected to the output terminal of the second NOT gate, the second input terminal is connected to the output terminal of the first OR gate, and the output terminal serves as the second output terminal in the logic gate circuit. Corresponding to the first group of processing circuits of the first path, the first input terminal of the first AND gate of the two logic gate circuits below is used to connect to the first clock signal and the second input terminal is used to connect to the second clock signal; the first input terminal of the first OR gate is used to connect to the third clock signal and the second input terminal is used to connect to the fourth clock signal. Corresponding to the second group of processing circuits in the second channel, the first input terminal of the first AND gate in the two logic gate circuits below is used to connect to the second clock signal and the second input terminal is used to connect to the third clock signal; the first input terminal of the first OR gate is used to connect to the fourth clock signal and the second input terminal is used to connect to the first clock signal. Corresponding to the third group of processing circuits in the third path, the first input terminal of the first AND gate in the two logic gate circuits below is used to connect to the third clock signal and the second input terminal is used to connect to the fourth clock signal; the first input terminal of the first OR gate is used to connect to the first clock signal and the second input terminal is used to connect to the second clock signal. Corresponding to the fourth group of processing circuits in the fourth path, the first input of the first AND gate in the two logic gate circuits below is used to connect to the fourth clock signal and the second input is used to connect to the first clock signal; the first input of the first OR gate is used to connect to the second clock signal and the second input is used to connect to the third clock signal.

[0012] Furthermore, the merging and serialization driving module under the i-th DAC slice includes a merging and serialization driving circuit corresponding to the positive output terminal and a merging and serialization driving circuit corresponding to the negative output terminal; wherein, the pulse input terminal of the merging and serialization driving circuit corresponding to the positive output terminal is used to receive the first pulse signal in the four parallel pulse signal groups and the output terminal is used to output the positive serialization differential signal in the serialization differential signal corresponding to the i-th bit; the pulse input terminal of the merging and serialization driving circuit corresponding to the negative output terminal is used to receive the second pulse signal in the four parallel pulse signal groups and the output terminal is used to output the negative serialization differential signal in the serialization differential signal corresponding to the i-th bit. The merging and serialization driving circuit includes a serialization module, an impedance matching resistor, a first tunable circuit and a second tunable circuit corresponding to the weight settings of the i-th group of DAC slices. The first terminal of the first tunable circuit is connected to the power supply, the second terminal is connected to the first terminal of the serialization module, and the control terminal is connected to the control module; the first terminal of the second tunable circuit is connected to the second terminal of the serialization module, the second terminal is grounded, and the control terminal is connected to the control module. The control terminal of the serialization module serves as the pulse input terminal of the merging and serialization driving circuit, and its output terminal is connected to one end of the impedance matching resistor, with the other end of the impedance matching resistor serving as the output terminal of the merging and serialization driving circuit. The control module is used to adjust the equivalent impedance of the first tunable circuit and the second tunable circuit so that the total equivalent output impedance of the merging and serializing driver module under the i-th DAC slice matches the target output impedance corresponding to the i-th DAC slice.

[0013] Furthermore, the serialization module includes two controllable switch groups; The first terminal of the first controllable switch group serves as the first terminal of the serialization module, and the second terminal is connected to the first terminal of the second controllable switch group, with the common terminal of the connection serving as the output terminal of the serialization module. The second terminal of the second controllable switch group serves as the second terminal of the serialization module; Corresponding to the merging and serializing drive circuit at the positive output terminal, the control terminal of the first controllable switch group in the lower serialization module is used to receive the first pulse sub-signal in the four parallel first pulse signals, and the control terminal of the second controllable switch group is used to receive the second pulse sub-signal in the four parallel first pulse signals. Corresponding to the negative output terminal of the merging and serializing drive circuit, the control terminal of the first controllable switch group in the lower serialization module is used to receive the first pulse sub-signal in the four parallel second pulse signals, and the control terminal of the second controllable switch group is used to receive the second pulse sub-signal in the four parallel second pulse signals.

[0014] Furthermore, both the first tunable circuit and the second tunable circuit include a controllable switch array; The controllable switch array includes 15 first controllable switches with size parameters corresponding to the weights of the i-th group of DAC slices. The first controllable switches are connected in parallel and the control terminal of each first controllable switch is connected to the control module. The first controllable switch is used to turn on and off according to the 4-bit binary code output by the control module, so that the equivalent impedance of the controllable switch array presents a target binary weight relationship.

[0015] To address the aforementioned technical problems, the present invention also provides a high-speed serial communication system, including a transmitting device based on the DSP-DAC architecture as described above.

[0016] This application provides a transmitting device and a high-speed serial communication system based on a DSP-DAC architecture. The device includes a digital processing unit and a data path unit connected in sequence. The data path unit includes a low-speed data processing module and a high-speed data processing module. The high-speed data processing module includes A groups of DAC slices, each group of which includes a differential-pulse generation module and a merging-serialization driving module. The digital processing unit is used to convert and process the signal to be transmitted based on multi-tap FIR feedforward equalization to obtain B parallel A-bit data signals. In the A-bit data signals, A1 bits use binary code and A2 bits use thermometer code. The low-speed data processing module is used to serialize the B parallel A-bit data signals to obtain C parallel A-bit data signals. The differential-pulse generation module of the i-th group of DAC slices... The pulse generation module receives the i-th parallel data signal from C channels and performs differential and pulse generation processing on it based on a preset non-full-rate clock to obtain a C-channel parallel pulse signal corresponding to the i-th bit. The pulse width of the pulse signal under any channel is one symbol period, and the pulse signals corresponding to the i-th parallel data signal of a group of C channels are delayed by one symbol period. The output terminals of the merging and serialization driving modules of the A-group DAC slices are connected in parallel. The merging and serialization driving module in the i-group DAC slice receives the C-channel parallel pulse signal corresponding to the i-th bit, performs merging and serialization processing on it, and drives the weight corresponding to the i-group DAC slice through the SST driving structure to output the serialized differential signal corresponding to the i-th bit. Then, the A-bit serialized differential signals are superimposed to obtain the target serialized differential signal. As can be seen, this scheme combines the final stage of parallel data to serial data processing with the output drive to set up a merging and serialization driver module. This allows the full-rate signal nodes to be limited to the final output stage, which simplifies the front-end circuit design, eliminates the need for a pre-driver, reduces overall power consumption and area, and ensures the high speed and integrity of the output target serialized differential signal, which is beneficial for practical applications.

[0017] The above description is only an overview of the technical solution of this application. In order to better understand the technical means of this application, it can be implemented according to the contents of the specification. In order to make the above and other objects, features and advantages of this application more obvious and understandable, the following are specific embodiments of this application. Attached Figure Description

[0018] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings: Figure 1 A schematic diagram of a transmitting device based on a DSP-DAC architecture provided by the present invention; Figure 2 A schematic diagram of another transmitting device based on a DSP-DAC architecture provided by the present invention; Figure 3 This invention provides a schematic diagram of the structure of a high-speed data processing module. Figure 4 This invention provides a schematic diagram of the data stream output after processing by a single-ended to differential converter module. Figure 5 A schematic diagram of the data stream output after processing by the retiming module is provided by the present invention; Figure 6 This is a schematic diagram of the data stream output after processing by the 1UI pulse generation module provided by the present invention; Figure 7 A schematic diagram of a 1 / 4 rate four-phase clock signal provided by the present invention; Figure 8 This invention provides a schematic diagram of the structure of the first group of processing circuits corresponding to the first channel; Figure 9 This invention provides a schematic diagram of the structure of the second group of processing circuits corresponding to the second path; Figure 10 This invention provides a schematic diagram of the structure of the third group of processing circuits corresponding to the third channel; Figure 11 This invention provides a schematic diagram of the structure of the fourth group of processing circuits corresponding to the fourth channel; Figure 12 A schematic diagram of a merging and serializing drive circuit corresponding to the positive output terminal is provided by the present invention; Figure 13 This is a schematic diagram of a merging and serialization driving circuit corresponding to the negative output terminal provided by the present invention. Detailed Implementation

[0019] The core of this invention is to provide a transmitter and a high-speed serial communication system based on a DSP-DAC architecture. It combines the final stage of parallel data to serial data conversion with the output drive to set up a merging and serialization driver module. This allows the full-rate signal nodes to be limited to the final output stage, which simplifies the front-end circuit design, eliminates the need for a pre-driver, and helps reduce overall power consumption and area, while ensuring the high speed and integrity of the output target serialized differential signal.

[0020] The technical solutions of the embodiments of this application will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application are within the scope of protection of this application.

[0021] The terms "first," "second," etc., used in this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class, without limiting the number of objects; for example, a first object can be one or more. Furthermore, in this application, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects have an "or" relationship.

[0022] Please refer to Figure 1 , Figure 1 This is a schematic diagram of a transmitting device based on a DSP-DAC architecture provided by the present invention.

[0023] The transmitting device based on the DSP-DAC architecture includes a digital processing unit 1 and a data path unit 2 connected in sequence. The data path unit 2 includes a low-speed data processing module 21 and a high-speed data processing module 22. The high-speed data processing module 22 includes A-group DAC slices 221. Each group of DAC slices 221 includes a differential-pulse generation module 31 and a merging-serialization driving module 32. Digital processing unit 1 is used to convert and process the signal to be transmitted based on multi-tap FIR feedforward equalization to obtain B parallel A-bit data signals; A1 bit in the A-bit data signal uses binary code and A2 bit uses thermometer code, A1+A2=A, A1 and A2 are both integers and the number of bits in A2 is higher than A1; The low-speed data processing module 21 is used to serialize the B-channel parallel A-bit data signals to obtain the C-channel parallel A-bit data signals, where A is an integer greater than 1, B and C are even numbers greater than 1 and B > C. The differential-pulse generation module 31 of the i-th DAC slice 221 is used to receive the i-th bit data signal of C parallel channels, and perform differential and pulse generation processing on it based on a preset non-full rate clock to obtain the corresponding i-th bit, C parallel pulse signal. The pulse width of the pulse signal under any channel is one symbol period, and the pulse signals corresponding to the i-th bit data signal of a group of C parallel channels are delayed by one symbol period in sequence, 1≤i≤A and i is an integer. The outputs of the merging and serialization driving modules 32 of the A-group DAC slice 221 are connected in parallel. The merging and serialization driving module 32 in the i-th group DAC slice 221 is used to receive the C-channel parallel pulse signal corresponding to the i-th bit, perform merging and serialization processing on it, and drive it according to the weight corresponding to the i-th group DAC slice 221 through the SST driving structure to output the serialized differential signal corresponding to the i-th bit. Then, the A-bit serialized differential signals are superimposed to obtain the target serialized differential signal.

[0024] In this embodiment, the transmitting device can essentially be understood as a transmitter. The signal to be transmitted can be a PAM signal (such as a PAM4 signal) or an NRZ signal (Non-Return-to-Zero), without any particular limitation. The transmitting device is based on a DSP-DAC architecture and can flexibly apply high-order pulse amplitude modulation (i.e., PAM-4, PAM-6, or PAM-8). The DSP module 12 in the digital processing unit 1 can use an FIR filter (Finite Impulse Response) to efficiently implement an 8-tap feedforward equalizer (FFE).

[0025] Specifically, the digital processing unit 1 can convert and process the signal to be transmitted based on a multi-tap FIR feedforward equalizer (specifically, an 8-tap FIR feedforward equalizer) to obtain B parallel A-bit data signals. The high A2 bits of the A-bit data signal use thermometer code and the low A1 bits use binary code. More specifically, the high-speed data processing module 22 can be based on an 8-bit DAC, corresponding to A=9, A1=6, and A2=3. It should be noted that the high 3-bit thermometer code here is essentially a 3-bit thermometer code converted from 2-bit binary code.

[0026] Each DAC slice 221 processes C parallel data signals to achieve a segmented coding architecture, where C can be 4. Regarding the C parallel pulse signal generated by the i-th DAC slice 221 corresponding to the i-th bit, the pulse signal under any one path is essentially a group of pulse signals, as described in the following embodiments, and will not be repeated here. A group of C parallel i-th bit data signals refers to the C parallel i-th bit data signal corresponding to one transmission cycle (further illustrations will be provided in the following embodiments). The corresponding pulse signals are sequentially delayed by one symbol cycle. Taking C=4 as an example, the timing of the pulse signal under the second path is delayed by one symbol cycle compared to the timing of the pulse signal under the first path, the timing of the pulse signal under the third path is delayed by one symbol cycle compared to the timing of the pulse signal under the second path, and the timing of the pulse signal under the fourth path is delayed by one symbol cycle compared to the timing of the pulse signal under the third path. Furthermore, due to limitations in image display and to avoid confusing wiring, Figure 1 The diagram of the routes will be omitted for now.

[0027] The output of the merging and serialization driver module 32 of the i-th DAC slice 221 specifically includes a positive output terminal and a negative output terminal. Therefore, the positive output terminal of the A-group DAC slice 221 is connected to the i-th DAC slice 221, and the negative output terminal of the A-group DAC slice 221 is connected to the i-th DAC slice 221 to output the target serialized differential signal. It can be understood that, as Figure 1 As shown, the transmitting device may also include an output matching network. The common terminal connected to the positive output of the A-group DAC slice 221 is connected to the positive input of the output matching network, and the common terminal connected to the negative output of the A-group DAC slice 221 is connected to the negative input of the output matching network. The differential output terminal of the output matching network serves as the output terminal TXout of the transmitting device. The output matching network can be used to eliminate signal reflection, filter and shape to suppress high-frequency noise, and calibrate signal amplitude to adapt to channel attenuation characteristics. The specific structure of the output matching network is not particularly limited here, and can be flexibly set according to actual application requirements.

[0028] For any DAC slice 221, the merging and serializing driver module 32 is essentially based on the SST driver structure (Source-Series Terminated) and integrates the serializing module 321 into the SST driver structure. This module serializes and merges C parallel pulse signals into a single high-speed differential signal. The SST driver structure drives the signal according to the weights corresponding to the i-th group of DAC slices 221 to output the serialized differential signal corresponding to the i-th bit. (In addition to this output drive, output impedance matching can also be achieved based on the first tunable circuit 322 and the second tunable circuit 323 in the merging and serializing driver module 32, as described in the following embodiments, which will not be elaborated here.) Furthermore, the weights corresponding to different groups of DAC slices 221 are different, thereby enabling the output drive of each DAC slice 221 to achieve the resolution of a preset number of bits DAC (e.g., for an 8-bit DAC, depending on the above segmented encoding architecture, the output drive of each DAC slice 221 can jointly achieve 8-bit, 256-level conversion accuracy). The specific settings of these weights are described in the following embodiments.

[0029] In addition, such as Figure 1 As shown, the transmitting device may also include a clock path module 4, which can be used to generate the clock signal required by the low-speed data processing module 21 and the high-speed data processing module 22 of the device to perform their respective functions.

[0030] In summary, this application provides a transmitting device based on a DSP-DAC architecture. In this scheme, the final stage of parallel data to serial data conversion is combined with the output drive to set up a merging and serialization drive module 32. This can limit the full-rate signal nodes only to the final output stage, which is beneficial to simplifying the front-end circuit design. There is no need to set up a pre-driver, which is beneficial to reducing the overall power consumption and area. At the same time, it ensures the high speed and integrity of the output target serialized differential signal, which is beneficial to practical applications.

[0031] Based on the above embodiments: Please refer to Figure 2 , Figure 2 This is a schematic diagram of another transmitting device based on a DSP-DAC architecture provided by the present invention.

[0032] In some embodiments, the digital processing unit 1 includes a pseudo-random binary sequence generator 11 and a DSP module 12 connected in sequence. The pseudo-random binary sequence generator 11 is used to generate B parallel data signals based on the signal to be transmitted; DSP module 12 is used to perform multi-tap FIR feedforward equalization and binary code to thermometer code processing on the B-channel parallel signals to obtain the A-bit data signal of the B-channel parallel signals.

[0033] Specifically, the pseudo-random binary sequence generator 11 here is the PRBS generator (Parallel Pseudo-random Bit Sequence), corresponding to a 64-bit PRBS generator, B=64, which means that it can generate 64 parallel data signals based on the signal to be transmitted (these parallel data signals are essentially pseudo-random binary parallel data signals); the DSP module 12 uses an FIR filter to efficiently implement multi-tap FIR feedforward equalization (specifically, it can be 8 taps), thereby obtaining B parallel A-bit data signals, for example, A=9 and A1=6, A2=3.

[0034] Corresponding to Figure 2 Taking the PAM4 signal to be transmitted, B=64, A=9 as an example, the 64 marked at the output of the pseudo-random binary sequence generator 11 represents 64 parallel data signals, and 64×9b represents 64 parallel 9-bit data signals. Figure 2 The 'b' in the text is used to indicate the number of bits in the data. 3T+6B indicates that the high 3 bits use thermometer code and the low 6 bits use binary code.

[0035] In some embodiments, the low-speed data processing module 21 includes K parallel circuits connected in sequence, where K is an integer greater than 1; Each parallel circuit includes multiple 2:1 MUX modules connected in parallel, and the number of 2:1 MUX modules connected in parallel varies in different parallel circuits, so as to realize the conversion of B-channel parallel A-bit data signals to C-channel parallel A-bit data signals.

[0036] Specifically, the low-speed data processing module 21, based on the 2:1 MUX module (Multiplexer) configured according to the above circuit structure, converts B parallel A-bit data signals to C parallel A-bit data signals. For example, taking B=64 and C=4 as an example, K=4, and the first parallel circuit includes 32 sets of parallel 2:1 MUX modules, such as... Figure 2 As shown, the 64 parallel 9-bit data signals output by DSP module 12 pass through the first parallel circuit ( Figure 2 After processing (labeled as 64:32MUX module 211), 32 parallel 9-bit data signals are obtained. Figure 2 (labeled as 32×9b); the second parallel circuit includes 16 sets of 2:1 MUX modules connected in parallel, such as... Figure 2 As shown, 32 parallel 9-bit data signals pass through a second parallel circuit ( Figure 2 After processing (labeled as 32:16MUX module 212), 16 parallel 9-bit data signals are obtained. Figure 2 (labeled as 16×9b); the third parallel circuit includes 8 sets of 2:1 MUX modules connected in parallel, such as Figure 2 As shown, the 16 parallel 9-bit data signals pass through the third parallel circuit ( Figure 2 (The 16:8 MUX module 213 is used as an example) After processing, 8 parallel 9-bit data signals are obtained. Figure 2 (marked as 8×9b); the fourth parallel circuit includes four sets of 2:1 MUX modules connected in parallel, such as... Figure 2 As shown, the 8 parallel 9-bit data signals pass through the fourth parallel circuit ( Figure 2 After processing (labeled as 8:4MUX module 214), four parallel 9-bit data signals are obtained. Figure 2 (labeled as 4×9b).

[0037] It should also be noted that each parallel circuit requires a corresponding clock signal to operate, such as... Figure 2 As shown, the clock path module 4 in the transmitting device may include a buffer 41, five frequency divider circuits, and an IQ phase calibration circuit 43 based on phase interpolation. The input differential half-rate clock signal CLK2 sequentially passes through the buffer 41 and the first frequency divider circuit 421 to generate a 1 / 4 rate four-phase clock signal. This 1 / 4 rate four-phase clock signal is then finely adjusted by the IQ phase calibration circuit 43 to ensure a precise 90-degree phase difference between each clock signal under the four-phase clock, thereby obtaining a corrected and precise 1 / 4 rate four-phase clock signal CLK4 (used by the retiming module 312 and the IUI pulse generation module 313 in subsequent embodiments). (The 1 / 4 rate four-phase clock signal refers to this clock signal). The 1 / 4 rate four-phase clock signal CLK4 is divided by the second frequency divider circuit 422 to generate clock signal CLK8, which is applied to the 8:4 MUX module 214. Clock signal CLK8 is divided by the third frequency divider circuit 423 to generate clock signal CLK16, which is applied to the 16:8 MUX module 213. Clock signal CLK16 is divided by the fourth frequency divider circuit 424 to generate clock signal CLK32, which is applied to the 32:16 MUX module 212. Clock signal CLK32 is divided by the fifth frequency divider circuit 425 to generate clock signal CLK64, which is applied to the 64:32 MUX module 211.

[0038] In some embodiments, A=9 and A1=6, A2=3; The weights of DAC slices 221 in groups 1 to 221 in groups 6 are 1, 2, 4, 8, 16, and 32 respectively, to achieve weighted drive control of the lower 6 bits of binary code; the weights of DAC slices 221 in groups 7 to 9 in groups 221 are 64, 64, and 64 respectively, to achieve weighted drive control of the higher 3 bits of thermometer code.

[0039] For details, please refer to Figure 3 , Figure 3 This is a schematic diagram of a high-speed data processing module provided by the present invention. The high-speed data processing module 22 includes 9 DAC slices 221 to implement an 8-bit DAC. Figure 3 The nine DAC slices 221 are illustrated in array form, and the connection diagrams at the output terminals of each merging and serializing driver module 32 are temporarily omitted. It can be seen that this application uses a segmented DAC, namely: high-side (MSB segment): 3-bit thermometer code (corresponding to T2, T1, T0) is responsible for processing the most significant 3 bits (MSBs); low-side (LSB segment): 6-bit binary code (corresponding to B5, B4, B3, B2, B1, B0) is responsible for processing the least significant 6 bits (LSBs); the segmented combination of the high three thermometer codes and the low six binary codes has nine corresponding signal input channels (T2, T1, T0, B5, B4, B3, B2, B1, B0), each channel having 4 parallel data inputs, such as... Figure 3 As shown.

[0040] The implementation of 8-bit DAC resolution relies on this segmented coding architecture. The low-order segment (LSB) control (corresponding to the lower 6 bits in the 8-bit array) is driven by binary weighting (specifically, controlling the first and second tunable arrays in the corresponding DAC slice 221). The weights of the DAC slice 221 from the least significant bit to the most significant bit are 1, 2, 4, 8, 16, and 32, respectively. This allows for output currents of the corresponding DAC slice 221 to be 1×, 2×, 4×, 8×, 16×, and 32× (e.g., ...). Figure 3 As shown); the high-segment (MSBs) control (also corresponding to the high 2 bits of 8 bits, corresponding to the thermometer code in this application, and the highest bit is represented by two thermometer codes) is driven by a thermometer code weighted method (specifically, controlling the first tunable array and the second tunable array in the corresponding DAC slice 221). The weights of the DAC slice 221 corresponding to the lowest and highest thermometer codes are 64, 64, and 64 (the last two 64s are derived from a 128), thereby achieving 64×, 64×, and 64× (e.g., ...) of the output current of the corresponding DAC slice 221. Figure 3 As shown), the nine DAC slices 221 together achieve 8-bit (256 levels) conversion accuracy. This high resolution is suitable for both 8-tap FIR feedforward equalization and high-order PAM signal applications.

[0041] Furthermore, based on the above structural configuration, it should be noted that the segmented DAC in this application achieves significant optimizations in accuracy, linearity, dynamic performance, and power consumption area compared to traditional binary weighted or full thermometer-coded DAC structures. Specifically, this is reflected in the following: First, this structure fundamentally guarantees the monotonicity of the digital-to-analog conversion. The high-order bits control three identical merging and serialization driver modules 32 using thermometer-coded methods. Each encoding step only turns one module on or off, avoiding the nonlinear transitions caused by multiple resistor mismatches during major bit transitions (such as from 01111111 to 10000000) in traditional binary structures, ensuring a strictly monotonic conversion characteristic curve. Second, this architecture can reduce differential nonlinearity (DNL) and integral nonlinearity (Integral). Nonlinearity (INL) error; the high-segment modules can be physically designed based on matching techniques such as common centroid layout on the layout, effectively suppressing errors caused by process gradients and mismatches. The lower 6 bits still use binary weighting, which avoids the huge decoding logic and unit array required by the full thermometer code structure while ensuring accuracy, significantly saving area and reducing dynamic power consumption. Third, this encoding method effectively suppresses output glitches and harmonic distortion. The glitch energy during the switching of high-segment thermometer codes is lower than the binary conversion of multiple bits jumping at the same time, which helps to improve dynamic performance and improve spurious-free dynamic range (SFDR).

[0042] In some embodiments, C=4, the differential-pulse generation module 31 under the i-th DAC slice 221 includes a single-ended to differential module 311, a retiming module 312 and a 1UI pulse generation module 313 connected in sequence; The single-ended to differential module 311 is used to receive the i-th bit data signal from four parallel channels and perform single-ended to differential processing on it using a differential clock signal to obtain the first intermediate differential signal from four parallel channels corresponding to the i-th bit. The retiming module 312 is used to receive the first intermediate differential signal corresponding to the i-th bit, which is 4 parallel channels, and to use the 1 / 4 rate four-phase clock signal CLK4 to synchronize and delay it with 1UI, so as to obtain the second intermediate differential signal corresponding to the i-th bit, which is 4 parallel channels and is delayed by one symbol period in sequence. The 1UI pulse generation module 313 is used to receive the second intermediate differential signal corresponding to the i-th bit, which is 4 parallel channels and sequentially delayed by one symbol period, and to perform narrow pulse generation processing using the 1 / 4 rate four-phase clock signal CLK4 to obtain a pulse signal group corresponding to the i-th bit, which is 4 parallel channels; the pulse signal group under any channel includes a first pulse signal corresponding to the positive output terminal and a second pulse signal corresponding to the negative output terminal, and the pulse width of the first pulse signal and the second pulse signal is one symbol period, and the two adjacent pulse signal groups under any channel are separated by 3 symbol periods.

[0043] Specifically, the i-th bit data signal in four parallel channels is essentially a parallel single-ended data signal. Through the single-ended to differential converter 311, the four parallel first intermediate differential signals corresponding to the i-th bit can be obtained. That is, the output of the single-ended to differential converter 311 includes the first intermediate differential signal of the first channel, the first intermediate differential signal of the second channel, the first intermediate differential signal of the third channel, and the first intermediate differential signal of the fourth channel. It can be understood that the first intermediate differential signal in any channel includes a positive differential signal and a negative differential signal, and the positive differential signal and the negative differential signal are out of phase. Furthermore, the differential clock signal mentioned here includes two clock signals with opposite phases. In practical applications, the 1 / 4-speed quad-phase clock signal CLK4 includes a first clock signal CLK4_1 (corresponding to 0 degrees phase), a second clock signal CLK4_2 (corresponding to 90 degrees phase), a third clock signal CLK4_3 (corresponding to 180 degrees phase), and a fourth clock signal CLK4_4 (corresponding to 270 degrees phase), all with phase differences of 90 degrees. The differential clock signals can be selected from the first clock signal CLK4_1 and the third clock signal CLK4_3, which have a phase difference of 180 degrees. The specific circuit configuration of the single-ended to differential module 311 is not specifically limited here; it can be flexibly configured according to the actual application. Please refer to [reference needed]. Figure 4 , Figure 4 This is a schematic diagram of the data stream output after processing by a single-ended to differential converter module provided by the present invention. Here, din0, din1, din2, and din3 correspond to 4 channels. Figure 4 In this context, d0, d1, d2, and d3 represent a set of first intermediate differential signals in one transmission cycle, while d4, d5, d6, and d7 represent a set of first intermediate differential signals in the next transmission cycle.

[0044] The retiming module 312 can use a 1 / 4-speed four-phase clock signal CLK4 to synchronize and delay four parallel first intermediate differential signals by 1UI (Unit Interval, which in this application refers to a symbol period) to obtain four parallel second intermediate differential signals that are sequentially delayed by one symbol period. Each second intermediate differential signal includes a positive differential signal and a negative differential signal, with the positive and negative differential signals having opposite phases. The timing of the second intermediate differential signals under the first, second, third, and fourth channels is sequentially delayed by one symbol period. The retiming module 312 outputs a first-channel second intermediate differential signal, a second-channel second intermediate differential signal, a third-channel second intermediate differential signal, and a fourth-channel second intermediate differential signal. The timing of the second-channel second intermediate differential signal is delayed by one symbol period from the timing of the first-channel second intermediate differential signal; the timing of the third-channel second intermediate differential signal is delayed by one symbol period from the timing of the second-channel second intermediate differential signal; and the timing of the fourth-channel second intermediate differential signal is delayed by one symbol period from the timing of the third-channel second intermediate differential signal. The specific circuit configuration of this retiming module 312 is not specifically limited here; it can be flexibly configured according to the actual application. Please refer to [reference needed]. Figure 5 , Figure 5 This is a schematic diagram of the data stream output after processing by the retiming module provided by the present invention. Here, din0, din1, din2, and din3 correspond to 4 channels. Figure 5 In this diagram, d0, d1, d2, and d3 represent a set of second intermediate differential signals in one transmission cycle (which can be seen to be delayed by one symbol cycle in sequence), and d4, d5, d6, and d7 represent a set of second intermediate differential signals in the next transmission cycle (which can also be seen to be delayed by one symbol cycle in sequence). It is evident that by setting the retiming module 312, timing deviations and jitter accumulated in previous processing stages can be eliminated, while ensuring that the setup and hold times of the data before entering the 1UI pulse generation module 313 meet timing requirements.

[0045] The UI pulse generation module 313 uses a 1 / 4 rate four-phase clock signal CLK4 to perform narrow pulse generation processing on four parallel second intermediate differential signals that are sequentially delayed by one symbol period to obtain four parallel pulse signal groups. In any path, two adjacent pulse signal groups are separated by three symbol periods (i.e., in any path, two adjacent first pulse signals are separated by three symbol periods, and two adjacent second pulse signals are separated by three symbol periods). This ensures that in one transmission cycle, the four pulse signal groups corresponding to the i-th bit data signal of a group of four parallel signals are sequentially delayed by one symbol period, thereby ensuring that there is no overlap between these four pulse signal groups.

[0046] More specifically, the output of the 1UI pulse generation module 313 includes a first pulse signal group (including a first pulse signal corresponding to the merging and serialization driving circuit at the positive output terminal and a second pulse signal corresponding to the merging and serialization driving circuit at the negative output terminal), a second pulse signal group (including a first pulse signal corresponding to the merging and serialization driving circuit at the positive output terminal and a second pulse signal corresponding to the merging and serialization driving circuit at the negative output terminal), a third pulse signal group (including a first pulse signal corresponding to the merging and serialization driving circuit at the positive output terminal and a second pulse signal corresponding to the merging and serialization driving circuit at the negative output terminal), and a fourth pulse signal group (including a first pulse signal corresponding to the merging and serialization driving circuit at the positive output terminal and a second pulse signal corresponding to the merging and serialization driving circuit at the negative output terminal); please refer to Figure 6 , Figure 6 This is a schematic diagram of the data stream output after processing by the 1UI pulse generation module provided by the present invention. Here, din0, din1, din2, and din3 still correspond to 4 channels. Figure 6 In the diagram, d0, d1, d2, and d3 represent a group of pulse signals under one transmission cycle (it can be seen that the pulse width of the pulse signal group under each channel is one symbol cycle and there is a 3 symbol cycle interval between two adjacent pulse signal groups under any channel). d4, d5, d6, and d7 represent a group of pulse signals under the next transmission cycle (it can be seen that the pulse width of the pulse signal group under each channel is one symbol cycle and there is a 3 symbol cycle interval between two adjacent pulse signal groups under any channel).

[0047] In some embodiments, the 1UI pulse generation module 313 includes 4 sets of processing circuits. The j-th set of processing circuits corresponding to the j-th channel includes two logic gate circuits. The input terminal of the first logic gate circuit is used to receive the positive differential signal of the j-th channel second intermediate differential signal and the output terminal is used to output the first pulse signal corresponding to the positive output terminal. The input terminal of the second logic gate circuit is used to receive the negative differential signal of the j-th channel second intermediate differential signal and the output terminal is used to output the second pulse signal corresponding to the negative output terminal. 1≤j≤4 and j is an integer. The logic gate circuit includes two NOT gates, two AND gates, and two OR gates; the 1 / 4 rate four-phase clock signal CLK4 includes a first clock signal CLK4_1, a second clock signal CLK4_2, a third clock signal CLK4_3, and a fourth clock signal CLK4_4, which are sequentially 90 degrees out of phase. The inputs of the first NOT gate U1 and the second NOT gate U2 are connected, and the common terminal of the connection is used as the input of the logic gate circuit. The first input terminal of the second AND gate U4 is connected to the output terminal of the first NOT gate U1, and the second input terminal is connected to the output terminal of the first AND gate U3. The output terminal serves as the first output terminal in the logic gate circuit. The first input terminal of the second OR gate U6 is connected to the output terminal of the second NOT gate U2, and the second input terminal is connected to the output terminal of the first OR gate U5. The output terminal serves as the second output terminal in the logic gate circuit. Corresponding to the first group of processing circuits 61 of the first channel, the first input terminal of the first AND gate U3 of the two logic gate circuits below is used to receive the first clock signal and the second input terminal is used to receive the second clock signal; the first input terminal of the first OR gate U5 is used to receive the third clock signal and the second input terminal is used to receive the fourth clock signal. Corresponding to the second group of processing circuits 62 of the second channel, the first input terminal of the first AND gate U3 of the two logic gate circuits below is used to receive the second clock signal and the second input terminal is used to receive the third clock signal; the first input terminal of the first OR gate U5 is used to receive the fourth clock signal and the second input terminal is used to receive the first clock signal. Corresponding to the third group of processing circuits 63 of the third channel, the first input terminal of the first AND gate U3 of the two logic gate circuits below is used to receive the third clock signal and the second input terminal is used to receive the fourth clock signal; the first input terminal of the first OR gate U5 is used to receive the first clock signal and the second input terminal is used to receive the second clock signal. Corresponding to the fourth group of processing circuits 64 of the fourth channel, the first input terminal of the first AND gate U3 of the two logic gate circuits below is used to receive the fourth clock signal and the second input terminal is used to receive the first clock signal; the first input terminal of the first OR gate U5 is used to receive the second clock signal and the second input terminal is used to receive the third clock signal.

[0048] First, it should be noted that please refer to Figure 7 , Figure 7 A schematic diagram of a 1 / 4 rate four-phase clock signal provided by the present invention shows that the first clock signal CLK4_1, the second clock signal CLK4_2, the third clock signal CLK4_3 and the fourth clock signal CLK4_4 are 90 degrees out of phase. Specifically, a set of processing circuits is set up for each channel, and each set of processing circuits includes two logic gate circuits. Please refer to [the relevant documentation]. Figure 8 , Figure 9 , Figure 10 and Figure 11 , Figure 8 This is a schematic diagram of the structure of the first group of processing circuits corresponding to the first channel provided by the present invention. Figure 9 This is a schematic diagram of the structure of the second group of processing circuits corresponding to the second channel provided by the present invention. Figure 10 This is a schematic diagram of the structure of the third group of processing circuits corresponding to the third channel provided by the present invention. Figure 11 This invention provides a schematic diagram of the fourth group of processing circuits corresponding to the fourth channel; the specific structure corresponding to the above-mentioned 1UI pulse generation module 313 is as follows: Figure 8 As shown, in the first group of processing circuits 61, the input terminal of the first logic gate circuit 611 is used to receive the positive differential signal din0p in the first channel second intermediate differential signal and output the first pulse signal corresponding to the positive output terminal (including the first pulse sub-signal d0_pmos output by the second output terminal of the first logic gate circuit 611 and the second pulse sub-signal d0_nmos output by the first output terminal). The input terminal of the second logic gate circuit 612 is used to receive the negative differential signal din0n in the first channel second intermediate differential signal and output the second pulse signal corresponding to the negative output terminal (including the first pulse sub-signal d0_pmos output by the second output terminal of the second logic gate circuit 612 and the second pulse sub-signal d0_nmos output by the first output terminal).

[0049] like Figure 9 As shown, in the second group of processing circuits 62, the input terminal of the first logic gate circuit 621 is used to receive the positive differential signal din1p in the second intermediate differential signal and output the first pulse signal corresponding to the positive output terminal (including the first pulse sub-signal d1_pmos output by the second output terminal of the first logic gate circuit 621 and the second pulse sub-signal d1_nmos output by the first output terminal). The input terminal of the second logic gate circuit 622 is used to receive the negative differential signal din1n in the second intermediate differential signal and output the second pulse signal corresponding to the negative output terminal (including the first pulse sub-signal d1_pmos output by the second output terminal of the second logic gate circuit 622 and the second pulse sub-signal d1_nmos output by the first output terminal).

[0050] like Figure 10In the third group of processing circuits 63, the input terminal of the first logic gate circuit 631 is used to receive the positive differential signal din2p in the third channel second intermediate differential signal and output the first pulse signal corresponding to the positive output terminal of the third channel (including the first pulse sub-signal d2_pmos output by the second output terminal of the first logic gate circuit 631 and the second pulse sub-signal d2_nmos output by the first output terminal). The input terminal of the second logic gate circuit 632 is used to receive the negative differential signal din2n in the third channel second intermediate differential signal and output the second pulse signal corresponding to the negative output terminal of the third channel (including the first pulse sub-signal D2_pmos output by the second output terminal of the second logic gate circuit 632 and the second pulse sub-signal D2_nmos output by the first output terminal).

[0051] like Figure 11 As shown, in the fourth group of processing circuits 64, the input terminal of the first logic gate circuit 641 is used to receive the positive differential signal din3p in the fourth channel second intermediate differential signal and output the first pulse signal corresponding to the positive output terminal of the fourth channel (including the first pulse sub-signal d3_pmos output by the second output terminal of the first logic gate circuit 641 and the second pulse sub-signal d3_nmos output by the first output terminal). The differential input terminal of the second logic gate circuit is used to receive the negative differential signal in the fourth channel second intermediate differential signal and output the second pulse signal corresponding to the negative output terminal of the fourth channel (including the first pulse sub-signal D3_pmos output by the second output terminal of the second logic gate circuit 642 and the second pulse sub-signal D3_nmos output by the first output terminal).

[0052] Furthermore, the working logic of the logic gate circuit is further explained. For example, taking the first logic gate circuit 611 under the first group of processing circuits 61 as an example, if the level state of the signal din0p received at the input terminal of the logic gate circuit corresponds to logic 0, and the level state of the first clock signal CLK4_1 is 1 and the level state of the second clock signal CLK4_2 is 1, then the level state of the output signal at its first output terminal is 1 (that is, the level state of the second pulse sub-signal d0_nmos is 1); if ... then the level state of the first clock signal CLK4_1 is 1. The level state of p corresponds to logic 1, and the level state of the third clock signal CLK4_3 is 0, and the level state of the fourth clock signal CLK4_4 is 0. Therefore, the level state of the output signal at the second output terminal is 0 (that is, the level state of the first pulse sub-signal d0_pmos is 0). The overlap time of two adjacent clock signals of the 1 / 4 rate four-phase clock signal CLK4 being high (corresponding to a level state of 1) or low (corresponding to a level state of 0) is 1 symbol period. Therefore, the pulse width of the pulse signal after processing by the logic gate circuit is 1 symbol period.

[0053] As can be seen, the 1UI pulse generation module 313 is based on logic gate circuits, which does not require complex analog circuits and has a simple circuit structure. At the same time, since the switching characteristics of digital logic gates (i.e., OR gates, AND gates, NOT gates) are stable and less affected by environmental factors such as temperature and voltage, the generated pulse signal has good stability and can meet the stringent timing accuracy requirements of high-speed serial communication and other scenarios.

[0054] Please refer to Figure 12 and Figure 13 , Figure 12 This is a schematic diagram of a merging and serializing driver circuit corresponding to the positive output terminal provided by the present invention. Figure 13 This is a schematic diagram of a merging and serialization driving circuit corresponding to the negative output terminal provided by the present invention.

[0055] In some embodiments, the merging and serialization driving module 32 under the i-th DAC slice 221 includes a merging and serialization driving circuit corresponding to the positive output terminal and a merging and serialization driving circuit corresponding to the negative output terminal; wherein, the pulse input terminal of the merging and serialization driving circuit corresponding to the positive output terminal is used to receive the first pulse signal in the four parallel pulse signal groups and the output terminal Toutp is used to output the positive serialization differential signal in the serialization differential signal corresponding to the i-th bit; the pulse input terminal of the merging and serialization driving circuit corresponding to the negative output terminal is used to receive the second pulse signal in the four parallel pulse signal groups and the output terminal Toutn is used to output the negative serialization differential signal in the serialization differential signal corresponding to the i-th bit. The merging and serialization driving circuit includes a serialization module 321, an impedance matching resistor R1, a first tunable circuit 322 and a second tunable circuit 323 corresponding to the weight settings of the i-th DAC slice 221; The first terminal of the first tunable circuit 322 is connected to the power supply VPDRV, the second terminal is connected to the first terminal of the serialization module 321, and the control terminal is connected to the control module; the first terminal of the second tunable circuit 323 is connected to the second terminal of the serialization module 321, the second terminal is grounded, and the control terminal is connected to the control module. The control terminal of the serialization module 321 serves as the pulse input terminal of the merging serialization drive circuit, and its output terminal is connected to one end of the impedance matching resistor R1, while the other end of the impedance matching resistor R1 serves as the output terminal of the merging serialization drive circuit. The control module is used to adjust the equivalent impedance of the first tunable circuit 322 and the second tunable circuit 323 so that the total equivalent output impedance of the merging and serializing drive module 32 under the i-th DAC slice 221 matches the target output impedance corresponding to the i-th DAC slice 221.

[0056] In this embodiment, this setting can reliably realize the serialization drive output of 4 parallel data and output impedance matching; specifically, corresponding to C=4, the merged serialization drive module 32 here is essentially based on the SST drive structure, and the serialization module 321 (i.e., the 4:1 serialization module 321) is integrated into the SST drive structure to obtain the module. The first tuning circuit is connected in series at the top of the pull-up branch of the merging and serializing drive circuit (this pull-up branch is composed of the first controllable switch group 51 in the serialization module 321 and the first tuning circuit), and the second tuning circuit is connected in series at the bottom of the pull-down branch of the merging and serializing drive circuit (this pull-down branch is composed of the second controllable switch group 52 in the serialization module 321 and the second tuning circuit). Specifically, the control module can adjust the equivalent impedance of the first tunable circuit 322 and the second tunable circuit 323 by outputting a set of binary weighted control signals (corresponding to 4-bit binary codes). The functions of the first tunable circuit 322 and the second tunable circuit 323 are reflected in two aspects: First, as on-chip impedance calibration, in conjunction with the equivalent impedance of the serialization module 321. Working in conjunction with the impedance matching resistor R1, the total equivalent output impedance of the combined serialization drive module is adjustable, thus solving the impedance mismatch problem caused by process deviations, compensating for process deviations, and achieving impedance calibration and accurate output matching. Secondly, by selecting and setting the size parameters of the transistor arrays under the first tunable circuit 322 and the second tunable circuit 323 in the i-th DAC slice 221, the weight settings corresponding to the i-th DAC slice 221 are realized, thereby enabling the transistor arrays under the first tunable circuit 322 and the second tunable circuit 323 to be enabled and selected as SST drive structures within the DAC slices 221 with different weights, converting the digital signal into an analog voltage signal with the corresponding output swing.

[0057] More specifically, in some embodiments, both the first tunable circuit 322 and the second tunable circuit 323 include a controllable switch array; The controllable switch array includes 15 first controllable switches with size parameters corresponding to the weights of the i-th DAC slice 221. The first controllable switches are connected in parallel and the control terminal of each first controllable switch is connected to the control module. The first controllable switch is used to turn on and off according to the 4-bit binary code output by the control module, so that the equivalent impedance of the controllable switch array presents the target binary weight relationship.

[0058] Specifically, the first controllable switch corresponding to the first tunable circuit 322 can be a P-channel MOSFET (Metal-Oxide Semiconductor Field Effect Transistor), and the first controllable switch corresponding to the second tunable circuit 323 can be an N-channel MOSFET; such as Figure 12 As shown, corresponding to the merging and serialization drive circuit under the positive output terminal, the control signal (i.e., 4-bit binary code form) received by the first tunable circuit 322 is labeled with Tune1P<3:0> and the control signal (i.e., 4-bit binary code form) received by the second tunable circuit 323 is labeled with Tune1N<3:0>; as Figure 13 As shown, corresponding to the merging and serialization drive circuit under the negative output terminal, the control signal (i.e., 4-bit binary code form) received by the first tunable circuit 322 is labeled with Tune2P<3:0> and the control signal (i.e., 4-bit binary code form) received by the second tunable circuit 323 is labeled with Tune2N<3:0>; furthermore, Figure 12 and Figure 13 The diagram illustrates 15 first controllable switches connected in parallel, labeled in the form of ×15 units.

[0059] The size parameter here refers to the aspect ratio of the MOSFET. Within the same group of DAC slices 221, the aspect ratios of all 60 P-channel MOSFETs in the two controllable switch arrays corresponding to the positive output and the two controllable switch arrays corresponding to the negative output are the same. Furthermore, the aspect ratio correspondence of the P-channel MOSFETs in different groups of DAC slices 221 follows a weighted correspondence, which can be expressed as follows: the aspect ratio of each P-channel MOSFET in the first group of DAC slices 221 is 1×, the aspect ratio of each P-channel MOSFET in the second group of DAC slices 221 is 2×, and the aspect ratio of the third group of DAC slices 221 is... The aspect ratio of each P-channel MOSFET under chip 221 is 4×, the aspect ratio of each P-channel MOSFET under chip 221 in the fourth group of DAC chips is 8×, the aspect ratio of each P-channel MOSFET under chip 221 in the fifth group of DAC chips is 16×, the aspect ratio of each P-channel MOSFET under chip 221 in the sixth group of DAC chips is 32×, the aspect ratio of each P-channel MOSFET under chip 221 in the seventh group of DAC chips is 64×, the aspect ratio of each P-channel MOSFET under chip 221 in the eighth group of DAC chips is 64×, and the aspect ratio of each P-channel MOSFET under chip 221 in the ninth group of DAC chips is 64×.

[0060] The controllable switch array here can be understood as a tunable and controllable switch array based on binary weighted control. That is, the array is controlled by a 4-bit binary code. The target binary weight relationship here refers to 1×, 2×, 4×, 8×, which means that the 15 MOSFETs are divided into 4 groups, and each group includes 1, 2, 4, and 8 MOSFETs. Then each bit of the 4-bit binary code controls the simultaneous conduction and cutoff of each MOSFET in a group of MOSFETs.

[0061] The control module here can be an external calibration circuit module or an internal state machine, without any particular limitation. The total equivalent output impedance of the serialization drive module 32 consists of three parts: first, the resistance value of the impedance matching resistor R1, which accounts for the majority of the impedance; second, the equivalent on-resistance of the controllable switches under each controllable switch group in the serialization module 321; and third, the equivalent on-resistance of the controllable switch array under the first tunable circuit 322 and the second tunable circuit 323. By dynamically controlling the on and off of specific controllable switches under the controllable switch array, the equivalent on-resistance of the pull-up branch and the pull-down branch can be finely adjusted so that the sum of the equivalent on-resistance and the fixed resistor always approaches the target output impedance design corresponding to the DAC slice 221 of the corresponding group.

[0062] As can be seen, the above settings can reliably achieve serialized drive output of 4 parallel data channels and output impedance matching.

[0063] In some embodiments, the serialization module 321 includes two controllable switch groups; The first end of the first controllable switch group 51 serves as the first end of the serialization module 321, and the second end is connected to the first end of the second controllable switch group 52, with the common end of the connection serving as the output end of the serialization module 321. The second terminal of the second controllable switch group 52 serves as the second terminal of the serialization module 321; Corresponding to the merging and serialization driving circuit at the positive output terminal, the control terminal of the first controllable switch group 51 in the lower serialization module 321 is used to receive the first pulse sub-signal in the four parallel first pulse signals, and the control terminal of the second controllable switch group 52 is used to receive the second pulse sub-signal in the four parallel first pulse signals. Corresponding to the merging and serialization driving circuit at the negative output terminal, the control terminal of the first controllable switch group 51 in the lower serialization module 321 is used to receive the first pulse sub-signal in the four parallel second pulse signals, and the control terminal of the second controllable switch group 52 is used to receive the second pulse sub-signal in the four parallel second pulse signals.

[0064] Specifically, each controllable switch group includes four controllable switches; that is, the first controllable switch group 51 includes four second controllable switches, which can specifically be P-channel MOSFETs; the second controllable switch group 52 includes four third controllable switches, which can specifically be N-channel MOSFETs; for example... Figure 12 As shown, the first controllable switch group 51 under the serialization module 321 corresponding to the positive output terminal includes P-channel MOSFET Q1, P-channel MOSFET Q2, P-channel MOSFET Q3, and P-channel MOSFET Q4, and the second controllable switch group 52 includes N-channel MOSFET Q5, N-channel MOSFET Q6, N-channel MOSFET Q7, and N-channel MOSFET Q8; as Figure 13 As shown, the first controllable switch group 51 under the serialization module 321 corresponding to the negative output terminal includes P-channel MOSFET Q9, P-channel MOSFET Q10, P-channel MOSFET Q11 and P-channel MOSFET Q12, and the second controllable switch group 52 includes N-channel MOSFET Q13, N-channel MOSFET Q14, N-channel MOSFET Q15 and N-channel MOSFET Q16.

[0065] To elaborate, in the aforementioned Figures 8 to 11 Based on the circuit structure and textual description, regarding the merging and serializing drive circuit corresponding to the positive output terminal, the first controllable switch group 51 and the second controllable switch group 52 are as follows: Figure 12 As shown, corresponding to the first path: the control terminal of P-channel MOSFET Q1 is used to receive the first pulse sub-signal d0_pmos, and the control terminal of N-channel MOSFET Q5 is used to receive the second pulse sub-signal d0_nmos; corresponding to the second path: the control terminal of P-channel MOSFET Q2 is used to receive the first pulse sub-signal d1_pmos, and the control terminal of N-channel MOSFET Q6 is used to receive the second pulse sub-signal d1_nmos; corresponding to the third path: the control terminal of P-channel MOSFET Q3 is used to receive the first pulse sub-signal d2_pmos, and the control terminal of N-channel MOSFET Q7 is used to receive the second pulse sub-signal d2_nmos; corresponding to the fourth path: the control terminal of P-channel MOSFET Q4 is used to receive the first pulse sub-signal d3_pmos, and the control terminal of N-channel MOSFET Q8 is used to receive the second pulse sub-signal d3_nmos. The output terminal Toutp of the merging and serialization driver circuit corresponding to the positive output terminal of each DAC slice 221 is connected, and the common terminal of the connection serves as the positive output terminal of the entire high-speed data processing module 22.

[0066] For the merging and serializing drive circuit corresponding to the negative output terminal, the first controllable switch group 51 and the second controllable switch group 52 are as follows: Figure 13As shown, corresponding to the first path: the control terminal of P-channel MOSFET Q9 is used to receive the first pulse sub-signal D0_pmos, and the control terminal of N-channel MOSFET Q13 is used to receive the second pulse sub-signal D0_nmos; corresponding to the second path: the control terminal of P-channel MOSFET Q10 is used to receive the first pulse sub-signal D1_pmos, and the control terminal of N-channel MOSFET Q14 is used to receive the second pulse sub-signal D1_nmos; corresponding to the third path: the control terminal of P-channel MOSFET Q11 is used to receive the first pulse sub-signal D2_pmos, and the control terminal of N-channel MOSFET Q15 is used to receive the second pulse sub-signal D2_nmos; corresponding to the fourth path: the control terminal of P-channel MOSFET Q12 is used to receive the first pulse sub-signal D3_pmos, and the control terminal of N-channel MOSFET Q16 is used to receive the second pulse sub-signal D3_nmos. The common terminal of the merging and serialization drive circuit corresponding to the negative output terminal of each DAC slice 221 is connected and serves as the negative output terminal of the entire high-speed data processing module 22.

[0067] Further explanation of the operation of serialization module 321: For four parallel pulse signal groups in one transmission cycle, the first pulse signal group is selected in the first UI time period, the second pulse signal group is selected in the second UI time period, and so on. In four consecutive UI time periods, the four parallel pulse signal groups are sampled and selected to the output node in sequence to realize data serialization and synthesize a high-speed serial data stream with a rate four times that of the input pulse signal group. It can be understood that the driving logic of the combining serialization driving circuit corresponding to the positive output terminal and the combining serialization driving circuit corresponding to the negative output terminal are completely symmetrical and complementary. For example, corresponding to the first pulse signal group being selected, when the level state of the signal din0p received at the input terminal of the first logic gate circuit 611 under the first group processing circuit 61 corresponds to logic 1 (at this time, the level state of the signal din0n received at the input terminal of the second logic gate circuit 612 is the corresponding logic 0), then the first controllable switch group 51 corresponding to the positive output terminal is selected (specifically, the P-channel MOSFET Q1 is turned on) and the second controllable switch group 52 corresponding to the negative output terminal is selected (specifically, the N-channel MOSFET Q13 is turned on). At this time, the output terminal Toutp of the merging and serializing module 321 corresponding to the positive output terminal outputs a high level, and the output terminal Toutn of the merging and serializing module 321 corresponding to the negative output terminal outputs a low level. The differential output voltage is positive; conversely, when the signal din0p received by the input terminal of the first logic gate circuit 611 in the first group of processing circuits corresponds to logic 0 (at this time, the signal din0n received by the input terminal of the second logic gate circuit 612 corresponds to logic 1), the second controllable switch group 52 corresponding to the positive output terminal is selected (specifically, the N-channel MOSFET Q5 is turned on) and the first controllable switch group 51 corresponding to the negative output terminal is selected (specifically, the P-channel MOSFET Q9 is turned on). At this time, the output terminal Toutp of the merging and serializing module 321 corresponding to the positive output terminal outputs a low level, and the output terminal Toutn of the merging and serializing module 321 corresponding to the negative output terminal outputs a high level, and the corresponding differential output voltage is negative.

[0068] The present invention also provides a high-speed serial communication system, including a transmitter based on the DSP-DAC architecture as described above.

[0069] For a description of the high-speed serial communication system provided in this application, please refer to the above-described embodiment of the transmitter based on the DSP-DAC architecture; further details will not be repeated here.

[0070] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section. Relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one" does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0071] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A transmitting device based on a DSP-DAC architecture, characterized in that, It includes a digital processing unit and a data path unit connected in sequence. The data path unit includes a low-speed data processing module and a high-speed data processing module. The high-speed data processing module includes A groups of DAC slices. Each group of DAC slices includes a differential-pulse generation module and a merging-serialization driving module. The digital processing unit is used to convert and process the signal to be transmitted based on multi-tap FIR feedforward equalization to obtain B parallel A-bit data signals; in the A-bit data signal, A1 bit adopts binary code and A2 bit adopts thermometer code, A1+A2=A, A1 and A2 are both integers and the number of bits of A2 is higher than A1; The low-speed data processing module is used to serialize the B-channel parallel A-bit data signals to obtain C-channel parallel A-bit data signals, where A is an integer greater than 1, B and C are even numbers greater than 1 and B > C. The differential-pulse generation module of the i-th DAC slice is used to receive the i-th bit data signal of C parallel channels, and to perform differential and pulse generation processing on it based on a preset non-full rate clock to obtain the corresponding i-th bit, C parallel pulse signal. The pulse width of the pulse signal under any channel is one symbol period, and each pulse signal corresponding to the i-th bit data signal of a group of C parallel channels is delayed by one symbol period in sequence, 1≤i≤A and i is an integer. The outputs of the merging and serialization driving modules of the A-group DAC slices are connected in parallel. The merging and serialization driving module in the i-th DAC slice is used to receive the C-channel parallel pulse signal corresponding to the i-th bit, perform merging and serialization processing on it, and drive it according to the weight corresponding to the i-th DAC slice through the SST driving structure to output the serialized differential signal corresponding to the i-th bit. Then, the A-bit serialized differential signals are superimposed to obtain the target serialized differential signal.

2. The transmitting device based on the DSP-DAC architecture as described in claim 1, characterized in that, The digital processing unit includes a pseudo-random binary sequence generator and a DSP module connected in sequence. The pseudo-random binary sequence generator is used to generate B parallel data signals based on the signal to be transmitted. The DSP module is used to perform multi-tap FIR feedforward equalization and binary-to-thermometer code processing on the B-channel parallel signals to obtain the A-bit data signal in the B-channel parallel signals.

3. The transmitting device based on the DSP-DAC architecture as described in claim 1, characterized in that, The low-speed data processing module includes K parallel circuits connected in sequence, where K is an integer greater than 1; Each of the parallel circuits includes multiple 2:1 MUX modules connected in parallel, and the number of 2:1 MUX modules connected in parallel varies in different parallel circuits, so as to realize the conversion of B-channel parallel A-bit data signals to C-channel parallel A-bit data signals.

4. The transmitting device based on the DSP-DAC architecture as described in any one of claims 1 to 3, characterized in that, A=9 and A1=6, A2=3; The weights of DAC slices from group 1 to group 6 are 1, 2, 4, 8, 16, and 32 respectively, to achieve weighted drive control of the lower 6 bits of binary code; the weights of DAC slices from group 7 to group 9 are 64, 64, and 64 respectively, to achieve weighted drive control of the higher 3 bits of thermometer code.

5. The transmitting device based on the DSP-DAC architecture as described in claim 4, characterized in that, C=4, the differential-pulse generation module under the i-th DAC slice includes a single-ended to differential module, a retiming module and a 1UI pulse generation module connected in sequence; The single-ended to differential module is used to receive the i-th bit data signal from four parallel channels and perform single-ended to differential processing on it using a differential clock signal to obtain the first intermediate differential signal from four parallel channels corresponding to the i-th bit. The retiming module is used to receive the first intermediate differential signal corresponding to the i-th bit, which is 4 parallel channels, and to use a 1 / 4 rate four-phase clock signal to synchronize and delay it with 1UI, so as to obtain the second intermediate differential signal corresponding to the i-th bit, which is 4 parallel channels and is delayed by one symbol period in sequence. The 1UI pulse generation module is used to receive the second intermediate differential signal corresponding to the i-th bit, which is 4 parallel channels and sequentially delayed by one symbol period, and to perform narrow pulse generation processing using the 1 / 4 rate four-phase clock signal to obtain a pulse signal group corresponding to the i-th bit, which is 4 parallel channels. The pulse signal group under any path includes a first pulse signal corresponding to the positive output terminal and a second pulse signal corresponding to the negative output terminal, and the pulse width of the first pulse signal and the second pulse signal is one symbol period. The two adjacent pulse signal groups under any path are separated by 3 symbol periods.

6. The transmitting device based on the DSP-DAC architecture as described in claim 5, characterized in that, The 1UI pulse generation module includes 4 sets of processing circuits. The j-th set of processing circuits corresponding to the j-th channel includes two logic gate circuits. The input of the first logic gate circuit is used to receive the positive differential signal of the j-th channel second intermediate differential signal and the output is used to output the first pulse signal corresponding to the positive output terminal. The input of the second logic gate circuit is used to receive the negative differential signal of the j-th channel second intermediate differential signal and the output is used to output the second pulse signal corresponding to the negative output terminal. 1≤j≤4 and j is an integer. The logic gate circuit includes two NOT gates, two AND gates, and two OR gates; the 1 / 4 rate four-phase clock signal includes a first clock signal, a second clock signal, a third clock signal, and a fourth clock signal with phases differing by 90 degrees in sequence; The inputs of the first NOT gate and the second NOT gate are connected, and the common terminal of the connection is used as the input of the logic gate circuit. The first input terminal of the second AND gate is connected to the output terminal of the first NOT gate, the second input terminal is connected to the output terminal of the first AND gate, and the output terminal serves as the first output terminal among the output terminals of the logic gate circuit. The first input terminal of the second OR gate is connected to the output terminal of the second NOT gate, the second input terminal is connected to the output terminal of the first OR gate, and the output terminal serves as the second output terminal in the logic gate circuit. Corresponding to the first group of processing circuits of the first path, the first input terminal of the first AND gate of the two logic gate circuits below is used to connect to the first clock signal and the second input terminal is used to connect to the second clock signal; the first input terminal of the first OR gate is used to connect to the third clock signal and the second input terminal is used to connect to the fourth clock signal. Corresponding to the second group of processing circuits in the second channel, the first input terminal of the first AND gate in the two logic gate circuits below is used to connect to the second clock signal and the second input terminal is used to connect to the third clock signal; the first input terminal of the first OR gate is used to connect to the fourth clock signal and the second input terminal is used to connect to the first clock signal. Corresponding to the third group of processing circuits in the third path, the first input terminal of the first AND gate in the two logic gate circuits below is used to connect to the third clock signal and the second input terminal is used to connect to the fourth clock signal; the first input terminal of the first OR gate is used to connect to the first clock signal and the second input terminal is used to connect to the second clock signal. Corresponding to the fourth group of processing circuits in the fourth path, the first input of the first AND gate in the two logic gate circuits below is used to connect to the fourth clock signal and the second input is used to connect to the first clock signal; the first input of the first OR gate is used to connect to the second clock signal and the second input is used to connect to the third clock signal.

7. The transmitting device based on the DSP-DAC architecture as described in claim 6, characterized in that, The merging and serialization driver module under the i-th DAC slice includes a merging and serialization driver circuit corresponding to the positive output terminal and a merging and serialization driver circuit corresponding to the negative output terminal; wherein, the pulse input terminal of the merging and serialization driver circuit corresponding to the positive output terminal is used to receive the first pulse signal in the four parallel pulse signal groups and the output terminal is used to output the positive serialization differential signal in the serialization differential signal corresponding to the i-th bit; the pulse input terminal of the merging and serialization driver circuit corresponding to the negative output terminal is used to receive the second pulse signal in the four parallel pulse signal groups and the output terminal is used to output the negative serialization differential signal in the serialization differential signal corresponding to the i-th bit. The merging and serialization driving circuit includes a serialization module, an impedance matching resistor, a first tunable circuit and a second tunable circuit corresponding to the weight settings of the i-th group of DAC slices. The first terminal of the first tunable circuit is connected to the power supply, the second terminal is connected to the first terminal of the serialization module, and the control terminal is connected to the control module; the first terminal of the second tunable circuit is connected to the second terminal of the serialization module, the second terminal is grounded, and the control terminal is connected to the control module. The control terminal of the serialization module serves as the pulse input terminal of the merging and serialization driving circuit, and its output terminal is connected to one end of the impedance matching resistor, with the other end of the impedance matching resistor serving as the output terminal of the merging and serialization driving circuit. The control module is used to adjust the equivalent impedance of the first tunable circuit and the second tunable circuit so that the total equivalent output impedance of the merging and serializing driver module under the i-th DAC slice matches the target output impedance corresponding to the i-th DAC slice.

8. The transmitting device based on the DSP-DAC architecture as described in claim 7, characterized in that, The serialization module includes two controllable switch groups; The first terminal of the first controllable switch group serves as the first terminal of the serialization module, and the second terminal is connected to the first terminal of the second controllable switch group, with the common terminal of the connection serving as the output terminal of the serialization module. The second terminal of the second controllable switch group serves as the second terminal of the serialization module; Corresponding to the merging and serializing drive circuit at the positive output terminal, the control terminal of the first controllable switch group in the lower serialization module is used to receive the first pulse sub-signal in the four parallel first pulse signals, and the control terminal of the second controllable switch group is used to receive the second pulse sub-signal in the four parallel first pulse signals. Corresponding to the negative output terminal of the merging and serializing drive circuit, the control terminal of the first controllable switch group in the lower serialization module is used to receive the first pulse sub-signal in the four parallel second pulse signals, and the control terminal of the second controllable switch group is used to receive the second pulse sub-signal in the four parallel second pulse signals.

9. The transmitting device based on the DSP-DAC architecture as described in claim 8, characterized in that, Both the first tunable circuit and the second tunable circuit include a controllable switch array; The controllable switch array includes 15 first controllable switches with size parameters corresponding to the weights of the i-th group of DAC slices. The first controllable switches are connected in parallel and the control terminal of each first controllable switch is connected to the control module. The first controllable switch is used to turn on and off according to the 4-bit binary code output by the control module, so that the equivalent impedance of the controllable switch array presents a target binary weight relationship.

10. A high-speed serial communication system, characterized in that, Including the transmitting device based on the DSP-DAC architecture as described in any one of claims 1 to 9.

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