Low-power-consumption remote wake-up circuit of CAN FD transceiver

Abstract

The invention discloses a low-power-consumption remote wake-up circuit of a CAN FD transceiver. The low-power-consumption remote wake-up circuit comprises a comparator, a filtering time detection module and a wake-up circuit module. The comparator is used for comparing the level of the CANH and the level of the CANL, when the CANH is larger than the CANL, a high level is output and marked as a dominant state, and when the CANH is smaller than the CANL, a low level is output and marked as an implicit state. The filtering time detection module is composed of a phase inverter and a capacitor; the wake-up circuit module is composed of a digital logic circuit so as to achieve the function of multi-filtering dominant wake-up. When the CAN FD transceiver enters a low-power-consumption mode, the CAN FD transceiver receives CANH and CANL signals, the comparator compares the levels of the CANH and CANL signals and outputs the signals to the filtering time detection module, and the signals with dominant or implicit signal pulse width time smaller than tFilter are filtered out; through the wake-up circuit module, when an input signal satisfies an ''explicit-implicit-explicit'' signal sequence, the signal received by the CAN FD transceiver is output, and the low-power-consumption mode is not quitted, so that remote wake-up of the CAN FD transceiver is realized.

Description

Technical Field

[0001] This invention relates to the field of CAN FD transceiver technology, and in particular to a low-power remote wake-up circuit for a CAN FD transceiver. Background Technology

[0002] In applications such as automotive electronics, industrial control, and battery-powered equipment, many ECUs (Electronic Control Units) are in a "sleep" or "standby" state most of the time to save power. These nodes must be able to be quickly woken up under certain conditions to resume normal communication. When the application environment of a CAN bus transceiver chip is temporarily in standby mode or does not require communication, in order to reduce the chip's power consumption, the CAN bus transceiver chip can implement a standby mode in addition to the normal mode, thereby effectively reducing its energy consumption.

[0003] Early CAN transceivers used a local wake-up method, directly powering on the CAN transceiver and controller via a GPIO pin or a dedicated wake-up pin on the MCU. This method was entirely controlled by the master controller and independent of the CAN bus itself, making remote wake-up impossible; that is, nodes could not be woken up via messages on the CAN bus.

[0004] To support remote wake-up, the transceiver integrates a low-power monitoring circuit. This circuit is connected in parallel with the normal transmit / receive channel but operates independently. Its core technology is as follows: 1. Bus Dominance State Detection: When the CAN bus is in the recessive state (logic "1", approximately 2.5V), the CANH and CANL voltages are close. When a node starts sending a dominant bit (logic "0"), the CANH voltage increases and the CANL voltage decreases, generating a differential voltage.

[0005] 2. Comparator circuit: continuously monitors the bus differential voltage or single-line to ground voltage.

[0006] 3. Threshold detection: When the detected voltage exceeds a preset wake-up threshold and continues for a certain period of time, it is judged as a valid wake-up event.

[0007] 4. Selective wake-up (wake-up with specific message): such as Figure 4 As shown, the CAN FD transceiver employs a multi-filter dominant wake-up mode. This means that wake-up is triggered only when three data frames appear on the bus, containing two dominant signals and one recessive signal, with the recessive signal positioned between the two dominant signals. The minimum length of the data frame must be greater than the protocol preset value t. Filter .

[0008] In low-power mode, both the transmitting and receiving circuits are inactive, but the receiver section still needs to be woken up to operate normally and detect the bus level. When a valid signal is detected, the CAN FD transceiver circuit is woken up and outputs the received dominant and recessive signals, completing the signal output in low-power mode without exiting the low-power mode. Summary of the Invention

[0009] The purpose of this invention is to provide a low-power remote wake-up circuit for a CAN FD transceiver. This circuit compares the CANH and CANL levels of the CAN FD transceiver using a comparator, and the output signal passes through a filtering signal detection module with a filtering pulse width less than t. Filter The signal is detected by the wake-up detection module. When the signal meets the "show-hide-show" condition, the CAN FD transceiver chip is woken up and data is transmitted in low power mode.

[0010] To address the aforementioned technical problems, this invention provides a low-power remote wake-up circuit for a CAN FD transceiver, comprising: a comparator, a filtering time detection module, and a wake-up circuit module; The filtering time detection module includes inverters INV1 and INV2, and capacitor C1; the wake-up circuit module includes logic module one, logic module two, logic module three, AND gate AND1, AND gate AND2, AND gate AND3, AND gate AND4, inverters INV3, INV4, and INV5, OR gate OR1, OR gate OR2, OR gate OR3, buffer Buffer1, and buffer Buffer2. Inverter INV1 shapes the comparator's output signal, capacitor C1 is used for charging and discharging, and the minimum filter length is less than t. Filter When the signal pulse width time meets the requirements, the inverter INV2 flips to transmit the signal normally. The signal enters the wake-up circuit module. Logic module one detects whether the first signal is a dominant signal; logic module two detects whether the next signal is a recessive signal; and logic module three detects whether the next signal is a dominant signal. Only when the wake-up signal sequence of dominant-recessive-dominant is satisfied is the CAN FD transceiver woken up and signal transmission begins. The comparator's input is the CANH and CANL signals received by the CAN FD transceiver, and its output is connected to the input of the inverter INV1. The output terminal of inverter INV1 is connected to the first terminal of capacitor C1 and the input terminal of inverter INV2; the output terminal of inverter INV2 is connected to the D input terminal of logic module one, the A0 input terminal of logic module two, the D input terminal of logic module three, and the second input terminal of OR gate OR1; the second terminal of capacitor C1 is connected to GND. The A0 input of logic module 1 is connected to the D input of logic module 2, the Y output of logic module 3, the second input of AND gate AND1, and the first input of AND gate AND3; the A1 input of logic module 1 is connected to the Y output of logic module 2, the A1 input of logic module 3, the first input of AND gate AND1, the first input of AND gate AND4, and the input of inverter INV4; the B input of logic module 1 is connected to the B input of logic module 2, the B input of logic module 3, and the output of buffer Buffer2. The Y output of logic module 1 is connected to the A1 input of logic module 2, the A0 input of logic module 3, the first input of AND gate AND2, and the input of inverter INV5. The second input of AND gate AND2 is connected to the output of AND gate AND1, and the output of AND gate AND2 is connected to the input of inverter INV3. The output of inverter INV3 is connected to the first input of OR gate OR1. The output of OR gate OR1 is connected to the input of buffer Buffer1. The output of inverter INV4 is connected to the second input of AND gate AND3, the output of inverter INV5 is connected to the second input of AND gate AND4, the output of AND gate AND3 is connected to the first input of OR gate OR2, the output of AND gate AND4 is connected to the second input of OR gate OR2, the output of OR gate OR2 is connected to the first input of OR gate OR3, the second input of OR gate OR3 is connected to the enable signal OE, and its output is connected to the input of buffer Buffer2.

[0011] In one embodiment, the logic module one includes inverters INV11, INV12, INV13, and INV14, NOR11, NOR12, and NOR13, AND11 and AND12, T buffers T_Buffer11 and T_Buffer12, buffer Buffer11, capacitors C11, C12, and C13; The input of inverter INV11 is connected to the D port signal, and its output is connected to the first input of AND gate AND11. The inputs of NOR gate NOR11 are connected to the A0 and A1 port signals respectively, and its output is connected to the second input of AND gate AND11. The output of AND gate AND11 is connected to the first input of AND gate AND12. The input of inverter INV12 is connected to signal B and is connected to the first input of NOR gate NOR12. The output of inverter INV12 is connected to the second input of AND gate AND12. The output of AND gate AND12 is connected to the input of inverter INV13. The output of inverter INV13 is connected to the input of buffer T_Buffer11. Buffer T_Buffer11 is composed of two cascaded inverters. The output of the first inverter is connected to the first terminal of capacitor C11. The output of the second inverter is connected to the first terminal of capacitor C12 and the input of buffer T_Buffer12. Buffer T_Buffer12 is composed of two cascaded inverters. The output of the first inverter is connected to the first terminal of capacitor C13. The output of the second inverter is connected to the input of inverter INV14. The output of inverter INV14 is connected to the second input of NOR13, the second input of NOR12 is connected to the output of NOR13, the output of NOR12 is connected to the first input of NOR13 and the input of buffer Buffer11, the output of buffer Buffer11 is the output signal Y of logic module two, the second end of capacitor C11 is connected to GND, the second end of capacitor C12 is connected to GND, and the second end of capacitor C13 is connected to GND.

[0012] In one embodiment, the structure of logic module two is the same as that of logic module three, and includes inverters INV21, INV22, INV23, and INV24, NOR21 and NOR22, AND21, AND22, and AND23, T buffer T_Buffer21, T buffer T_Buffer22, buffer Buffer21, capacitor C21, capacitor C22, and capacitor C23. The input of inverter INV21 is connected to the D port signal, and its output is connected to the second input of AND gate AND21. The input of AND gate AND21 is connected to the A1 port signal, and its output is connected to the first input of AND gate AND22. The second input of AND gate AND22 is connected to the A0 port signal, and its output is connected to the first input of AND gate AND23. The input of inverter INV22 is connected to the B port signal and is connected to the first input of NOR gate NOR21. The output of inverter INV22 is connected to the second input of AND gate AND23. The output of AND gate AND23 is connected to the input of inverter INV23. The output of inverter INV23 is connected to the input of buffer T_Buffer21. Buffer T_Buffer21 is composed of two cascaded inverters. The output of the first inverter is connected to the first terminal of capacitor C21. The output of the second inverter is connected to the first terminal of capacitor C22 and the input of buffer T_Buffer22. Buffer T_Buffer22 is composed of two cascaded inverters. The output of the first inverter is connected to the first terminal of capacitor C23. The output of the second inverter is connected to the input of inverter INV24. The output of inverter INV24 is connected to the second input of NOR22. The second input of NOR21 is connected to the output of NOR22. The output of NOR21 is connected to the first input of NOR22 and the input of buffer Buffer21. The output of buffer Buffer21 is the output signal of logic module three. The second terminal of capacitor C21, the second terminal of capacitor C22, and the second terminal of capacitor C23 are all connected to GND.

[0013] In one embodiment, the comparator outputs a high level when the CANH signal voltage is greater than the CANL signal voltage, and outputs a low level when the CANH signal voltage is less than the CANL signal voltage.

[0014] This invention provides a low-power remote wake-up circuit for a CAN FD transceiver, comprising: a comparator, a filtering time detection module, and a wake-up circuit module. The comparator compares the levels of CANH and CANL. When CANH is greater than CANL, it outputs a high level, indicating a dominant state; when CANH is less than CANL, it outputs a low level, indicating a recessive state. When the CAN FD transceiver enters low-power mode, the CANH and CANL signals received by the CAN FD transceiver are compared by the comparator to determine their levels. The comparator output signal then enters the filtering time detection module, filtering for dominant or recessive signals with a pulse width time less than t. Filter The signal is received by the CAN FD transceiver; then, through the wake-up circuit module, when the input signal meets the "show-hide-show" signal sequence, the signal received by the CAN FD transceiver is output without exiting the low-power mode, thus realizing the remote wake-up of the CAN FD transceiver. Attached Figure Description

[0015] Figure 1 A schematic diagram of a low-power remote wake-up circuit for a CAN FD transceiver; Figure 2 LOGIC 1 module structure diagram for low-power remote wake-up circuit of CAN FD transceiver; Figure 3 LOGIC 2 module structure diagram for low-power remote wake-up circuit of CAN FD transceiver; Figure 4 A schematic diagram of the WUP waveform in the multi-filter explicit wake-up mode; Figure 5 This is a schematic diagram of the transmission characteristic curve of an inverter; Figure 6 A schematic diagram illustrating the charging and discharging of the capacitor under different input conditions; Figure 7 This is a schematic diagram of the simulation waveform. Detailed Implementation

[0016] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, provides a further detailed explanation of a low-power remote wake-up circuit for a CAN FD transceiver proposed in this invention. The advantages and features of this invention will become clearer from the following description. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention.

[0017] This invention provides a low-power remote wake-up circuit for a CAN FD transceiver, comprising a comparator (Comp1), a filtering time detection module, and a wake-up circuit module. The comparator compares the levels of CANH and CANL. When CANH is greater than CANL, it outputs a high level, indicating a dominant state; when CANH is less than CANL, it outputs a low level, indicating a recessive state. When the CAN FD transceiver enters low-power mode, the CANH and CANL signals received by the CAN FD transceiver are compared by the comparator to determine their levels. The comparator output signal then enters the filtering time detection module, filtering for dominant or recessive signals with a pulse width time less than t. Filter The signal is received by the CAN FD transceiver; then, through the wake-up circuit module, when the input signal meets the "show-hide-show" signal sequence, the signal received by the CAN FD transceiver is output without exiting the low-power mode, thus realizing remote wake-up of the CAN FD transceiver. Its simulation waveform is as follows: Figure 7 As shown.

[0018] like Figure 1 As shown, the input of the comparator is the CANH and CANL signals received by the CAN FD transceiver, and the output is connected to the inverter INV1.

[0019] The filtering time detection module includes inverters INV1 and INV2, and capacitor C1. The output of inverter INV1 is connected to the first terminal of capacitor C1 and the input of inverter INV2. The output of inverter INV2 is connected to the D input of logic module LOGIC 1, the A0 input of logic module LOGIC 2, the D input of logic module LOGIC 3, and the second input of OR gate OR1. The second terminal of capacitor C1 is connected to GND.

[0020] The wake-up circuit module includes logic modules LOGIC 1, LOGIC 2, LOGIC 3, AND gates AND1, AND2, AND3, AND4, inverters INV3, INV4, INV5, OR gates OR1, OR2, OR3, buffers Buffer1 and Buffer2. The A0 input of logic module LOGIC 1 is connected to the D input of logic module LOGIC 2, the Y output of logic module LOGIC 3, the second input of AND gate AND1, and the first input of AND gate AND3. The A1 input of logic module LOGIC 1 is connected to the Y output of logic module LOGIC 2, the A1 input of logic module LOGIC 3, the first input of AND gate AND1, the first input of AND gate AND4, and the input of inverter INV4. The B input of logic module LOGIC 1 is connected to the B input of logic module LOGIC 2, the B input of logic module LOGIC 3, and the output of buffer Buffer2. The Y output of logic module LOGIC 1 is connected to the A1 input of logic module LOGIC 2, the A0 input of logic module LOGIC 3, the first input of AND gate AND2, and the input of inverter INV5. The second input of AND gate AND2 is connected to the output of AND gate AND1, and the output of AND gate AND2 is connected to the input of inverter INV3. The output of inverter INV3 is connected to the first input of OR gate OR1. The output of OR gate OR1 is connected to the input of buffer Buffer1. The output of inverter INV4 is connected to the second input of AND gate AND3. The output of inverter INV5 is connected to the second input of AND gate AND4. The output of AND gate AND3 is connected to the first input of OR gate OR2. The output of AND gate AND4 is connected to the second input of OR gate OR2. The output of OR gate OR2 is connected to the first input of OR gate OR3, the second input of OR gate OR3 is connected to the enable signal OE, and its output is connected to the input of buffer Buffer2.

[0021] The structure of logic module LOGIC 1 is as follows: Figure 2As shown, the system includes inverters INV11, INV12, INV13, and INV14; NOR11, NOR12, and NOR13; AND11 and AND12; T buffers T_Buffer11 and T_Buffer12; buffer Buffer11; and capacitors C11, C12, and C13. The input of inverter INV11 is connected to the D port signal, and its output is connected to the first input of AND11. The inputs of NOR11 are connected to the A0 and A1 port signals, respectively, and its output is connected to the second input of AND11. The output of AND11 is connected to the first input of AND12. The input of inverter INV12 is connected to signal B and also connected to the first input of NOR12; the output of inverter INV12 is connected to the second input of AND12. The output of AND gate AND12 is connected to the input of inverter INV13. The output of inverter INV13 is connected to the input of buffer T_Buffer11. Buffer T_Buffer11 consists of two cascaded inverters: the output of the first inverter is connected to the first terminal of capacitor C11, and the output of the second inverter is connected to the first terminal of capacitor C12 and the input of buffer T_Buffer12. Buffer T_Buffer12 consists of two cascaded inverters: the output of the first inverter is connected to the first terminal of capacitor C13, and the output of the second inverter is connected to the input of inverter INV14. The output of inverter INV14 is connected to the second input of NOR gate NOR13. The second input of NOR gate NOR12 is connected to the output of NOR gate NOR13, and the output of NOR gate NOR12 is connected to the first input of NOR gate NOR13 and the input of buffer Buffer11. The output of buffer Buffer11 is the output signal Y of the LOGIC 2 module. The second terminal of capacitor C11 is connected to GND. The second terminal of capacitor C12 is connected to GND. The second terminal of capacitor C13 is connected to GND.

[0022] The structure of the logic module LOGIC 2 is as follows: Figure 3As shown in the figure, it includes inverter INV21, inverter INV22, inverter INV23, inverter INV24, NOR gate NOR21, NOR gate NOR22, AND gate AND21, AND gate AND22, AND gate AND23, T buffer T_Buffer21, T buffer T_Buffer22, buffer Buffer21, capacitor C21, capacitor C22, and capacitor C23. The input terminal of inverter INV21 is externally connected to the D port signal, and the output terminal is connected to the second input terminal of AND gate AND21. The input terminal of AND gate AND21 is externally connected to the A1 port signal, and the output terminal is connected to the first input terminal of AND gate AND22. The second input terminal of AND gate AND22 is externally connected to the A0 port signal, and the output terminal is connected to the first input terminal of AND gate AND23. The input terminal of inverter INV22 is externally connected to the B port signal and is connected to the first input terminal of NOR gate NOR21, and the output terminal of inverter INV22 is connected to the second input terminal of AND gate AND23. The output terminal of AND gate AND23 is connected to the input terminal of inverter INV23. The output terminal of inverter INV23 is connected to the input terminal of buffer T_Buffer21. Buffer T_Buffer21 is cascaded by two inverters, where the output terminal of the first inverter is connected to the first end of capacitor C21, and the output terminal of the second inverter is connected to the first end of capacitor C22 and the input terminal of buffer T_Buffer22. Buffer T_Buffer22 is cascaded by two inverters, where the output terminal of the first inverter is connected to the first end of capacitor C23, and the output terminal of the second inverter is connected to the input terminal of inverter INV24. The output terminal of inverter INV24 is connected to the second input terminal of NOR gate NOR22. The second input terminal of NOR gate NOR21 is connected to the output terminal of NOR gate NOR22, and the output terminal of NOR gate NOR21 is connected to the first input terminal of NOR gate NOR22 and the input terminal of buffer Buffer21. The output of buffer Buffer21 is the output signal of the LOGIC 3 module. The second end of capacitor C21 is connected to GND. The second end of capacitor C22 is connected to GND. The second end of capacitor C23 is connected to GND.

[0023] The circuit structure of logic module LOGIC 3 is the same as that of logic module LOGIC 2.

[0024] The specific working principle is analyzed as follows: The comparator compares the signals CANH and CANL of the CAN transceiver and outputs high and low level signals: when CANH > CANL, it outputs a high level; when CANH < CANL, it outputs a low level. The signal passes through the filter time detection module. Inverter INV1 is used to shape the output of the comparator, and the capacitor C1Used for charging delay, inverter INV2 is used to restore the polarity of the transmitted signal. The transmission characteristic curve of the inverter is... Figure 5 It can be seen that when the input signal is lower than the switching voltage V m When the input signal is higher than the switching voltage V, the inverter output is high; when the input signal is higher than the switching voltage V, the inverter output is high. m When the time is right, the output is low.

[0025] like Figure 6 As can be seen, the inverter consists of P1 and N1. Considering the ideal condition of the inverter's MOSFET being turned on, when the input V... in0 Less than the inverter switching voltage V m When P1 is turned on, N1 is turned off. VDD charges capacitor C1 through P1. The on-resistance of P1 at this time is set to R. eqp From the capacitor charging formula, we know:

[0026] If you want to know the elapsed time t Filter1 After that, the output voltage of inverter INV1 can reach the switching voltage VDD / 2 of inverter INV2, then:

[0027] Conversely, when input V in0 Greater than the inverter switching voltage V m When P1 is turned off, N1 is turned on. In the capacitor... C The charge stored in 1 is discharged to GND through transistor N1. At this time, the on-resistance of transistor N1 is set to R. eqn Similarly, after t Filter2 After that, the output voltage of inverter INV1 can drop below the switching voltage VDD / 2 of inverter INV2, then:

[0028] Therefore, the output of inverter INV2 can only output a duration greater than the set t. Fliter signal V in Next, we move on to the wake-up circuit module. The logic modules within the wake-up module are designed with the following functions: First, it is necessary to know that the SR latch has the function table shown in Table 1 below: S R Q Q* Function 0 0 0 0 Keep 0 0 1 1 Keep 0 1 0 0 Set to 0 0 1 1 0 Set to 0 1 0 0 1 Set 1 1 0 1 1 Set 1 1 1 0 indefinite Undefined 1 1 1 indefinite Undefined Table 1 SR Latch Function Table For the overall circuit diagram, the inputs of AND gate AND3 are the inverted O2 and O3, so the output is low. Similarly, the inputs of AND4 are the inverted O1 and O2, so the output is also low. Therefore, the output of OR gate OR2 is low. The enable signal OE is high before it is established, and becomes low after it is established. Therefore, the output signal through OR gate OR3 is still the OE signal. The output of buffer Buffer2 connected to the B terminal of logic modules LOGIC 1, LOGIC 2 and LOGIC 3 is also the OE signal.

[0029] For logic module LOGIC 1, its output signal is O1, port A1 is connected to signal O2, port A0 is connected to signal O3, and port D is connected to input signal V. in .

[0030] Please see Figure 2 and Figure 3 When the B terminal signal of logic module LOGIC 1 is 1, the inverter INV12 outputs a low level. After passing through AND gate AND12, the output is low level. Then, after passing through inverter INV13, buffer T_Buffer11, buffer T_Buffer12, and inverter INV14, the output is still low level. Therefore, the output Y=0 (set to 0). When the B-terminal signal of logic module LOGIC 1 is 0, the high-level output of inverter INV12 does not affect the output of AND gate AND12. When the D input is low (dominant), the output of inverter INV11 is high. A0 outputs O3, and A1 outputs O2. When no dominant or recessive signal is received, A0 and A1 are low, resulting in a high-level output through NOR gate NOR11 and AND gate AND11. Therefore, the output of inverter INV14 is high, and after passing through the SR latch, the output is high, so Y = VDD (set to 1). When the D input is high (recessive), the output of inverter INV14 is low, so output O1 remains low.

[0031] Function Summary: When a dominant signal is detected, the O1 output flips to a high level; when a recessive signal is detected, the output remains at its original low level.

[0032] Considering that the O2 and O3 outputs use the same logic module LOGIC 2, only the input signal connection is different, the output signals O2 and O3 will be described separately below.

[0033] For logic module LOGIC 2, its output signal is O2. The O1 signal is connected to port A1, and the input signal V is connected to port A0. in The D port is connected to the O3 signal.

[0034] When no dominant or recessive signal is detected, O3(D) is low, and when a dominant signal is detected, O1(A1) flips high. Therefore, the AND gate AND21 outputs a high level, so when V in When (A0) is high (when it is the second recessive signal), the AND gate AND22 outputs high. After the enable is established, the inverter INV22 outputs high. Therefore, the AND gate AND23 outputs high, the inverter INV24 outputs high, B is low, SR outputs high, and after passing through the buffer Buffer21, O2(Y) outputs high.

[0035] Conversely, if V in When (A0) is low (in the dominant state), the inverter INV24 output is low, B is low, the SR latch is in the holding state, and the output is low.

[0036] Function Description: After the system detects the first dominant level, the O2 (Y) output will flip to high only when the second recessive level is detected.

[0037] For logic module LOGIC 3, its output signal is O3, port A0 is connected to signal O1, port A1 is connected to signal O2, and port D is connected to input signal V. in Signal.

[0038] When the input signal V in After the input show-hide signal is received, O2 (A1) toggles to a high level, and the input signal V... in (D) The output of the inverter INV21 is inverted and fed to the input of the AND gate AND21. When A1 is high, the input is from low to high. After inversion, it is from high to low. When the output of the inverter INV21 is low, the output of the AND gate AND21 is low. When a high level is detected, that is, when the third dominant input level arrives, the output of the AND gate AND21 is high. Therefore, the output of the AND gate AND21 and V... in The pulse width time of the dominant-recessive signal is delayed, plus the delay time of AND gate AND21. The output of O1 (A0) toggles high, B is high, so the output signal of AND gate AND23 is the signal of AND gate ADN21, which is output to the output of inverter INV24. When the output signal of INV24 is low, the enable OE is low after it is established. Therefore, in order to maintain the signal before the enable OE is established, the enable OE is high before establishment, and the SR output is low. Therefore, the output is low. When the signal at the output of inverter INV24 is high, the SR output is high. When it is low, it is still maintained. Therefore, even if a dominant-recessive-dominant signal appears after the input signal, the SR output is always high, and the output of O3 (Y) toggles high.

[0039] Function Summary: When a visible-hidden-visible signal is detected, O3(Y) flips to a high level.

[0040] Since the signal can have different states, the circuit's operating state under different conditions is analyzed below: Signals that satisfy multiple filtering wake-up modes: "Show-Hide-Show".

[0041] The function of logic module LOGIC 1 is as follows: when a dominant pulse is input, the output is high; and since its output signal O1 is transmitted to logic module LOGIC 2, logic module LOGIC 2 can only receive the output signal V when O1 is high. in The corresponding function of the excitation output is: when the input is a recessive pulse, the output is high; similarly, the output O1 of logic module LOGIC 1 and the output O2 of logic module LOGIC 2 also control the function of logic module LOGIC 3: when the signal satisfies the first two logic outputs being high, and the input is a dominant pulse, the output O3 is high. Thus, the signal satisfies the "dominant-recessive-dominant" characteristic. The outputs O1, O2, and O3 are high, which, after passing through AND gates AND1 and AND2 and inverter INV3, results in a low output. Then, after passing through OR gate OR1 (where the output is only controlled by the input signal Vin), and finally through buffer Buffer1, the output signal V is obtained. out =V in .

[0042] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A low-power remote wake-up circuit for a CAN FD transceiver, characterized in that, include: Comparator, filter time detection module, wake-up circuit module; The filtering time detection module includes inverters INV1 and INV2, and capacitor C1; the wake-up circuit module includes logic module one, logic module two, logic module three, AND gate AND1, AND gate AND2, AND gate AND3, AND gate AND4, inverters INV3, INV4, and INV5, OR gate OR1, OR gate OR2, OR gate OR3, buffer Buffer1, and buffer Buffer2. The inverter INV1 shapes the output signal of the comparator, the capacitor C1 is used for charging and discharging, and filters the signal with a minimum length less than t Filter When the pulse width time of the signal meets the requirement, the inverter INV2 flips to normally transmit the signal. The signal enters the wake-up circuit module. Logic module one detects whether the first signal is a dominant signal; logic module two detects whether the next signal is a recessive signal; and logic module three detects whether the next signal is a dominant signal. Only when the wake-up signal sequence of dominant-recessive-dominant is satisfied is the CAN FD transceiver woken up and signal transmission begins. The comparator's input is the CANH and CANL signals received by the CAN FD transceiver, and its output is connected to the input of the inverter INV1. The output terminal of inverter INV1 is connected to the first terminal of capacitor C1 and the input terminal of inverter INV2; the output terminal of inverter INV2 is connected to the D input terminal of logic module one, the A0 input terminal of logic module two, the D input terminal of logic module three, and the second input terminal of OR gate OR1; the second terminal of capacitor C1 is connected to GND. The A0 input of logic module 1 is connected to the D input of logic module 2, the Y output of logic module 3, the second input of AND gate AND1, and the first input of AND gate AND3; the A1 input of logic module 1 is connected to the Y output of logic module 2, the A1 input of logic module 3, the first input of AND gate AND1, the first input of AND gate AND4, and the input of inverter INV4; the B input of logic module 1 is connected to the B input of logic module 2, the B input of logic module 3, and the output of buffer Buffer2. The Y output of logic module 1 is connected to the A1 input of logic module 2, the A0 input of logic module 3, the first input of AND gate AND2, and the input of inverter INV5. The second input of AND gate AND2 is connected to the output of AND gate AND1, and the output of AND gate AND2 is connected to the input of inverter INV3. The output of inverter INV3 is connected to the first input of OR gate OR1. The output of OR gate OR1 is connected to the input of buffer Buffer1. The output of inverter INV4 is connected to the second input of AND gate AND3, the output of inverter INV5 is connected to the second input of AND gate AND4, the output of AND gate AND3 is connected to the first input of OR gate OR2, the output of AND gate AND4 is connected to the second input of OR gate OR2, the output of OR gate OR2 is connected to the first input of OR gate OR3, the second input of OR gate OR3 is connected to the enable signal OE, and its output is connected to the input of buffer Buffer2.

2. The low-power remote wake-up circuit for a CAN FD transceiver as described in claim 1, characterized in that, The logic module one includes inverters INV11, INV12, INV13, and INV14, NOR11, NOR12, and NOR13, AND11 and AND12, T buffers T_Buffer11 and T_Buffer12, buffer Buffer11, capacitors C11, C12, and C13; The input of inverter INV11 is connected to the D port signal, and its output is connected to the first input of AND gate AND11. The inputs of NOR gate NOR11 are connected to the A0 and A1 port signals respectively, and its output is connected to the second input of AND gate AND11. The output of AND gate AND11 is connected to the first input of AND gate AND12. The input of inverter INV12 is connected to signal B and is connected to the first input of NOR gate NOR12. The output of inverter INV12 is connected to the second input of AND gate AND12. The output of AND gate AND12 is connected to the input of inverter INV13. The output of inverter INV13 is connected to the input of buffer T_Buffer11. Buffer T_Buffer11 is composed of two cascaded inverters. The output of the first inverter is connected to the first terminal of capacitor C11. The output of the second inverter is connected to the first terminal of capacitor C12 and the input of buffer T_Buffer12. Buffer T_Buffer12 is composed of two cascaded inverters. The output of the first inverter is connected to the first terminal of capacitor C13. The output of the second inverter is connected to the input of inverter INV14. The output of inverter INV14 is connected to the second input of NOR13, the second input of NOR12 is connected to the output of NOR13, the output of NOR12 is connected to the first input of NOR13 and the input of buffer Buffer11, the output of buffer Buffer11 is the output signal Y of logic module two, the second end of capacitor C11 is connected to GND, the second end of capacitor C12 is connected to GND, and the second end of capacitor C13 is connected to GND.

3. The low-power remote wake-up circuit for a CAN FD transceiver as described in claim 1, characterized in that, The structure of logic module two is the same as that of logic module three, and includes inverters INV21, INV22, INV23, and INV24, NOR21 and NOR22, AND21, AND22, and AND23, T buffer T_Buffer21, T buffer T_Buffer22, buffer Buffer21, capacitor C21, capacitor C22, and capacitor C23 respectively. The input of inverter INV21 is connected to the D port signal, and its output is connected to the second input of AND gate AND21. The input of AND gate AND21 is connected to the A1 port signal, and its output is connected to the first input of AND gate AND22. The second input of AND gate AND22 is connected to the A0 port signal, and its output is connected to the first input of AND gate AND23. The input of inverter INV22 is connected to the B port signal and is connected to the first input of NOR gate NOR21. The output of inverter INV22 is connected to the second input of AND gate AND23. The output of AND gate AND23 is connected to the input of inverter INV23. The output of inverter INV23 is connected to the input of buffer T_Buffer21. Buffer T_Buffer21 is composed of two cascaded inverters. The output of the first inverter is connected to the first terminal of capacitor C21. The output of the second inverter is connected to the first terminal of capacitor C22 and the input of buffer T_Buffer22. Buffer T_Buffer22 is composed of two cascaded inverters. The output of the first inverter is connected to the first terminal of capacitor C23. The output of the second inverter is connected to the input of inverter INV24. The output of inverter INV24 is connected to the second input of NOR22. The second input of NOR21 is connected to the output of NOR22. The output of NOR21 is connected to the first input of NOR22 and the input of buffer Buffer21. The output of buffer Buffer21 is the output signal of logic module three. The second terminal of capacitor C21, the second terminal of capacitor C22, and the second terminal of capacitor C23 are all connected to GND.

4. The low-power remote wake-up circuit for a CAN FD transceiver as described in claim 1, characterized in that, In the comparator, when the CANH signal voltage is greater than the CANL, the comparator outputs a high level; when the CANH signal voltage is less than the CANL, the comparator outputs a low level.

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