Write method and write circuit based on RRAM chip

Abstract

The invention provides a writing method and a writing circuit based on an RRAM chip, and relates to the technical field of memory circuit design, the method comprises the following steps: when a writing instruction for a target RRAM chip is received, reading a formation state flag of the target RRAM chip; wherein if the formation state flag is not formed, the target RRAM chip does not execute one-time initialization operation; and when the formation state flag is not formed, executing an initialization operation on the target RRAM chip, and setting the target RRAM chip in the first logic state through the initialization operation to complete the write-in instruction. According to the method and the device, the optimal writing reliability and data stability can be provided for key application scenes, such as a solidified test program code, a storage equipment calibration parameter or a secure root key, which only need to write data at one time.

Description

Technical Field

[0001] This invention relates to the field of memory circuit design technology, and in particular to a writing method and writing circuit based on an RRAM chip. Background Technology

[0002] In current RRAM technology, the standard application process is as follows: the RRAM chip completes full address forming (i.e., full address initialization) during the mass production testing phase and is then delivered. After receiving the chip, the user directly writes and erases data based on the initialized chip through repeated set / reset operations.

[0003] However, with the increase in the number of set / reset operations, the resistive state of the device drifts, causing the read window, which characterizes data reliability, to continuously shrink and the false read rate to rise sharply. For critical application scenarios such as embedding test program code, storage device calibration parameters, or security root keys, where data only needs to be written once, the storage state is placed within a resistive window that is not at its maximum and will continue to degrade due to subsequent possible cyclic operations. Therefore, the data reliability, durability margin, and energy efficiency provided by current RRAM chips for one-time writes do not reach the optimal level. Summary of the Invention

[0004] To address the shortcomings of existing technologies, this invention provides a writing method and writing circuit based on RRAM chips, which solves the problem that the reliability of single-write data is limited by the standard initialization process and cannot be optimized in existing technologies.

[0005] According to an embodiment of the present invention, a first aspect provides a write method based on an RRAM chip, comprising:

[0006] When a write command to the target RRAM chip is received, the formation status flag of the target RRAM chip is read. If the formation status flag is not formed, it means that the target RRAM chip has not performed a one-time initialization operation; When the formation status flag is not formed, the initialization operation is performed on the target RRAM chip, and the target RRAM chip is set to the first logic state through the initialization operation to complete the write instruction.

[0007] Optionally, the formation status flag can be managed through a globally unified flag or a locally independent flag. When managing through the global unified flag bit, the full capacity of the target RRAM chip is used as the first management granularity; When managing with the local independent flag bit, at least one of the address block, byte, or storage unit of the target RRAM chip is used as the second management granularity.

[0008] Optionally, when the formation status flag is managed through the globally unified flag bit, the formation status flag is determined based on the first flag bit and the second flag bit; The first flag bit is used to indicate whether the target RRAM chip has been written with data through the initialization operation; the second flag bit is used to indicate whether all memory cells of the target RRAM chip have performed the initialization operation. The first flag bit indicates that the target RRAM chip has been written with data through the initialization operation, and the second flag bit indicates that all memory cells of the target RRAM chip have performed the initialization operation, and the formation status flag is formed; The first flag bit indicates that the target RRAM chip has been written with data through the initialization operation, and the second flag bit indicates that some memory cells of the target RRAM chip have not performed the initialization operation. The initialization operation is performed on all memory cells of the target RRAM chip so that the target RRAM chip completes full address initialization. The first flag indicates that the target RRAM chip has not been written with data through the initialization operation, and the formation status flag is not formed.

[0009] Optionally, when managing the formation status flag through the local independent flag bit, the second management granularity is used as the basic management unit; For a basic management unit, if the formation status flag of the basic management unit is not formed, then the initialization operation is performed on the basic unit, and the basic unit is set to the first logical state to complete the write instruction through the initialization operation.

[0010] Optionally, it also includes: When the formation status flag is not formed, the initialization operation is performed on the target RRAM chip, and then the write instruction is completed by performing a set / reset operation to set the target RRAM chip to the first logic state or the second logic state.

[0011] Optionally, it also includes: After the write instruction is completed, the formation status flag of the target RRAM chip is modified to "formed".

[0012] Optionally, if the formation status flag is formed, the write instruction is completed by performing a set / reset operation.

[0013] The second aspect provides a write circuit based on an RRAM chip, including a read circuit, an RRAM forming circuit, a status flag forming write circuit connected to the read circuit, and a set / reset write circuit. The RRAM forming circuit is used to perform an initialization operation on the target RRAM chip so that the read circuit reads a forming status flag indicating whether the target RRAM chip has undergone an initialization operation; The read circuit is configured to perform the RRAM chip-based write method as described above.

[0014] Optionally, it also includes a verification read circuit, which verifies the target RRAM chip after writing to it; The reading circuit may be the same as or different from the verification reading circuit.

[0015] Optionally, the same or different circuit configurations can be used to read the formation status flag of the target RRAM chip and to read the data status after the set / reset operation.

[0016] Compared to existing technologies, this invention offers the following advantages: it utilizes the physical resistance window between the "unformed" and "formed" states of the target RRAM chip to characterize data and thus achieve data writing. Specifically, if the formation state flag of the target RRAM chip is detected as "unformed," a one-time initialization operation permanently transforms the resistance state of the target RRAM chip from an initial ultra-high resistance state to a stable low resistance state. Simultaneously, the initialization of the target chip and data writing are achieved. This provides optimal write reliability and data stability for critical application scenarios requiring only one-time data writing, such as embedding test program code, storing device calibration parameters, or secure root keys. Attached Figure Description

[0017] Figure 1 This is a schematic diagram illustrating the implementation process of the write method based on an RRAM chip according to an embodiment of the present invention; Figure 2 This is a schematic diagram illustrating the implementation process of the write method based on an RRAM chip according to an embodiment of the present invention; Figure 3 For based on Figure 1 A flowchart illustrating the application logic; Figure 4 For based on Figure 2 A flowchart illustrating the application logic; Figure 5 For based on Figure 3 and Figure 4 A flowchart illustrating the comprehensive application logic; Figure 6This is a schematic diagram of the composition structure of the write circuit based on the RRAM chip in an embodiment of the present invention. Detailed Implementation

[0018] The technical solutions of the present invention will be further described below with reference to the accompanying drawings and embodiments.

[0019] like Figure 1 As shown, this embodiment of the invention proposes a write method based on an RRAM chip, including: S101. When a write instruction to the target RRAM chip is received, the formation status flag of the target RRAM chip is read. S102. When the formation state flag is not formed, the initialization operation is performed on the target RRAM chip, and the target RRAM chip is set to the first logic state through the initialization operation to complete the write instruction.

[0020] According to step S101 above, when the RRAM chip receives a write instruction from the host system or controller for a specific memory cell of the RRAM chip, the write method based on the RRAM chip shown in this embodiment of the invention is initiated. Furthermore, in step S101 above, the formation status flag is a binary state, including "formed" and "not formed," which are used to indicate whether the target RRAM chip has undergone a one-time initialization operation or not.

[0021] In step S102 above, the first logic state corresponds to the "formed" state of the target RRAM chip. Since the "unformed" state of the target RRAM chip usually corresponds to the initial resistance state of the target RRAM chip before initialization, i.e., the ultra-high resistance state, in this embodiment of the invention, the first logic state corresponds to the stable low resistance state of the target RRAM chip.

[0022] For example, the detailed implementation of step S102 above is as follows: apply a high voltage pulse to the target RRAM chip, which may be the specific memory cell mentioned above, so that this part is permanently transformed from the initial high resistance state to a stable low resistance state, that is, the first logic state mentioned above. This process is both an initialization operation and a data write operation.

[0023] Based on this, the RRAM chip-based write method proposed in this embodiment of the invention utilizes the physical resistance window between the "unformed" and "formed" states of the target RRAM chip to characterize data and thus achieve data writing. Specifically, as shown in step S102 above, if the formation state flag of the target RRAM chip is detected as "unformed," a one-time initialization operation is performed to permanently change the resistance state of the target RRAM chip from an initial ultra-high resistance state to a stable low resistance state. At the same time, the initialization of the target chip and data writing are realized. This provides optimal write reliability and data stability for key application scenarios such as embedding test program code, storage device calibration parameters, or security root keys, where data only needs to be written once.

[0024] To adapt to different application scenarios and design constraints, this embodiment of the invention provides two configurable formation status flag management modes for the formation status flags shown in the above steps, which manage the formation status flags through a globally unified flag bit or a locally independent flag bit.

[0025] In practical applications, when managing with the global unified flag bit, the full capacity of the target RRAM chip is used as the first management granularity, thereby directly identifying the initialization state of the entire RRAM chip, which is simple and has minimal overhead.

[0026] It should be noted that in the global unified management mode, that is, when the formation status flag is managed through the global unified flag bit, the formation status flag is determined according to the first flag bit and the second flag bit; wherein, the first flag bit is used to indicate whether the target RRAM chip has been written with data through the initialization operation; the second flag bit is used to indicate whether all memory cells of the target RRAM chip have performed the initialization operation.

[0027] Based on this, for example, determining the formation status flag according to the first flag bit and the second flag bit includes three cases: ① The first flag bit indicates that the target RRAM chip has been written with data through the initialization operation and the second flag bit indicates that all memory cells of the target RRAM chip have performed the initialization operation, and the formation status flag is formed; ② The first flag bit indicates that the target RRAM chip has been written with data through the initialization operation and the second flag bit indicates that some memory cells of the target RRAM chip have not performed the initialization operation, and the initialization operation is performed on all memory cells of the target RRAM chip so that the target RRAM chip completes full address initialization; ③ The first flag bit indicates that the target RRAM chip has not been written with data through the initialization operation, and the formation status flag is not formed.

[0028] In practical applications, write operations require prior initialization. Therefore, after data has been written through initialization, all addresses must be initialized before writing new data. For the second scenario mentioned above, all addresses still need to be initialized to avoid write failures or data errors.

[0029] In practical applications, when managing through the local independent flag bit, at least one of the address block, byte, or storage unit of the target RRAM chip is used as the second management granularity, wherein the hierarchical order of address block, byte, and storage unit is address block > byte > storage unit.

[0030] It should be noted that in the local independent management mode, that is, when the formation status flag is managed through the local independent flag bit, the second management granularity is used as the basic management unit; for a basic management unit, if the formation status flag of the basic management unit is not formed, the initialization operation is performed on the basic unit, and the basic unit is set to the first logical state to complete the write instruction through the initialization operation.

[0031] Based on this, for example, in the hierarchical order of address block > byte > storage unit, it can be seen that the management overhead of address block as the second management granularity is greater than that of byte as the second management granularity, and the management overhead of byte as the second management granularity is greater than that of storage unit as the second management granularity. Therefore, the embodiments of the present invention can perform fine-grained management and support more flexible on-demand initialization strategies, such as dynamically adjusting the second management granularity according to the error rate to dynamically balance reliability and efficiency; or, for example, implementing mixed granularity management within the same chip according to data importance, specifically, using byte as the second management granularity for critical data areas and address block as the second management granularity for ordinary data areas.

[0032] Considering the balance between management overhead and flexibility, a preferred implementation uses address blocks as the second level of management granularity. Using bytes and storage units as the second level of management granularity typically occurs in extreme, specialized applications where significant metadata overhead is acceptable. For example, in security chips with stringent requirements for combating physical attacks and side-channel analysis, storage unit-level granularity can be used to manage each key bit independently, achieving fully discretized physical isolation and access control. In architectures simulating in-memory computing or neuromorphic computing, byte or unit-level granularity can be used to precisely match the mapping and management needs of synaptic weight matrices. In redundant storage systems for ultra-high reliability aerospace or medical electronics, byte-level granularity can be used to minimize updates to critical parameters and isolate faults. In these scenarios, the performance, security, and reliability gains from fine-grained management far outweigh the increased metadata storage overhead.

[0033] In practical applications, compared to full-address initialization, the flexible on-demand initialization strategy only requires operation on a portion of the RRAM chip's memory cells, such as 1 / 256th. This reduces initialization power consumption and latency to approximately 1 / 256th, significantly lowering initial power consumption and time, which is crucial for battery-powered devices or systems requiring rapid startup. Furthermore, the local independent management mode strictly limits initialization operations to a certain range, physically isolating risks and preventing accidental damage to other stored critical data due to the initialization of only a portion of the memory cells.

[0034] Step S102 above is an optional step when the formation state flag is not formed, such as... Figure 2 As shown, in one embodiment, another optional step is also included, namely: S103. When the formation state flag is not formed, perform the initialization operation on the target RRAM chip, and then perform a set / reset operation to set the target RRAM chip to the first logic state or the second logic state to complete the write instruction.

[0035] In step S103 above, the set operation sets the target RRAM chip to the first logic state, and the reset operation sets the target RRAM chip to the second logic state. The first logic state is the same as that shown in step S102 above, which corresponds to the initial resistance state of the target RRAM chip before initialization, i.e., the ultra-high resistance state. Therefore, the second logic state corresponds to the stable low resistance state.

[0036] According to such Figure 2 The write method based on RRAM chips described in this embodiment of the invention is still applicable to general scenarios involving multiple reads and writes, and is compatible with the standard application process of current RRAM technology, that is, first initialize the full address, and then realize the writing and erasing of data through repeated set / reset operations.

[0037] for Figure 1 and Figure 2 The writing method based on RRAM chips shown in the present invention also illustrates a corresponding multiple write loop process.

[0038] based on Figure 1 Application logic such as Figure 3 As shown in the flowchart, after completing the write instruction through initialization when the formation status flag is not formed, the formation status flag of the target RRAM chip is modified to be formed. Therefore, when the next write instruction is received, based on the formation status flag being formed, the application logic shown in step S102 is no longer followed; instead, the write instruction is completed by performing a set / reset operation. Alternatively, if the formation status flag is formed, the write instruction is directly completed by performing a set / reset operation.

[0039] based on Figure 2 Application logic such as Figure 4 As shown in the flowchart, when the formation status flag is not formed, an initialization operation is performed first. Then, after completing the write instruction through a set / reset operation, the formation status flag of the target RRAM chip is modified to be formed. Therefore, when the next write instruction is received, based on the formation status flag being formed, the application logic shown in step S102 is no longer followed; instead, the write instruction is completed by executing a set / reset operation. Alternatively, if the formation status flag is formed, the write instruction is directly completed by executing a set / reset operation.

[0040] like Figure 5 As shown, it will be as follows Figure 3 The multiple write loop process shown and as follows Figure 4 The multiple write loop processes shown are merged to obtain a comprehensive, configurable multiple write loop master control process. This master control process can dynamically select to execute either the globally unified write path or the locally independently managed write path in the above embodiments, based on the configuration of system flag bits, thereby adapting to different application scenarios and reliability requirements within a unified framework.

[0041] based on Figure 5 This invention can be applied to general scenarios requiring multiple read / write operations based on actual needs. For critical application scenarios such as embedding test program code, storage device calibration parameters, or security root keys, where data only needs to be written once, the write instruction is completed in an initialization manner according to steps S101 and S102. This fully utilizes the native large read window between the "not formed" and "formed" states, providing critical data with storage reliability and anti-interference capabilities far exceeding those of traditional cyclic write paths. For chips that have already completed the one-time writing of critical data, the above-described procedure can also be followed. Figure 3 or Figure 5 The flowchart shown illustrates how a write command is completed by executing a set / reset operation, allowing it to be used in a general scenario requiring multiple reads and writes. For general scenarios requiring only multiple reads and writes, an initialization operation is performed first, as shown in steps S101 and S103, and then a write command is completed using a set / reset operation based on the initialized chip, following the aforementioned steps. Figure 4 or Figure 5 The flowchart shown illustrates that, in subsequent use, the write command is still completed by executing a set / reset operation.

[0042] It should be noted that, in this embodiment of the invention, it is also proposed to manage the formation state flag through a globally unified flag bit or a locally independent flag bit. When managing the formation state flag through the locally independent flag bit, the second management granularity is used as the basic management unit, thereby enabling mixed-granularity management within the same chip. Therefore, in practical applications, according to the above... Figure 3 or Figure 5 The flowchart shown illustrates that after the fixed startup code, security key, or device identifier is written to a specific area, the remaining storage space can be used as a regular non-volatile memory. Frequent data updates and erasures can be performed through standard set / reset operations, thereby achieving domain-based management and hybrid reuse of storage resources.

[0043] like Figure 6 As shown, this embodiment of the invention also provides a write circuit based on an RRAM chip, including a read circuit 61, an RRAM forming circuit 62, a forming status flag write circuit 63 connected to the read circuit 61, and a set / reset write circuit 64. The RRAM forming circuit is used to perform an initialization operation on the target RRAM chip, so that the read circuit reads a forming status flag indicating whether the target RRAM chip has undergone an initialization operation. The read circuit is configured to execute the RRAM chip-based write method as shown in the above embodiments.

[0044] In one embodiment, the formation status flag is a non-volatile storage medium, which may be OTP, Flash, RRAM itself, or other storage media, stored in a separate non-volatile memory, or stored in a designated storage area of ​​the RRAM circuit's own array.

[0045] In one embodiment, the write circuit based on the RRAM chip further includes a verification read circuit, which verifies the data written to the target RRAM chip after writing. It should be noted that the read circuit and the verification read circuit may be the same circuit or different circuits. When they are the same circuit, the read circuit performs the function of the verification read circuit, determining whether the currently read data is the data to be written. When they are different circuits, the read circuit independently determines whether an initialization operation has been performed on the target RRAM chip and / or whether the write instruction has been completed through the initialization operation.

[0046] In one embodiment, reading the formation status flag of the target RRAM chip and reading the data status after set / reset operations can employ two circuit configuration strategies: First, sharing the same set of sensitive amplifier circuits and reading parameters, which helps save chip area and simplify design; second, using different sensitive amplifier circuits or programmable reading parameters, which requires increasing corresponding circuit overhead, but allows for detection optimization for different states. For example, for suspected uninitialized memory cells, a higher reading voltage or a more sensitive current detection mode can be applied to clearly distinguish between ultra-high impedance states and conventional high impedance states, significantly improving the reliability, robustness, and anti-false positive capability of state identification.

[0047] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A write method based on an RRAM chip, characterized in that, include: When a write command to the target RRAM chip is received, the formation status flag of the target RRAM chip is read. If the formation status flag is not formed, it means that the target RRAM chip has not performed a one-time initialization operation; When the formation status flag is not formed, the initialization operation is performed on the target RRAM chip, and the target RRAM chip is set to the first logic state through the initialization operation to complete the write instruction.

2. The write method based on an RRAM chip as described in claim 1, characterized in that, The formation status flags are managed through globally unified flags or locally independent flags. When managing through the global unified flag bit, the full capacity of the target RRAM chip is used as the first management granularity; When managing with the local independent flag bit, at least one of the address block, byte, or storage unit of the target RRAM chip is used as the second management granularity.

3. The write method based on an RRAM chip as described in claim 2, characterized in that, When the formation status flag is managed through the globally unified flag bit, the formation status flag is determined based on the first flag bit and the second flag bit. The first flag bit is used to indicate whether the target RRAM chip has been written with data through the initialization operation; The second flag bit is used to indicate whether all memory cells of the target RRAM chip have performed the initialization operation; The first flag bit indicates that the target RRAM chip has been written with data through the initialization operation, and the second flag bit indicates that all memory cells of the target RRAM chip have performed the initialization operation, and the formation status flag is formed; The first flag bit indicates that the target RRAM chip has been written with data through the initialization operation, and the second flag bit indicates that some memory cells of the target RRAM chip have not performed the initialization operation. The initialization operation is performed on all memory cells of the target RRAM chip so that the target RRAM chip completes full address initialization. The first flag indicates that the target RRAM chip has not been written with data through the initialization operation, and the formation status flag is not formed.

4. The write method based on an RRAM chip as described in claim 2, characterized in that, When managing the formation status flag through the local independent flag bit, the second management granularity is used as the basic management unit; For a basic management unit, if the formation status flag of the basic management unit is not formed, then the initialization operation is performed on the basic unit, and the basic unit is set to the first logical state to complete the write instruction through the initialization operation.

5. The write method based on an RRAM chip as described in claim 1, characterized in that, Also includes: When the formation status flag is not formed, the initialization operation is performed on the target RRAM chip, and then the write instruction is completed by performing a set / reset operation to set the target RRAM chip to the first logic state or the second logic state.

6. The write method based on an RRAM chip as described in claim 1 or 5, characterized in that, Also includes: After the write instruction is completed, the formation status flag of the target RRAM chip is modified to "formed".

7. The write method based on an RRAM chip as described in claim 6, characterized in that, If the formation status flag is formed, the write instruction is completed by performing a set / reset operation.

8. A write circuit based on an RRAM chip, characterized in that, It includes a read circuit, an RRAM forming circuit, a status flag writing circuit connected to the read circuit, and a set / reset write circuit; The RRAM forming circuit is used to perform an initialization operation on the target RRAM chip so that the read circuit reads a forming status flag indicating whether the target RRAM chip has undergone an initialization operation; The read circuit is configured to perform the write method based on an RRAM chip as described in any one of claims 1 to 7.

9. The write circuit based on an RRAM chip as described in claim 8, characterized in that, It also includes a verification read circuit, which verifies the target RRAM chip after writing to it; The reading circuit may be the same as or different from the verification reading circuit.

10. The write circuit based on an RRAM chip as described in claim 8, characterized in that, The formation status flag of the target RRAM chip and the data status after the set / reset operation can be read using the same or different circuit configurations.

Images