Intelligent time control for switching between stages of device via single capacitor
By using a single current switch and capacitor to switch between different bias currents, the time control redundancy problem in the sys-en and SS stages of the prior art is solved, resulting in a smaller chip area and lower cost circuit design.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- TEXAS INSTRUMENTS INC
- Filing Date
- 2025-11-10
- Publication Date
- 2026-05-22
AI Technical Summary
Existing timing control circuitry systems require separate timing generation circuits in the sys-en and SS phases of the device, leading to increased chip size overhead and cost.
Using a single current switch and capacitor, the charging time of the capacitor is controlled by switching between different bias currents. The timing control circuitry of the sys-en and SS stages is integrated to reduce redundant logic circuitry.
It reduces chip area and cost, while achieving effective timing control of the sys-en and SS stages, simplifying circuit design.
Smart Images
Figure CN122073468A_ABST
Abstract
Description
Technical Field
[0001] This disclosure generally relates to electronic circuits. Background Technology
[0002] Timing control is critical for various phases of a device (e.g., a switching regulator). Specifically, after the regulator powers on (power-on phase), it enters the system-en phase, where there is a time delay of approximately one hundred microseconds as the device waits for its internal power supply to stabilize. Following the sys-en phase is the soft-start (SS) phase, which typically lasts for several milliseconds to provide a smooth output voltage (Vout). Due to these timing differences, time control for the sys-en and SS phases is traditionally handled by separate timing generation circuitry. For example, the delay in the sys-en phase might be generated by a digital counter comprising multiple D flip-flops, while the timing of the SS phase could be generated by charging a capacitor. Additionally, extra analog control circuitry is typically required to separate the sys-en and SS phases. These redundant circuitry systems often result in significant chip size overhead and waste. Summary of the Invention
[0003] In one example, a device includes a first current source configured to provide a first bias current and a second current source configured to provide a second bias current, wherein the first bias current is greater than the second bias current. The device further includes a current switch configured to receive the first bias current and the second bias current at its two input terminals and to provide an output current at an output terminal, wherein the output current is one of the first bias current and the second bias current selected by a current switch control signal to the current switch. The device further includes a capacitor coupled between the output terminal and a ground terminal, wherein the capacitor is charged by the output current and provides an output voltage at the output terminal.
[0004] In another example, a method includes providing a first bias current via a first current source and a second bias current via a second current source, wherein the first bias current is greater than the second bias current. The method further includes: receiving the first bias current and the second bias current at two input terminals of a current switch; and providing an output current at an output terminal of the current switch, wherein the output current is one of the first bias current and the second bias current selected by a current switch control signal to the current switch. The method further includes: charging a capacitor coupled between the output terminal and a ground terminal through the output current; and providing an output voltage at the output terminal. Attached Figure Description
[0005] Figure 1 This is a schematic diagram of a time control system used to switch between different stages of the device, as shown in the example.
[0006] Figure 2 This is an explanation from an example. Figure 1 A graph showing the waveforms of multiple signals switching between different stages.
[0007] Figure 3A It is a graph illustrating the waveforms of the output voltage SS_INT and the comparison output signal DONE during the hiccup protection phase; Figure 3B This is a schematic diagram of the time control circuit system used during hiccup current protection mode in the example.
[0008] Figure 4A It is a graph illustrating the waveforms related to clock jitter in the example, and Figure 4B This is a schematic diagram of a clock jitter circuit system. Detailed Implementation
[0009] Use the same reference numerals or other reference indicators in the figures to indicate the same or similar features (functionally and / or structurally).
[0010] Figure 1 This is a schematic diagram illustrating an example of a time control system 100 used for switching between different stages of the device. For example... Figure 1 As shown in the example, system 100 includes a first current source 102 configured to provide a first bias current I1 and a second current source 104 configured to provide a second bias current I2. In one example, the first bias current I1 is greater than the second bias current I2. System 100 further includes a current switch 106 configured to receive the first bias current I1 from the first current source 102 and the second bias current I2 from the second current source 104 at its two input terminals 103 and 105, respectively. Current switch 106 is configured to provide an output current at an output terminal 107, wherein the output current is one of a first bias current and a second bias current selected by a current switch control signal SYS_EN to current switch 106. The current switch control signal SYS_EN to current switch 106 switches between the first bias current I1 and the second bias current I2, wherein the first bias current I1 is larger and charges faster than the second bias current I2. System 100 further includes a single capacitor 108 coupled between output terminal 107 and ground terminal. During operation, capacitor 108 is charged by one of the output currents from current switch 106—a first bias current I1 and a second bias current I2—and capacitor 108 provides an output voltage SS_INT at output terminal 107.
[0011] Figure 1 The system 100 shown uses only a single capacitor 108 to generate different time / delay types, thus eliminating redundant time control logic (e.g., digital counters and other digital and / or analog circuitry) and the additional capacitors required for the clock. Therefore, system 100 reduces chip area and cost. By switching between different bias currents I1 and I2 via a single current switch 106, system 100 controls the charging time of the single capacitor 108 for different switching phases of the device, making it large (e.g., ms) with a small bias current I2 or small (e.g., μs) with a large bias current I1. Thus, the traditionally separate time control circuitry for the sys-en and SS phases of the device can be integrated into a single circuit system, as discussed in detail below.
[0012] In one example, system 100 further includes a discharge switch 112 coupled between output terminal 107 and ground terminal, wherein discharge switch 112 is controlled by a discharge / reset signal. When discharge switch 112 is turned off by a discharge signal, output voltage SS_INT is maintained at its current level. When discharge switch 112 is turned on by a discharge signal, output terminal 107 is connected to ground terminal and capacitor 108 is discharged, thereby resetting output voltage SS_INT to low or 0.
[0013] In one example, system 100 further includes a voltage comparator 108 configured to receive an output voltage SS_INT and a reference voltage Vref as its two inputs, and to provide a comparison output voltage / signal DONE at its comparison output terminal 115 based on a comparison between the output voltage SS_INT and the reference voltage Vref. In one example, when the output voltage SS_INT is less than the reference voltage Vref, the comparison output signal DONE remains low. When the output voltage SS_INT is equal to the reference voltage Vref, the comparison output signal DONE goes high.
[0014] In one example, system 100 further includes a reset (RS) latch 116 configured to receive a comparison output signal DONE and a current switch control signal SYS_EN as its two inputs S and R, respectively, and to generate a latch output signal SS_DONE within a specific time period. In one example, the reset (RS) latch 116 sets the latch output signal SS_DONE high based on the comparison output signal DONE and resets the latch output signal SS_DONE low based on the current switch control signal SYS_EN.
[0015] In one example, system 100 further includes a control logic unit 110 configured to receive a comparison output signal DONE and a latch output signal SS_DONE as its inputs, and to generate a current switching control signal SYS_EN to current switch 106 to switch between a first bias current I1 and a second bias current I2 as the output current from current switch 106. In this example, the current switching control signal SYS_EN generated by control logic unit 110 is an analog timing control signal that separates various different phases of the device, such as a power-on phase and a system enable phase. In one example, control logic unit 110 is configured to use a finite state machine to control the transitions between the various phases represented by the states of the finite state machine, and to avoid various fault reset conditions via the current switching control signal SYS_EN.
[0016] In one example, control logic unit 110 is configured to generate a discharge signal to turn discharge switch 112 on or off, thereby resetting or maintaining the output voltage SS_INT at output voltage terminal 107, respectively. In another example, a set of periodic pulses of the comparison output signal DONE is used as a reset signal to discharge capacitor 108. Control logic unit 110 is configured to count the number of periodic pulses of the comparison output signal DONE in the set to determine when to discharge capacitor 108.
[0017] Figure 2 This is an explanation Figure 1 A graph showing waveform examples of multiple signals switching between different stages. For example... Figure 2 As shown, the current switch control signal SYS_EN is initially low, which selects a large bias current I1 as the output current during the pre_SS (or sys-en) phase. As capacitor 108 is rapidly charged by the large bias current I1 during the pre_SS phase, the output voltage SS_INT rises rapidly and linearly until it reaches the reference voltage Vref. At this point, voltage comparator 108 sets the comparator output signal DONE high, causing control logic unit 110 to send a discharge signal to turn on discharge switch 112, thereby discharging capacitor 108. Once capacitor 108 has discharged, the output voltage SS_INT drops back low, which also lowers the comparator output signal DONE and generates a pulse in the comparator output signal DONE. One or more such pulses in the comparator output signal DONE (e.g., ...) Figure 2 After detecting and counting the two pulses shown in the image, the control logic unit 110 changes the current switch control signal SYS_EN high. (As shown in the image) Figure 2As demonstrated in the example, each fast charging cycle of capacitor 108 requires approximately 40 μs. Therefore, the current switching control signal SYS_EN provides a delay of approximately 80 μs for the system enable phase within two fast charging cycles.
[0018] When the current switch control signal SYS_EN goes high, the output current from the current switch 106 switches from a large bias current I1 to a small bias current I2, and the capacitor 108 enters a slow charging phase, such as the SS phase, during which the output voltage SS_INT rises slowly and linearly. Figure 2 As demonstrated in the example, the slow charging SS phase can last for approximately 4 ms until the output voltage SS_INT reaches the reference voltage Vref. At this point, instead of resetting the output voltage SS_INT, the control logic unit 110 can adjust the latch output signal SS_DONE based on the latch output signal SS_DONE. Figure 2 The output voltage SS_INT is held high for a specific time period during the SS_DONE phase. Here, the latch output signal SS_DONE is generated by the reset latch 116 based on the comparison output signal DONE and the current switch control signal SYS_EN.
[0019] In one instance, the output voltage SS_INT generated by system 100 can be used (e.g., multiplexed) to meet the timing requirements of additional stages and / or applications beyond the sys-en and SS stages discussed above. For a non-limiting instance, the output voltage SS_INT can also be used for timing control of hiccup protection and jitter stages / modes / characteristics following the SS_DONE stage. In the event of a hiccup mode causing a persistent short circuit or fault condition, the hiccup protection stage is activated to shut down the device within a hiccup time period (T_hiccup), such as 88 ms.
[0020] Figure 3A This is a graph illustrating examples of the waveforms of the output voltage SS_INT and the comparison output signal DONE during the hiccup protection phase. Figure 3B This is a schematic diagram of an illustrative example of a time control circuit system 300 used during hiccup current protection mode.
[0021] like Figure 3A As illustrated in the example, the hiccup protection phase may include multiple slow charging cycles, each containing a slow ramp-up of the output voltage SS_INT and a subsequent reset, as discussed above for the slow charging SS cycle. This generates a set of periodic pulses in the comparison output signal DONE. These periodic pulses in the comparison output signal DONE are then used as the clock input to the timing control circuitry system 300, which may include, for example, […]. Figure 3BThe illustrated digital counter consists of multiple D flip-flops 302 connected in series. In one example, the set of periodic pulses for the comparison output signal DONE is selected / multiplexed from multiple clock sources. In one example, the number of D flip-flops 302 in the timing control circuitry system 300 is flexibly determined by the desired hiccup time. For a non-limiting example, if each slow charge cycle is 4 ms, then 22 slow charge cycles and the corresponding number of D flip-flops 302 are required to achieve a hiccup time of 88 ms.
[0022] In the case of clock jitter, by inserting the triangular current source I1 into the oscillating current I osc From the oscillating current I osc Extracting the triangular current source I1 to generate the jitter current I dither The jitter current I dither A clock with frequency f triangular jitter within a specific frequency range (fmin, fmax) is used to generate a clock according to the following equation:
[0023]
[0024] Figure 4A It is a graph illustrating waveform examples related to clock jitter, and Figure 4B This is a schematic diagram illustrating a clock jitter circuit system 400. The output voltage SS_INT generated by system 100 is a ramp signal, but as... Figure 4A As shown, the slant signal can be further shaped by the system 100 into a triangular waveform signal linearly modulated between two threshold levels Vthh and Vthl by controlling the discharge current and charging current in a cycle-by-cycle manner. Figure 4B The voltage-to-current (V2I) conversion circuit 402 shown is used to convert the triangular waveform of SS_INT into a triangular current source I1, where the value of I1 is limited to a specific range, i.e., Imin (e.g., 0 A) < I1 < Imax (e.g., 37 nA). The triangular current source I1 is then fed into a current comparator 404, which compares I1 with a reference current Iref and generates a first clock switching signal vgate1. In one example, vgate1 is also used as an input to a D flip-flop 406 to generate a second clock switching signal vgate2, which is approximately half the frequency of vgate1, as shown below. Figure 4A As shown in the diagram. Clock switching signals vgate1 and vgate2 are then used to control a set of FETs, such as 408, 410, and 412, to insert I1 into the oscillation current I. osc From the oscillating current I osc Extracting I1 to generate the jitter current I dither The jitter current I ditherUsed to generate a jitter clock within the frequency range (fmin, fmax) as follows:
[0025] ●vgate1=1 and vgate2=0: Idither=Iosc+I1, and the clock frequency f increases to fmax;
[0026] ● vgate1=0 and vgate2=0, Idither=Iosc+I1, and the clock frequency f decreases to fref;
[0027] ●vgate1=1, and vgate2=1, Idither=Iosc-I1, and the clock frequency f decreases to fmin;
[0028] ● vgate1=0, vgate2=1, Idither=Iosc-I1, and the clock frequency f increases to fref;
[0029] Where fref is the reference frequency between fmin and fmax, such as Figure 4A It is displayed in the middle.
[0030] In this description, the term "coupling" may encompass a connection, communication, or signaling path that enables the functional relationship to be consistent with this description. For example, if device A generates a signal to control device B to perform an action, then: (a) in a first instance, device A is coupled to device B via a direct connection; or (b) in a second instance, device A is coupled to device B via an intermediate component C, provided that the intermediate component C does not alter the functional relationship between device A and device B, such that device B is controlled by device A via the control signal generated by device A.
[0031] Furthermore, in this specification, the term "based on" means "at least partially based on". Therefore, if X is based on Y, then X may depend on Y and any number of other factors.
[0032] A device “configured to” perform a task or function may be configured (e.g., programmed and / or hardwired) to perform the function during manufacturing by the manufacturer, and / or may be user-configurable (or reconfigurable) to perform the function and / or other additional or alternative functions after manufacturing. The configuration may be achieved through firmware and / or software programming of the device, through the construction and / or layout of hardware components and the interconnection of the device, or a combination thereof.
[0033] In this specification, unless otherwise stated, “about,” “approximately,” or “substantially” before a parameter means within + / -10% of the parameter, or, if the parameter is zero, within a reasonable range of values around zero.
[0034] Modifications to the described embodiments are possible within the scope of the claims, and other embodiments are also possible.
Claims
1. An apparatus comprising: A first current source, configured to provide a first bias current; A second current source configured to provide a second bias current, wherein the first bias current is greater than the second bias current; Current switch, which is configured to It receives the first bias current and the second bias current at its two input terminals; as well as An output current is provided at the output terminal, wherein the output current is one of a first bias current and a second bias current selected by a current switch control signal to the current switch; and A capacitor coupled between the output terminal and the ground terminal, wherein the capacitor is charged by the output current and provides an output voltage at the output terminal.
2. The device according to claim 1, further comprising: A discharge switch coupled between the output terminal and the ground terminal, wherein the discharge switch is controlled by a discharge signal.
3. The device according to claim 2, further comprising: Voltage comparator, which is configured to It receives the output voltage and the reference voltage as its two inputs; as well as A comparison output signal is provided based on the comparison between the output voltage and the reference voltage.
4. The device according to claim 3, further comprising: Reset latch, which is configured to The system receives the comparison output signal and the current switch control signal as its inputs. as well as Based on the comparison output signal and the current switch control signal, a latch output signal is generated for a specific time period.
5. The device according to claim 4, further comprising: Control logic unit, which is configured to It receives the comparison output signal and the latch output signal as its inputs; as well as A current switch control signal is generated to the current switch to select one of the first bias current and the second bias current as the output current from the current switch.
6. The device according to claim 5, wherein: The control logic unit is configured to generate the discharge signal to the discharge switch to reset or maintain the output voltage at the output terminal.
7. The device according to claim 5, wherein: The control logic unit is configured to control the output voltage for the system enable phase of the device by selecting the first bias current to charge the capacitor via the current switch control signal.
8. The device according to claim 5, wherein: The control logic unit is configured to control the output voltage for the soft-start phase of the device by selecting the second bias current to charge the capacitor via the current switch control signal.
9. The device according to claim 5, wherein: The control logic unit is configured to control the output voltage for the device's hiccup protection phase, wherein the output voltage is used to generate a clock signal within multiple slow charging cycles.
10. The device according to claim 5, wherein: The control logic unit is configured to control the output voltage for clock jitter, wherein the output voltage is used to generate a clock with frequency triangular jitter within a specific frequency range.
11. A method comprising: A first bias current is provided via a first current source; A second bias current is provided via a second current source, wherein the first bias current is greater than the second bias current; The first bias current and the second bias current are received at the two input terminals of the current switch; An output current is provided at the output terminal of the current switch, wherein the output current is one of a first bias current and a second bias current selected by a current switch control signal to the current switch; The output current charges the capacitor coupled between the output terminal and the ground terminal. as well as An output voltage is provided at the output terminal.
12. The method of claim 11, further comprising: The capacitor is discharged via a discharge switch coupled between the output terminal and the ground terminal, wherein the discharge switch is controlled by a discharge signal.
13. The method of claim 12, further comprising: The output voltage and the reference voltage are received as the two inputs of the voltage comparator; as well as A comparison output signal is provided based on the comparison between the output voltage and the reference voltage.
14. The method of claim 13, further comprising: The comparison output signal and the current switch control signal are received as inputs to the reset latch; as well as Based on the comparison output signal and the current switch control signal, a latch output signal is generated for a specific time period.
15. The method of claim 14, further comprising: The comparison output signal and the latch output signal are received as inputs to the control logic; as well as A current switch control signal is generated to the current switch to select one of the first bias current and the second bias current as the output current from the current switch.
16. The method of claim 15, further comprising: A discharge signal is generated to the discharge switch to reset or maintain the output voltage at the output terminal.
17. The method of claim 15, further comprising: The output voltage is controlled for the system startup phase of the device by selecting the first bias current to charge the capacitor via the current switch control signal.
18. The method of claim 15, further comprising: The output voltage is controlled for the soft-start phase of the device by selecting the second bias current to charge the capacitor via the current switch control signal.
19. The method of claim 15, further comprising: The output voltage is controlled for the hiccup phase of the device, wherein the output voltage is used to generate a clock signal within multiple slow charging cycles.
20. The method of claim 15, further comprising: The output voltage is used to control clock jitter, wherein the output voltage is used to generate triangular clock jitter with frequencies within a specific frequency range.