Method and device for calling interrupt communication system between para-virtualization processors
By configuring the semi-virtualized inter-processor interrupt features and interrupt call functions for the virtual processor, and directly updating the interrupt descriptor, the performance overhead caused by multiple context switches in the traditional virtualization architecture is solved, thus improving virtual machine performance.
Patent Information
- Application Number
- CN202512057646.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-31
- Publication Date
- 2026-05-26
AI Technical Summary
In traditional virtualization architectures, the implementation of inter-processor interrupts relies on software emulation by the virtual machine monitor, which results in multiple context switches for each interrupt operation, increasing performance overhead.
Configure the virtual processor with paravirtualized inter-processor interrupt features, set up interrupt call functions, directly update the interrupt descriptor of the target virtual processor, reduce the intervention of the virtual machine monitor, and handle interrupt requests directly through hardware.
This reduces the number of times the virtual machine rolls back from the guest state to the host state, thus improving virtual machine performance.
Smart Images
Figure CN122086520A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of computer virtualization technology, and in particular to a method, apparatus, electronic device, and readable storage medium for invoking a semi-virtualized inter-processor interrupt communication system. Background Technology
[0002] In computer technology, a virtual machine refers to a complete logical computer system that is simulated by software, has full hardware system functions, and runs in a completely isolated environment.
[0003] In traditional virtualization architectures, the implementation of inter-processor interrupts relies entirely on a software simulation layer provided by the virtual machine monitor. When it is necessary to notify or synchronize another virtual processor, it follows the same programming model as the physical machine and attempts to perform a write operation to the interrupt command register of the local high-level programmable interrupt controller corresponding to the target virtual CPU.
[0004] However, in a virtualized environment, the aforementioned local advanced programmable interrupt controller is typically simulated by the virtual machine monitor. The write operation triggers a virtual machine exit, causing the CPU to switch from guest mode back to host mode. Subsequently, the virtual machine monitor processes the interrupt request, determines how to deliver it to the target virtual machine, and then returns control to the target virtual CPU via the virtual machine. This mechanism results in multiple context switches accompanying each inter-processor interrupt, leading to increased performance overhead. Summary of the Invention
[0005] In view of the above problems, embodiments of the present invention are proposed to provide a method, apparatus, electronic device, and readable storage medium for invoking a semi-virtualized inter-processor interrupt communication system that overcomes or at least partially solves the above problems.
[0006] In a first aspect, embodiments of the present invention provide a method for invoking a semi-virtualized inter-processor interrupt communication system, the method comprising: Configure semi-virtualized inter-processor interrupt features for the virtual processor; Determine whether the virtual processor enables the inter-processor interrupt feature of the semi-virtualized processor; If the virtual processor enables the semi-virtualized inter-processor interrupt feature, then an interrupt call function is set for the virtual processor so that the interrupt call function is called when an interrupt request is sent; In response to the call to the interrupt call function, the interrupt descriptor corresponding to the target virtual processor is directly updated so that the target virtual processor can process the interrupt request.
[0007] Optionally, configuring the semi-virtualized inter-processor interrupt feature for the virtual processor includes: Configure the interrupt descriptor for the virtual processor; The virtual processor is marked as having configured paravirtualized inter-processor interrupt features, so that the virtual processor can enable the paravirtualized inter-processor interrupt features.
[0008] Optionally, configuring the interrupt descriptor for the virtual processor includes: Allocate a memory region for the virtual processor as an interrupt descriptor region; The address of the interrupt descriptor region is stored in the virtual machine control structure corresponding to the virtual processor, so that the interrupt descriptor can be directly updated when the interrupt call function is invoked.
[0009] Optionally, the interrupt descriptor includes an interrupt request bitmap field; The step of directly updating the interrupt descriptor corresponding to the target virtual processor in response to the interrupt call function includes: Write interrupt commands to the virtual advanced programmable interrupt controller; In response to the interrupt command, the address of the interrupt descriptor of the target virtual processor is obtained from the virtual machine control structure through the hardware interrupt delivery module, and the interrupt request bitmap field of the interrupt descriptor of the target virtual processor is directly updated.
[0010] Optionally, configuring the interrupt descriptor for the virtual processor includes: The interrupt descriptor is configured for the virtual processor through a global synchronization registration notification mechanism, which ensures that the interrupt descriptor is configured only once.
[0011] Optionally, configuring the interrupt descriptor for the virtual processor includes: The interrupt descriptor is configured for the virtual processor by invoking input / output control commands; The method further includes: The input / output control commands are added to the whitelist of the secure computing mode so that the hypervisor and the kernel-mode virtual machine monitor to which the virtual processor belongs can share the address of the interrupt descriptor.
[0012] Optionally, setting the interrupt call function for the virtual processor includes: During the startup phase of the client machine to which the virtual processor belongs, the function called when sending an interrupt request is switched to the interrupt call function; When the switching conditions are met, the function called when the interrupt request was sent will be switched back to the default calling function; the default calling function refers to the implementation method of completing the interrupt request transmission through software simulation. The switching conditions include any one of the following: the feature flag corresponding to the semi-virtualized inter-processor interrupt feature does not exist; the valid flag bit of the status register of the semi-virtualized inter-processor interrupt feature is not in a valid state; or the readback verification fails after the semi-virtualized inter-processor interrupt feature is enabled.
[0013] Secondly, embodiments of the present invention provide a semi-virtualized inter-processor interrupt communication device, the device comprising: The semi-virtualization interrupt feature configuration module is used to configure the inter-processor interrupt features for the virtual processor. The semi-virtualization interrupt feature determination module is used to determine whether the virtual processor enables the inter-semi-virtualization interrupt feature; An interrupt call function setting module is used to set an interrupt call function for the virtual processor if the virtual processor enables the inter-paravirtualized processor interrupt feature, so that the interrupt call function can be called when an interrupt request is sent; The interrupt descriptor update module is used to directly update the interrupt descriptor corresponding to the target virtual processor in response to the call of the interrupt call function, so that the target virtual processor can process the interrupt request.
[0014] Optionally, the semi-virtualization interrupt feature configuration module includes the following sub-modules: An interrupt descriptor configuration submodule is used to configure the interrupt descriptor for the virtual processor; The semi-virtualization interrupt feature flag submodule is used to flag the virtual processor as having configured semi-virtualization inter-processor interrupt features, so that the virtual processor can enable the semi-virtualization inter-processor interrupt features.
[0015] Optionally, the interrupt descriptor configuration submodule includes the following units: A memory region allocation unit is used to allocate a memory region as an interrupt descriptor region for the virtual processor. An interrupt descriptor storage unit is used to store the address of the interrupt descriptor region into the virtual machine control structure corresponding to the virtual processor, so that the interrupt descriptor can be directly updated when the interrupt call function is invoked.
[0016] Optionally, the interrupt descriptor includes an interrupt request bitmap field; The interrupt descriptor update module includes the following sub-modules: The interrupt command writing submodule is used to write interrupt commands to the virtual high-level programmable interrupt controller; The interrupt request bitmap field update submodule is used to respond to the interrupt command by obtaining the address of the interrupt descriptor of the target virtual processor from the virtual machine control structure through the hardware interrupt delivery module, and directly updating the interrupt request bitmap field of the interrupt descriptor of the target virtual processor.
[0017] Optionally, the interrupt descriptor configuration submodule includes the following units: The first interrupt descriptor configuration unit is used to configure the interrupt descriptor for the virtual processor through a global synchronization registration notification mechanism, wherein the global synchronization registration notification mechanism is used to ensure that the interrupt descriptor is configured only once.
[0018] Optionally, the interrupt descriptor configuration submodule includes the following units: The second interrupt descriptor configuration unit is used to configure the interrupt descriptor for the virtual processor by calling input / output control commands; The device also includes the following modules: The whitelist addition module is used to add the input / output control commands to the whitelist of the secure computing mode, so that the hypervisor and the kernel-mode virtual machine monitor to which the virtual processor belongs can share the address of the interrupt descriptor.
[0019] Optionally, the interrupt call function setting module includes the following sub-modules: The interrupt call function switching submodule is used to switch the function called when sending an interrupt request to the interrupt call function during the startup phase of the guest machine to which the virtual processor belongs; The default calling function switches back to the submodule, which is used to switch back to the default calling function when the interrupt request is sent when the switching conditions are met; the default calling function refers to the implementation method of completing the interrupt request transmission through software simulation; The switching conditions include any one of the following: the feature flag corresponding to the semi-virtualized inter-processor interrupt feature does not exist; the valid flag bit of the status register of the semi-virtualized inter-processor interrupt feature is not in a valid state; or the readback verification fails after the semi-virtualized inter-processor interrupt feature is enabled.
[0020] Thirdly, embodiments of the present invention provide an electronic device including a processor, a memory, and a program or instructions stored in the memory and executable on the processor, wherein when the program or instructions are executed by the processor, the steps of the invocation method of the semi-virtualized inter-processor interrupt communication system as described in the first aspect are implemented.
[0021] Fourthly, embodiments of the present invention provide a readable storage medium storing a program or instructions, which, when executed by a processor, implement the steps of the invocation method for a semi-virtualized inter-processor interrupt communication system as described in the first aspect.
[0022] The embodiments of the present invention have the following advantages: This invention configures a semi-virtualized inter-processor interrupt feature for a virtual processor. After determining that the semi-virtualized inter-processor interrupt feature is enabled, an interrupt call function is set. When an interrupt request is subsequently transmitted, the interrupt descriptor corresponding to the target virtual processor is directly updated in response to the call of the interrupt call function, so that the target virtual processor can process the interrupt request without the intervention of the virtual machine monitor. This reduces the number of times the virtual machine rolls back from the guest state to the host state and improves the performance of the virtual machine. Attached Figure Description
[0023] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0024] Figure 1 This is a flowchart illustrating the steps of a method for invoking a semi-virtualized inter-processor interrupt communication system according to an embodiment of the present invention. Figure 2 This is a flowchart illustrating a calling method for a semi-virtualized inter-processor interrupt communication system provided in an embodiment of the present invention; Figure 3 This is a structural block diagram of a semi-virtualized inter-processor interrupt communication device provided in an embodiment of the present invention. Detailed Implementation
[0025] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0026] The terms "first," "second," etc., used in the specification and claims of this invention are used to distinguish similar objects and are not used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention can be implemented in orders other than those illustrated or described herein. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.
[0027] In computer technology, a virtual machine (VM) refers to a complete logical computer system simulated by software, possessing full hardware system functionality, and running in a completely isolated environment. In traditional virtualization architectures, the implementation of inter-processor interrupts relies entirely on a software simulation layer provided by the virtual machine monitor. When it is necessary to notify or synchronize another virtual processor, it follows the same programming model as the physical machine, attempting to write to the interrupt command register of the local high-level programmable interrupt controller corresponding to the target virtual CPU.
[0028] However, in a virtualized environment, the registers perceived by the guest are actually a virtualized hardware interface presented by the virtual machine monitor through memory mapping technology. When the guest executes a memory write instruction to access the interrupt command register, the CPU will immediately generate a virtual machine exit event, forcing it to jump from the guest environment into the virtual machine monitor in the host kernel.
[0029] After the virtual machine monitor takes over control, it first needs to parse the reason and detailed parameters of this exit. This includes reading the data the guest machine attempted to write and decoding key information such as the interrupt vector and target processor identifier. Subsequently, the monitor must query its internally maintained virtual machine state data structure to map the abstract target processor identifier to a specific target virtual processor instance. After decoding and routing, the virtual machine monitor uses pure software instructions to simulate the hardware effects that this write operation should produce.
[0030] After all simulation operations are completed, the virtual machine monitor returns control to the guest machine by executing the "virtual machine enter" instruction. At this point, the CPU needs to perform a complete context restore, load the guest machine's processor state, and enable the guest machine to continue execution from where it left off after the exit instruction was triggered.
[0031] Therefore, a single inter-processor interrupt in a traditional architecture is essentially a hardware instruction that is completely intercepted and transformed into a software-simulated process. The aforementioned write operation triggers a virtual machine exit, causing the CPU to switch from guest mode back to host mode. Subsequently, the virtual machine monitor processes the interrupt request, determines how to deliver it to the target virtual machine, and after processing, returns control to the target virtual CPU via the virtual machine. This mechanism results in multiple context switches accompanying each inter-processor interrupt, leading to increased performance overhead.
[0032] One of the core concepts of this invention is to configure semi-virtualized inter-processor interrupt features for the virtual processor, and after determining that the semi-virtualized inter-processor interrupt features are enabled, to set an interrupt call function for the virtual processor. In response to the call of the interrupt call function, the interrupt descriptor corresponding to the virtual processor can be directly updated, so that the virtual processor can process the interrupt request, thereby reducing the system overhead caused by context switching.
[0033] Figure 1 This is a flowchart of the steps of a calling method for a semi-virtualized inter-processor interrupt communication system provided in an embodiment of the present invention.
[0034] like Figure 1 As shown, the method may specifically include the following steps: Step 101: Configure the semi-virtualized inter-processor interrupt feature for the virtual processor; In real-world applications, a single physical server, or host machine, can run multiple virtual machines (VMs). Each VM contains one or more virtual processors (vCPUs), which share the computing resources of the physical CPU. To enable efficient collaboration among the multiple vCPUs within a VM, inter-processor interrupt (IPI) communication is required. Traditional virtual IPI implementations rely on software emulation by the Virtual Machine Monitor (VMM), resulting in significant context switching overhead for each communication.
[0035] In this embodiment of the invention, the semi-virtualized inter-processor interrupt communication system consists of three core components that work together to create and manage the virtual processor, including: The user-space hypervisor is a monitoring software (ctc-hypervisor) developed based on Rust. It is a device simulator and management program in the host user space, responsible for the lifecycle management of virtual machines and the software simulation of I / O devices.
[0036] The kernel-mode virtual machine monitor is a monitoring software (PhantomVirt) developed based on Rust. It is a virtualization module in the host kernel used to utilize the hardware virtualization extensions of the CPU (such as Intel VT-x) to be responsible for the virtualization scheduling of physical CPU and memory resources. It can write the configuration information provided by the hypervisor into the hardware-related control structures and set the corresponding enable flags.
[0037] The guest kernel, or operating system kernel inside the virtual machine, is used to detect whether the host machine provides semi-virtualized inter-processor interrupt features at startup and dynamically adjust the functions called when passing interrupt requests internally, so as to reduce context switching by utilizing IPI features.
[0038] It is worth noting that, considering the limitations of C language in concurrency and memory safety, which may lead to unpredictable behavior in complex virtualization environments, this embodiment of the invention is based on the Rust language. The user-mode hypervisor and kernel-mode virtual machine monitor are respectively implemented in Rust as ctc-hypervisor and PhantomVirt. It is understood that Rust's memory safety, type safety, and concurrency control features can improve the stability and reliability of both kernel and user-mode code.
[0039] In real-world applications, after issuing a command to start a specific virtual machine, the ctc-hypervisor process is launched. During initialization, ctc-hypervisor checks whether the command-line parameters specify enabling Paravirtualization-Inter-Processor Interrupt (PV-IPI). If PV-IPI is enabled in the command line, it configures PV-IPI for the virtual processor.
[0040] In some embodiments, step 101 specifically includes the following sub-steps: Sub-step S11: Configure the interrupt descriptor for the virtual processor; In some embodiments, sub-step S11 includes the following refined steps: Allocate a memory region for the virtual processor as an interrupt descriptor region; The address of the interrupt descriptor region is stored in the virtual machine control structure (VMCS) corresponding to the virtual processor, so that the interrupt descriptor can be directly updated when the interrupt call function is invoked.
[0041] In practical applications, the ctc-hypervisor allocates a dedicated physical memory region for each virtual processor as a Posted-Interrupt Descriptor (PI Desc) region, and determines the guest physical address of the PI Descriptor and the number of pages it occupies.
[0042] In some embodiments, sub-step S11 includes the following refined steps: The interrupt descriptor is configured for the virtual processor by invoking input / output control commands.
[0043] In some embodiments, the method further includes: The input / output control commands are added to the whitelist of the secure computing mode so that the hypervisor and the kernel-mode virtual machine monitor to which the virtual processor belongs can share the address of the interrupt descriptor.
[0044] The ctc-hypervisor passes the client physical address of the PI Desc to the PhantomVirt by calling the input / output control command ioctl(PhantomVirt_SET_PVIPI_ADDR), which causes the PhantomVirt to record the PI Desc address and set the PI Desc to the valid flag indicating that it is ready.
[0045] To ensure the secure execution of the address passing operation, the input / output control command (PhantomVirt_SET_PVIPI_ADDR) can be pre-added to the whitelist of the host machine's secure computing model, i.e., the trusted list. This strategy ensures that only authorized and legitimate ctc-hypervisors can initiate this operation, thereby preventing malicious or unauthorized programs from tampering with interrupt configuration data, enhancing the overall security of the system, and enabling the virtual machine hypervisor (ctc-hypervisor) belonging to the virtual processor and the kernel-mode virtual machine monitor (PhantomVirt) to securely share the address of the interrupt descriptor.
[0046] In some embodiments, the timing of the input / output control command ioctl is restricted to before the virtual processor is created, and PhantomVirt performs a validity check on the PI Desc address after receiving the ioctl. The validity check includes at least address alignment verification and address accessibility verification, and the valid flag is set upon successful verification.
[0047] Sub-step S12: The virtual processor is marked as having configured semi-virtualized inter-processor interrupt features, so that the virtual processor can enable the semi-virtualized inter-processor interrupt features.
[0048] In practical applications, after receiving the PI Desc address, PhantomVirt writes it into a specific field of the virtual machine control structure corresponding to this virtual processor, such as the Posted-Interrupt Descriptor Address field. Simultaneously, PhantomVirt internally sets the PV-IPI feature status flags of this virtual processor, such as the valid flag, to be active, indicating that the hardware channel has been successfully configured for this virtual processor. This process serves as a clear signal to the virtual processor that PV-IPI can be enabled subsequently.
[0049] In some embodiments, the interrupt descriptor is configured for the virtual processor through a global synchronization registration notification mechanism, which ensures that the interrupt descriptor is configured only once.
[0050] To prevent duplicate configurations, a global synchronization registration notification mechanism can be used to configure the interrupt descriptor for the virtual processor. This mechanism ensures that the configuration process of the interrupt descriptor for any virtual processor is executed only once throughout the entire virtual machine's lifetime. Specifically, the ONCE synchronization primitive can be used to ensure that the aforementioned input / output control command calls are executed only once, thereby avoiding duplicate executions and potential errors.
[0051] The ONCE synchronization primitive is a thread-safe initialization tool provided in the Rust standard library that ensures that global variables or operations are initialized only once. By using synchronization primitives in the Rust standard library, it is ensured that the aforementioned input / output control commands are executed only once, avoiding resource contention and initialization errors, and enhancing system stability.
[0052] Step 102: Determine whether the virtual processor enables the inter-processor interrupt feature of the semi-virtualized processor; In practical application scenarios, during the startup phase of the guest kernel to which the virtual processor belongs, the guest kernel detects whether the host machine supports the PV-IPI feature and reads the model-specific register MSR_PhantomVirt_PV_IPI to determine whether the valid flag is valid, that is, to determine whether the host machine has declared support for the PV-IPI feature at the software level.
[0053] The fields of the MSR_PhantomVirt_PV_IPI mentioned therein include at least: Bit 0: Valid flag for PI Desc, indicating that PhantomVirt is ready and has recorded the PI Desc address; Bit 1: Enable flag for PV-IPI, used by the client to request PV-IPI and by the client to read back to determine whether PhantomVirt has completed the enable configuration; Bits 8-11: Page count of PI Desc; Bits 12-63: Client physical base address of PI Desc (addr).
[0054] When valid is confirmed, the guest kernel writes the enable flag to MSR_PhantomVirt_PV_IPI to request the PV-IPI feature to be enabled, and performs a readback verification to confirm the enabling result.
[0055] When the startup is successful, it will trigger the virtualization control related to the virtual APIC and Posted Interrupt in PhantomVirt configuration, so that the guest's access to the interrupt command register (ICR register) in x2APIC mode for the virtual processor will no longer be intercepted, thereby avoiding the virtual machine exiting VM-exit during subsequent IPI transmission.
[0056] Step 103: If the virtual processor enables the semi-virtualized inter-processor interrupt feature, then set an interrupt call function for the virtual processor so that the interrupt call function can be called when an interrupt request is sent; In some embodiments, step 103 specifically includes the following sub-steps: Sub-step S21: During the startup phase of the client machine to which the virtual processor belongs, the function called when sending the interrupt request is switched to the interrupt call function; In practical applications, after enabling PV-IPI during the guest kernel's boot phase, the kernel switches the function called when sending an interrupt request to the interrupt call function. Specifically, the entry function for sending IPI and the ICR read / write function can be switched to a PV-IPI sending function group. This PV-IPI sending function group triggers the hardware Posted Interrupt mechanism by writing to the ICR, causing the hardware to directly update the PI Desc corresponding to the target virtual processor to complete the interrupt request delivery.
[0057] In some embodiments, the PV-IPI sending function group, in addition to updating the entry function for sending IPI, also includes switching the ICR read and write functions (icr_read and icr_write) to ensure that after PV-IPI is enabled, the ICR access performed by the client conforms to the configuration of "do not intercept x2APIC ICR", so that the IPI sending path does not generate VM-exit during runtime.
[0058] Sub-step S22: When the switching condition is met, the function called when sending the interrupt request is switched back to the default calling function; the default calling function refers to the implementation method of completing the interrupt request transmission through software simulation. It is understood that, in order to ensure the reliability of the system in abnormal or unavailable scenarios, this embodiment of the invention sets up a safe rollback mechanism. Specifically, if the guest kernel meets the switching conditions during the startup phase, it switches back to the default function call implementation.
[0059] In some embodiments, the switching conditions include any one of the following: the feature flag corresponding to the semi-virtualized inter-processor interrupt feature does not exist, the valid flag bit of the status register of the semi-virtualized inter-processor interrupt feature is not in a valid state, or the readback verification fails after the semi-virtualized inter-processor interrupt feature is enabled.
[0060] Specifically, the switching condition is: the host machine has not declared support for the PV-IPI feature, that is, the corresponding PhantomVirt_FEATURE_PV_IPI flag does not exist in the virtualization feature bitmap; Although the host machine declares support for PV-IPI features, when it comes to the specific virtual processor reading the MSR_PhantomVirt_PV_IPI register, its valid flag is not valid; The guest kernel attempted to enable the PV-IPI feature, but after writing the enable flag, the read-back verification failed, confirming that the enabling operation had failed. When any of the above conditions are met, the guest kernel switches back to the default function called when sending the interrupt request. This default function follows a traditional, software-simulated path to deliver the interrupt request. Its write operations to the virtual interrupt command register are intercepted by the virtualization hardware, inevitably causing a virtual machine exit. Subsequently, the host monitor takes over, simulating the interrupt delivery process through complex software routines. Although this path incurs significant performance overhead, it serves as a safety fallback mechanism, ensuring system reliability.
[0061] Step 104: In response to the call to the interrupt call function, directly update the interrupt descriptor corresponding to the target virtual processor so that the target virtual processor can process the interrupt request.
[0062] When one virtual processor needs to interrupt another virtual processor, the interrupt call function set in step S103 will be called. The execution of this function will trigger a series of hardware-driven operations to directly update the interrupt descriptor.
[0063] In some embodiments, the interrupt descriptor includes an interrupt request bitmap field.
[0064] In some embodiments, step 104 specifically includes the following sub-steps: Sub-step S31: Write an interrupt command to the virtual high-level programmable interrupt controller; In sub-step S32, in response to the interrupt command, the address of the interrupt descriptor of the target virtual processor is obtained from the virtual machine control structure through the hardware interrupt delivery module, and the interrupt request bitmap field of the interrupt descriptor of the target virtual processor is directly updated.
[0065] In real-world applications where the sending virtual processor needs to send an interrupt request to the target virtual processor, an interrupt command is first written to the interrupt command register of the sending virtual processor's virtual advanced programmable interrupt controller (vAPIc). This interrupt command includes key information such as the target virtual processor's identifier and interrupt vector number. Because the host machine has removed the interception, this write operation is recognized at the hardware level as a special "Posted-Interrupt triggered command" and will not cause a traditional virtual machine exit.
[0066] After the CPU hardware detects the aforementioned special write, the hardware interrupt delivery module, namely the VT-x postedinterrupt hardware mechanism, obtains the address of the interrupt descriptor of the target virtual processor from the Virtual Machine Control Structure (VMCS) based on the interrupt command, and directly updates the interrupt request bitmap field pir of the target virtual processor's interrupt descriptor. Specifically, the posted interrupt hardware mechanism represents the IPI request delivered to the target virtual processor by setting the bit in pir corresponding to the interrupt vector.
[0067] In some embodiments, the interrupt descriptor includes a notification vector field.
[0068] In some embodiments, the method further includes: Inspect the notification vector field of the interrupt descriptor; If the value of the notification vector field is valid, a notification event is sent to the virtual processor; the notification event is used to notify the virtual processor to process the interrupt request.
[0069] The interrupt descriptor also includes a notification vector field nv and a notification destination field ndst. After the bitmap update is completed, the posted interrupt hardware mechanism will automatically check the notification vector field nv in the interrupt descriptor. When nv is a valid value, a notification event is triggered based on the nv and ndst to prompt the processor core carrying the target virtual processor to synchronize the pir and inject the IPI as a virtual interrupt into the target virtual processor.
[0070] This invention configures a semi-virtualized inter-processor interrupt feature for a virtual processor. After determining that the semi-virtualized inter-processor interrupt feature is enabled, an interrupt call function is set. When an interrupt request is subsequently transmitted, the interrupt descriptor corresponding to the target virtual processor is directly updated in response to the call of the interrupt call function, so that the target virtual processor can process the interrupt request without the intervention of the virtual machine monitor. This reduces the number of times the virtual machine rolls back from the guest state to the host state and improves the performance of the virtual machine.
[0071] It should be noted that, for the sake of simplicity, the method embodiments are all described as a series of actions. However, those skilled in the art should understand that the embodiments of the present invention are not limited to the described order of actions, because according to the embodiments of the present invention, some steps can be performed in other orders or simultaneously. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are preferred embodiments, and the actions involved are not necessarily essential to the embodiments of the present invention.
[0072] Figure 2 This is an application flowchart of a calling method for a semi-virtualized inter-processor interrupt communication system provided in an embodiment of the present invention.
[0073] To enable those skilled in the art to better understand the embodiments of the present invention, see below. Figure 2 An example will be used to illustrate an embodiment of the present invention: 1) The cloud management platform issues a command to start the virtual machine, and the ctc-hypervisor process is launched. The cloud management platform issues a command to the specified physical server, i.e., the host machine, to create and start a virtual machine based on the needs of the user or upper-layer application. After receiving the command, the host machine starts the ctc-hypervisor process.
[0074] 2) If PV-IPI is enabled in the ctc-hypervisor command-line parameters, then ctc-hypervisor will send the PIDesc address to PhantomVirt. The ctc-hypervisor checks whether PV-IPI is enabled in the command-line parameters. If it is confirmed that PV-IPI is enabled in the command line, it allocates a block of physical memory for each virtual processor of the virtual machine as its dedicated interrupt descriptor PIDesc, and determines the guest physical address of PI Desc and the number of pages it occupies.
[0075] Subsequently, ctc-hypervisor invokes specific input / output control commands to pass the client physical address of each PI Desc to PhantomVirt.
[0076] 3) PhantomVirt saves the PI Desc address and sets PV-IPI valid for the virtual machine. PhantomVirt records the received PI Desc address in the internal data structure of the corresponding vCPU and writes this address into a specific field of the virtual machine control structure corresponding to that vCPU to complete the hardware configuration. Simultaneously, PhantomVirt sets the PV-IPI feature flag (valid flag) of the virtual machine to be valid.
[0077] 4) ctc-hypervisor starts running the virtual machine After completing the configurations in steps 1) to 3) above, ctc-hypervisor continues to execute the normal startup process of the virtual machine and starts running the virtual machine.
[0078] 5) The guest kernel checks if PV-IPI is available. After the virtual machine starts running, the Guest kernel checks whether PV-IPI is available during the startup phase. Specifically, it reads the model-specific register MSR_PhantomVirt_PV_IPI to determine whether the valid flag is valid, that is, to check whether the host machine has declared support for the PV-IPI feature at the software level.
[0079] Once the validity is confirmed, the Guest kernel writes the enable flag to MSR_PhantomVirt_PV_IPI to request the PV-IPI feature to be enabled, and performs a read-back verification to confirm the enabling result. When the enabling result is successful, it triggers the virtualization control related to PhantomVirt configuring the virtual APIC and Posted Interrupt, so that the guest's access to the interrupt command register (ICR register) in x2APIC mode for the virtual processor is no longer intercepted, thereby avoiding virtual machine exit during subsequent IPI transmission.
[0080] 6) If PV-IPI is available, set the interrupt call function. After enabling PV-IPI during the guest kernel's boot phase, the kernel switches the function called when sending an interrupt request to the interrupt call function. Specifically, the entry function for sending IPI and the ICR read / write function can be switched to a PV-IPI sending function group. This PV-IPI sending function group triggers the hardware Posted Interrupt mechanism by writing to the ICR, causing the hardware to directly update the PI Desc corresponding to the target virtual processor to complete the interrupt request delivery.
[0081] In some embodiments, the PV-IPI sending function group, in addition to updating the entry function for sending IPI, also includes switching the ICR read and write functions (icr_read and icr_write) to ensure that after PV-IPI is enabled, the ICR access performed by the client conforms to the configuration of "do not intercept x2APIC ICR (MSR 0x830)", so that the IPI sending path does not generate VM-exit during runtime.
[0082] In addition, if PV-IPI is unavailable, the kernel will continue to use the original default function call that would cause the virtual machine to exit, ensuring system reliability and safe rollback.
[0083] It should be noted that the invocation method for the semi-virtualized inter-processor interrupt communication system provided in this embodiment of the invention can be executed by an invocation device for the semi-virtualized inter-processor interrupt communication system, or by a control module within that invocation device for executing the invocation method for loading the semi-virtualized inter-processor interrupt communication system. This embodiment of the invention uses the execution of the invocation method for loading the semi-virtualized inter-processor interrupt communication system by an invocation device for the semi-virtualized inter-processor interrupt communication system as an example to illustrate the invocation method for the semi-virtualized inter-processor interrupt communication system provided in this embodiment of the invention.
[0084] Figure 3 This is a structural block diagram of a calling device for a semi-virtualized inter-processor interrupt communication system provided in an embodiment of the present invention.
[0085] like Figure 3 As shown in the figure, the invocation device for a semi-virtualized inter-processor interrupt communication system provided in this embodiment of the invention may specifically include the following modules: The semi-virtualization interrupt feature configuration module 301 is used to configure the semi-virtualized inter-processor interrupt features for the virtual processor; The semi-virtualization interrupt feature determination module 302 is used to determine whether the virtual processor enables the inter-semi-virtualization interrupt feature; Interrupt call function setting module 303 is used to set an interrupt call function for the virtual processor if the virtual processor enables the inter-paravirtualized processor interrupt feature, so as to call the interrupt call function when an interrupt request is sent; The interrupt descriptor update module 304 is used to directly update the interrupt descriptor corresponding to the target virtual processor in response to the call of the interrupt call function, so that the target virtual processor can process the interrupt request.
[0086] In some embodiments, the semi-virtualization interrupt feature configuration module includes the following sub-modules: An interrupt descriptor configuration submodule is used to configure the interrupt descriptor for the virtual processor; The semi-virtualization interrupt feature flag submodule is used to flag the virtual processor as having configured semi-virtualization inter-processor interrupt features, so that the virtual processor can enable the semi-virtualization inter-processor interrupt features.
[0087] In some embodiments, the interrupt descriptor configuration submodule includes the following units: A memory region allocation unit is used to allocate a memory region as an interrupt descriptor region for the virtual processor. An interrupt descriptor storage unit is used to store the address of the interrupt descriptor region into the virtual machine control structure corresponding to the virtual processor, so that the interrupt descriptor can be directly updated when the interrupt call function is invoked.
[0088] In some embodiments, the interrupt descriptor includes an interrupt request bitmap field; The interrupt descriptor update module includes the following sub-modules: The interrupt command writing submodule is used to write interrupt commands to the virtual high-level programmable interrupt controller; The interrupt request bitmap field update submodule is used to respond to the interrupt command by obtaining the address of the interrupt descriptor of the target virtual processor from the virtual machine control structure through the hardware interrupt delivery module, and directly updating the interrupt request bitmap field of the interrupt descriptor of the target virtual processor.
[0089] In some embodiments, the interrupt descriptor configuration submodule includes the following units: The first interrupt descriptor configuration unit is used to configure the interrupt descriptor for the virtual processor through a global synchronization registration notification mechanism, wherein the global synchronization registration notification mechanism is used to ensure that the interrupt descriptor is configured only once.
[0090] In some embodiments, the interrupt descriptor configuration submodule includes the following units: The second interrupt descriptor configuration unit is used to configure the interrupt descriptor for the virtual processor by calling input / output control commands; The device also includes the following modules: The whitelist addition module is used to add the input / output control commands to the whitelist of the secure computing mode, so that the hypervisor and the kernel-mode virtual machine monitor to which the virtual processor belongs can share the address of the interrupt descriptor.
[0091] In some embodiments, the interrupt call function setting module includes the following sub-modules: The interrupt call function switching submodule is used to switch the function called when sending an interrupt request to the interrupt call function during the startup phase of the guest machine to which the virtual processor belongs; The default calling function switches back to the submodule, which is used to switch back to the default calling function when the interrupt request is sent when the switching conditions are met; the default calling function refers to the implementation method of completing the interrupt request transmission through software simulation; The switching conditions include any one of the following: the feature flag corresponding to the semi-virtualized inter-processor interrupt feature does not exist; the valid flag bit of the status register of the semi-virtualized inter-processor interrupt feature is not in a valid state; or the readback verification fails after the semi-virtualized inter-processor interrupt feature is enabled.
[0092] This invention configures a semi-virtualized inter-processor interrupt feature for a virtual processor. After determining that the semi-virtualized inter-processor interrupt feature is enabled, an interrupt call function is set. When an interrupt request is subsequently transmitted, the interrupt descriptor corresponding to the target virtual processor is directly updated in response to the call of the interrupt call function, so that the target virtual processor can process the interrupt request without the intervention of the virtual machine monitor. This reduces the number of times the virtual machine rolls back from the guest state to the host state and improves the performance of the virtual machine.
[0093] As the apparatus embodiment is basically similar to the method embodiment, it is described in a relatively simple manner. For relevant details, please refer to the description of the method embodiment.
[0094] This invention also provides an electronic device, including a processor, a memory, and a program or instructions stored in the memory and executable on the processor. When the program or instructions are executed by the processor, they implement the various processes of the above-described embodiment of the calling method for the semi-virtualized inter-processor interrupt communication system and achieve the same technical effect. To avoid repetition, they will not be described again here.
[0095] It should be noted that the electronic devices in the embodiments of the present invention include the mobile electronic devices and non-mobile electronic devices described above.
[0096] This invention also provides a readable storage medium storing a program or instructions. When the program or instructions are executed by a processor, they implement the various processes of the above-described embodiment of the calling method for the semi-virtualized inter-processor interrupt communication system and achieve the same technical effect. To avoid repetition, they will not be described again here.
[0097] The processor is the processor in the electronic device described in the above embodiments. The readable storage medium includes computer-readable storage media, such as computer read-only memory (ROM), random access memory (RAM), magnetic disk, or optical disk.
[0098] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.
[0099] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, apparatus, or computer program products. Therefore, embodiments of the present invention can take the form of entirely hardware embodiments, entirely software embodiments, or embodiments combining software and hardware aspects. Furthermore, embodiments of the present invention can take the form of computer program products implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.
[0100] Embodiments of the present invention are described with reference to flowchart illustrations and / or block diagrams of methods, terminal devices (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, as well as combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing terminal device to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal device, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.
[0101] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing terminal device to operate in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1The function specified in one or more boxes.
[0102] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal equipment, causing a series of operational steps to be performed on the computer or other programmable terminal equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable terminal equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.
[0103] Although preferred embodiments of the present invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the embodiments of the present invention.
[0104] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or terminal device. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or terminal device that includes said element.
[0105] The foregoing has provided a detailed description of the calling method, apparatus, electronic device, and readable storage medium of a semi-virtualized inter-processor interrupt communication system provided by the present invention. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.
Claims
1. A method for invoking a semi-virtualized inter-processor interrupt communication system, characterized in that, The method comprises: configuring a virtual processor with a semi-virtualized inter-processor interrupt feature; determining whether the virtual processor enables the semi-virtualized inter-processor interrupt feature; if the virtual processor enables the semi-virtualized inter-processor interrupt feature, setting an interrupt call function for the virtual processor to call the interrupt call function when sending an interrupt request; in response to the call of the interrupt call function, directly updating an interrupt descriptor corresponding to a target virtual processor to make the target virtual processor process the interrupt request.
2. The invocation method of claim 1, wherein, The configuration of the virtual processor with the semi-virtualized inter-processor interrupt feature comprises: configuring the virtual processor with the interrupt descriptor; flagging the virtual processor as having been configured with the semi-virtualized inter-processor interrupt feature to enable the virtual processor to enable the semi-virtualized inter-processor interrupt feature.
3. The invocation method of claim 2, wherein, The configuration of the virtual processor with the interrupt descriptor comprises: allocating a memory region for the virtual processor as an interrupt descriptor region; storing the address of the interrupt descriptor region into a virtual machine control structure corresponding to the virtual processor to enable the interrupt call function to directly update the interrupt descriptor when called.
4. The invocation method of claim 2, wherein, The interrupt descriptor comprises an interrupt request bitmap field. The direct updating of the interrupt descriptor corresponding to the target virtual processor in response to the call of the interrupt call function comprises: writing an interrupt command to a virtual advanced programmable interrupt controller; in response to the interrupt command, obtaining the address of the interrupt descriptor of the target virtual processor from the virtual machine control structure through a hardware interrupt delivery module, and directly updating the interrupt request bitmap field of the interrupt descriptor of the target virtual processor.
5. The invocation method of claim 2, wherein, The configuration of the virtual processor with the interrupt descriptor comprises: configuring the virtual processor with the interrupt descriptor through a global synchronization registration notification mechanism, which is used to ensure that the interrupt descriptor is configured only once.
6. The invocation method of claim 2, wherein, The configuration of the virtual processor with the interrupt descriptor comprises: configuring the virtual processor with the interrupt descriptor by calling an input / output control command; The method further comprises: adding the input / output control command to a whitelist of a secure computing mode to enable a virtual machine hypervisor and a kernel-mode virtual machine monitor to which the virtual processor belongs to share the address of the interrupt descriptor.
7. The invocation method of claim 4, wherein, The setting of the interrupt call function for the virtual processor comprises: switching the function called when sending an interrupt request to the interrupt call function in a start-up phase of a guest to which the virtual processor belongs; when a switching condition is met, switching the function called when sending an interrupt request back to a default call function; the default call function refers to an implementation manner of completing the delivery of an interrupt request through software simulation; the switching condition comprises any one of the following: a feature flag corresponding to the semi-virtualized inter-processor interrupt feature does not exist, an effective flag bit of a state register of the semi-virtualized inter-processor interrupt feature is not in an effective state, and a read-back verification of the semi-virtualized inter-processor interrupt feature fails after being enabled.
8. An invocation apparatus of a semi-virtualized inter-processor interrupt communication system, characterized by, The apparatus comprises: The semi-virtualization interrupt feature configuration module is used to configure the inter-processor interrupt features for the virtual processor. The semi-virtualization interrupt feature determination module is used to determine whether the virtual processor enables the inter-semi-virtualization interrupt feature; An interrupt call function setting module is used to set an interrupt call function for the virtual processor if the virtual processor enables the inter-paravirtualized processor interrupt feature, so that the interrupt call function can be called when an interrupt request is sent; The interrupt descriptor update module is used to directly update the interrupt descriptor corresponding to the target virtual processor in response to the call of the interrupt call function, so that the target virtual processor can process the interrupt request.
9. An electronic device, comprising: It includes a processor, a memory, and a program or instructions stored in the memory and executable on the processor, wherein when the program or instructions are executed by the processor, they implement the steps of the invocation method of the semi-virtualized inter-processor interrupt communication system as described in claims 1-7.
10. A readable storage medium, characterized by, The readable storage medium stores a program or instructions that, when executed by a processor, implement the steps of the invocation method of the semi-virtualized inter-processor interrupt communication system as described in claims 1-7.