Methods, apparatus, equipment and media for optimizing interrupt handling in virtualization systems

Abstract

This invention discloses a method, apparatus, device, and medium for optimizing interrupt handling in a virtualization system, relating to the field of virtualization technology. The method includes configuring the Virtual Machine Monitor (HMGM) to configure MSI interrupt routing; the Virtual Machine Provider (VE) receives requests from the Virtual Machine (VM) or the Virtual Machine Interrupt Service (SPI) and, based on the current state, initiates an MSI interrupt request to the HMGM; the Message Interrupt Handling Component (ITS) in the HMGM receives the MSI interrupt request and converts it into an LPI interrupt, which is then sent to the VM or the HMGM. The HMGM configuration of the HMGM specifies the MSI and LPI interrupts sent to the VM, and specifies the MSI interrupts sent to the HMGM. This application enables communication between virtual machines and between a virtual machine and the host without additional computing power loss, effectively optimizing interrupt handling in automotive processors.

Description

Technical Field

[0001] This application relates to the field of virtual technology, specifically to a method, apparatus, device, and medium for optimizing interrupt handling in a virtualized system. Background Technology

[0002] In the virtualization system of the automotive processor, only LPI (Locality-specific Peripheral Interrupt) interrupts can be directly sent to the virtual machine without causing it to exit. Other interrupts cause the virtual machine to trap into the hypervisor, which then processes the interrupt and forwards it back to the virtual machine. For this architecture: 1. Virtual machine trapping itself consumes computing power, and frequent device interrupt trapping can significantly reduce system performance; 2. The automotive system has frequent communication needs between virtual machines and between virtual machines and the host, requiring virtual machines to actively initiate interrupts. Using interrupts for communication leads to significant computing power consumption; 3. The hypervisor's interrupt handling itself increases the real-time response time of virtual machine interrupts.

[0003] Therefore, it is evident that whether the virtual machine initiates an interrupt or an SPI interrupt, it will cause the virtual machine to enter the hypervisor. Consequently, the existing interrupt handling methods have the following problems: 1. Virtual machine entry into the hypervisor causes corresponding computing overhead; 2. Frequent virtual machine entry into the hypervisor will cause significant computing overhead for SPI device passthrough, inter-virtual machine, and virtual machine-host communication based on this mechanism; 3. The latency introduced by the virtual machine entry action itself is unacceptable for real-time sensitive systems, making it impossible to deploy such systems within virtual machines. Summary of the Invention

[0004] This application provides a method, apparatus, device, and medium for optimizing interrupt handling in a virtualization system, which enables communication between virtual machines and between virtual machines and the host without additional computing power loss, effectively optimizing interrupt handling of the vehicle processor.

[0005] In a first aspect, embodiments of this application provide a method for optimizing interrupt handling in a virtualization system, the method comprising: Configure the GIC in the hypervisor to complete the configuration of MSI interrupt routing; VE receives requests from VM or SPI and, based on the current state, initiates an MSI interrupt request to GIC; The Message Interrupt Handling Component (ITS) in GIC receives MSI interrupt requests and converts them into LPI interrupts, which are then sent to the VM or the Hypervisor.

[0006] In conjunction with the first aspect, in one implementation, the VE receives a request from the VM or SPI, and based on the current state, initiates an MSI interrupt request to the GIC, specifically including: The VM requests an interrupt from the VE, and the VE, based on its current state, initiates an MSI interrupt request to the GIC; or... SPI requests VE, and VE, based on its current state, initiates an MSI interrupt request to GIC.

[0007] In conjunction with the first aspect, in one implementation, the hypervisor is configured with a GIC, wherein the configuration specifies the MSI interrupt and LPI interrupt to be sent to the VM, and specifies the MSI interrupt to be sent to the hypervisor.

[0008] Secondly, embodiments of this application provide a virtualization system interrupt handling optimization apparatus for implementing the virtualization system interrupt handling optimization method described above. The virtualization system interrupt handling optimization apparatus includes a VE, wherein the VE includes: For the VM, it provides an interface for initiating LPI interrupts; The host-facing component provides an interface to a first component that faces the VM to determine, based on pre-configuration, whether an LPI interrupt can be sent to the system. LPI interrupt management is used to determine whether an LPI interrupt can be sent to the system based on pre-configuration. Oriented towards the GIC, it is used to send LPI interrupts to the system; An LPI timer is a tick used to provide a direct data transmission mechanism for the system.

[0009] In conjunction with the second aspect, in one implementation, the LPI interrupt management includes a first component and a second component for SPI interrupts, which determines, based on a pre-configuration, whether an LPI interrupt can be sent to the system.

[0010] In conjunction with the second aspect, in one implementation method, The first component includes a first unit and a second unit; The first unit is used to store the LPI interrupt number requested by the VM; The second unit is used to arbitrate the VM's request.

[0011] In conjunction with the second aspect, in one implementation method, The second component includes a third unit, a fourth unit, and an SPI interrupt manager; The third unit is used to store the SPI-LPI interrupt number conversion table set by the Host; The fourth unit is used to arbitrate and monitor the requests from the SPI interrupt manager.

[0012] In conjunction with the second aspect, in one embodiment, the virtualization system interrupt handling optimization apparatus further includes a pass-through device for SPI interrupts.

[0013] Thirdly, embodiments of this application provide a virtualization system interrupt handling optimization device, the virtualization system interrupt handling optimization device including a processor, a memory, and a virtualization system interrupt handling optimization program stored in the memory and executable by the processor, wherein when the virtualization system interrupt handling optimization program is executed by the processor, it implements the steps of the virtualization system interrupt handling optimization method described above.

[0014] Fourthly, embodiments of this application provide a computer-readable storage medium storing a virtualization system interrupt handling optimization program, wherein when the virtualization system interrupt handling optimization program is executed by a processor, it implements the steps of the virtualization system interrupt handling optimization method described above.

[0015] The beneficial effects of the technical solutions provided in this application include: It can solve the problem that virtual machines in automotive processors will enter the hypervisor when they initiate an interrupt, and solve the problem that virtual machines in automotive processors need to enter the hypervisor before they can receive SPI interrupts. It can also realize communication between virtual machines and between virtual machines and the host without additional computing power loss, effectively optimizing the interrupt handling of automotive processors. Attached Figure Description

[0016] Figure 1 This is a flowchart illustrating the optimized interrupt handling method for the virtualization system in this application; Figure 2 This is a schematic diagram of the functional modules of the virtualization system interrupt handling optimization device of this application; Figure 3 This is a schematic diagram of the hardware structure of the interrupt handling optimization device for the virtualization system in this application. Detailed Implementation

[0017] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present application.

[0018] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0019] In the first aspect, the embodiments of this application provide a virtualization system interrupt handling optimization method, which can solve the problem that virtual machines in the vehicle processor will enter the hypervisor when they initiate an interrupt, and solve the problem that virtual machines in the vehicle processor need to enter the hypervisor before they can receive SPI interrupts. At the same time, it can realize communication between virtual machines and between virtual machines and hosts without additional computing power loss.

[0020] In one embodiment, reference is made to Figure 1 , Figure 1 This is a flowchart illustrating the optimized interrupt handling method for the virtualization system described in this application. Figure 1 As shown, the optimization methods for interrupt handling in virtualization systems include: S1: Configure the Hypervisor with GIC to complete the configuration of MSI interrupt routing; where GIC, or GenericInterrupt Controller, is an interrupt controller, and MSI, or Message Signaled Interrupts, is an interrupt method. Specifically, the Hypervisor is configured with GIC to complete the configuration of MSI interrupt routing. S2: VE receives requests from VM (virtual machine) or SPI, and based on its current state (i.e., based on VE's own current state to determine whether it can initiate an MSI interrupt request to GIC), initiates an MSI interrupt request to GIC; VE stands for Virtualization Enhancement; SPI stands for Shared Peripheral Interrupt. Specifically, the VM requests the VE, and the VE, based on its current state, initiates an MSI interrupt request to the GIC; or, the SPI requests the VE, and the VE, based on its current state, initiates an MSI interrupt request to the GIC. S3: The Interrupt Translation Service (ITS) component in the GIC receives MSI interrupt requests and converts them into LPI interrupts, which are then sent to the VM or Hypervisor. ITS is a key component in the GICv3 / v4 architecture for handling message-based interrupts (such as MSI). Specifically, the GIC ITS converts received MSI interrupts into LPI interrupts and then sends them to the VM or Hypervisor.

[0021] It should be noted that the Hypervisor configuration GIC specifies which MSI and LPI interrupts are sent to the VM, and which MSI interrupts are sent to the Hypervisor. In other words, it configures which MSI and LPI interrupts are sent to the VM and which MSI interrupts are sent to the Hypervisor.

[0022] This application solves the problem that virtual machines initiating interrupts in automotive processors cause them to enter the hypervisor, and addresses the issue that virtual machines in automotive processors must first enter the hypervisor before they can receive SPI interrupts. Simultaneously, it enables communication between virtual machines and between virtual machines and the host without additional computing power loss. Specifically, it implements a method for virtual machines to actively initiate interrupts and receive SPI interrupts without causing them to exit. The application of this application is not limited to various hypervisor systems such as L4re, QNX, SEL4, XEN, and Linux. Furthermore, this application effectively solves the computing power consumption problem caused by virtual machines actively initiating communication activities in virtualization systems. The core of this application lies in converting virtual machine MMIO write operations into a direct interrupt data transmission mechanism under the automotive processor architecture, and converting SPI interrupts into a direct interrupt data transmission mechanism under the automotive processor architecture.

[0023] Secondly, embodiments of this application also provide a virtualization system interrupt handling optimization apparatus for implementing the virtualization system interrupt handling optimization method described above. This virtualization system interrupt handling optimization apparatus includes: a Hypervisor configuring the GIC to complete the MSI interrupt routing implementation configuration; a VE receiving a request from the VM or SPI, and initiating an MSI interrupt request to the GIC according to the current state; and a Message Interrupt Handling Component (ITS) in the GIC receiving the MSI interrupt request and converting it into an LPI interrupt to be sent to the VM or Hypervisor. Specifically, the VE receiving the request from the VM or SPI and initiating an MSI interrupt request to the GIC according to the current state includes: the VM requesting the VE, and the VE initiating an MSI interrupt request to the GIC according to the current state; or, the SPI requesting the VE, and the VE initiating an MSI interrupt request to the GIC according to the current state. The Hypervisor configuring the GIC is configured to specify the MSI interrupts and LPI interrupts sent to the VM, and to specify the MSI interrupts sent to the Hypervisor.

[0024] This invention addresses the issue of virtual machines (VMs) entering a hypervisor state when initiating interrupts in automotive processors, and resolves the problem that VMs in automotive processors must first enter a hypervisor state before receiving SPI interrupts. Simultaneously, it enables communication between VMs and between a VM and the host without additional computing power loss. Specifically, it implements a method for VMs to actively initiate interrupts and receive SPI interrupts without causing the VM to exit. This application is not limited to various hypervisor systems such as L4re, QNX, SEL4, XEN, and Linux, and effectively solves the computing power consumption problem caused by VMs actively initiating communication activities in virtualization systems. The core of this application lies in converting VM MMIO write operations into a Directly Deliver Interrupt mechanism under the automotive processor architecture, and converting SPI interrupts into a Directly Deliver Interrupt mechanism under the automotive processor architecture.

[0025] In one embodiment, reference is made to Figure 2 , Figure 2 This is a schematic diagram of the functional modules of the virtualization system interrupt handling optimization device of this application. Figure 2 As shown, the virtualization system interrupt handling optimization device includes VE, which comprises VM-oriented, Host-oriented, LPI interrupt management, GIC-oriented, and LPI timer components. In other words, VE mainly includes components for VM, Host, LPI interrupt management, GIC, and LPI timer.

[0026] For VMs, an interface is provided to initiate LPI interrupts. That is, an interface that can initiate LPI interrupts is provided. Through this interface, a VE is requested, and the VE initiates an MSI interrupt or an LPI interrupt.

[0027] For the Host (the physical computer or server running the virtualization software), it provides the interface for the first component, that is, an interface with internal settings for the Host. The first component is used to face the VM to determine, based on pre-configuration, whether an LPI interrupt can be sent to the system.

[0028] For LPI interrupt management, it is used to determine whether an LPI interrupt can be sent to the system based on pre-configuration, that is, whether an LPI interrupt can be sent to the on-board processor. Pre-configuration includes, for example, configuring a threshold for interrupt storms (for a specific VM or interrupt number); if this threshold is exceeded, LPI interrupts cannot be sent to the on-board processor.

[0029] Furthermore, LPI interrupt management includes a first component and a second component for SPI interrupts. The first component is for VM-facing operations to determine, based on pre-configuration, whether an LPI interrupt can be sent to the system, and the second component is for SPI interrupt-facing operations to determine, based on pre-configuration, whether an LPI interrupt can be sent to the system.

[0030] The first component includes a first unit and a second unit; the first unit is used to store the LPI interrupt number requested by the VM; the second unit is used to arbitrate the VM's request.

[0031] The second component includes a third unit, a fourth unit, and an SPI interrupt manager. The third unit stores the SPI-LPI interrupt number conversion table set by the host; the fourth unit arbitrates and monitors the requests from the SPI interrupt manager.

[0032] For GIC, it is used to send LPI interrupts to the system, that is, to send LPI interrupts to the vehicle processor.

[0033] For the LPI timer, it is used to provide the system with a direct data transmission mechanism tick (time unit), that is, to provide the vehicle processor with a direct data transmission mechanism tick.

[0034] Furthermore, the virtualization system interrupt handling optimization device also includes a pass-through device for SPI interrupts. The pass-through device is a hardware device that directly allocates physical devices to virtual machines via PCI / PCIe pass-through technology.

[0035] It should be further noted that the virtualization system interrupt handling optimization device described in this application comprises a Hypervisor and a virtual machine kernel in its software composition. The Hypervisor is responsible for configuring the GIC and directly sends LPI interrupts initiated by the virtual machine and converted from SPI to the virtual machine through the GIC's LPI interrupt direct data transmission mechanism. The virtual machine kernel is used to implement the module for actively initiating interrupts and is provided for use by communication and other components (such as DDS) to implement the SPI interrupt manager interrupt domain of the first component and seamlessly connect to the SPI device driver.

[0036] This application solves the problem that virtual machines initiating interrupts in automotive processors cause them to enter the hypervisor, and addresses the issue that virtual machines in automotive processors must first enter the hypervisor before they can receive SPI interrupts. Simultaneously, it enables communication between virtual machines and between virtual machines and the host without additional computing power loss. Specifically, it implements a method for virtual machines to actively initiate interrupts and receive SPI interrupts without causing them to exit. The application of this application is not limited to various hypervisor systems such as L4re, QNX, SEL4, XEN, and Linux. Furthermore, this application effectively solves the computing power consumption problem caused by virtual machines actively initiating communication activities in virtualization systems. The core of this application lies in converting virtual machine MMIO write operations into a direct interrupt data transmission mechanism under the automotive processor architecture, and converting SPI interrupts into a direct interrupt data transmission mechanism under the automotive processor architecture.

[0037] Thirdly, embodiments of this application provide a virtualization system interrupt handling optimization device, which can be a personal computer (PC), laptop computer, server, or other device with data processing capabilities.

[0038] Reference Figure 3 , Figure 3 This is a schematic diagram of the hardware structure of the virtualization system interrupt handling optimization device involved in the embodiments of this application. In the embodiments of this application, the virtualization system interrupt handling optimization device may include a processor, a memory, a communication interface, and a communication bus.

[0039] The communication bus can be of any type and is used to interconnect the processor, memory, and communication interface.

[0040] Communication interfaces include input / output (I / O) interfaces, physical interfaces, and logical interfaces used for interconnecting devices within the virtualization system's interrupt handling optimization device, as well as interfaces used for interconnecting the virtualization system's interrupt handling optimization device with other devices (such as other computing devices or user equipment). Physical interfaces can be Ethernet interfaces, fiber optic interfaces, ATM interfaces, etc.; user equipment can be displays, keyboards, etc.

[0041] Memory can be various types of storage media, such as random access memory (RAM), read-only memory (ROM), non-volatile RAM (NVRAM), flash memory, optical storage, hard disk, programmable ROM (PROM), erasable PROM (EPROM), electrically erasable PROM (EEPROM), etc.

[0042] The processor can be a general-purpose processor, which can call a virtualization system interrupt handling optimization program stored in memory and execute the virtualization system interrupt handling optimization method provided in the embodiments of this application. For example, the general-purpose processor can be a central processing unit (CPU). The method executed when the virtualization system interrupt handling optimization program is called can refer to the various embodiments of the virtualization system interrupt handling optimization method of this application.

[0043] The virtualization system interrupt handling optimization method includes: configuring the GIC in the hypervisor to complete the MSI interrupt routing configuration; receiving requests from the VM or SPI and initiating an MSI interrupt request to the GIC based on the current state; the message interrupt handling component (ITS) in the GIC receiving the MSI interrupt request and converting it into an LPI interrupt, which is then sent to the VM or the hypervisor. Specifically, the process of the VE receiving requests from the VM or SPI and initiating an MSI interrupt request to the GIC based on the current state includes: the VM requesting the VE, which then initiates an MSI interrupt request to the GIC based on the current state; or the SPI requesting the VE, which then initiates an MSI interrupt request to the GIC based on the current state. The hypervisor configuration of the GIC specifies the MSI and LPI interrupts to be sent to the VM, and also specifies the MSI interrupts to be sent to the hypervisor.

[0044] This application solves the problem that virtual machines initiating interrupts in automotive processors cause them to enter the hypervisor, and addresses the issue that virtual machines in automotive processors must first enter the hypervisor before they can receive SPI interrupts. Simultaneously, it enables communication between virtual machines and between virtual machines and the host without additional computing power loss. Specifically, it implements a method for virtual machines to actively initiate interrupts and receive SPI interrupts without causing them to exit. The application of this application is not limited to various hypervisor systems such as L4re, QNX, SEL4, XEN, and Linux. Furthermore, this application effectively solves the computing power consumption problem caused by virtual machines actively initiating communication activities in virtualization systems. The core of this application lies in converting virtual machine MMIO write operations into a direct interrupt data transmission mechanism under the automotive processor architecture, and converting SPI interrupts into a direct interrupt data transmission mechanism under the automotive processor architecture.

[0045] Those skilled in the art will understand that Figure 3 The hardware structure shown does not constitute a limitation of this application and may include more or fewer components than shown, or combine certain components, or have different component arrangements.

[0046] Fourthly, embodiments of this application also provide a computer-readable storage medium.

[0047] The present application provides a computer-readable storage medium storing a virtualization system interrupt handling optimization program, wherein when the virtualization system interrupt handling optimization program is executed by a processor, it implements the steps of the virtualization system interrupt handling optimization method described above.

[0048] The virtualization system interrupt handling optimization method includes: configuring the GIC in the hypervisor to complete the MSI interrupt routing configuration; receiving requests from the VM or SPI and initiating an MSI interrupt request to the GIC based on the current state; the message interrupt handling component (ITS) in the GIC receiving the MSI interrupt request and converting it into an LPI interrupt, which is then sent to the VM or the hypervisor. Specifically, the process of the VE receiving requests from the VM or SPI and initiating an MSI interrupt request to the GIC based on the current state includes: the VM requesting the VE, which then initiates an MSI interrupt request to the GIC based on the current state; or the SPI requesting the VE, which then initiates an MSI interrupt request to the GIC based on the current state. The hypervisor configuration of the GIC specifies the MSI and LPI interrupts to be sent to the VM, and also specifies the MSI interrupts to be sent to the hypervisor.

[0049] This application solves the problem that virtual machines initiating interrupts in automotive processors cause them to enter the hypervisor, and addresses the issue that virtual machines in automotive processors must first enter the hypervisor before they can receive SPI interrupts. Simultaneously, it enables communication between virtual machines and between virtual machines and the host without additional computing power loss. Specifically, it implements a method for virtual machines to actively initiate interrupts and receive SPI interrupts without causing them to exit. The application of this application is not limited to various hypervisor systems such as L4re, QNX, SEL4, XEN, and Linux. Furthermore, this application effectively solves the computing power consumption problem caused by virtual machines actively initiating communication activities in virtualization systems. The core of this application lies in converting virtual machine MMIO write operations into a direct interrupt data transmission mechanism under the automotive processor architecture, and converting SPI interrupts into a direct interrupt data transmission mechanism under the automotive processor architecture.

[0050] The terms "comprising" and "having," and any variations thereof, in the specification, claims, and accompanying drawings of this application are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to such process, method, product, or apparatus. The terms "first," "second," and "third," etc., are used to distinguish different objects, etc., and do not indicate a sequence, nor do they limit "first," "second," and "third" to different types.

[0051] In the description of the embodiments of this application, terms such as "exemplary," "for example," or "for instance" are used to indicate examples, illustrations, or explanations. Any embodiment or design described as "exemplary," "for example," or "for instance" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of terms such as "exemplary," "for example," or "for instance" is intended to present the relevant concepts in a concrete manner.

[0052] In the description of the embodiments of this application, unless otherwise stated, " / " means "or". For example, A / B can mean A or B. The "and / or" in the text is merely a description of the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist simultaneously, and B exists alone. In addition, in the description of the embodiments of this application, "multiple" means two or more.

[0053] In some processes described in the embodiments of this application, multiple operations or steps are included in a specific order. However, it should be understood that these operations or steps may not be executed in the order they appear in the embodiments of this application, or they may be executed in parallel. The sequence number of the operation is only used to distinguish different operations, and the sequence number itself does not represent any execution order. In addition, these processes may include more or fewer operations, and these operations or steps may be executed sequentially or in parallel, and these operations or steps may be combined.

[0054] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) as described above, and includes several instructions to cause a terminal device to execute the methods described in the various embodiments of this application.

[0055] The above are merely preferred embodiments of this application and do not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A method for optimizing interrupt handling in a virtualization system, characterized in that, The virtualization system interrupt handling optimization method includes: Configure the GIC in the hypervisor to complete the configuration of MSI interrupt routing; VE receives requests from VM or SPI and, based on the current state, initiates an MSI interrupt request to GIC; The Message Interrupt Handling Component (ITS) in GIC receives MSI interrupt requests and converts them into LPI interrupts, which are then sent to the VM or the Hypervisor.

2. The virtualization system interrupt handling optimization method as described in claim 1, characterized in that, The VE receives requests from the VM or SPI and, based on the current state, initiates an MSI interrupt request to the GIC, specifically including: The VM requests an interrupt from the VE, and the VE, based on its current state, initiates an MSI interrupt request to the GIC; or... SPI requests VE, and VE, based on its current state, initiates an MSI interrupt request to GIC.

3. The virtualization system interrupt handling optimization method as described in claim 1, characterized in that, The Hypervisor is configured with GIC, wherein the configuration specifies the MSI and LPI interrupts sent to the VM, and specifies the MSI interrupt sent to the Hypervisor.

4. A virtualization system interrupt handling optimization apparatus, used to implement the virtualization system interrupt handling optimization method according to any one of claims 1 to 3, characterized in that, The virtualization system interrupt handling optimization device includes a VE, wherein the VE comprises: For the VM, it provides an interface for initiating LPI interrupts; The host-facing component provides an interface to a first component that faces the VM to determine, based on pre-configuration, whether an LPI interrupt can be sent to the system. LPI interrupt management is used to determine whether an LPI interrupt can be sent to the system based on pre-configuration. Oriented towards the GIC, it is used to send LPI interrupts to the system; An LPI timer is a tick used to provide a direct data transmission mechanism for the system.

5. The virtualization system interrupt handling optimization device as described in claim 4, characterized in that: The LPI interrupt management includes a first component and a second component for SPI interrupts, which determines whether an LPI interrupt can be sent to the system based on a pre-configured configuration.

6. The virtualization system interrupt handling optimization device as described in claim 5, characterized in that: The first component includes a first unit and a second unit; The first unit is used to store the LPI interrupt number requested by the VM; The second unit is used to arbitrate the VM's request.

7. The virtualization system interrupt handling optimization device as described in claim 5, characterized in that: The second component includes a third unit, a fourth unit, and an SPI interrupt manager; The third unit is used to store the SPI-LPI interrupt number conversion table set by the Host; The fourth unit is used to arbitrate and monitor the requests from the SPI interrupt manager.

8. The virtualization system interrupt handling optimization device as described in claim 4, characterized in that: The virtualization system interrupt handling optimization apparatus also includes a pass-through device for SPI interrupts.

9. A virtualization system interrupt handling optimization device, characterized in that, The virtualization system interrupt handling optimization device includes a processor, a memory, and a virtualization system interrupt handling optimization program stored in the memory and executable by the processor, wherein when the virtualization system interrupt handling optimization program is executed by the processor, it implements the steps of the virtualization system interrupt handling optimization method as described in any one of claims 1 to 3.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a virtualization system interrupt handling optimization program, wherein when the virtualization system interrupt handling optimization program is executed by a processor, it implements the steps of the virtualization system interrupt handling optimization method as described in any one of claims 1 to 3.

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