Method and device for calling amplitude and phase compensation data based on phased array antenna

Abstract

This invention provides a method and device for retrieving phased array antenna amplitude and phase compensation data, comprising: after the beam control system is powered on, the FPGA sequentially reads the pre-stored phased array antenna amplitude and phase compensation data in the NOR flash memory according to a predetermined storage rule; the NOR flash memory transmits the compensation data back to the FPGA, and the FPGA stores the data through a first-in-first-out (FIFO) pipelined architecture; the FPGA uses a memory interface generator (MIG) IP core to configure communication with DDR3, and temporarily stores the compensation data in DDR3 according to the predetermined storage rule; when the FPGA performs compensation operation, it generates the address of the corresponding frequency channel according to the predetermined storage rule, and reads the compensation data in DDR3 back to the FPGA through the memory interface generator (MIG) IP core; the FPGA performs data compensation calculation on the read-back compensation data to complete beamforming.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of antenna data processing technology, and in particular to a method and device for retrieving amplitude and phase compensation data of a phased array antenna. Background Technology

[0002] When a phased array antenna achieves beam pointing, the beam control system needs to first calculate the phase of the target azimuth, and then perform amplitude and phase compensation on the calculated data to achieve the required beamforming effect. In small-scale antenna systems, the number of antenna elements is small and the frequency requirements are few. During the beam control system design, amplitude and phase compensation data is stored in NOR FLASH. Upon power-up, the FPGA communicates with the NOR FLASH to temporarily store all amplitude and phase compensation data in the FPGA's on-chip memory resources (BRAM resources). When needed, the amplitude and phase compensation data for the corresponding frequency can be quickly retrieved for compensation processing to meet the specified beam switching time. However, in large-scale antenna systems, the number of antenna elements and frequency requirements increase, leading to a surge in the amount of amplitude and phase compensation data to be processed. At this point, the BRAM storage resources in the FPGA become insufficient, and the data size exceeds the BRAM resource capacity. Furthermore, BRAM is a scarce resource within the FPGA; a larger capacity BRAM usually means selecting a more expensive, higher-level FPGA chip, which significantly increases project costs. Secondly, using a large amount of BRAM to cache compensation data also crowds out the storage resources required for other logic functions. Therefore, in phased array antenna beam control systems, seeking larger compensation data storage space, meeting the specified beam switching time, and realizing rapid retrieval of large-scale compensation data are particularly crucial. Summary of the Invention

[0003] To address the aforementioned problems in related technologies, embodiments of the present invention provide a method and device for retrieving amplitude and phase compensation data from a phased array antenna.

[0004] In a first aspect, embodiments of the present invention provide a method for retrieving phased array antenna amplitude and phase compensation data, comprising: after the beam control system is powered on, the FPGA sequentially reads the phased array antenna amplitude and phase compensation data pre-stored in the NOR flash memory according to a predetermined storage rule; the NOR flash memory transmits the compensation data back to the FPGA, and the FPGA stores the data through a first-in-first-out (FIFO) pipelined architecture; the FPGA uses a memory interface generator (MIG) IP core to configure communication with DDR3, and temporarily stores the compensation data in DDR3 according to the predetermined storage rule; when the FPGA performs compensation operations, it generates the address of the corresponding frequency channel according to the predetermined storage rule, and reads the compensation data in DDR3 back to the FPGA through the memory interface generator (MIG) IP core; the FPGA performs data compensation calculations on the read-back compensation data to complete beamforming.

[0005] Based on the above method embodiments, the present invention provides a method for calling phased array antenna amplitude and phase compensation data, wherein the phased array antenna amplitude and phase compensation data is the amplitude and phase compensation data of all channels of the phased array antenna at various weighted frequency points.

[0006] Based on the above method embodiments, the method for calling phased array antenna amplitude and phase compensation data provided in this embodiment of the invention includes the NOR flash memory transmitting compensation data back to the FPGA, and the FPGA storing data through a first-in-first-out (FIFO) pipeline architecture. The operation of the FPGA storing data through the FIFO pipeline architecture is executed synchronously with the operation of the FPGA reading the pre-stored data in the NOR flash memory after the wave control system is powered on.

[0007] Based on the above method embodiments, the present invention provides a method for calling phased array antenna amplitude and phase compensation data. The FPGA uses a memory interface generator (MIG) IP core to configure and communicate with DDR3, and temporarily stores the compensation data in DDR3 according to a predetermined storage rule. The compensation data is compensation data temporarily stored in a first-in-first-out (FIFO) memory, and the FPGA temporarily stores the compensation data in DDR3 sequentially according to the predetermined storage rule.

[0008] Based on the above method embodiments, the present invention provides a method for calling phased array antenna amplitude and phase compensation data. When the FPGA performs compensation operation, it generates the address of the corresponding frequency channel according to the predetermined storage rules, and reads back the compensation data in DDR3 to the FPGA through the memory interface generator MIG IP core. The method includes: when the FPGA performs compensation operation, it first establishes a communication connection with DDR3, then generates the address of the corresponding frequency channel and performs the compensation data readback operation.

[0009] Based on the above method embodiments, the present invention provides a method for calling phased array antenna amplitude and phase compensation data, wherein the FPGA model is Guowei SMQ7K410TFFG900.

[0010] Based on the above method embodiments, the method for calling phased array antenna amplitude and phase compensation data provided in this embodiment of the invention uses two NOR flash memory chips of model HWD29GL01GP-C; the DDR3 memory chip is model SM41J256M16M, and the DDR3 memory chip is equipped with a memory power supply chip of model SM51200.

[0011] Secondly, embodiments of the present invention provide a device for retrieving phased array antenna amplitude and phase compensation data, comprising: a first main module, used to enable the FPGA to sequentially read the pre-stored phased array antenna amplitude and phase compensation data in the NOR flash memory according to a predetermined storage rule after the beam control system is powered on; a second main module, used to enable the NOR flash memory to transmit compensation data back to the FPGA, and the FPGA to store the data through a first-in-first-out (FIFO) pipelined architecture; a third main module, used to enable the FPGA to use a memory interface generator (MIG) IP core to configure communication with DDR3, and temporarily store the compensation data in DDR3 according to a predetermined storage rule; a fourth main module, used to enable the FPGA to generate the address of the corresponding frequency channel according to the predetermined storage rule when performing compensation operations, and read the compensation data in DDR3 back to the FPGA through the memory interface generator (MIG) IP core; and a fifth main module, used to enable the FPGA to perform data compensation calculation on the read-back compensation data to complete beamforming.

[0012] Thirdly, embodiments of the present invention provide an electronic device, comprising:

[0013] At least one processor, at least one memory, and a communication interface; wherein,

[0014] The processor, memory, and communication interface communicate with each other;

[0015] The memory stores program instructions that can be executed by the processor. The processor calls the program instructions to execute the calling method based on phased array antenna amplitude and phase compensation data provided by any of the various implementations of the first aspect.

[0016] Fourthly, embodiments of the present invention provide a non-transitory computer-readable storage medium storing computer instructions that cause a computer to execute a calling method based on phased array antenna amplitude and phase compensation data provided by any of the various implementations of the first aspect.

[0017] The present invention provides a method and device for retrieving phase and amplitude compensation data of a phased array antenna. Through circuit design and control of FPGA-supported FLASH and DDR3 chips, it ensures the temporary storage of large-scale compensation data and guarantees that the stored data can be quickly retrieved after receiving a compensation command, thereby completing high-quality beamforming. DDR3 is used as a cache pool for large-scale compensation data, and an efficient data cache layer is built between the FPGA and DDR3, enabling the beam control system to quickly retrieve large-scale compensation data. DDR3 chips can provide huge capacity in Gb units, and the cost per unit capacity is far lower than that of FPGA BRAM, perfectly solving the capacity bottleneck problem. Furthermore, through reasonable architecture design, it meets the speed requirements of large-scale phased array antenna calculations. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention or related technologies, the drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a schematic diagram of the calling method based on phased array antenna amplitude and phase compensation data provided in an embodiment of the present invention;

[0020] Figure 2 This is a schematic diagram of the structure of the device for calling phased array antenna amplitude and phase compensation data provided in an embodiment of the present invention;

[0021] Figure 3 A schematic diagram of the physical structure of an electronic device provided in an embodiment of the present invention;

[0022] Figure 4 A schematic diagram of the hardware architecture of the method for calling phased array antenna amplitude and phase compensation data provided in an embodiment of the present invention;

[0023] Figure 5 This is a schematic diagram of the software architecture of the method for calling phased array antenna amplitude and phase compensation data provided in an embodiment of the present invention. Detailed Implementation

[0024] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. In addition, the technical features of the various embodiments or individual embodiments provided by the present invention can be arbitrarily combined to form feasible technical solutions. Such combinations are not constrained by the order of steps and / or structural composition patterns, but must be based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such combination of technical solutions does not exist and is not within the scope of protection claimed by the present invention. If there are step numbers in the following embodiments, they are only set for ease of explanation and the order between steps is not limited. The execution order of each step in the embodiments can be adaptively adjusted according to the understanding of those skilled in the art.

[0025] This invention provides a method for retrieving amplitude and phase compensation data from a phased array antenna. See [link to relevant documentation]. Figure 1 The method includes: after the beam control system is powered on, the FPGA sequentially reads the phased array antenna amplitude and phase compensation data pre-stored in the NOR flash memory according to a predetermined storage rule; the NOR flash memory sends the compensation data back to the FPGA, and the FPGA stores the data through a first-in-first-out (FIFO) pipelined architecture; the FPGA uses a memory interface generator (MIG) IP core to communicate with DDR3 for configuration, and temporarily stores the compensation data in DDR3 according to the predetermined storage rule; when the FPGA performs compensation operations, it generates the address of the corresponding frequency channel according to the predetermined storage rule, and reads the compensation data in DDR3 back to the FPGA through the memory interface generator (MIG) IP core; the FPGA performs data compensation calculations on the read-back compensation data to complete beamforming.

[0026] See the corresponding software architecture. Figure 5 In the software design process, after the beamforming system is powered on, initialization is performed first. The FPGA generates read addresses and enable signals according to specified storage rules and sends them to the FLASH memory. It then sequentially reads the amplitude and phase compensation data for all channels of the phased array antenna at various weighted frequency points, pre-stored in the FLASH. Upon receiving the address and enable signals, the FLASH sends the compensation data at the corresponding address back to the FPGA. The FPGA then stores the data using a FIFO pipeline architecture. Next, the MIG IP core communicates with the DDR3 chip for configuration, sending the compensation data in the FIFO to the DDR3 chip for buffering according to specified storage rules, awaiting retrieval. When the FPGA performs compensation operations, it starts calling the compensation data from the DDR3, generates the address of the corresponding frequency channel according to the specified storage rules, reads the data back to the FPGA via the MIG IP core, performs amplitude and phase compensation calculations, and completes beamforming.

[0027] Based on the above method embodiments, as an optional embodiment, the present invention provides a method for calling phased array antenna amplitude and phase compensation data, wherein the phased array antenna amplitude and phase compensation data is the amplitude and phase compensation data of all channels of the phased array antenna at various weighted frequency points.

[0028] The phase-array antenna amplitude and phase compensation data is the core foundational data for ensuring antenna beam performance. Its coverage spans the entire critical dimension of phase-array antenna operation—encompassing amplitude and phase characteristic calibration information for all weighted frequency points and all channels. From a frequency point perspective, "various weighted frequency points" include all nominal frequency points within the antenna's operating band, as well as key test frequencies such as band edges and bandwidth midpoints. Each frequency point is matched with a specific weighting strategy required for beamforming (such as Taylor weighting, Chebyshev weighting, etc.). Different weightings correspond to different beam pointing and sidelobe suppression requirements, necessitating targeted compensation benchmarks. From a channel perspective, "all channels" covers all independent channels of the antenna's transmit and receive links, including links containing core modules such as signal amplification, phase shifting, and feeding. Due to component consistency deviations and link loss differences, each channel will experience amplitude attenuation and phase shift at different frequency points. The compensation data must accurately match the deviation characteristics of each channel at the corresponding frequency point, providing precise calibration basis for beamforming and ensuring stable beam scanning and signal transmission / reception performance.

[0029] Based on the above method embodiments, as an optional embodiment, the method for calling phased array antenna amplitude and phase compensation data provided in this embodiment of the invention includes the NOR flash memory transmitting compensation data back to the FPGA, and the FPGA storing data through a first-in-first-out (FIFO) pipelined architecture. The operation of the FPGA storing data through the FIFO pipelined architecture is executed synchronously with the operation of the FPGA reading the pre-stored data in the NOR flash memory after the wave control system is powered on.

[0030] In the process of transmitting compensation data from NOR flash memory to the FPGA, the FIFO (First-In-First-Out) pipelined architecture is the core support for achieving efficient data storage. Its storage operation is synchronized with the FPGA's reading of pre-stored data from the NOR flash memory after the waveguide system powers on, significantly improving the collaborative efficiency of system startup and data processing. From an architectural perspective, the FIFO pipelined design can adapt to timing differences in data transmission. After the compensation data transmitted from NOR flash memory is input via the interface link, the FIFO will buffer it sequentially according to the "first-in, first-out" principle, avoiding data loss or congestion caused by sudden data transmissions or fluctuations in the FPGA's subsequent processing rate. In terms of synchronous execution logic, after the waveguide system powers on and initializes, it will simultaneously trigger two operations: first, the FPGA initiates a batch reading of pre-stored basic compensation data from the NOR flash memory to provide a benchmark for initial system calibration; second, the FIFO architecture synchronously activates the data storage function, receiving and temporarily storing the dynamic compensation data transmitted from the NOR flash memory in real time. This synchronous design eliminates the timing gap between data reading and registering, ensuring seamless connection between initial reference data and dynamic compensation data, and providing continuous and stable data input for subsequent FPGA processing such as beamforming.

[0031] Based on the above method embodiments, as an optional embodiment, the method for calling phased array antenna amplitude and phase compensation data provided in this embodiment of the invention involves the FPGA using a memory interface generator (MIG) IP core to configure and communicate with DDR3, and temporarily storing the compensation data in DDR3 according to a predetermined storage rule. This includes: the compensation data is compensation data temporarily stored in a first-in-first-out (FIFO) memory, and the FPGA temporarily stores the compensation data in DDR3 sequentially according to the predetermined storage rule.

[0032] The compensation data specifically refers to the phased array antenna amplitude and phase compensation data temporarily stored in the first-in-first-out (FIFO) memory in real time. This data, after being returned from NOR flash memory, is first buffered and adapted by the FIFO, and then the FPGA performs ordered temporary storage to DDR3, forming an efficient data flow link of "FIFO buffering - FPGA scheduling - DDR3 storage". The temporary storage characteristic of the FIFO provides the foundation for data synchronization: it buffers the continuous compensation data returned from flash memory through a pipelined architecture, resolving the timing difference between the NOR flash read rate and the FPGA processing rate, and avoiding data loss or congestion. The FPGA, as the core scheduling unit, must strictly follow predetermined storage rules to execute operations. These rules typically include three-dimensional mapping logic—dividing DDR3 storage partitions according to "channel number - weighted frequency point - data type" to ensure accurate classification of compensation data for different channels and frequencies. Simultaneously, the storage process must adapt to the high-speed characteristics of DDR3: the FPGA writes data in batches through burst transmission mode, using an address auto-increment mechanism to achieve continuous temporary storage, and embeds CRC checksums during the writing process for data integrity verification. This move makes DDR3 a high-speed cache pool for compensation data, laying the foundation for fast data retrieval during subsequent beamforming and ensuring the real-time performance of the phased array antenna.

[0033] Based on the above method embodiments, as an optional embodiment, the method for calling phased array antenna amplitude and phase compensation data provided in this embodiment of the invention includes the following steps: when the FPGA performs compensation operation, it generates the address of the corresponding frequency channel according to the predetermined storage rules, and reads back the compensation data in DDR3 to the FPGA through the memory interface generator MIG IP core. The steps include: when the FPGA performs compensation operation, it first establishes a communication connection with DDR3, then generates the address of the corresponding frequency channel and performs the compensation data readback operation.

[0034] The core process of FPGA compensation operations revolves around a "communication establishment - address generation - data readback" chain, with precise coordination among each step ensuring compensation accuracy and real-time performance. The communication establishment phase is the fundamental prerequisite for data interaction: the FPGA first activates its built-in DDR3 controller, initializing it by configuring timing parameters such as clock frequency, read / write latency, and burst length. Then, it performs a handshake interaction with the DDR3 via the chip select (CS) and readiness (READY) signals. After bidirectional link verification is successful, a stable communication channel is established to avoid data transmission errors caused by timing mismatches. The address generation phase requires precise positioning: based on the current compensation requirements, the FPGA calls a preset address mapping algorithm, combining the target frequency code and channel number to generate a physical address—the high-order bits correspond to the frequency partition, the middle bit identifies the channel number, and the low-order bits indicate the data offset, ensuring a complete match between the address and the "frequency-channel" memory partition in the DDR3.

[0035] The data readback operation emphasizes efficiency and reliability: After the address is generated, the FPGA immediately sends the read command and the target address. The DDR3 transmits the corresponding compensation data in batches according to the burst transmission mode. At the same time, the FPGA verifies the data integrity in real time through the CRC check module. The readback data is directly sent to the compensation calculation unit to provide accurate input for subsequent amplitude and phase calibration, ensuring the real-time performance and accuracy of the compensation operation.

[0036] Based on the above method embodiments, as an optional embodiment, the method for calling phased array antenna amplitude and phase compensation data provided in this embodiment of the invention uses a Guowei SMQ7K410TFFG900 FPGA.

[0037] Based on the above method embodiments, as an optional embodiment, the method for calling phased array antenna amplitude and phase compensation data provided in this embodiment of the invention uses two NOR flash memory chips of model HWD29GL01GP-C; the DDR3 memory chip is model SM41J256M16M of Guowei, and the DDR3 memory chip is equipped with a memory power supply chip of model SM51200 of Guowei.

[0038] See Figure 4In the hardware circuit design, the fast call module consists of one FPGA main chip, two NORFLASH chips, one DDR3 chip, and a memory power supply chip. In the specific implementation, the FPGA main chip is the Shenzhen Guowei SMQ7K410TFFG900, the FLASH chip is the Chengdu Huawi HWD29GL01GP-C, and the DDR3 and memory power supply LDO chips are the Guowei SM41J256M16M and SM51200, respectively. The DDR3 chip contains clock signals, address and control signals, data signals, power supply, and reference voltage. During hardware routing, impedance control must be followed; single-ended and differential signals must meet impedance requirements. To ensure timing synchronization, strict equal-length constraints must be set for different signal groups.

[0039] In addition, DDR3 systems require multiple power supplies. VDD (1.5V) powers the DDR3 chip core and I / O, requiring ample decoupling capacitors. During routing, capacitors should be placed as close as possible to the power supply pins of the DDR3 chip. VTT (0.75V) powers the termination resistors for the address / command lines. The VTT power supply must have strong source and sink capabilities because rapidly changing currents occur during signal switching, and it also requires adequate decoupling. VREF (0.75V) provides a reference voltage for the DDR3 input buffer. It must be very clean and stable, typically generated using a dedicated low-noise LDO with added RC filtering.

[0040] The method for retrieving phase and amplitude compensation data from a phased array antenna provided in this invention ensures the temporary storage of large-scale compensation data through circuit design and control of FPGA-supported FLASH and DDR3 chips. Simultaneously, it guarantees that the stored data can be quickly retrieved upon receiving a compensation command, thereby achieving high-quality beamforming. DDR3 is used as a cache pool for large-scale compensation data, constructing an efficient data cache layer between the FPGA and DDR3, enabling the beam control system to quickly retrieve large-scale compensation data. DDR3 chips can provide a huge capacity in gigabytes (Gb), and the cost per unit capacity is far lower than that of FPGA's BRAM, perfectly solving the capacity bottleneck problem. Furthermore, through a reasonable architecture design, it meets the speed requirements for large-scale phased array antenna calculations.

[0041] The implementation of the various embodiments of this invention is based on programmed processing (i.e., software) using a device with processor functionality. Therefore, in practical engineering, the technical solutions and functions of the various embodiments of this invention can be encapsulated into various modules. Based on this reality, and building upon the above embodiments, the embodiments of this invention provide a device for calling phased array antenna amplitude and phase compensation data. This device is used to execute the calling method based on phased array antenna amplitude and phase compensation data in the above method embodiments. See also... Figure 2The device includes: a first main module, used to enable the FPGA to sequentially read the phased array antenna amplitude and phase compensation data pre-stored in the NOR flash memory according to a predetermined storage rule after the beam control system is powered on; a second main module, used to enable the NOR flash memory to transmit compensation data back to the FPGA, and the FPGA to store the data through a first-in-first-out (FIFO) pipelined architecture; a third main module, used to enable the FPGA to communicate with the DDR3 memory using the memory interface generator (MIG) IP core, and temporarily store the compensation data in the DDR3 memory according to the predetermined storage rule; a fourth main module, used to enable the FPGA to generate the address of the corresponding frequency channel according to the predetermined storage rule when performing compensation operations, and read the compensation data in the DDR3 memory back to the FPGA through the memory interface generator (MIG) IP core; and a fifth main module, used to enable the FPGA to perform data compensation calculations on the read-back compensation data to complete beamforming.

[0042] The device for retrieving phased array antenna amplitude and phase compensation data provided in this embodiment of the invention employs... Figure 2 Several modules within the system, through circuit design and control using FPGA-supported FLASH and DDR3 chips, ensure the temporary storage of large-scale compensation data while guaranteeing rapid retrieval of stored data upon receiving compensation commands, thereby achieving high-quality beamforming. DDR3 is used as a cache pool for large-scale compensation data, constructing an efficient data cache layer between the FPGA and DDR3, enabling the beam control system to quickly retrieve large-scale compensation data. DDR3 chips can provide massive capacities in gigabytes, and the cost per unit capacity is far lower than that of FPGA's BRAM, perfectly solving the capacity bottleneck problem. Furthermore, through a reasonable architecture design, it meets the speed requirements for large-scale phased array antenna calculations.

[0043] It should be noted that the apparatus in the device embodiments provided by the present invention can be used not only to implement the methods in the above method embodiments, but also to implement the methods in other method embodiments provided by the present invention. The difference lies only in setting corresponding functional modules (i.e., software). Its principle is basically the same as that of the above device embodiments provided by the present invention. As long as those skilled in the art, based on the above device embodiments and referring to the specific technical solutions in other method embodiments, obtain corresponding technical means and technical solutions composed of these technical means by combining technical features, and under the premise of ensuring the practicality of the technical solution, they can improve the apparatus in the above device embodiments to obtain corresponding device-type embodiments (i.e., software) for implementing the methods in other method-type embodiments. For example:

[0044] Based on the above device embodiments, as an optional embodiment, the device for calling phased array antenna amplitude and phase compensation data provided in this embodiment of the invention further includes: a first submodule, used to realize that the phased array antenna amplitude and phase compensation data is the amplitude and phase compensation data of all channels under various weighted frequency points of the phased array antenna.

[0045] Based on the above device embodiments, as an optional embodiment, the device for calling phased array antenna amplitude and phase compensation data provided in this embodiment of the invention further includes: a second submodule, used to realize the NOR flash memory back to the FPGA, the FPGA registers the data through a first-in-first-out (FIFO) pipeline architecture, including: the operation of the FPGA registering the data through the FIFO pipeline architecture is executed synchronously with the operation of the FPGA starting to read the pre-stored data in the NOR flash memory after the wave control system is powered on.

[0046] Based on the above device embodiments, as an optional embodiment, the device for calling phased array antenna amplitude and phase compensation data provided in this embodiment of the invention further includes: a third submodule, used to enable the FPGA to configure communication with DDR3 using the memory interface generator MIG IP core, and to temporarily store the compensation data in DDR3 according to a predetermined storage rule, including: the compensation data is compensation data temporarily stored in the first-in-first-out memory FIFO, and the FPGA temporarily stores the compensation data in DDR3 sequentially according to the predetermined storage rule.

[0047] Based on the above device embodiments, as an optional embodiment, the device for calling phased array antenna amplitude and phase compensation data provided in this embodiment of the invention further includes: a fourth submodule, used to generate the address of the corresponding frequency channel according to the predetermined storage rules when the FPGA performs compensation operation, and read back the compensation data in DDR3 to the FPGA through the memory interface generator MIG IP core, including: when the FPGA performs compensation operation, it first establishes a communication connection with DDR3, then generates the address of the corresponding frequency channel and performs the compensation data readback operation.

[0048] Based on the above device embodiments, as an optional embodiment, the device for calling phased array antenna amplitude and phase compensation data provided in this embodiment of the invention further includes: a fifth sub-module, used to implement the FPGA model as Guowei SMQ7K410TFFG900.

[0049] Based on the above device embodiments, as an optional embodiment, the device for calling phased array antenna amplitude and phase compensation data provided in this embodiment of the invention further includes: a sixth submodule, used to implement that the number of NOR flash memory chips is 2 and the model is Huawi HWD29GL01GP-C; the DDR3 is model Guowei SM41J256M16M, and the DDR3 is equipped with a memory power supply chip, the model of which is Guowei SM51200.

[0050] The method in this embodiment of the invention is implemented using an electronic device; therefore, it is necessary to introduce the relevant electronic device. For this purpose, this embodiment of the invention provides an electronic device, such as... Figure 3 As shown, the electronic device includes at least one processor, a communications interface, at least one memory, and a communications bus, wherein the at least one processor, the communications interface, and the at least one memory communicate with each other via the communications bus. The at least one processor can invoke logical instructions stored in the at least one memory to execute all or part of the steps of the methods provided in the foregoing method embodiments.

[0051] Furthermore, when the logical instructions in at least one of the aforementioned memories can be implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to related technologies, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various method embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0052] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0053] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the parts that contribute to the related technology, can be embodied in the form of software products. These computer software products can be stored in computer-readable storage media, such as ROM / RAM, magnetic disks, optical disks, etc., and include several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0054] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. Based on this understanding, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than those shown in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, or sometimes in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0055] It should be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element. Any expressions such as "predetermined threshold," "preset threshold," etc., without specifying a particular value, can be determined by those skilled in the art through simple experimentation or appropriate adjustments.

[0056] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A calling method based on phase-amplitude compensation data of a phased array antenna, characterized in that, The method comprises the following steps: After the wave control system is powered on, the FPGA reads the phased array antenna amplitude and phase compensation data pre-stored in the NOR flash memory according to a predetermined storage rule; The NOR flash memory returns the compensation data to the FPGA, and the FPGA stores the data through the first-in-first-out memory FIFO pipeline architecture; the FPGA uses the memory interface generator MIG IP core to configure and communicate with the DDR3, and temporarily stores the compensation data in the DDR3 according to the predetermined storage rule; when the FPGA performs compensation operation, the FPGA generates the address of the corresponding frequency point channel according to the predetermined storage rule, and reads the compensation data in the DDR3 back to the FPGA through the memory interface generator MIG IP core; the FPGA performs data compensation calculation on the read compensation data, and completes beamforming.

2. The method of claim 1, wherein the method is based on the amplitude and phase compensation data of the phased array antenna. The phased array antenna amplitude and phase compensation data are the amplitude and phase compensation data of all channels under various weighting frequencies of the phased array antenna.

3. The calling method based on the phase-amplitude compensation data of the phased array antenna according to claim 2, characterized in that, The NOR flash memory returns the compensation data to the FPGA, and the FPGA stores the data through the first-in-first-out memory FIFO pipeline architecture, which comprises the following steps:

4. The calling method based on the phase-amplitude compensation data of the phased array antenna according to claim 3, characterized in that, The FPGA uses the memory interface generator MIG IP core to configure and communicate with the DDR3, and temporarily stores the compensation data in the DDR3 according to the predetermined storage rule, which comprises the following steps:

5. The method for retrieving phased array antenna amplitude and phase compensation data according to claim 4, characterized in that, When the FPGA performs compensation operation, the FPGA generates the address of the corresponding frequency point channel according to the predetermined storage rule, and reads the compensation data in the DDR3 back to the FPGA through the memory interface generator MIG IP core, which comprises the following steps:

6. The method of claim 5, wherein the calling the phase-amplitude compensation data based on the phased array antenna comprises: The FPGA of the present application is SMQ7K410TFFG900 of Guomicro.

7. The method of claim 6, wherein the calling the phase-amplitude compensation data based on the phased array antenna comprises: calling the phase-amplitude compensation data based on the phased array antenna when the phased array antenna is used. The number of NOR flash memories is 2, and the model is HWD29GL01GP-C of Huamicro; the model of the DDR3 is SM41J256M16M of Guomicro, and the DDR3 is matched with a memory power supply chip, and the model of the memory power supply chip is SM51200 of Guomicro.

8. A calling device based on phase-amplitude compensation data of a phased array antenna, characterized in that, The method comprises the following steps: The first main module is used to realize that, after the wave control system is powered on, the FPGA reads the phased array antenna amplitude and phase compensation data pre-stored in the NOR flash memory according to a predetermined storage rule; The second main module is used to transmit compensation data from NOR flash memory to the FPGA, and the FPGA stores the data through a FIFO pipeline architecture. The third main module is used to enable the FPGA to communicate with DDR3 using the memory interface generator (MIG) IP core, and temporarily store the compensation data in DDR3 according to a predetermined storage rule. The fourth main module is used to generate the address of the corresponding frequency channel according to the predetermined storage rule when the FPGA performs compensation operations, and read the compensation data in DDR3 back to the FPGA through the memory interface generator (MIG) IP core. The fifth main module is used to implement data compensation calculations on the read-back compensation data by the FPGA to complete beamforming.

9. An electronic device, comprising: include: At least one processor, at least one memory, and a communication interface; wherein, The processor, memory, and communication interface communicate with each other; The memory stores program instructions that can be executed by the processor, which invokes the program instructions to perform the method described in any one of claims 1 to 7.

10. A non-transitory computer-readable storage medium, comprising: The non-transitory computer-readable storage medium stores computer instructions that cause the computer to perform the method described in any one of claims 1 to 7.

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