Systems and methods for distortion mitigation

Abstract

A system and method for distortion reduction. In some embodiments, a system for distortion reduction includes a transmitter comprising pulse amplitude modulation driver circuitry. The pulse amplitude modulation driver circuitry may include a main driver comprising a most significant bit (MSB) amplifier and a least significant bit (LSB) amplifier. The LSB amplifiers may include an upper arm and a lower arm, the strength of which is adjustable.

Description

[0001] Cross-references to related applications

[0002] This application claims priority and benefit to U.S. Provisional Application No. 63 / 724,880, filed November 25, 2024, entitled “UNIVERSAL CHIPLET INTERCONNECT EXPRESS (UCIE) PULSE AMPLITUDE MODULATION 4 (PAM4) TX / RX PREDISTORTION”, the entire contents of which are incorporated herein by reference. Technical Field

[0003] One or more aspects of the embodiments of this disclosure relate to data links, and more specifically to systems and methods for distortion mitigation in data links. Background Technology

[0004] Data links can be used in a variety of applications, such as between separately packaged devices or between dies in a multi-chip module.

[0005] The various aspects of this disclosure relate to this overall technical environment.

[0006] The information disclosed in this background section is only intended to enhance the understanding of the background art, and therefore the information discussed in this background section does not necessarily constitute prior art. Summary of the Invention

[0007] According to embodiments of the present disclosure, a system for distortion mitigation is provided, the system comprising: a transmitter including a pulse amplitude modulation driver circuit, the pulse amplitude modulation driver circuit including: a main driver including a most significant bit (MSB) amplifier and a least significant bit (LSB) amplifier, wherein the LSB amplifier includes an upper arm and a lower arm, the strength of the upper arm or the strength of the lower arm being adjustable.

[0008] In some embodiments, the strength of the upper arm is adjustable, and the upper arm includes: a switching transistor; and a strength adjustment transistor connected in series with the switching transistor.

[0009] In some embodiments, the strength of the lower arm is adjustable independently of the strength of the upper arm, and the lower arm includes a switching transistor and a strength adjustment transistor connected in series with the switching transistor of the lower arm.

[0010] In some embodiments, the system further includes a feedforward equalizer (FFE) driver, the FFE driver including an MSB amplifier and an LSB amplifier.

[0011] In some embodiments, the LSB amplifier of the FFE driver includes an upper arm and a lower arm, and the strength of the upper arm and the strength of the lower arm of the LSB amplifier of the FFE driver are independently adjustable.

[0012] In some embodiments, the MSB amplifier includes an upper arm and a lower arm, and the strength of the upper arm or the lower arm of the MSB amplifier is adjustable.

[0013] In some embodiments, the transmitter is configured to receive an instruction from a receiver connected to the transmitter and adjust the strength of the upper arm or the lower arm based on the instruction.

[0014] In some embodiments, the instruction is a command to adjust the strength of the upper arm or the lower arm.

[0015] In some embodiments, the indicator is an indicator of eye size.

[0016] In some embodiments, the system further includes a receiver configured to generate the indication based on a measure of distortion of a pulse amplitude modulated signal received from the transmitter.

[0017] In some embodiments, the measure of distortion is a Shmoo array.

[0018] According to embodiments of the present disclosure, a method for distortion mitigation is provided, comprising: receiving an indication from a receiver connected to the transmitter by a transmitter; and adjusting the predistortion characteristics of a pulse amplitude modulation driver circuit of the transmitter based on the indication.

[0019] In some embodiments: the pulse amplitude modulation driver circuit includes a main driver, the main driver including a most significant bit (MSB) amplifier and a least significant bit (LSB) amplifier; and the LSB amplifier includes an upper arm and a lower arm, the intensity of the upper arm or the intensity of the lower arm being adjustable.

[0020] In some embodiments, the strength of the upper arm is adjustable, and the upper arm includes: a switching transistor; and a strength adjustment transistor connected in series with the switching transistor.

[0021] In some embodiments, the strength of the lower arm is adjustable independently of the strength of the upper arm, and the lower arm includes a switching transistor and a strength adjustment transistor connected in series with the switching transistor of the lower arm.

[0022] In some embodiments, the method further includes a feedforward equalizer (FFE) driver, the FFE driver including an MSB amplifier and an LSB amplifier.

[0023] In some embodiments, the LSB amplifier of the FFE driver includes an upper arm and a lower arm, and the strength of the upper arm and the strength of the lower arm of the LSB amplifier of the FFE driver are independently adjustable.

[0024] In some embodiments, the MSB amplifier includes an upper arm and a lower arm, and the strength of the upper arm or the lower arm of the MSB amplifier is adjustable.

[0025] According to embodiments of this disclosure, a method for distortion mitigation is provided, comprising: receiving a pulse amplitude modulated signal from a transmitter connected to the receiver by a receiver; generating a metric of distortion based on the signal; and sending an indication to the transmitter, the indication being based on the metric of distortion.

[0026] In some embodiments, generating a metric of distortion includes generating a Shmoo array. Attached Figure Description

[0027] These and other features and advantages of this disclosure will be appreciated and understood by referring to the specification, claims and drawings, wherein:

[0028] Figure 1A This is a block diagram of a system including multiple interconnected digital circuits according to embodiments of the present disclosure;

[0029] Figure 1B This is a block diagram of two interconnected digital circuits according to embodiments of the present disclosure;

[0030] Figure 1C This is a block diagram of a transmitter and receiver according to embodiments of the present disclosure;

[0031] Figure 2 This is an eye according to an embodiment of the present disclosure;

[0032] Figure 3A This is a circuit diagram of a 4-level pulse amplitude modulation (PAM4) driver circuit according to an embodiment of the present disclosure;

[0033] Figure 3B This is a circuit diagram of an amplifier according to an embodiment of the present disclosure;

[0034] Figure 3C It is a circuit of an amplifier including an intensity adjustment transistor according to an embodiment of the present disclosure;

[0035] Figure 4 This is a Shmoo diagram according to an embodiment of the present disclosure;

[0036] Figure 5AThis is a flowchart of a method for transmitting PAM4 data according to embodiments of the present disclosure; and

[0037] Figure 5B This is a flowchart of a method for transmitting PAM4 data according to an embodiment of the present disclosure. Detailed Implementation

[0038] The specific embodiments described below with reference to the accompanying drawings are intended to describe aspects of some embodiments of systems and methods for distortion mitigation in data links provided by this disclosure, and are not intended to represent only the forms in which this disclosure can be constructed or utilized. This description illustrates features of this disclosure in conjunction with the illustrated embodiments. However, it should be understood that the same or equivalent functions and structures can be implemented through different embodiments, which are also intended to be included within the scope of this disclosure. As indicated elsewhere herein, the same element reference numerals are intended to indicate the same elements or features.

[0039] In various electronic and computer systems, it may be desirable to enable components within the system—such as graphics cards, hard disk drives (including solid-state drives (SSDs), memory devices, network components or adapters, or other peripheral components or devices)—to communicate with each other using high-speed data transmission links. Such high-speed data links can include, for example, Universal Chipple Interconnect Express (UCIe), Peripheral Component Interconnect Express (PCIe), Knights Landing Token Interface (KTI), Ultra Path Interconnect (UPI), Quick Path Interconnect (QPI), Universal Serial Bus (USB), and others. These data links enable relatively high data transmission speeds, flexible bandwidth allocation, simultaneous data transmission, relatively low latency, and other characteristics.

[0040] In a data link, data can be transmitted from a transmitter component or circuit (hereinafter referred to as the "transmitter") to a receiver component or circuit (hereinafter referred to as the "receiver") along with a clock signal. A clock signal that may include two complementary signals can be generated by two phase interpolators in the transmitter. In some systems, the bit stream may carry an embedded clock. In some embodiments, the clock is transmitted separately as a forwarding clock.

[0041] In such a data link, 4-level pulse amplitude modulation (PAM4) can be used to increase throughput at a given clock frequency. However, if distortion (e.g., in the transmitter, in the channel, or in the receiver) alters the received waveform and, for example, causes the waveform to exhibit an eye diagram where one or more eyes are smaller than in a normally functioning link, then PAM4 may face performance degradation.

[0042] In some embodiments, this distortion can be mitigated using pre-distortion in the transmitter. For example, if the received signal has a smaller-than-normal upper eye size and the other two eyes (middle and lower eyes) larger than normal, the transmitter can apply pre-distortion that amplifies the upper eye (and reduces the size of the other two eyes) so that when the signal subsequently becomes distorted (e.g., in the transmitter, in the channel, or in the receiver), the upper eye returns to (e.g., reduced to) its normal size by distortion) the same applies to the other two eyes. In some embodiments, the receiver characterizes the distortion and provides the transmitter with an indication of the distortion characteristics or how to apply pre-distortion suitable for mitigating the distortion exhibited at the receiver.

[0043] The transmitter can apply predistortion using a driver that includes a most significant bit amplifier (HNP) and a least significant bit amplifier (LSB), one or both of which can be configured to apply predistortion. For example, the LSB may include two switching transistors configured as inverters, and a corresponding intensity adjustment transistor connected in series with each switching transistor, limiting the current flowing through the switching transistors when they are turned on. Each of the intensity adjustment transistors can be controlled by an intensity control signal generated by the transmitter based on an instruction received from the receiver. Adjusting the intensity adjustment transistors causes a level shift in the PAM4 eye diagram, resulting in a change in eye size. As mentioned above, such a change can be used as predistortion, which can mitigate additional changes in eye size that may result from subsequent distortion the signal may experience.

[0044] The receiver can use a Shmoo array to evaluate the distortion characteristics of the received signal. The Shmoo array can be used to estimate eye size; based on this estimate, the transmitter can apply appropriate predistortion. Because distortion is measured at the receiver, the applied predistortion can mitigate all distortions in the channel, including those occurring at the transmitter, channel, and receiver.

[0045] Figure 1AA system-level diagram of a system comprising multiple digital circuits 105 is shown. Each of these circuits may be a single semiconductor chip (e.g., a silicon digital integrated circuit), such as a tensor stream processing unit (TPU), a central processing unit (CPU), a graphics processing unit (GPU), or an application-specific integrated circuit (e.g., a silicon application-specific integrated circuit (ASIC)), a hard disk drive (e.g., a solid-state drive (SSD)), a memory device, a network component or adapter, or other peripheral components or devices. The digital circuits 105 may be connected via multiple data links 110, each of which may be a data link utilizing a data link protocol or mechanism. Such data links allow, for example, the digital circuits 105 to send data to each other (e.g., data to be processed, or data already processed by one or more of the digital circuits 105). For example, a first digital circuit 105 may process the data it receives (e.g., from off-chip or on-chip memory) and send the result to a second digital circuit 105. Communication between the multiple digital circuits 105 and other circuits (e.g., memory circuitry for storing the data to be processed) may be performed via additional data links (not shown).

[0046] In some embodiments, each of the data links 110 is a Universal Chipplet Interconnect Express (UCIe) data link, but embodiments of this disclosure are not limited thereto, and data link 110 may utilize other data link protocols or mechanisms according to various embodiments. The Universal Chipplet Interconnect Express (UCIe) data link may be a data link compliant with the open industry standard (UCIe standard) and designed to facilitate die-to-die interconnects and communication between dies (or “chiplets”) in a multi-chip module (e.g., in a multi-chip system-on-a-chip (SoC)). UCIe may be used as a package-level universal interconnect (e.g., within the package of a multi-chip module (e.g., a multi-chip SoC)).

[0047] The UCIe standard defines standardized die-to-die interconnects, including the physical layer, protocol stack, software model, and compliance test procedures. Standardization allows components manufactured by different companies to be compatible with each other. The UCIe physical layer supports relatively fast data transfer rates (e.g., up to 32 gigabits per second) over multiple channels (e.g., between 16 and 64 channels). Similar to Peripheral Component Interconnect Fast (PCIe) 6.0 links, UCIe links can use 256-byte Flow Control Units (FLITs) for data transfer. The UCIe standard's physical specifications are based on the Advanced Interface Bus (AIB) specifications; these physical specifications contribute to high performance and power efficiency.

[0048] The UCIe protocol layer is based on the Compute Fast Link (CXL) standard and includes the CXL.io (PCIe), CXL.mem, and CXL.cache protocols. UCIe-compliant data links are compatible with a variety of interconnect technologies, including organic substrates for standard 2D packages and embedded silicon bridges (e.g., embedded multi-die interconnect bridges EMIB), silicon interposers, and fan-out embedded bridges. Such interconnect technologies can enhance bandwidth density and power efficiency. UCIe-compliant data links exhibit significantly higher I / O performance and lower power consumption than, for example, PCIe serializer-deserializers (SerDes). For example, for a 45 μm bump pitch, a UCIe-compliant data link can provide a bandwidth density of up to 1.35 TB / s per square millimeter.

[0049] UCIe-compliant data links can be used in a variety of applications, including high-performance computing data centers, edge computing, and automotive and high-reliability applications. UCIe-compliant data links are suitable for high-performance computing applications where efficient interconnects between chips can be critical. In data centers, using UCIe-compliant data links enables the integration of various chips, allowing for customized solutions.

[0050] Artificial intelligence and machine learning applications can benefit from the high bandwidth and low latency offered by UCIe-compliant data links. By enabling efficient data transmission between dies, UCIe-compliant data links make it possible to rapidly process and analyze large datasets. In edge computing, UCIe-compliant data links can serve as part of the infrastructure for deploying and managing dies at the network edge.

[0051] In automotive and high-reliability applications, UCIe-compliant data links can provide runtime health monitoring and remediation features (which are part of the UCIe specification). These features ensure the robustness and reliability of the data links, allowing them to be used in safety-critical systems. UCIe-compliant data links are compatible with three-dimensional (3D) packaging, enabling high package density.

[0052] Figure 1B A data link 110 between a first digital circuit 105a and a second digital circuit 105b in digital circuitry 105 is shown. The first digital circuit 105a includes a transmitter (Tx) (e.g., a UCIe transmitter) 115, and the second digital circuit 105b includes a receiver (Rx) (e.g., a UCIe receiver) 120. Although for ease of illustration and description, Figure 1BA first digital circuit 105a including a transmitter 115 and a second digital circuit 105b including a receiver 120 are shown, but in various embodiments, each digital circuit may include both a transmitter and a receiver or a transceiver. The transmitter 115 is operable to, for example, convert or encode digital data from the first digital circuit 105a into a bit stream and transmit the bit stream to the receiver 120 of the second digital circuit 105b via a physical medium (e.g., conductive wiring, optical fiber, etc.) of the data link 110.

[0053] Figure 1C The connection between transmitter 115 and receiver 120 is illustrated. Data link 110 may include a data channel 125 and a clock channel, each of which may include a pair of conductors forming a transmission line for transmitting complementary (e.g., differential) signals. The conductor widths and the spacing between the conductors in each pair can be selected to provide the characteristic impedance specified by the UCIe standard, and (i) the data and clock outputs of transmitter 115 and (ii) the data and clock inputs of receiver 120 can both be impedance matched to the characteristic impedance of the transmission line. Figure 1C As shown, the two differential signals (CKP and CKN) of the clock signal can be generated by a first phase interpolator (PI) 140 and a second phase interpolator 145. The sideband channel 135 can be used to send feedback or control signals (e.g., indications related to distortion in the signal received by receiver 120) from receiver 120 to transmitter 115.

[0054] In data links, high data rates can be advantageous for reducing the number of channels required to carry a given throughput. Higher data rates can be achieved by using higher clock rates. However, losses can be a barrier; for example, for 64 gigabits per second (Gb / s) non-return-to-zero (NRZ), the maximum clock and data frequencies could be 32 gigahertz (GHz). Losses at 32 GHz can be significant, making data recovery challenging. Therefore, in some embodiments, 4-level pulse amplitude modulation (PAM4) signaling can be used to increase link throughput or reduce the clock rate (e.g., half the clock rate compared to an NRZ link with the same throughput).

[0055] In a PAM4 link, the linearity of the transmitter and receiver may be imperfect, and the nonlinearity of these components can limit or degrade link performance. Nonlinearity can lead to unequal data eye widths and heights, and may limit the maximum achievable data rate. Figure 2 An example eye diagram at the receiver in a PAM4 link with distortion is shown. It can be seen that the upper eye has a smaller height than the middle or lower eye. This reduced size of the upper eye may increase the link's error rate.

[0056] In some embodiments, the eye diagram (e.g., the size of the upper eye) of the waveform received by the receiver is improved by applying predistortion to the signal transmitted by transmitter 115, as discussed in further detail below. Such predistortion applied at transmitter 115 can counteract the distortion the waveform undergoes after transmission, resulting in a superior eye diagram of the received waveform. For example, if the upper eye is smaller than the middle and lower eyes, the predistortion applied at the transmitter can result in an eye diagram of the transmitted waveform where the upper eye is larger than the middle and lower eyes, such that all three eyes in the eye diagram of the received waveform are approximately the same size.

[0057] To apply predistortion to the transmitted waveform, a method similar to... Figure 3A The circuit. Figure 3A The circuitry includes a master driver and a feedforward equalizer (FFE) driver. The master driver includes a most significant bit (MSB) amplifier 305 and a least significant bit (LSB) amplifier 310, while the FFE driver includes an MSB amplifier 315 and an LSB amplifier 320. The feedforward equalizer amplifiers 315 and 320 can each be driven using two bits (the most significant bit and the least significant bit) of the most recently transmitted symbol. This retransmission of the most recently transmitted symbol (e.g., with reduced amplitude) can suppress inter-symbol interference.

[0058] Figure 3A Each of the MSB amplifiers 305 and 315 shown is an inverter. Figure 3B A circuit diagram of such an inverter is shown, which has an upper arm 325 and a lower arm 330, each including a corresponding transistor driven by an input. The transistors in the upper arm 325 and the lower arm 330 can be referred to as switching transistors because each transistor can be turned on or off during operation. Figure 3B The amplifier is shown as comprising two n-channel metal-oxide-semiconductor (NMOS) transistors, wherein the transistor in upper arm 325 is driven by inverter 335. In some embodiments, the transistor in upper arm 325 is alternatively a p-channel metal-oxide-semiconductor (PMOS) transistor, and no inverter is present.

[0059] Figure 3CA circuit diagram of a least effective bit amplifier (e.g., least effective bit amplifier 310 of a master driver or least effective bit amplifier 320 of a feedforward driver, which can be constructed using the same circuitry) is shown. The amplifier includes two switching transistors 340 (one in the upper arm 325 and one in the lower arm 330) and two intensity adjustment transistors 345 (one in the upper arm 325 and one in the lower arm 330). Each of the intensity adjustment transistors 345 can be (independently) controlled by a corresponding intensity control signal (an upper arm intensity control signal applied to the gate of the intensity adjustment transistor 345 in the upper arm 325, and a lower arm intensity control signal applied to the gate of the intensity adjustment transistor 345 in the lower arm 330). The intensity adjustment transistors 345 can operate as current limiting devices, each limiting the current flowing through the corresponding switching transistor 340 (e.g., limiting the current flowing through the switching transistor 340 in the same arm as the intensity adjustment transistor 345).

[0060] The intensity adjustment transistor 345 of the least significant bit amplifier 310 of the main driver can be adjusted to apply predistortion to the transmitted signal. The four levels generated by the PAM4 transmitter are referred to as level 0, level 1, level 2, and level 3 (where level 0 is ground, level 3 is VDD, and the other two levels are between level 0 and level 3, with level 2 being higher than level 1). It can be seen that the intensity adjustment transistor 345 of the least significant bit amplifier 310 of the main driver has little or no effect on levels 0 and 3, which are ground and VDD respectively, because when the output is at level 0 or level 3, both the most significant bit amplifier 305 and the least significant bit amplifier 310 of the main driver provide connections to ground (when the output is at level 0) or to VDD (when the output is at level 3).

[0061] The voltage output at level 1, where the most significant bit is low and the least significant bit is high, is determined by two factors: (i) the strength of the lower arm 330 of the most significant bit amplifier 305 of the main driver that draws a first current to ground, and (ii) the strength of the upper arm 325 of the least significant bit amplifier 310 of the main driver that draws a second current less than the first current from VDD. The remainder of the first current is drawn from the output such that a corresponding voltage (e.g., approximately equal to the product of (i) the remainder of the current and (ii) the characteristic impedance of the transmission line to which the transmitter is connected) appears at the output of the PAM4 driver circuit. Therefore, increasing the strength of the upper arm 325 of the least significant bit amplifier 310 of the main driver may tend to increase level 1, and decreasing the strength of the upper arm 325 of the least significant bit amplifier 310 of the main driver may tend to decrease level 1. The strength of the upper arm 325 of the Least Effective Bit Amplifier 310 of the main driver can be adjusted by adjusting the upper arm strength control signal of the gate of the transistor to adjust the strength of the upper arm 325 of the Least Effective Bit Amplifier 310 of the main driver, so as to (i) increase the current flowing through the transistor (to increase the upper arm strength) or (ii) decrease the current flowing through the transistor (to decrease the upper arm strength).

[0062] Similarly, the voltage output of level 2 (where the most significant bit is high and the least significant bit is low) is determined by two factors: (i) the strength of the upper arm 330 of the most significant bit amplifier 305 of the main driver drawing a first current from VDD, and (ii) the strength of the lower arm 330 of the least significant bit amplifier 310 of the main driver drawing a second current less than the first current to ground. The remainder of the first current flows into the output, thereby generating a corresponding voltage at the output of the PAM4 driver circuit. Therefore, increasing the strength of the lower arm 330 of the least significant bit amplifier 310 of the main driver may tend to decrease level 2, and decreasing the strength of the lower arm 330 of the least significant bit amplifier 310 of the main driver may tend to increase level 2. Thus, adjusting the control signals for the strength of the upper and lower arms of the least significant bit amplifier 310 of the main driver can be used to adjust levels 1 and 2, thereby achieving predistortion to produce any desired combination of three-eye sizes.

[0063] In some embodiments, the intensity adjustment transistor 345 of the least effective bit amplifier 320 of the feedforward driver can be adjusted in the same manner so that a pre-distorted level is transmitted in subsequent symbols (with a reduced amplitude) to provide more effective inter-symbol interference cancellation than that provided by transmitting previously transmitted symbols without pre-distortion.

[0064] In some embodiments, the strengths of both the most active bit amplifier 315 and the least active bit amplifier 320 of the feedforward driver are less than the corresponding strengths of the most active bit amplifier 305 and the least active bit amplifier 310 of the main driver, in a ratio corresponding to the amount of inter-symbol interference applied to the channel. This can be achieved by manufacturing the switching transistor of the most active bit amplifier 315 of the feedforward driver with a narrower channel than the transistor of the most active bit amplifier 305 of the main driver, and by controlling the strength adjustment transistor 345 of the least active bit amplifier 320 of the feedforward driver to provide reduced strength to both arms (other than any strength adjustment made for predistortion applications).

[0065] In some embodiments, the most effective bit amplifier 315 of the feedforward driver is based on Figure 3C The amplifier, and the intensity adjustment transistor 345 of the most effective bit amplifier 315 of the feedforward driver, is used to adjust the amplitude of the feedforward equalization modulation. In such an embodiment, the common-mode or average intensity of all intensity adjustment transistors 345 of the feedforward equalization driver can be adjusted during operation, for example, using a minimum mean square controller that can detect and minimize inter-symbol interference.

[0066] In some embodiments, the most effective bit amplifier 305 of the main driver is based on Figure 3C The amplifier, and the intensity adjustment transistor 345 of the most effective bit amplifier 305 of the main driver is used to apply predistortion, which is a supplement or alternative to the predistortion applied by the intensity adjustment transistor 345 of the least effective bit amplifier 310 of the main driver. If the least effective bit amplifier 310 of the main driver is not used to apply predistortion, then it can be based on Figure 3B Amplifier.

[0067] In some embodiments, receiver 120 detects distortion in the received waveform and sends an indication to transmitter 115 based on the detected distortion. The transmitter may then adjust intensity adjustment transistor 345 to reduce distortion. For example, the receiver may include three clock-controlled comparators, one for each eye of the PAM4 waveform. During normal operation, each comparator may have a threshold approximately centered on the corresponding eye of the waveform, and the slicing clock may be approximately synchronized with the highest point of each eye. To generate a Shmoo array (which is an array of digital values ​​(0 or 1) in a rectangular array of time along the horizontal axis and voltage along the vertical axis), the receiver may scan the slice clock time offset and, for each slice clock time offset, scan each reference voltage up and down. During these scans, if the error rate exceeds the threshold, the receiver may store zero in the array element corresponding to the current time and voltage coordinates, and if the error rate is below the threshold, it may store one. Figure 4 An example of a Shmoo graph is shown, which is a graphical representation of a Shmoo array, where each zero is represented by a gray dot and each one by a white dot. Figure 4 In the Shmoo diagram, the lower white area is smaller than the other two white areas, which suggests that in the received waveform, the lower eye is smaller than the other two eyes (as a result, for example, the amount of lower threshold voltage that can be changed without causing unacceptable errors).

[0068] Therefore, this instruction that the receiver can send to the transmitter can be a Shmoo array (from which the transmitter can infer which or which eyes should be magnified and which or which eyes should be minimized), or the instruction can be a measurement of each eye (e.g., height or width), or an instruction to increase or decrease the intensity control signal of one of the intensity adjustment transistors 345. The system and method described herein (where the distortion measured by the receiver is used to adjust the pre-distortion applied by the transmitter) can have the advantage of (at least partially) eliminating (i) distortion caused by nonlinearity in the transmitter 115, (ii) any nonlinearity in the channel between the transmitter 115 and the receiver 120, and (iii) distortion caused by nonlinearity in the receiver 120.

[0069] Figure 5A Methods for sending PAM4 data are shown in some embodiments. Although Figure 5A Various operations in this method are illustrated, but the embodiments according to this disclosure are not limited thereto. For example, according to some embodiments, such a method may include additional or fewer operations, or the order of operations may vary, without departing from the spirit and scope of the embodiments according to this disclosure (unless otherwise expressly stated or implied).

[0070] Figure 5A The method includes: at 505, the transmitter receiving an instruction from a receiver connected to the transmitter; and at 510, based on the instruction, the transmitter adjusting the predistortion characteristics of the transmitter's 4-level pulse amplitude modulation (PAM4) driver circuit. For example, as discussed above, the receiver may send an instruction to the transmitter, either a Shmoo array or an intensity control signal for adjusting the intensity adjustment transistor 345, and in response, the transmitter may adjust the intensity control signal of the intensity adjustment transistor 345, thereby adjusting the predistortion characteristics of the transmitter's 4-level pulse amplitude modulation (PAM4) driver circuit.

[0071] Figure 5B Methods for sending PAM4 data are shown in some embodiments. Although Figure 5BVarious operations in this method are illustrated, but the embodiments according to this disclosure are not limited thereto. For example, according to some embodiments, such a method may include additional or fewer operations, or the order of operations may vary, without departing from the spirit and scope of the embodiments according to this disclosure (unless otherwise expressly stated or implied).

[0072] Figure 5B The method includes receiving a 4-level pulse amplitude modulation (PAM4) signal from a transmitter connected to the receiver at 515, and generating a measure of distortion based on the signal at 520. For example, as discussed above, the receiver may receive the signal from the transmitter, generate a Shmoo array, and infer from the Shmoo array that one eye of the eye diagram is smaller than the other two eyes. The method also includes sending an indication to the transmitter at 525 based on the measure of distortion.

[0073] Although some examples described herein are in the context of PAM4 modulation, this disclosure is not limited to such embodiments, and, for example, similar systems and methods can be used to mitigate distortion in 8-level pulse amplitude modulation or 16-level pulse amplitude modulation systems.

[0074] As used herein, a “part” of something means “at least some” of that thing, and therefore can mean less than or all of that thing. Thus, a “part” of something includes, as a special case, the whole thing, i.e., an example where the whole thing is a part of something. As used herein, when a second quantity is “within Y” of a first quantity X, it means that the second quantity is at least XY and at most X + Y. As used herein, when a second number is “within Y%” of a first number, it means that the second number is at least (1-Y / 100) times the first number and at most (1+Y / 100) times the first number. As used herein, the term “or” should be interpreted as “and / or”, such that, for example, “A or B” means any one of “A” or “B” or “A and B”.

[0075] The background techniques provided in the Background section of this disclosure are included only to set the context, and the content of this section is not to be considered prior art. Any component or combination of components described (e.g., in any system diagram included herein) can be used to perform one or more operations of any flowchart included herein. Furthermore, (i) the operations are example operations and may involve various additional steps not explicitly covered, and (ii) the temporal order of the operations may vary.

[0076] The terms “processing circuitry” and “means for processing” are used herein to refer to any combination of hardware, firmware, and software for processing data or digital signals. Processing circuitry hardware may include, for example, application-specific integrated circuits (ASICs), general-purpose or special-purpose central processing units (CPUs), digital signal processors (DSPs), graphics processing units (GPUs), and programmable logic devices such as field-programmable gate arrays (FPGAs). In processing circuitry, as used herein, each function is performed by hardware configured (i.e., hardwired) to perform said function, or by more general-purpose hardware (e.g., a CPU) configured to execute instructions stored in a non-transitory storage medium. Processing circuitry may be fabricated on a single printed circuit board (PCB) or distributed across several interconnected PCBs. Processing circuitry may include other processing circuitry; for example, processing circuitry may include two processing circuits, an FPGA and a CPU, interconnected on a PCB.

[0077] As used in this article, the term “array” refers to an ordered collection of numbers, regardless of how they are stored (e.g., whether they are stored in contiguous memory locations or in a linked list).

[0078] As used herein, when a method (e.g., adjustment) or a first quantity (e.g., a first variable) is referred to as “based on” a second quantity (e.g., a second variable), it means that the second quantity is an input to the method or affects the first quantity. For example, the second quantity may be an input to a function that computes the first quantity (e.g., a unique input or one of several inputs), or the first quantity may be equal to the second quantity, or the first quantity may be the same as the second quantity (e.g., stored in one or more locations in memory that are the same as the second quantity).

[0079] It will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or portion from another. Therefore, without departing from the spirit and scope of the inventive concept, the first element, component, region, layer, or portion discussed herein may be referred to as the second element, component, region, layer, or portion.

[0080] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the inventive concept. As used herein, the terms “substantially,” “approximately,” and similar terms are used as approximate terms rather than terms of degree and are intended to explain the inherent biases of measured or calculated values ​​that can be recognized by one of ordinary skill in the art.

[0081] As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. Expressions such as “at least one of…” modify the entire column of elements, not a single element within that column, when following an element in a column. Furthermore, when describing embodiments of the inventive concept, the use of “may” refers to “one or more embodiments of this disclosure.” Additionally, the term “exemplary” is intended to refer to an example or illustration. As used herein, the terms “use,” “using…,” and “using…” can be considered synonymous with the terms “utilize,” “utilize…,” and “taken…”, respectively.

[0082] Any numerical range described herein is intended to include all subranges containing the same numerical precision within the range. For example, a range “1.0 to 10.0” or “between 1.0 and 10.0” is intended to include all subranges between the minimum value 1.0 and the maximum value 10.0 (inclusive), i.e., a minimum value equal to or greater than 1.0 and a maximum value equal to or less than 10.0, such as 2.4 to 7.6. Similarly, a range described as “within 35% of 10” is intended to include all subranges between the listed minimum value 6.5 (i.e., (1-35 / 100) multiplied by 10) and the listed maximum value 13.5 (i.e., (1+35 / 100) multiplied by 10) (and inclusive of both values), i.e., a minimum value equal to or greater than 6.5 and a maximum value equal to or less than 13.5, such as 7.4 to 10.6. Any maximum numerical limit described herein is intended to include all lower numerical limits contained therein, and any minimum numerical limit described in this specification is intended to include all higher numerical limits contained therein.

[0083] It should be understood that when a component is referred to as “directly connected” or “directly coupled” to another component, there are no intermediate components. As used herein, “normal connection” means a connection via an electrical path that may contain any intermediate components, including those whose presence qualitatively alters the behavior of the circuit. As used herein, “connection” means (i) a “direct connection” or (ii) a connection with intermediate components that do not qualitatively affect the behavior of the circuit (e.g., a low-value resistor or inductor, or a short segment of a transmission line).

[0084] Some embodiments may include the features stated by the following numbers.

[0085] 1. A system for distortion reduction, comprising:

[0086] The transmitter includes: a pulse amplitude modulation driver circuit, the pulse amplitude modulation driver circuit including: a main driver, the main driver including a most significant bit (MSB) amplifier and a least significant bit (LSB) amplifier.

[0087] The LSB amplifier includes an upper arm and a lower arm, and the strength of the upper arm or the lower arm is adjustable.

[0088] 2. The system according to statement 1, wherein the strength of the upper arm is adjustable, and the upper arm comprises:

[0089] Switching transistors; and

[0090] An intensity adjustment transistor is connected in series with the switching transistor.

[0091] 3. The system according to statement 1 or statement 2, wherein:

[0092] The strength of the lower arm is adjustable independently of the strength of the upper arm, and

[0093] The lower arm includes:

[0094] Switching transistors, and

[0095] An intensity adjustment transistor is connected in series with the switching transistor of the lower arm.

[0096] 4. The system according to any one of the foregoing statements further includes a feedforward equalizer (FFE) driver, the feedforward equalizer (FFE) driver including an MSB amplifier and an LSB amplifier.

[0097] 5. The system according to statement 4, wherein:

[0098] The LSB amplifier of the FFE driver includes an upper arm and a lower arm, and

[0099] The strength of the upper arm and the lower arm of the LSB amplifier in the FFE driver are independently adjustable.

[0100] 6. The system according to any one of the foregoing statements, wherein:

[0101] The MSB amplifier includes an upper arm and a lower arm, and

[0102] The strength of the upper arm or the lower arm of the MSB amplifier is adjustable.

[0103] 7. The system according to any one of the foregoing statements, wherein the transmitter is configured to:

[0104] Receive instructions from the receiver connected to the transmitter, and

[0105] Adjust the strength of the upper arm or the lower arm based on the instructions.

[0106] 8. The system according to statement 7, wherein the instruction is a command to adjust the strength of the upper arm or the strength of the lower arm.

[0107] 9. The system according to statement 7, wherein the indicator is an indicator of eye size.

[0108] 10. The system according to any one of statements 7 to 9, further comprising the receiver, wherein the receiver is configured to generate the indication based on a measure of distortion of a pulse amplitude modulated signal received from the transmitter.

[0109] 11. The system according to statement 10, wherein the measure of the distortion is a Shmoo array.

[0110] 12. A method for distortion reduction, comprising:

[0111] The transmitter receives instructions from a receiver connected to it; and

[0112] Based on the instruction, the transmitter adjusts the predistortion characteristics of the transmitter's pulse amplitude modulation driver circuit.

[0113] 13. The method according to statement 12, wherein:

[0114] The pulse amplitude modulation driver circuit includes a main driver, which includes a most significant bit (MSB) amplifier and a least significant bit (LSB) amplifier; and

[0115] The LSB amplifier includes an upper arm and a lower arm, and the strength of the upper arm or the lower arm is adjustable.

[0116] 14. The method according to statement 12 or statement 13, wherein the strength of the upper arm is adjustable, and the upper arm comprises:

[0117] Switching transistors; and

[0118] An intensity adjustment transistor is connected in series with the switching transistor.

[0119] 15. The method according to any one of statements 12 to 14, wherein:

[0120] The strength of the lower arm is adjustable independently of the strength of the upper arm, and

[0121] The lower arm includes:

[0122] Switching transistors; and

[0123] An intensity adjustment transistor is connected in series with the switching transistor of the lower arm.

[0124] 16. The method according to any one of statements 12 to 15 further includes a feedforward equalizer (FFE) driver, said FFE driver including an MSB amplifier and an LSB amplifier.

[0125] 17. The method according to statement 16, wherein:

[0126] The LSB amplifier of the FFE driver includes an upper arm and a lower arm, and

[0127] The strength of the upper arm and the lower arm of the LSB amplifier in the FFE driver are independently adjustable.

[0128] 18. The method according to any one of statements 12 to 17, wherein:

[0129] The MSB amplifier includes an upper arm and a lower arm, and

[0130] The strength of the upper arm or the lower arm of the MSB amplifier is adjustable.

[0131] 19. A method for distortion reduction, comprising:

[0132] The receiver receives pulse amplitude modulated signals from a transmitter connected to the receiver;

[0133] A measure of distortion generated based on the signal; and

[0134] An instruction is sent to the transmitter, the instruction being based on a measure of the distortion.

[0135] 20. The method according to statement 19, wherein the generation of the metric of distortion includes generating a Shmoo array.

[0136] Although exemplary embodiments of systems and methods for distortion mitigation in data links have been specifically described and illustrated herein, many modifications and variations will be apparent to those skilled in the art. Therefore, it should be understood that systems and methods for distortion mitigation in data links constructed according to the principles of this disclosure may be implemented in ways other than those specifically described herein. The invention is also defined in the following claims and their equivalents.

Claims

1. A system for distortion reduction, comprising: The transmitter includes a pulse amplitude modulation driver circuit, which includes a main driver that includes a most significant bit (MSB) amplifier and a least significant bit (LSB) amplifier. The LSB amplifier includes an upper arm and a lower arm, and the strength of the upper arm or the lower arm is adjustable.

2. The system according to claim 1, wherein, The strength of the upper arm is adjustable, and the upper arm includes: Switching transistors; and An intensity adjustment transistor is connected in series with the switching transistor.

3. The system according to claim 2, wherein: The strength of the lower arm is adjustable independently of the strength of the upper arm, and The lower arm includes: Switching transistors; and An intensity adjustment transistor is connected in series with the switching transistor of the lower arm.

4. The system according to claim 1 further includes a feedforward equalizer (FFE) driver, the FFE driver including an MSB amplifier and an LSB amplifier.

5. The system according to claim 4, wherein: The LSB amplifier of the FFE driver includes an upper arm and a lower arm, and The strength of the upper arm and the lower arm of the LSB amplifier in the FFE driver are independently adjustable.

6. The system according to claim 1, wherein: The MSB amplifier includes an upper arm and a lower arm, and The intensity of the upper arm of the MSB amplifier or the intensity of the lower arm of the MSB amplifier is adjustable.

7. The system according to claim 1, wherein, The transmitter is configured to: Receive instructions from the receiver connected to the transmitter, and The strength of the upper arm or the strength of the lower arm is adjusted based on the instruction.

8. The system according to claim 7, wherein, The instruction is a command to adjust the strength of the upper arm or the strength of the lower arm.

9. The system according to claim 7, wherein, The indicator is an indicator of eye size.

10. The system of claim 7, further comprising the receiver, wherein the receiver is configured to generate the indication based on a measure of distortion of a pulse amplitude modulation signal received from the transmitter.

11. The system according to claim 10, wherein, The distortion is measured by the Shmoo array.

12. A method for distortion reduction, comprising: The transmitter receives an instruction from a receiver connected to the transmitter. and Based on the instruction, the transmitter adjusts the predistortion characteristics of the transmitter's pulse amplitude modulation driver circuit.

13. The method according to claim 12, wherein: The pulse amplitude modulation driver circuit includes a main driver, which includes a most significant bit (MSB) amplifier and a least significant bit (LSB) amplifier; and The LSB amplifier includes an upper arm and a lower arm, the strength of which is adjustable.

14. The method according to claim 13, wherein, The strength of the upper arm is adjustable, and the upper arm includes: Switching transistors; and An intensity adjustment transistor is connected in series with the switching transistor.

15. The method of claim 14, wherein: The strength of the lower arm is adjustable independently of the strength of the upper arm, and The lower arm includes: Switching transistors; and An intensity adjustment transistor is connected in series with the switching transistor of the lower arm.

16. The method of claim 14, further comprising a feedforward equalizer (FFE) driver, the FFE driver comprising an MSB amplifier and an LSB amplifier.

17. The method of claim 16, wherein: The LSB amplifier of the FFE driver includes an upper arm and a lower arm, and The intensity of the upper arm and the intensity of the lower arm of the LSB amplifier of the FFE driver are independently adjustable.

18. The method of claim 14, wherein: The MSB amplifier includes an upper arm and a lower arm, and The intensity of the upper arm of the MSB amplifier or the intensity of the lower arm of the MSB amplifier is adjustable.

19. A method for distortion reduction, comprising: The receiver receives a pulse amplitude modulated signal from a transmitter connected to the receiver; A measure of distortion is generated based on the signal; and An instruction is sent to the transmitter, the instruction being based on a measure of the distortion.

20. The method according to claim 19, wherein, The generation of the metric of distortion includes generating a Shmoo array.

Images