An LED epitaxial wafer and its preparation method

Abstract

This invention discloses an LED epitaxial wafer and its fabrication method, relating to the field of semiconductor device technology. The fabrication method includes: providing a substrate, sequentially growing an N-GaN layer, a multi-quantum-well light-emitting layer, and a P-GaN layer on the substrate; sequentially cleaning the grown structure with an organic solvent, acid washing, and drying; placing the dried structure in a plasma environment, first introducing a cleaning gas for plasma cleaning, the cleaning gas including at least one of argon and helium; then introducing a mixed gas for plasma modification, the mixed gas being composed of oxygen and a gas selected from argon and helium; then sequentially depositing an amorphous ITO seed layer and a crystalline ITO host layer; after deposition, performing annealing treatment to obtain the LED epitaxial wafer. This invention can solve the technical problems of high potential barrier, low hole injection efficiency, and poor interface stability at the ITO / P-GaN contact interface in the prior art.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device technology, and more specifically to an LED epitaxial wafer and its preparation method. Background Technology

[0002] GaN-based LEDs have been widely used in lighting, display backlighting, and optical communication due to their advantages such as high efficiency, energy saving, long lifespan, and tunable spectrum. In the structure of GaN-based LED devices, the P-GaN layer is the key to achieving efficient hole injection and radiative recombination, and its contact performance with the transparent conductive layer directly determines the device's operating voltage, light output efficiency, and long-term reliability.

[0003] Currently, ITO is the most commonly used transparent conductive contact material for P-GaN layers. However, due to the presence of a natural oxide layer and magnesium acceptor passivation on the surface of P-GaN layers, the ITO / P-GaN contact interface often faces technical bottlenecks such as high specific contact resistance, uneven hole injection, and poor interface stability. This leads to increased device operating voltage, limited light extraction efficiency, and decreased long-term operational reliability. Summary of the Invention

[0004] In view of the shortcomings of the prior art, the purpose of this invention is to provide a method for preparing LED epitaxial wafers and the same method, which aims to solve at least one problem in the background art.

[0005] This invention provides a method for preparing an LED epitaxial wafer, the method comprising: A substrate is provided on which an N-GaN layer, a multiple quantum well light-emitting layer, and a P-GaN layer are sequentially grown. The grown structure was then sequentially cleaned with organic solvents, acid-washed, and dried. The dried structure is placed in a plasma environment, and a cleaning gas is first introduced to perform plasma cleaning on the surface of the P-GaN layer. The cleaning gas includes at least one of argon and helium. The P-GaN layer is then subjected to plasma modification by introducing a mixed gas, which consists of oxygen and a gas selected from argon and helium. An amorphous ITO seed layer and a crystalline ITO host layer are sequentially deposited on the surface of a modified P-GaN layer; After deposition, annealing is performed to obtain LED epitaxial wafers.

[0006] According to one aspect of the above technical solution, the steps of organic solvent cleaning, acid washing, and drying are then performed sequentially, specifically including: The cleaning process involved sequentially cleaning with acetone, deionized water, and isopropanol, with each cleaning cycle using an ultrasonic power of 100W-300W and a cleaning time of 5-10 minutes. Pickling was performed using hydrochloric acid solution at room temperature, with a volume concentration of 1%-5% and a pickling time of 30s-180s. After rinsing with deionized water 2-3 times, dry by rotation at 50℃-80℃ for 5-10 minutes.

[0007] According to one aspect of the above technical solution, in the plasma cleaning step, the process temperature is room temperature and the vacuum degree is <5×10⁻⁶. -5 Pa, pressure is 0.5Pa-2Pa, plasma gun power is 100W-800W, cleaning gas flow rate is 10sccm-80sccm, and processing time is 10s-90s.

[0008] According to one aspect of the above technical solution, in the plasma modification step, the vacuum degree is <5×10⁻⁶. -5 The pressure is 0.1Pa-1Pa, the process temperature is 80℃-150℃, the plasma gun power is 500W-1000W, the mixed gas flow rate is 30sccm-120sccm, and the processing time is 60s-180s.

[0009] According to one aspect of the above technical solution, oxygen accounts for 2%-20% of the gas flow rate in the mixed gas.

[0010] According to one aspect of the above technical solution, the deposition step of the amorphous ITO seed layer includes: Vacuum degree < 5 × 10 -5 Under conditions of pressure of 0.5Pa-3Pa and process temperature <50℃, argon and oxygen are introduced, and the evaporation source is In2O3 and SnO2 with a mass ratio of (8-10):1, resulting in an amorphous ITO seed layer with a thickness of 1nm-5nm. The total flow rate of argon and oxygen is 30 sccm-80 sccm, the oxygen gas flow rate accounts for 8%-20%, the plasma gun power is 450W-650W, and the evaporation rate is 3nm / min-8nm / min.

[0011] According to one aspect of the above technical solution, the deposition step of the crystalline ITO host layer includes: Vacuum degree < 5 × 10 -5 Under conditions of pressure of 0.5Pa-3Pa and process temperature of 50℃-200℃, argon and oxygen are introduced, and the evaporation source is In2O3 and SnO2 with a mass ratio of (8-10):1, resulting in a crystalline ITO host layer with a thickness of 15nm-500nm. The total flow rate of argon and oxygen is 100 sccm-400 sccm, the oxygen gas flow rate accounts for 2%-10%, the plasma gun power is 800W-1200W, and the evaporation rate is 10nm / min-50nm / min.

[0012] According to one aspect of the above technical solution, the annealing process includes: Heat from room temperature to 400℃ at a heating rate of 8℃ / min-12℃ / min, then heat to 400℃-600℃ at a rate of 2℃ / min-7℃ / min, and anneal for 2min-30min. Then cool down to 300℃ at a rate of 2℃ / min-7℃ / min, followed by natural cooling.

[0013] Another aspect of the present invention is to provide an LED epitaxial wafer, which is prepared by the above-described method for preparing an LED epitaxial wafer. The LED epitaxial wafer includes a substrate and an N-GaN layer, a multiple quantum well light-emitting layer, a P-GaN layer, and an ITO layer sequentially stacked on the substrate.

[0014] Furthermore, the thickness of the N-GaN layer is 2μm-4μm. The multi-quantum-well light-emitting layer comprises periodically alternating InGaN well layers and GaN barrier layers with a period of 5-15. The thickness of the InGaN well layers is 2.5nm-3.5nm, and the thickness of the GaN barrier layers is 8nm-12nm. The thickness of the P-GaN layer is 100nm-300nm.

[0015] Compared with the prior art, the beneficial effects of the present invention are as follows: By combining plasma treatment with mixed gas and deposition of amorphous ITO seed layer, multiple interface optimization effects are achieved. The plasma treatment with mixed gas can reduce the surface barrier of P-GaN layer and increase the effective hole concentration through chemical activation, and remove surface oxide layer and impurities through physical sputtering, thereby improving the bandgap matching between ITO and P-GaN. The amorphous ITO seed layer can form a dense, low-defect transition layer that perfectly covers the atomic-level fluctuations on the surface of P-GaN layer, significantly reducing the interface state density and suppressing interface diffusion and oxidation. This fundamentally solves the core problems of high interface barrier, uneven hole injection, and poor stability in traditional ITO / P-GaN. Attached Figure Description

[0016] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which: Figure 1 This is a schematic diagram of the structure of the LED epitaxial wafer of the present invention; Component symbol explanation in the attached diagram: Substrate 1, N-GaN layer 2, multi-quantum-well light-emitting layer 3, P-GaN layer 4, ITO layer 5, amorphous ITO seed layer 51, crystalline ITO host layer 52. Detailed Implementation

[0017] To make the objectives, features, and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Several embodiments of the present invention are shown in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of the present invention will be more thorough and complete.

[0018] It should be noted that when an element is referred to as being "fixed to" another element, it can be directly on the other element or there may be an intervening element. When an element is considered to be "connected" to another element, it can be directly connected to the other element or there may be an intervening element. The terms "vertical," "horizontal," "left," "right," "upper," "lower," and similar expressions used herein are for illustrative purposes only and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as limiting the invention.

[0019] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal communication between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances. The term "and / or" as used herein includes any and all combinations of one or more of the related listed items.

[0020] This invention provides a method for preparing an LED epitaxial wafer, the method comprising steps S1-S6. Step S1: Provide a substrate, and sequentially grow an N-GaN layer, a multi-quantum-well light-emitting layer, and a P-GaN layer on the substrate; Specifically, a patterned sapphire substrate is provided, and an N-GaN layer, a multiple quantum well light-emitting layer, and a P-GaN layer are epitaxially grown sequentially on the substrate using metal-organic chemical vapor deposition (MOCVD).

[0021] The N-GaN layer has a thickness of 2μm-4μm, the multi-quantum-well light-emitting layer includes periodically alternating InGaN well layers and GaN barrier layers with a period of 5-15, the InGaN well layer has a thickness of 2.5nm-3.5nm, the GaN barrier layer has a thickness of 8nm-12nm, and the P-GaN layer has a thickness of 100nm-300nm.

[0022] Step S2 involves sequentially cleaning the grown structure with organic solvents, acid washing, and drying. Specifically, acetone, deionized water, and isopropanol are used for cleaning in sequence, with an ultrasonic power of 100W-300W for each cleaning and a cleaning time of 5-10 minutes to remove organic dirt from the surface.

[0023] Pickling was performed using hydrochloric acid solution at room temperature, with a volume concentration of 1%-5% and a pickling time of 30s-180s; this removed the GaO oxide layer from the surface of the P-GaN layer.

[0024] After rinsing with deionized water 2-3 times to remove acid residue, it is then rotary dried at 50℃-80℃ for 5-10 minutes.

[0025] Step S3: Place the dried structure in a plasma environment and first introduce a cleaning gas to perform plasma cleaning on the surface of the P-GaN layer. The cleaning gas includes at least one of argon and helium. The process involves continuous plasma treatment and subsequent ITO deposition using RPD (Reactive Plasma Deposition) equipment while maintaining a constant vacuum level. A pressure ramp plasma gun is employed to ensure the uniformity and controllability of the plasma.

[0026] Specifically, in the plasma cleaning step, the process temperature is room temperature and the vacuum degree is <5×10⁻⁶. -5 The treatment process involves a pressure of 0.5Pa-2Pa, a plasma gun power of 100W-800W, a cleaning gas flow rate of 10sccm-80sccm, and a treatment time of 10s-90s. This method removes trace adsorbates and native oxides from the surface and enhances activity.

[0027] Step S4: The P-GaN layer is then plasma modified by introducing a mixed gas, which consists of oxygen and a gas selected from argon and helium. Specifically, in the plasma modification step, the process temperature is 80℃-150℃, the plasma gun power is 500W-1000W, the flow rate of the mixed gas is 30sccm-120sccm, and the processing time is 60s-180s. This activates the surface of the P-GaN layer and reduces the potential barrier, improves the bandgap matching between the ITO and P-GaN layers, enhances the hole injection efficiency, and helps to reduce the operating voltage of the LED device and improve the photoelectric conversion efficiency.

[0028] Furthermore, oxygen accounts for 2%-20% of the gas flow rate in the mixed gas. Utilizing the synergistic effect of the mixed gas plasma, highly reactive oxygen ions, after being ionized, can consume electrons near the surface of the P-GaN layer, effectively increasing the effective hole concentration on the surface of the P-GaN layer. At the same time, low-energy argon or helium ions provide a slight and continuous physical sputtering effect, which can remove reaction byproducts generated during the modification process and any non-ideal surface layers that may be formed, making the modification process more uniform and controllable.

[0029] Step S5: An amorphous ITO seed layer and a crystalline ITO host layer are sequentially deposited on the surface of the modified P-GaN layer; Specifically, in a vacuum degree < 5 × 10 -5 Under conditions of pressure of 0.5Pa-3Pa and process temperature <50℃, argon and oxygen are introduced, and the evaporation source is In2O3 and SnO2 with a mass ratio of (8-10):1, resulting in an amorphous ITO seed layer with a thickness of 1nm-5nm. The total flow rate of argon and oxygen is 30 sccm-80 sccm, with oxygen accounting for 8%-20% of the total flow rate. The plasma gun power is 450W-650W, and the evaporation rate is 3nm / min-8nm / min. A transition layer is constructed between the P-GaN layer and the subsequent crystalline ITO substrate layer. Utilizing the characteristics of amorphous structures—no grain boundaries and high density—this layer perfectly covers the atomic-level undulations on the P-GaN layer surface, forming a continuous, pinhole-free interface layer. Simultaneously, the chemical passivation effect between the amorphous ITO seed layer and the P-GaN layer optimizes the interface lattice matching and suppresses interface diffusion and oxidation phenomena in subsequent processes.

[0030] That is, the amorphous ITO seed layer forms a dense, low-defect interface transition layer, which significantly reduces the interface state density, reduces carrier recombination loss, and significantly improves hole injection efficiency. At the same time, the adhesion between the amorphous ITO seed layer and the P-GaN layer and the crystalline ITO host layer is enhanced, providing a uniform and stable substrate for the subsequent growth of the crystalline ITO host layer.

[0031] Next, keeping the vacuum level and evaporation source constant, the pressure is 0.5Pa-3Pa, the temperature is raised to 50℃-200℃, argon and oxygen are introduced, and a crystalline ITO host layer with a thickness of 15nm-500nm is deposited. This serves as the core transparent conductive layer of the device, ensuring the device's current transmission capability and light extraction performance. Its crystal structure endows the material with low resistivity characteristics, while maintaining high visible light transmittance, thus balancing the electrical and optical performance of the device.

[0032] The total flow rate of argon and oxygen is 100 sccm-400 sccm, the oxygen gas flow rate accounts for 2%-10%, the plasma gun power is 800W-1200W, and the evaporation rate is 10nm / min-50nm / min.

[0033] The low resistivity and high visible light transmittance of the crystalline ITO host layer enable the current to be uniformly distributed within the thin film, allowing for efficient transmission to the surface of the P-GaN layer and achieving uniform hole injection. At the same time, the high transmittance ensures that photons generated by the multi-quantum-well light-emitting layer are emitted smoothly, reducing light absorption loss.

[0034] Step S6: After deposition is completed, annealing is performed to obtain the LED epitaxial wafer.

[0035] Specifically, the temperature is increased from room temperature to 400℃ at a rate of 8℃ / min-12℃ / min, and then increased to 400℃-600℃ at a rate of 2℃ / min-7℃ / min, and annealed for 2min-30min. Then cool down to 300℃ at a rate of 2℃ / min-7℃ / min, followed by natural cooling.

[0036] Annealing will drive atomic interdiffusion and chemical reaction at the ITO-P-GaN interface, further optimizing the interface structure and forming a stable low-resistance ohmic contact; at the same time, it will promote the fusion of the amorphous ITO seed layer and the crystalline ITO host layer, optimizing the crystal quality of the ITO layer; the gradient heating and cooling design can effectively avoid epitaxial wafer cracking or interface peeling caused by thermal stress.

[0037] Accordingly, please refer to Figure 1 The present application also provides an LED epitaxial wafer, which is prepared by the above-described method for preparing an LED epitaxial wafer. The LED epitaxial wafer includes a substrate 1 and N-GaN layer 2, multiple quantum well light-emitting layer 3, P-GaN layer 4, and ITO layer 5 sequentially stacked on the substrate 1.

[0038] The ITO layer 5 includes an amorphous ITO seed layer 51 stacked on top of the P-GaN layer 4, and a crystalline ITO host layer 52 stacked on top of the amorphous ITO seed layer 51.

[0039] The technical solution of the present invention will now be described in detail with reference to specific embodiments.

[0040] Example 1 Embodiment 1 of the present invention provides a method for preparing an LED epitaxial wafer, the method comprising steps S1-S6. Step S1: Provide a substrate, and sequentially grow an N-GaN layer, a multi-quantum-well light-emitting layer, and a P-GaN layer on the substrate; Specifically, a patterned sapphire substrate is provided, and an N-GaN layer, a multiple quantum well light-emitting layer, and a P-GaN layer are epitaxially grown sequentially on the substrate using metal-organic chemical vapor deposition (MOCVD).

[0041] The N-GaN layer has a thickness of 3 μm, the multi-quantum-well light-emitting layer includes periodically alternating InGaN well layers and GaN barrier layers with a period of 10, the InGaN well layer has a thickness of 3 nm, the GaN barrier layer has a thickness of 10 nm, and the P-GaN layer has a thickness of 200 nm.

[0042] Step S2 involves sequentially cleaning the grown structure with organic solvents, acid washing, and drying. Specifically, acetone, deionized water, and isopropanol were used for cleaning in sequence, with an ultrasonic power of 200W for each cleaning and a cleaning time of 8 minutes.

[0043] Pickling was performed using hydrochloric acid solution at room temperature with a volume concentration of 1% and a pickling time of 60 seconds.

[0044] After rinsing twice with deionized water for 7 minutes each time, it was then rotary dried at 60°C for 8 minutes.

[0045] Step S3: Place the dried structure in a plasma environment and first introduce a cleaning gas, namely argon, to perform plasma cleaning on the surface of the P-GaN layer. Specifically, in the plasma cleaning step, the process temperature is room temperature and the vacuum degree is <5×10⁻⁶. -5 The pressure is 1 Pa, the power of the plasma gun is 200 W, the flow rate of the cleaning gas is 30 sccm, and the processing time is 60 s.

[0046] Step S4: The P-GaN layer is then plasma-modified by introducing a mixed gas, which consists of oxygen and helium. Specifically, in the plasma modification step, the vacuum degree is <5×10⁻⁶. -5The process conditions are as follows: pressure 0.5 Pa, process temperature 100℃, plasma gun power 800W, mixed gas flow rate 54 sccm, and processing time 100 s. Specifically, helium flow rate is 50 sccm and oxygen flow rate is 4 sccm.

[0047] Step S5: An amorphous ITO seed layer and a crystalline ITO host layer are sequentially deposited on the surface of the modified P-GaN layer; Specifically, in a vacuum degree < 5 × 10 -5 Under conditions of 1.5 Pa pressure, room temperature, argon and oxygen were introduced, and the deposition source was an In₂O₃ and SnO₂ mixture with a mass ratio of 9:1, resulting in a 3 nm thick amorphous ITO seed layer. The total flow rate of argon and oxygen was 40 sccm, the flow rate of argon was 36 sccm, the flow rate of oxygen was 4 sccm, the plasma gun power was 550W, and the evaporation rate was 3.5 nm / min.

[0048] Next, while keeping the vacuum level and evaporation source unchanged, the pressure was reduced to 0.9 Pa, the temperature was increased to 90 °C, and argon and oxygen were introduced to deposit a crystalline ITO substrate layer with a thickness of 30 nm.

[0049] The flow rate of argon was 160 sccm, the flow rate of oxygen was 10 sccm, the plasma gun power was 1000W, and the evaporation rate was 25 nm / min.

[0050] Step S6: After deposition is completed, annealing is performed to obtain the LED epitaxial wafer.

[0051] Specifically, the annealing atmosphere is nitrogen, the temperature is increased from room temperature to 400℃ at a rate of 10℃ / min, and then increased to 550℃ at a rate of 5℃ / min, and annealed for 10 min. Then cool down to 300℃ at a rate of 5℃ / min, and then allow to cool naturally.

[0052] Example 2 The present invention provides a method for preparing an LED epitaxial wafer in Embodiment 2. The difference between the method for preparing an LED epitaxial wafer in this embodiment and the method for preparing an LED epitaxial wafer in Embodiment 1 is that: The cleaning gas is helium with a flow rate of 50 sccm, and the plasma gun has a power of 600W.

[0053] Example 3 The present invention provides a method for preparing an LED epitaxial wafer in Embodiment 3. The difference between the method for preparing an LED epitaxial wafer in this embodiment and the method for preparing an LED epitaxial wafer in Embodiment 1 is that: The mixed gas consists of oxygen and argon, with an oxygen flow rate of 2 sccm and an argon flow rate of 40 sccm. The plasma gun has a power of 600W, the process temperature is 90℃, and the processing time is 90s.

[0054] Example 4 The present invention provides a method for preparing an LED epitaxial wafer in Embodiment 4. The difference between the method for preparing an LED epitaxial wafer in this embodiment and the method for preparing an LED epitaxial wafer in Embodiment 1 is that: In the annealing process, the annealing atmosphere is air (oxygen partial pressure 21%), the temperature is increased from room temperature to 400°C at a rate of 10°C / min, and then increased to 550°C at a rate of 5°C / min, and annealed for 5 min. Then cool down to 300℃ at a rate of 5℃ / min, and then allow to cool naturally.

[0055] Example 5 The present invention provides a method for preparing an LED epitaxial wafer in Embodiment 5. The difference between the method for preparing an LED epitaxial wafer in this embodiment and the method for preparing an LED epitaxial wafer in Embodiment 1 is that: In the annealing process, nitrogen is used as the annealing atmosphere, and the temperature is increased from room temperature to 400°C at a rate of 10°C / min for 2 minutes. Then, air is used as the annealing atmosphere, and the temperature is increased to 550°C at a rate of 5°C / min for 2 minutes. Then cool down to 300℃ at a rate of 5℃ / min, and then allow to cool naturally.

[0056] Example 6 The present invention provides a method for preparing an LED epitaxial wafer in Embodiment 6. The difference between the method for preparing an LED epitaxial wafer in this embodiment and the method for preparing an LED epitaxial wafer in Embodiment 1 is that: The mixed gas consists of oxygen and helium, with a helium flow rate of 52 sccm and an oxygen flow rate of 2 sccm.

[0057] Example 7 The present invention provides a method for preparing an LED epitaxial wafer in Embodiment 7. The difference between the method for preparing an LED epitaxial wafer in this embodiment and the method for preparing an LED epitaxial wafer in Embodiment 1 is that: The mixed gas consists of oxygen and helium, with a helium flow rate of 46 sccm and an oxygen flow rate of 8 sccm.

[0058] Example 8 The present invention provides a method for preparing an LED epitaxial wafer in Embodiment 8. The difference between the method for preparing an LED epitaxial wafer in this embodiment and the method for preparing an LED epitaxial wafer in Embodiment 1 is that: The mixed gas consists of oxygen and helium, with a helium flow rate of 100 sccm and an oxygen flow rate of 4 sccm.

[0059] Example 9 The present invention provides a method for preparing an LED epitaxial wafer in Embodiment 9. The difference between the method for preparing an LED epitaxial wafer in this embodiment and the method for preparing an LED epitaxial wafer in Embodiment 3 is that: The mixed gas consists of oxygen and argon, with an argon flow rate of 41 sccm and an oxygen flow rate of 1 sccm.

[0060] Example 10 The present invention provides a method for preparing an LED epitaxial wafer in Embodiment 10. The difference between the method for preparing an LED epitaxial wafer in this embodiment and the method for preparing an LED epitaxial wafer in Embodiment 3 is that: The mixed gas consists of oxygen and argon, with an argon flow rate of 36 sccm and an oxygen flow rate of 6 sccm.

[0061] Example 11 The method for preparing an LED epitaxial wafer provided in Embodiment 11 of the present invention differs from the method for preparing an LED epitaxial wafer in Embodiment 3 in that: The mixed gas consists of oxygen and argon, with an argon flow rate of 80 sccm and an oxygen flow rate of 2 sccm.

[0062] Example 12 The present invention provides a method for preparing an LED epitaxial wafer in Embodiment 12. The method for preparing the LED epitaxial wafer in this embodiment differs from the method for preparing the LED epitaxial wafer in Embodiment 1 in that: The thickness of the amorphous ITO seed layer is 2 nm.

[0063] Example 13 The present invention provides a method for preparing an LED epitaxial wafer in Embodiment 13. The difference between the method for preparing an LED epitaxial wafer in this embodiment and the method for preparing an LED epitaxial wafer in Embodiment 1 is that: The thickness of the amorphous ITO seed layer is 4 nm.

[0064] Comparative Example 1 The present invention provides a method for preparing an LED epitaxial wafer in Comparative Example 1. The difference between the method for preparing the LED epitaxial wafer in this comparative example and the method for preparing the LED epitaxial wafer in Example 1 is as follows: No mixed gas was introduced for plasma modification and deposition of an amorphous ITO seed layer; everything else remained unchanged.

[0065] Comparative Example 2 Comparative Example 2 of this invention provides a method for preparing an LED epitaxial wafer. The difference between the method for preparing the LED epitaxial wafer in this comparative example and the method for preparing the LED epitaxial wafer in Example 1 is that: No amorphous ITO seed layer was deposited; everything else remained the same.

[0066] Comparative Example 3 The present invention provides a method for preparing an LED epitaxial wafer in Comparative Example 3. The difference between the method for preparing the LED epitaxial wafer in this comparative example and the method for preparing the LED epitaxial wafer in Example 1 is as follows: No mixed gas was introduced for plasma modification; everything else remained unchanged.

[0067] Comparative Example 4 The present invention provides a method for preparing an LED epitaxial wafer in Comparative Example 4. The difference between the method for preparing the LED epitaxial wafer in this comparative example and the method for preparing the LED epitaxial wafer in Example 1 is as follows: For surface modification using helium alone, the helium flow rate is 40 sccm, and the other steps remain unchanged.

[0068] Comparative Example 5 The present invention provides a method for preparing an LED epitaxial wafer in Comparative Example 5. The difference between the method for preparing the LED epitaxial wafer in this comparative example and the method for preparing the LED epitaxial wafer in Example 1 is as follows: Surface modification was performed using oxygen alone, with an oxygen flow rate of 2 sccm, while other steps remained unchanged.

[0069] Comparative Example 6 The present invention provides a method for preparing an LED epitaxial wafer in Comparative Example 6. The difference between the method for preparing the LED epitaxial wafer in this comparative example and the method for preparing the LED epitaxial wafer in Example 3 is as follows: Surface modification was performed using argon gas alone, with a flow rate of 50 sccm, while other steps remained unchanged.

[0070] Please refer to Table 1 below, which shows the parameters corresponding to the above embodiments and comparative examples of the present invention.

[0071] Table 1:

[0072] It should be noted that the parameters corresponding to the embodiments and comparative examples were tested under the same conditions (tested on a 37mil×37mil flip chip, with a test current of 700mA), and the luminous efficiency was calculated by dividing the chip's optical power by its electrical power.

[0073] From Table 1, we can see that: Through comparison of examples and comparative examples, it is verified that plasma surface modification of mixed gas and deposition of amorphous ITO seed layer are indispensable and synergistic core technologies. The two work together to achieve high brightness, low voltage and high efficiency. When either is missing or applied alone, the device performance deteriorates significantly.

[0074] Secondly, there are clear patterns in the surface modification and ratio optimization of plasma with mixed gases: Example 3, which uses the O2 / Ar system, achieved the best overall performance, while Example 1, which uses the O2 / He system, had slightly lower brightness and voltage than Example 3. This indicates that the synergistic effect of physical sputtering and chemical activation of the O2 / Ar system is better at optimizing interface performance than the O2 / He system. In contrast, the single gas treatment in Comparative Examples 4-6 could not achieve this effect. Furthermore, deviations from the optimal gas ratio (Examples 9-11) lead to a comprehensive decline in performance. Specific gas components and precise ratios are crucial for the simultaneous optimization of brightness and voltage.

[0075] According to the data from Examples 1, 12, and 13, the thickness of the amorphous ITO seed layer is a sensitive parameter. The optimal thickness (Example 1) can achieve the best balance between maintaining high brightness (without affecting light extraction) and low voltage (minimizing series resistance). Too thin or too thick a thickness will affect the device performance.

[0076] Furthermore, optimization of other auxiliary processes also brought performance gains. For example, Example 5, which uses a two-step annealing method, can effectively improve the conductivity and light transmittance of the ITO layer, achieving a combined improvement in electrical and optical properties.

[0077] In summary, the technical solution of this invention systematically solves the ITO / P-GaN contact interface problem through the synergistic application of plasma surface modification of a mixed gas with a specific ratio and an amorphous ITO seed layer, achieving significant optimization of the three key indicators of brightness, voltage, and efficiency.

[0078] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0079] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this patent should be determined by the appended claims.

Claims

1. A method for preparing an LED epitaxial wafer, characterized in that, The preparation method includes: A substrate is provided on which an N-GaN layer, a multiple quantum well light-emitting layer, and a P-GaN layer are sequentially grown. The grown structure was then sequentially cleaned with organic solvents, acid-washed, and dried. The dried structure is placed in a plasma environment, and a cleaning gas is first introduced to perform plasma cleaning on the surface of the P-GaN layer. The cleaning gas includes at least one of argon and helium. The P-GaN layer is then subjected to plasma modification by introducing a mixed gas, which consists of oxygen and a gas selected from argon and helium. An amorphous ITO seed layer and a crystalline ITO host layer are sequentially deposited on the surface of a modified P-GaN layer; After deposition, annealing is performed to obtain LED epitaxial wafers.

2. The method for preparing an LED epitaxial wafer according to claim 1, characterized in that, The process then proceeds with organic solvent cleaning, acid washing, and drying, specifically including: The cleaning process involved sequentially cleaning with acetone, deionized water, and isopropanol, with each cleaning cycle using an ultrasonic power of 100W-300W and a cleaning time of 5-10 minutes. Pickling was performed using hydrochloric acid solution at room temperature, with a volume concentration of 1%-5% and a pickling time of 30s-180s. After rinsing with deionized water 2-3 times, dry by rotation at 50℃-80℃ for 5-10 minutes.

3. The method for preparing an LED epitaxial wafer according to claim 1, characterized in that, In the plasma cleaning step, the process temperature is room temperature and the vacuum degree is <5×10⁻⁶. -5 Pa, pressure 0.5Pa-2Pa, plasma gun power 100W-800W, cleaning gas flow rate 10sccm-80sccm, processing time 10s-90s.

4. The method for preparing an LED epitaxial wafer according to claim 1, characterized in that, In the plasma modification step, the vacuum level is <5×10⁻⁶. -5 The pressure is 0.1Pa-1Pa, the process temperature is 80℃-150℃, the plasma gun power is 500W-1000W, the mixed gas flow rate is 30sccm-120sccm, and the processing time is 60s-180s.

5. The method for preparing an LED epitaxial wafer according to claim 4, characterized in that, Oxygen accounts for 2%-20% of the gas flow rate in the mixed gas.

6. The method for preparing an LED epitaxial wafer according to claim 1, characterized in that, The deposition step of the amorphous ITO seed layer includes: Vacuum degree < 5 × 10 -5 Under conditions of pressure of 0.5Pa-3Pa and process temperature <50℃, argon and oxygen are introduced, and the evaporation source is In2O3 and SnO2 with a mass ratio of (8-10):1, resulting in an amorphous ITO seed layer with a thickness of 1nm-5nm. The total flow rate of argon and oxygen is 30 sccm-80 sccm, the oxygen gas flow rate accounts for 8%-20%, the plasma gun power is 450W-650W, and the evaporation rate is 3nm / min-8nm / min.

7. The method for preparing an LED epitaxial wafer according to claim 1, characterized in that, The deposition step of the crystalline ITO host layer includes: Vacuum degree < 5 × 10 -5 Under conditions of pressure of 0.5Pa-3Pa and process temperature of 50℃-200℃, argon and oxygen are introduced, and the evaporation source is In2O3 and SnO2 with a mass ratio of (8-10):1, resulting in a crystalline ITO host layer with a thickness of 15nm-500nm. The total flow rate of argon and oxygen is 100 sccm-400 sccm, the oxygen gas flow rate accounts for 2%-10%, the plasma gun power is 800W-1200W, and the evaporation rate is 10nm / min-50nm / min.

8. The method for preparing an LED epitaxial wafer according to claim 1, characterized in that, The annealing process includes: Heat from room temperature to 400℃ at a heating rate of 8℃ / min-12℃ / min, then heat to 400℃-600℃ at a rate of 2℃ / min-7℃ / min, and anneal for 2min-30min. Then cool down to 300℃ at a rate of 2℃ / min-7℃ / min, followed by natural cooling.

9. An LED epitaxial wafer, characterized in that, The LED epitaxial wafer is prepared by the method for preparing an LED epitaxial wafer according to any one of claims 1-8. The LED epitaxial wafer includes a substrate and an N-GaN layer, a multiple quantum well light-emitting layer, a P-GaN layer, and an ITO layer sequentially stacked on the substrate.

10. The LED epitaxial wafer according to claim 9, characterized in that, The thickness of the N-GaN layer is 2μm-4μm. The multi-quantum-well light-emitting layer comprises periodically alternating InGaN well layers and GaN barrier layers with a period of 5-15. The thickness of the InGaN well layers is 2.5nm-3.5nm, and the thickness of the GaN barrier layers is 8nm-12nm. The thickness of the P-GaN layer is 100nm-300nm.

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